1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "sysemu/cpus.h" 34 #include "hw/block/fdc.h" 35 #include "hw/ide.h" 36 #include "hw/pci/pci.h" 37 #include "hw/pci/pci_bus.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/timer/hpet.h" 40 #include "hw/firmware/smbios.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "multiboot.h" 44 #include "hw/timer/mc146818rtc.h" 45 #include "hw/dma/i8257.h" 46 #include "hw/timer/i8254.h" 47 #include "hw/input/i8042.h" 48 #include "hw/audio/pcspk.h" 49 #include "hw/pci/msi.h" 50 #include "hw/sysbus.h" 51 #include "sysemu/sysemu.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/kvm.h" 54 #include "sysemu/qtest.h" 55 #include "kvm_i386.h" 56 #include "hw/xen/xen.h" 57 #include "hw/xen/start_info.h" 58 #include "ui/qemu-spice.h" 59 #include "exec/memory.h" 60 #include "exec/address-spaces.h" 61 #include "sysemu/arch_init.h" 62 #include "qemu/bitmap.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "qemu/option.h" 66 #include "hw/acpi/acpi.h" 67 #include "hw/acpi/cpu_hotplug.h" 68 #include "hw/boards.h" 69 #include "acpi-build.h" 70 #include "hw/mem/pc-dimm.h" 71 #include "qapi/error.h" 72 #include "qapi/qapi-visit-common.h" 73 #include "qapi/visitor.h" 74 #include "qom/cpu.h" 75 #include "hw/nmi.h" 76 #include "hw/usb.h" 77 #include "hw/i386/intel_iommu.h" 78 #include "hw/net/ne2000-isa.h" 79 #include "standard-headers/asm-x86/bootparam.h" 80 81 /* debug PC/ISA interrupts */ 82 //#define DEBUG_IRQ 83 84 #ifdef DEBUG_IRQ 85 #define DPRINTF(fmt, ...) \ 86 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 87 #else 88 #define DPRINTF(fmt, ...) 89 #endif 90 91 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 92 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 93 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 94 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 95 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 96 97 #define E820_NR_ENTRIES 16 98 99 struct e820_entry { 100 uint64_t address; 101 uint64_t length; 102 uint32_t type; 103 } QEMU_PACKED __attribute((__aligned__(4))); 104 105 struct e820_table { 106 uint32_t count; 107 struct e820_entry entry[E820_NR_ENTRIES]; 108 } QEMU_PACKED __attribute((__aligned__(4))); 109 110 static struct e820_table e820_reserve; 111 static struct e820_entry *e820_table; 112 static unsigned e820_entries; 113 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 114 115 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 116 static size_t pvh_start_addr; 117 118 GlobalProperty pc_compat_3_1[] = { 119 { "intel-iommu", "dma-drain", "off" }, 120 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 121 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 122 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 123 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 124 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 125 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 126 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 127 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 128 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 129 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 130 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 131 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 132 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 133 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 136 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 137 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 138 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 139 }; 140 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 141 142 GlobalProperty pc_compat_3_0[] = { 143 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 144 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 145 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 146 }; 147 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 148 149 GlobalProperty pc_compat_2_12[] = { 150 { TYPE_X86_CPU, "legacy-cache", "on" }, 151 { TYPE_X86_CPU, "topoext", "off" }, 152 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 153 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 154 }; 155 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 156 157 GlobalProperty pc_compat_2_11[] = { 158 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 159 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 160 }; 161 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 162 163 GlobalProperty pc_compat_2_10[] = { 164 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 165 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 166 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 167 }; 168 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 169 170 GlobalProperty pc_compat_2_9[] = { 171 { "mch", "extended-tseg-mbytes", "0" }, 172 }; 173 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 174 175 GlobalProperty pc_compat_2_8[] = { 176 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 177 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 178 { "ICH9-LPC", "x-smi-broadcast", "off" }, 179 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 180 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 181 }; 182 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 183 184 GlobalProperty pc_compat_2_7[] = { 185 { TYPE_X86_CPU, "l3-cache", "off" }, 186 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 187 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 188 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 189 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 190 { "isa-pcspk", "migrate", "off" }, 191 }; 192 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 193 194 GlobalProperty pc_compat_2_6[] = { 195 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 196 { "vmxnet3", "romfile", "" }, 197 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 198 { "apic-common", "legacy-instance-id", "on", } 199 }; 200 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 201 202 GlobalProperty pc_compat_2_5[] = {}; 203 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 204 205 GlobalProperty pc_compat_2_4[] = { 206 PC_CPU_MODEL_IDS("2.4.0") 207 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 208 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 209 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 210 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 211 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 212 { TYPE_X86_CPU, "check", "off" }, 213 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 214 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 215 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 216 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 217 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 218 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 219 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 220 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 221 }; 222 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 223 224 GlobalProperty pc_compat_2_3[] = { 225 PC_CPU_MODEL_IDS("2.3.0") 226 { TYPE_X86_CPU, "arat", "off" }, 227 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 228 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 229 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 230 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 231 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 232 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 233 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 234 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 235 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 236 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 246 }; 247 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 248 249 GlobalProperty pc_compat_2_2[] = { 250 PC_CPU_MODEL_IDS("2.2.0") 251 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 252 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 266 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 267 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 268 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 269 }; 270 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 271 272 GlobalProperty pc_compat_2_1[] = { 273 PC_CPU_MODEL_IDS("2.1.0") 274 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 275 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 276 }; 277 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 278 279 GlobalProperty pc_compat_2_0[] = { 280 PC_CPU_MODEL_IDS("2.0.0") 281 { "virtio-scsi-pci", "any_layout", "off" }, 282 { "PIIX4_PM", "memory-hotplug-support", "off" }, 283 { "apic", "version", "0x11" }, 284 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 285 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 286 { "pci-serial", "prog_if", "0" }, 287 { "pci-serial-2x", "prog_if", "0" }, 288 { "pci-serial-4x", "prog_if", "0" }, 289 { "virtio-net-pci", "guest_announce", "off" }, 290 { "ICH9-LPC", "memory-hotplug-support", "off" }, 291 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 292 { "ioh3420", COMPAT_PROP_PCP, "off" }, 293 }; 294 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 295 296 GlobalProperty pc_compat_1_7[] = { 297 PC_CPU_MODEL_IDS("1.7.0") 298 { TYPE_USB_DEVICE, "msos-desc", "no" }, 299 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 300 { "hpet", HPET_INTCAP, "4" }, 301 }; 302 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 303 304 GlobalProperty pc_compat_1_6[] = { 305 PC_CPU_MODEL_IDS("1.6.0") 306 { "e1000", "mitigation", "off" }, 307 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 308 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 309 { "i440FX-pcihost", "short_root_bus", "1" }, 310 { "q35-pcihost", "short_root_bus", "1" }, 311 }; 312 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 313 314 GlobalProperty pc_compat_1_5[] = { 315 PC_CPU_MODEL_IDS("1.5.0") 316 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 317 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 318 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 319 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 320 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 321 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 322 { "virtio-net-pci", "any_layout", "off" }, 323 { TYPE_X86_CPU, "pmu", "on" }, 324 { "i440FX-pcihost", "short_root_bus", "0" }, 325 { "q35-pcihost", "short_root_bus", "0" }, 326 }; 327 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 328 329 GlobalProperty pc_compat_1_4[] = { 330 PC_CPU_MODEL_IDS("1.4.0") 331 { "scsi-hd", "discard_granularity", "0" }, 332 { "scsi-cd", "discard_granularity", "0" }, 333 { "scsi-disk", "discard_granularity", "0" }, 334 { "ide-hd", "discard_granularity", "0" }, 335 { "ide-cd", "discard_granularity", "0" }, 336 { "ide-drive", "discard_granularity", "0" }, 337 { "virtio-blk-pci", "discard_granularity", "0" }, 338 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 339 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 340 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 341 { "e1000", "romfile", "pxe-e1000.rom" }, 342 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 343 { "pcnet", "romfile", "pxe-pcnet.rom" }, 344 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 345 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 346 { "486-" TYPE_X86_CPU, "model", "0" }, 347 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 348 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 349 }; 350 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 351 352 void gsi_handler(void *opaque, int n, int level) 353 { 354 GSIState *s = opaque; 355 356 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 357 if (n < ISA_NUM_IRQS) { 358 qemu_set_irq(s->i8259_irq[n], level); 359 } 360 qemu_set_irq(s->ioapic_irq[n], level); 361 } 362 363 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 364 unsigned size) 365 { 366 } 367 368 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 369 { 370 return 0xffffffffffffffffULL; 371 } 372 373 /* MSDOS compatibility mode FPU exception support */ 374 static qemu_irq ferr_irq; 375 376 void pc_register_ferr_irq(qemu_irq irq) 377 { 378 ferr_irq = irq; 379 } 380 381 /* XXX: add IGNNE support */ 382 void cpu_set_ferr(CPUX86State *s) 383 { 384 qemu_irq_raise(ferr_irq); 385 } 386 387 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 388 unsigned size) 389 { 390 qemu_irq_lower(ferr_irq); 391 } 392 393 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 394 { 395 return 0xffffffffffffffffULL; 396 } 397 398 /* TSC handling */ 399 uint64_t cpu_get_tsc(CPUX86State *env) 400 { 401 return cpu_get_ticks(); 402 } 403 404 /* IRQ handling */ 405 int cpu_get_pic_interrupt(CPUX86State *env) 406 { 407 X86CPU *cpu = x86_env_get_cpu(env); 408 int intno; 409 410 if (!kvm_irqchip_in_kernel()) { 411 intno = apic_get_interrupt(cpu->apic_state); 412 if (intno >= 0) { 413 return intno; 414 } 415 /* read the irq from the PIC */ 416 if (!apic_accept_pic_intr(cpu->apic_state)) { 417 return -1; 418 } 419 } 420 421 intno = pic_read_irq(isa_pic); 422 return intno; 423 } 424 425 static void pic_irq_request(void *opaque, int irq, int level) 426 { 427 CPUState *cs = first_cpu; 428 X86CPU *cpu = X86_CPU(cs); 429 430 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 431 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 432 CPU_FOREACH(cs) { 433 cpu = X86_CPU(cs); 434 if (apic_accept_pic_intr(cpu->apic_state)) { 435 apic_deliver_pic_intr(cpu->apic_state, level); 436 } 437 } 438 } else { 439 if (level) { 440 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 441 } else { 442 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 443 } 444 } 445 } 446 447 /* PC cmos mappings */ 448 449 #define REG_EQUIPMENT_BYTE 0x14 450 451 int cmos_get_fd_drive_type(FloppyDriveType fd0) 452 { 453 int val; 454 455 switch (fd0) { 456 case FLOPPY_DRIVE_TYPE_144: 457 /* 1.44 Mb 3"5 drive */ 458 val = 4; 459 break; 460 case FLOPPY_DRIVE_TYPE_288: 461 /* 2.88 Mb 3"5 drive */ 462 val = 5; 463 break; 464 case FLOPPY_DRIVE_TYPE_120: 465 /* 1.2 Mb 5"5 drive */ 466 val = 2; 467 break; 468 case FLOPPY_DRIVE_TYPE_NONE: 469 default: 470 val = 0; 471 break; 472 } 473 return val; 474 } 475 476 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 477 int16_t cylinders, int8_t heads, int8_t sectors) 478 { 479 rtc_set_memory(s, type_ofs, 47); 480 rtc_set_memory(s, info_ofs, cylinders); 481 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 482 rtc_set_memory(s, info_ofs + 2, heads); 483 rtc_set_memory(s, info_ofs + 3, 0xff); 484 rtc_set_memory(s, info_ofs + 4, 0xff); 485 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 486 rtc_set_memory(s, info_ofs + 6, cylinders); 487 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 488 rtc_set_memory(s, info_ofs + 8, sectors); 489 } 490 491 /* convert boot_device letter to something recognizable by the bios */ 492 static int boot_device2nibble(char boot_device) 493 { 494 switch(boot_device) { 495 case 'a': 496 case 'b': 497 return 0x01; /* floppy boot */ 498 case 'c': 499 return 0x02; /* hard drive boot */ 500 case 'd': 501 return 0x03; /* CD-ROM boot */ 502 case 'n': 503 return 0x04; /* Network boot */ 504 } 505 return 0; 506 } 507 508 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 509 { 510 #define PC_MAX_BOOT_DEVICES 3 511 int nbds, bds[3] = { 0, }; 512 int i; 513 514 nbds = strlen(boot_device); 515 if (nbds > PC_MAX_BOOT_DEVICES) { 516 error_setg(errp, "Too many boot devices for PC"); 517 return; 518 } 519 for (i = 0; i < nbds; i++) { 520 bds[i] = boot_device2nibble(boot_device[i]); 521 if (bds[i] == 0) { 522 error_setg(errp, "Invalid boot device for PC: '%c'", 523 boot_device[i]); 524 return; 525 } 526 } 527 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 528 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 529 } 530 531 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 532 { 533 set_boot_dev(opaque, boot_device, errp); 534 } 535 536 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 537 { 538 int val, nb, i; 539 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 540 FLOPPY_DRIVE_TYPE_NONE }; 541 542 /* floppy type */ 543 if (floppy) { 544 for (i = 0; i < 2; i++) { 545 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 546 } 547 } 548 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 549 cmos_get_fd_drive_type(fd_type[1]); 550 rtc_set_memory(rtc_state, 0x10, val); 551 552 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 553 nb = 0; 554 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 555 nb++; 556 } 557 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 558 nb++; 559 } 560 switch (nb) { 561 case 0: 562 break; 563 case 1: 564 val |= 0x01; /* 1 drive, ready for boot */ 565 break; 566 case 2: 567 val |= 0x41; /* 2 drives, ready for boot */ 568 break; 569 } 570 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 571 } 572 573 typedef struct pc_cmos_init_late_arg { 574 ISADevice *rtc_state; 575 BusState *idebus[2]; 576 } pc_cmos_init_late_arg; 577 578 typedef struct check_fdc_state { 579 ISADevice *floppy; 580 bool multiple; 581 } CheckFdcState; 582 583 static int check_fdc(Object *obj, void *opaque) 584 { 585 CheckFdcState *state = opaque; 586 Object *fdc; 587 uint32_t iobase; 588 Error *local_err = NULL; 589 590 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 591 if (!fdc) { 592 return 0; 593 } 594 595 iobase = object_property_get_uint(obj, "iobase", &local_err); 596 if (local_err || iobase != 0x3f0) { 597 error_free(local_err); 598 return 0; 599 } 600 601 if (state->floppy) { 602 state->multiple = true; 603 } else { 604 state->floppy = ISA_DEVICE(obj); 605 } 606 return 0; 607 } 608 609 static const char * const fdc_container_path[] = { 610 "/unattached", "/peripheral", "/peripheral-anon" 611 }; 612 613 /* 614 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 615 * and ACPI objects. 616 */ 617 ISADevice *pc_find_fdc0(void) 618 { 619 int i; 620 Object *container; 621 CheckFdcState state = { 0 }; 622 623 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 624 container = container_get(qdev_get_machine(), fdc_container_path[i]); 625 object_child_foreach(container, check_fdc, &state); 626 } 627 628 if (state.multiple) { 629 warn_report("multiple floppy disk controllers with " 630 "iobase=0x3f0 have been found"); 631 error_printf("the one being picked for CMOS setup might not reflect " 632 "your intent"); 633 } 634 635 return state.floppy; 636 } 637 638 static void pc_cmos_init_late(void *opaque) 639 { 640 pc_cmos_init_late_arg *arg = opaque; 641 ISADevice *s = arg->rtc_state; 642 int16_t cylinders; 643 int8_t heads, sectors; 644 int val; 645 int i, trans; 646 647 val = 0; 648 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 649 &cylinders, &heads, §ors) >= 0) { 650 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 651 val |= 0xf0; 652 } 653 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 654 &cylinders, &heads, §ors) >= 0) { 655 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 656 val |= 0x0f; 657 } 658 rtc_set_memory(s, 0x12, val); 659 660 val = 0; 661 for (i = 0; i < 4; i++) { 662 /* NOTE: ide_get_geometry() returns the physical 663 geometry. It is always such that: 1 <= sects <= 63, 1 664 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 665 geometry can be different if a translation is done. */ 666 if (arg->idebus[i / 2] && 667 ide_get_geometry(arg->idebus[i / 2], i % 2, 668 &cylinders, &heads, §ors) >= 0) { 669 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 670 assert((trans & ~3) == 0); 671 val |= trans << (i * 2); 672 } 673 } 674 rtc_set_memory(s, 0x39, val); 675 676 pc_cmos_init_floppy(s, pc_find_fdc0()); 677 678 qemu_unregister_reset(pc_cmos_init_late, opaque); 679 } 680 681 void pc_cmos_init(PCMachineState *pcms, 682 BusState *idebus0, BusState *idebus1, 683 ISADevice *s) 684 { 685 int val; 686 static pc_cmos_init_late_arg arg; 687 688 /* various important CMOS locations needed by PC/Bochs bios */ 689 690 /* memory size */ 691 /* base memory (first MiB) */ 692 val = MIN(pcms->below_4g_mem_size / KiB, 640); 693 rtc_set_memory(s, 0x15, val); 694 rtc_set_memory(s, 0x16, val >> 8); 695 /* extended memory (next 64MiB) */ 696 if (pcms->below_4g_mem_size > 1 * MiB) { 697 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 698 } else { 699 val = 0; 700 } 701 if (val > 65535) 702 val = 65535; 703 rtc_set_memory(s, 0x17, val); 704 rtc_set_memory(s, 0x18, val >> 8); 705 rtc_set_memory(s, 0x30, val); 706 rtc_set_memory(s, 0x31, val >> 8); 707 /* memory between 16MiB and 4GiB */ 708 if (pcms->below_4g_mem_size > 16 * MiB) { 709 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 710 } else { 711 val = 0; 712 } 713 if (val > 65535) 714 val = 65535; 715 rtc_set_memory(s, 0x34, val); 716 rtc_set_memory(s, 0x35, val >> 8); 717 /* memory above 4GiB */ 718 val = pcms->above_4g_mem_size / 65536; 719 rtc_set_memory(s, 0x5b, val); 720 rtc_set_memory(s, 0x5c, val >> 8); 721 rtc_set_memory(s, 0x5d, val >> 16); 722 723 object_property_add_link(OBJECT(pcms), "rtc_state", 724 TYPE_ISA_DEVICE, 725 (Object **)&pcms->rtc, 726 object_property_allow_set_link, 727 OBJ_PROP_LINK_STRONG, &error_abort); 728 object_property_set_link(OBJECT(pcms), OBJECT(s), 729 "rtc_state", &error_abort); 730 731 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 732 733 val = 0; 734 val |= 0x02; /* FPU is there */ 735 val |= 0x04; /* PS/2 mouse installed */ 736 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 737 738 /* hard drives and FDC */ 739 arg.rtc_state = s; 740 arg.idebus[0] = idebus0; 741 arg.idebus[1] = idebus1; 742 qemu_register_reset(pc_cmos_init_late, &arg); 743 } 744 745 #define TYPE_PORT92 "port92" 746 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 747 748 /* port 92 stuff: could be split off */ 749 typedef struct Port92State { 750 ISADevice parent_obj; 751 752 MemoryRegion io; 753 uint8_t outport; 754 qemu_irq a20_out; 755 } Port92State; 756 757 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 758 unsigned size) 759 { 760 Port92State *s = opaque; 761 int oldval = s->outport; 762 763 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 764 s->outport = val; 765 qemu_set_irq(s->a20_out, (val >> 1) & 1); 766 if ((val & 1) && !(oldval & 1)) { 767 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 768 } 769 } 770 771 static uint64_t port92_read(void *opaque, hwaddr addr, 772 unsigned size) 773 { 774 Port92State *s = opaque; 775 uint32_t ret; 776 777 ret = s->outport; 778 DPRINTF("port92: read 0x%02x\n", ret); 779 return ret; 780 } 781 782 static void port92_init(ISADevice *dev, qemu_irq a20_out) 783 { 784 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 785 } 786 787 static const VMStateDescription vmstate_port92_isa = { 788 .name = "port92", 789 .version_id = 1, 790 .minimum_version_id = 1, 791 .fields = (VMStateField[]) { 792 VMSTATE_UINT8(outport, Port92State), 793 VMSTATE_END_OF_LIST() 794 } 795 }; 796 797 static void port92_reset(DeviceState *d) 798 { 799 Port92State *s = PORT92(d); 800 801 s->outport &= ~1; 802 } 803 804 static const MemoryRegionOps port92_ops = { 805 .read = port92_read, 806 .write = port92_write, 807 .impl = { 808 .min_access_size = 1, 809 .max_access_size = 1, 810 }, 811 .endianness = DEVICE_LITTLE_ENDIAN, 812 }; 813 814 static void port92_initfn(Object *obj) 815 { 816 Port92State *s = PORT92(obj); 817 818 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 819 820 s->outport = 0; 821 822 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 823 } 824 825 static void port92_realizefn(DeviceState *dev, Error **errp) 826 { 827 ISADevice *isadev = ISA_DEVICE(dev); 828 Port92State *s = PORT92(dev); 829 830 isa_register_ioport(isadev, &s->io, 0x92); 831 } 832 833 static void port92_class_initfn(ObjectClass *klass, void *data) 834 { 835 DeviceClass *dc = DEVICE_CLASS(klass); 836 837 dc->realize = port92_realizefn; 838 dc->reset = port92_reset; 839 dc->vmsd = &vmstate_port92_isa; 840 /* 841 * Reason: unlike ordinary ISA devices, this one needs additional 842 * wiring: its A20 output line needs to be wired up by 843 * port92_init(). 844 */ 845 dc->user_creatable = false; 846 } 847 848 static const TypeInfo port92_info = { 849 .name = TYPE_PORT92, 850 .parent = TYPE_ISA_DEVICE, 851 .instance_size = sizeof(Port92State), 852 .instance_init = port92_initfn, 853 .class_init = port92_class_initfn, 854 }; 855 856 static void port92_register_types(void) 857 { 858 type_register_static(&port92_info); 859 } 860 861 type_init(port92_register_types) 862 863 static void handle_a20_line_change(void *opaque, int irq, int level) 864 { 865 X86CPU *cpu = opaque; 866 867 /* XXX: send to all CPUs ? */ 868 /* XXX: add logic to handle multiple A20 line sources */ 869 x86_cpu_set_a20(cpu, level); 870 } 871 872 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 873 { 874 int index = le32_to_cpu(e820_reserve.count); 875 struct e820_entry *entry; 876 877 if (type != E820_RAM) { 878 /* old FW_CFG_E820_TABLE entry -- reservations only */ 879 if (index >= E820_NR_ENTRIES) { 880 return -EBUSY; 881 } 882 entry = &e820_reserve.entry[index++]; 883 884 entry->address = cpu_to_le64(address); 885 entry->length = cpu_to_le64(length); 886 entry->type = cpu_to_le32(type); 887 888 e820_reserve.count = cpu_to_le32(index); 889 } 890 891 /* new "etc/e820" file -- include ram too */ 892 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 893 e820_table[e820_entries].address = cpu_to_le64(address); 894 e820_table[e820_entries].length = cpu_to_le64(length); 895 e820_table[e820_entries].type = cpu_to_le32(type); 896 e820_entries++; 897 898 return e820_entries; 899 } 900 901 int e820_get_num_entries(void) 902 { 903 return e820_entries; 904 } 905 906 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 907 { 908 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 909 *address = le64_to_cpu(e820_table[idx].address); 910 *length = le64_to_cpu(e820_table[idx].length); 911 return true; 912 } 913 return false; 914 } 915 916 /* Enables contiguous-apic-ID mode, for compatibility */ 917 static bool compat_apic_id_mode; 918 919 void enable_compat_apic_id_mode(void) 920 { 921 compat_apic_id_mode = true; 922 } 923 924 /* Calculates initial APIC ID for a specific CPU index 925 * 926 * Currently we need to be able to calculate the APIC ID from the CPU index 927 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 928 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 929 * all CPUs up to max_cpus. 930 */ 931 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 932 { 933 uint32_t correct_id; 934 static bool warned; 935 936 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 937 if (compat_apic_id_mode) { 938 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 939 error_report("APIC IDs set in compatibility mode, " 940 "CPU topology won't match the configuration"); 941 warned = true; 942 } 943 return cpu_index; 944 } else { 945 return correct_id; 946 } 947 } 948 949 static void pc_build_smbios(PCMachineState *pcms) 950 { 951 uint8_t *smbios_tables, *smbios_anchor; 952 size_t smbios_tables_len, smbios_anchor_len; 953 struct smbios_phys_mem_area *mem_array; 954 unsigned i, array_count; 955 MachineState *ms = MACHINE(pcms); 956 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 957 958 /* tell smbios about cpuid version and features */ 959 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 960 961 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 962 if (smbios_tables) { 963 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 964 smbios_tables, smbios_tables_len); 965 } 966 967 /* build the array of physical mem area from e820 table */ 968 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 969 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 970 uint64_t addr, len; 971 972 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 973 mem_array[array_count].address = addr; 974 mem_array[array_count].length = len; 975 array_count++; 976 } 977 } 978 smbios_get_tables(mem_array, array_count, 979 &smbios_tables, &smbios_tables_len, 980 &smbios_anchor, &smbios_anchor_len); 981 g_free(mem_array); 982 983 if (smbios_anchor) { 984 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 985 smbios_tables, smbios_tables_len); 986 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 987 smbios_anchor, smbios_anchor_len); 988 } 989 } 990 991 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 992 { 993 FWCfgState *fw_cfg; 994 uint64_t *numa_fw_cfg; 995 int i; 996 const CPUArchIdList *cpus; 997 MachineClass *mc = MACHINE_GET_CLASS(pcms); 998 999 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 1000 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1001 1002 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1003 * 1004 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1005 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1006 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1007 * for CPU hotplug also uses APIC ID and not "CPU index". 1008 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1009 * but the "limit to the APIC ID values SeaBIOS may see". 1010 * 1011 * So for compatibility reasons with old BIOSes we are stuck with 1012 * "etc/max-cpus" actually being apic_id_limit 1013 */ 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1015 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1016 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1017 acpi_tables, acpi_tables_len); 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1019 1020 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1021 &e820_reserve, sizeof(e820_reserve)); 1022 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1023 sizeof(struct e820_entry) * e820_entries); 1024 1025 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1026 /* allocate memory for the NUMA channel: one (64bit) word for the number 1027 * of nodes, one word for each VCPU->node and one word for each node to 1028 * hold the amount of memory. 1029 */ 1030 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1031 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1032 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1033 for (i = 0; i < cpus->len; i++) { 1034 unsigned int apic_id = cpus->cpus[i].arch_id; 1035 assert(apic_id < pcms->apic_id_limit); 1036 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1037 } 1038 for (i = 0; i < nb_numa_nodes; i++) { 1039 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1040 cpu_to_le64(numa_info[i].node_mem); 1041 } 1042 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1043 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1044 sizeof(*numa_fw_cfg)); 1045 1046 return fw_cfg; 1047 } 1048 1049 static long get_file_size(FILE *f) 1050 { 1051 long where, size; 1052 1053 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1054 1055 where = ftell(f); 1056 fseek(f, 0, SEEK_END); 1057 size = ftell(f); 1058 fseek(f, where, SEEK_SET); 1059 1060 return size; 1061 } 1062 1063 struct setup_data { 1064 uint64_t next; 1065 uint32_t type; 1066 uint32_t len; 1067 uint8_t data[0]; 1068 } __attribute__((packed)); 1069 1070 1071 /* 1072 * The entry point into the kernel for PVH boot is different from 1073 * the native entry point. The PVH entry is defined by the x86/HVM 1074 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 1075 * 1076 * This function is passed to load_elf() when it is called from 1077 * load_elfboot() which then additionally checks for an ELF Note of 1078 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 1079 * parse the PVH entry address from the ELF Note. 1080 * 1081 * Due to trickery in elf_opts.h, load_elf() is actually available as 1082 * load_elf32() or load_elf64() and this routine needs to be able 1083 * to deal with being called as 32 or 64 bit. 1084 * 1085 * The address of the PVH entry point is saved to the 'pvh_start_addr' 1086 * global variable. (although the entry point is 32-bit, the kernel 1087 * binary can be either 32-bit or 64-bit). 1088 */ 1089 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 1090 { 1091 size_t *elf_note_data_addr; 1092 1093 /* Check if ELF Note header passed in is valid */ 1094 if (arg1 == NULL) { 1095 return 0; 1096 } 1097 1098 if (is64) { 1099 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 1100 uint64_t nhdr_size64 = sizeof(struct elf64_note); 1101 uint64_t phdr_align = *(uint64_t *)arg2; 1102 uint64_t nhdr_namesz = nhdr64->n_namesz; 1103 1104 elf_note_data_addr = 1105 ((void *)nhdr64) + nhdr_size64 + 1106 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1107 } else { 1108 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 1109 uint32_t nhdr_size32 = sizeof(struct elf32_note); 1110 uint32_t phdr_align = *(uint32_t *)arg2; 1111 uint32_t nhdr_namesz = nhdr32->n_namesz; 1112 1113 elf_note_data_addr = 1114 ((void *)nhdr32) + nhdr_size32 + 1115 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1116 } 1117 1118 pvh_start_addr = *elf_note_data_addr; 1119 1120 return pvh_start_addr; 1121 } 1122 1123 static bool load_elfboot(const char *kernel_filename, 1124 int kernel_file_size, 1125 uint8_t *header, 1126 size_t pvh_xen_start_addr, 1127 FWCfgState *fw_cfg) 1128 { 1129 uint32_t flags = 0; 1130 uint32_t mh_load_addr = 0; 1131 uint32_t elf_kernel_size = 0; 1132 uint64_t elf_entry; 1133 uint64_t elf_low, elf_high; 1134 int kernel_size; 1135 1136 if (ldl_p(header) != 0x464c457f) { 1137 return false; /* no elfboot */ 1138 } 1139 1140 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 1141 flags = elf_is64 ? 1142 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 1143 1144 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 1145 error_report("elfboot unsupported flags = %x", flags); 1146 exit(1); 1147 } 1148 1149 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 1150 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1151 NULL, &elf_note_type, &elf_entry, 1152 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1153 0, 0); 1154 1155 if (kernel_size < 0) { 1156 error_report("Error while loading elf kernel"); 1157 exit(1); 1158 } 1159 mh_load_addr = elf_low; 1160 elf_kernel_size = elf_high - elf_low; 1161 1162 if (pvh_start_addr == 0) { 1163 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1164 exit(1); 1165 } 1166 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1167 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1168 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1169 1170 return true; 1171 } 1172 1173 static void load_linux(PCMachineState *pcms, 1174 FWCfgState *fw_cfg) 1175 { 1176 uint16_t protocol; 1177 int setup_size, kernel_size, cmdline_size; 1178 int dtb_size, setup_data_offset; 1179 uint32_t initrd_max; 1180 uint8_t header[8192], *setup, *kernel; 1181 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1182 FILE *f; 1183 char *vmode; 1184 MachineState *machine = MACHINE(pcms); 1185 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1186 struct setup_data *setup_data; 1187 const char *kernel_filename = machine->kernel_filename; 1188 const char *initrd_filename = machine->initrd_filename; 1189 const char *dtb_filename = machine->dtb; 1190 const char *kernel_cmdline = machine->kernel_cmdline; 1191 1192 /* Align to 16 bytes as a paranoia measure */ 1193 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1194 1195 /* load the kernel header */ 1196 f = fopen(kernel_filename, "rb"); 1197 if (!f || !(kernel_size = get_file_size(f)) || 1198 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1199 MIN(ARRAY_SIZE(header), kernel_size)) { 1200 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1201 kernel_filename, strerror(errno)); 1202 exit(1); 1203 } 1204 1205 /* kernel protocol version */ 1206 #if 0 1207 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1208 #endif 1209 if (ldl_p(header+0x202) == 0x53726448) { 1210 protocol = lduw_p(header+0x206); 1211 } else { 1212 /* 1213 * Check if the file is an uncompressed kernel file (ELF) and load it, 1214 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1215 * If load_elfboot() is successful, populate the fw_cfg info. 1216 */ 1217 if (pcmc->pvh_enabled && 1218 load_elfboot(kernel_filename, kernel_size, 1219 header, pvh_start_addr, fw_cfg)) { 1220 fclose(f); 1221 1222 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1223 strlen(kernel_cmdline) + 1); 1224 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1225 1226 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1227 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1228 header, sizeof(header)); 1229 1230 /* load initrd */ 1231 if (initrd_filename) { 1232 gsize initrd_size; 1233 gchar *initrd_data; 1234 GError *gerr = NULL; 1235 1236 if (!g_file_get_contents(initrd_filename, &initrd_data, 1237 &initrd_size, &gerr)) { 1238 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1239 initrd_filename, gerr->message); 1240 exit(1); 1241 } 1242 1243 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1244 if (initrd_size >= initrd_max) { 1245 fprintf(stderr, "qemu: initrd is too large, cannot support." 1246 "(max: %"PRIu32", need %"PRId64")\n", 1247 initrd_max, (uint64_t)initrd_size); 1248 exit(1); 1249 } 1250 1251 initrd_addr = (initrd_max - initrd_size) & ~4095; 1252 1253 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1254 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1255 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1256 initrd_size); 1257 } 1258 1259 option_rom[nb_option_roms].bootindex = 0; 1260 option_rom[nb_option_roms].name = "pvh.bin"; 1261 nb_option_roms++; 1262 1263 return; 1264 } 1265 /* This looks like a multiboot kernel. If it is, let's stop 1266 treating it like a Linux kernel. */ 1267 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1268 kernel_cmdline, kernel_size, header)) { 1269 return; 1270 } 1271 protocol = 0; 1272 } 1273 1274 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1275 /* Low kernel */ 1276 real_addr = 0x90000; 1277 cmdline_addr = 0x9a000 - cmdline_size; 1278 prot_addr = 0x10000; 1279 } else if (protocol < 0x202) { 1280 /* High but ancient kernel */ 1281 real_addr = 0x90000; 1282 cmdline_addr = 0x9a000 - cmdline_size; 1283 prot_addr = 0x100000; 1284 } else { 1285 /* High and recent kernel */ 1286 real_addr = 0x10000; 1287 cmdline_addr = 0x20000; 1288 prot_addr = 0x100000; 1289 } 1290 1291 #if 0 1292 fprintf(stderr, 1293 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1294 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1295 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1296 real_addr, 1297 cmdline_addr, 1298 prot_addr); 1299 #endif 1300 1301 /* highest address for loading the initrd */ 1302 if (protocol >= 0x20c && 1303 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1304 /* 1305 * Linux has supported initrd up to 4 GB for a very long time (2007, 1306 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1307 * though it only sets initrd_max to 2 GB to "work around bootloader 1308 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1309 * has supported this. 1310 * 1311 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1312 * be loaded into any address. 1313 * 1314 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1315 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1316 * field). 1317 * 1318 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1319 */ 1320 initrd_max = UINT32_MAX; 1321 } else if (protocol >= 0x203) { 1322 initrd_max = ldl_p(header+0x22c); 1323 } else { 1324 initrd_max = 0x37ffffff; 1325 } 1326 1327 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1328 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1329 } 1330 1331 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1332 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1333 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1334 1335 if (protocol >= 0x202) { 1336 stl_p(header+0x228, cmdline_addr); 1337 } else { 1338 stw_p(header+0x20, 0xA33F); 1339 stw_p(header+0x22, cmdline_addr-real_addr); 1340 } 1341 1342 /* handle vga= parameter */ 1343 vmode = strstr(kernel_cmdline, "vga="); 1344 if (vmode) { 1345 unsigned int video_mode; 1346 /* skip "vga=" */ 1347 vmode += 4; 1348 if (!strncmp(vmode, "normal", 6)) { 1349 video_mode = 0xffff; 1350 } else if (!strncmp(vmode, "ext", 3)) { 1351 video_mode = 0xfffe; 1352 } else if (!strncmp(vmode, "ask", 3)) { 1353 video_mode = 0xfffd; 1354 } else { 1355 video_mode = strtol(vmode, NULL, 0); 1356 } 1357 stw_p(header+0x1fa, video_mode); 1358 } 1359 1360 /* loader type */ 1361 /* High nybble = B reserved for QEMU; low nybble is revision number. 1362 If this code is substantially changed, you may want to consider 1363 incrementing the revision. */ 1364 if (protocol >= 0x200) { 1365 header[0x210] = 0xB0; 1366 } 1367 /* heap */ 1368 if (protocol >= 0x201) { 1369 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1370 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1371 } 1372 1373 /* load initrd */ 1374 if (initrd_filename) { 1375 gsize initrd_size; 1376 gchar *initrd_data; 1377 GError *gerr = NULL; 1378 1379 if (protocol < 0x200) { 1380 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1381 exit(1); 1382 } 1383 1384 if (!g_file_get_contents(initrd_filename, &initrd_data, 1385 &initrd_size, &gerr)) { 1386 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1387 initrd_filename, gerr->message); 1388 exit(1); 1389 } 1390 if (initrd_size >= initrd_max) { 1391 fprintf(stderr, "qemu: initrd is too large, cannot support." 1392 "(max: %"PRIu32", need %"PRId64")\n", 1393 initrd_max, (uint64_t)initrd_size); 1394 exit(1); 1395 } 1396 1397 initrd_addr = (initrd_max-initrd_size) & ~4095; 1398 1399 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1400 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1401 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1402 1403 stl_p(header+0x218, initrd_addr); 1404 stl_p(header+0x21c, initrd_size); 1405 } 1406 1407 /* load kernel and setup */ 1408 setup_size = header[0x1f1]; 1409 if (setup_size == 0) { 1410 setup_size = 4; 1411 } 1412 setup_size = (setup_size+1)*512; 1413 if (setup_size > kernel_size) { 1414 fprintf(stderr, "qemu: invalid kernel header\n"); 1415 exit(1); 1416 } 1417 kernel_size -= setup_size; 1418 1419 setup = g_malloc(setup_size); 1420 kernel = g_malloc(kernel_size); 1421 fseek(f, 0, SEEK_SET); 1422 if (fread(setup, 1, setup_size, f) != setup_size) { 1423 fprintf(stderr, "fread() failed\n"); 1424 exit(1); 1425 } 1426 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1427 fprintf(stderr, "fread() failed\n"); 1428 exit(1); 1429 } 1430 fclose(f); 1431 1432 /* append dtb to kernel */ 1433 if (dtb_filename) { 1434 if (protocol < 0x209) { 1435 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1436 exit(1); 1437 } 1438 1439 dtb_size = get_image_size(dtb_filename); 1440 if (dtb_size <= 0) { 1441 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1442 dtb_filename, strerror(errno)); 1443 exit(1); 1444 } 1445 1446 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1447 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1448 kernel = g_realloc(kernel, kernel_size); 1449 1450 stq_p(header+0x250, prot_addr + setup_data_offset); 1451 1452 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1453 setup_data->next = 0; 1454 setup_data->type = cpu_to_le32(SETUP_DTB); 1455 setup_data->len = cpu_to_le32(dtb_size); 1456 1457 load_image_size(dtb_filename, setup_data->data, dtb_size); 1458 } 1459 1460 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1461 1462 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1463 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1464 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1465 1466 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1467 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1468 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1469 1470 option_rom[nb_option_roms].bootindex = 0; 1471 option_rom[nb_option_roms].name = "linuxboot.bin"; 1472 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1473 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1474 } 1475 nb_option_roms++; 1476 } 1477 1478 #define NE2000_NB_MAX 6 1479 1480 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1481 0x280, 0x380 }; 1482 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1483 1484 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1485 { 1486 static int nb_ne2k = 0; 1487 1488 if (nb_ne2k == NE2000_NB_MAX) 1489 return; 1490 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1491 ne2000_irq[nb_ne2k], nd); 1492 nb_ne2k++; 1493 } 1494 1495 DeviceState *cpu_get_current_apic(void) 1496 { 1497 if (current_cpu) { 1498 X86CPU *cpu = X86_CPU(current_cpu); 1499 return cpu->apic_state; 1500 } else { 1501 return NULL; 1502 } 1503 } 1504 1505 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1506 { 1507 X86CPU *cpu = opaque; 1508 1509 if (level) { 1510 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1511 } 1512 } 1513 1514 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) 1515 { 1516 Object *cpu = NULL; 1517 Error *local_err = NULL; 1518 1519 cpu = object_new(typename); 1520 1521 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1522 object_property_set_bool(cpu, true, "realized", &local_err); 1523 1524 object_unref(cpu); 1525 error_propagate(errp, local_err); 1526 } 1527 1528 void pc_hot_add_cpu(const int64_t id, Error **errp) 1529 { 1530 MachineState *ms = MACHINE(qdev_get_machine()); 1531 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1532 Error *local_err = NULL; 1533 1534 if (id < 0) { 1535 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1536 return; 1537 } 1538 1539 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1540 error_setg(errp, "Unable to add CPU: %" PRIi64 1541 ", resulting APIC ID (%" PRIi64 ") is too large", 1542 id, apic_id); 1543 return; 1544 } 1545 1546 pc_new_cpu(ms->cpu_type, apic_id, &local_err); 1547 if (local_err) { 1548 error_propagate(errp, local_err); 1549 return; 1550 } 1551 } 1552 1553 void pc_cpus_init(PCMachineState *pcms) 1554 { 1555 int i; 1556 const CPUArchIdList *possible_cpus; 1557 MachineState *ms = MACHINE(pcms); 1558 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1559 1560 /* Calculates the limit to CPU APIC ID values 1561 * 1562 * Limit for the APIC ID value, so that all 1563 * CPU APIC IDs are < pcms->apic_id_limit. 1564 * 1565 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1566 */ 1567 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1568 possible_cpus = mc->possible_cpu_arch_ids(ms); 1569 for (i = 0; i < smp_cpus; i++) { 1570 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, 1571 &error_fatal); 1572 } 1573 } 1574 1575 static void pc_build_feature_control_file(PCMachineState *pcms) 1576 { 1577 MachineState *ms = MACHINE(pcms); 1578 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1579 CPUX86State *env = &cpu->env; 1580 uint32_t unused, ecx, edx; 1581 uint64_t feature_control_bits = 0; 1582 uint64_t *val; 1583 1584 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1585 if (ecx & CPUID_EXT_VMX) { 1586 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1587 } 1588 1589 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1590 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1591 (env->mcg_cap & MCG_LMCE_P)) { 1592 feature_control_bits |= FEATURE_CONTROL_LMCE; 1593 } 1594 1595 if (!feature_control_bits) { 1596 return; 1597 } 1598 1599 val = g_malloc(sizeof(*val)); 1600 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1601 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1602 } 1603 1604 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1605 { 1606 if (cpus_count > 0xff) { 1607 /* If the number of CPUs can't be represented in 8 bits, the 1608 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1609 * to make old BIOSes fail more predictably. 1610 */ 1611 rtc_set_memory(rtc, 0x5f, 0); 1612 } else { 1613 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1614 } 1615 } 1616 1617 static 1618 void pc_machine_done(Notifier *notifier, void *data) 1619 { 1620 PCMachineState *pcms = container_of(notifier, 1621 PCMachineState, machine_done); 1622 PCIBus *bus = pcms->bus; 1623 1624 /* set the number of CPUs */ 1625 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1626 1627 if (bus) { 1628 int extra_hosts = 0; 1629 1630 QLIST_FOREACH(bus, &bus->child, sibling) { 1631 /* look for expander root buses */ 1632 if (pci_bus_is_root(bus)) { 1633 extra_hosts++; 1634 } 1635 } 1636 if (extra_hosts && pcms->fw_cfg) { 1637 uint64_t *val = g_malloc(sizeof(*val)); 1638 *val = cpu_to_le64(extra_hosts); 1639 fw_cfg_add_file(pcms->fw_cfg, 1640 "etc/extra-pci-roots", val, sizeof(*val)); 1641 } 1642 } 1643 1644 acpi_setup(); 1645 if (pcms->fw_cfg) { 1646 pc_build_smbios(pcms); 1647 pc_build_feature_control_file(pcms); 1648 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1649 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1650 } 1651 1652 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1653 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1654 1655 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1656 iommu->intr_eim != ON_OFF_AUTO_ON) { 1657 error_report("current -smp configuration requires " 1658 "Extended Interrupt Mode enabled. " 1659 "You can add an IOMMU using: " 1660 "-device intel-iommu,intremap=on,eim=on"); 1661 exit(EXIT_FAILURE); 1662 } 1663 } 1664 } 1665 1666 void pc_guest_info_init(PCMachineState *pcms) 1667 { 1668 int i; 1669 1670 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1671 pcms->numa_nodes = nb_numa_nodes; 1672 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1673 sizeof *pcms->node_mem); 1674 for (i = 0; i < nb_numa_nodes; i++) { 1675 pcms->node_mem[i] = numa_info[i].node_mem; 1676 } 1677 1678 pcms->machine_done.notify = pc_machine_done; 1679 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1680 } 1681 1682 /* setup pci memory address space mapping into system address space */ 1683 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1684 MemoryRegion *pci_address_space) 1685 { 1686 /* Set to lower priority than RAM */ 1687 memory_region_add_subregion_overlap(system_memory, 0x0, 1688 pci_address_space, -1); 1689 } 1690 1691 void xen_load_linux(PCMachineState *pcms) 1692 { 1693 int i; 1694 FWCfgState *fw_cfg; 1695 1696 assert(MACHINE(pcms)->kernel_filename != NULL); 1697 1698 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1699 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1700 rom_set_fw(fw_cfg); 1701 1702 load_linux(pcms, fw_cfg); 1703 for (i = 0; i < nb_option_roms; i++) { 1704 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1705 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1706 !strcmp(option_rom[i].name, "pvh.bin") || 1707 !strcmp(option_rom[i].name, "multiboot.bin")); 1708 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1709 } 1710 pcms->fw_cfg = fw_cfg; 1711 } 1712 1713 void pc_memory_init(PCMachineState *pcms, 1714 MemoryRegion *system_memory, 1715 MemoryRegion *rom_memory, 1716 MemoryRegion **ram_memory) 1717 { 1718 int linux_boot, i; 1719 MemoryRegion *ram, *option_rom_mr; 1720 MemoryRegion *ram_below_4g, *ram_above_4g; 1721 FWCfgState *fw_cfg; 1722 MachineState *machine = MACHINE(pcms); 1723 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1724 1725 assert(machine->ram_size == pcms->below_4g_mem_size + 1726 pcms->above_4g_mem_size); 1727 1728 linux_boot = (machine->kernel_filename != NULL); 1729 1730 /* Allocate RAM. We allocate it as a single memory region and use 1731 * aliases to address portions of it, mostly for backwards compatibility 1732 * with older qemus that used qemu_ram_alloc(). 1733 */ 1734 ram = g_malloc(sizeof(*ram)); 1735 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1736 machine->ram_size); 1737 *ram_memory = ram; 1738 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1739 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1740 0, pcms->below_4g_mem_size); 1741 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1742 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1743 if (pcms->above_4g_mem_size > 0) { 1744 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1745 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1746 pcms->below_4g_mem_size, 1747 pcms->above_4g_mem_size); 1748 memory_region_add_subregion(system_memory, 0x100000000ULL, 1749 ram_above_4g); 1750 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1751 } 1752 1753 if (!pcmc->has_reserved_memory && 1754 (machine->ram_slots || 1755 (machine->maxram_size > machine->ram_size))) { 1756 MachineClass *mc = MACHINE_GET_CLASS(machine); 1757 1758 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1759 mc->name); 1760 exit(EXIT_FAILURE); 1761 } 1762 1763 /* always allocate the device memory information */ 1764 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1765 1766 /* initialize device memory address space */ 1767 if (pcmc->has_reserved_memory && 1768 (machine->ram_size < machine->maxram_size)) { 1769 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1770 1771 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1772 error_report("unsupported amount of memory slots: %"PRIu64, 1773 machine->ram_slots); 1774 exit(EXIT_FAILURE); 1775 } 1776 1777 if (QEMU_ALIGN_UP(machine->maxram_size, 1778 TARGET_PAGE_SIZE) != machine->maxram_size) { 1779 error_report("maximum memory size must by aligned to multiple of " 1780 "%d bytes", TARGET_PAGE_SIZE); 1781 exit(EXIT_FAILURE); 1782 } 1783 1784 machine->device_memory->base = 1785 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1786 1787 if (pcmc->enforce_aligned_dimm) { 1788 /* size device region assuming 1G page max alignment per slot */ 1789 device_mem_size += (1 * GiB) * machine->ram_slots; 1790 } 1791 1792 if ((machine->device_memory->base + device_mem_size) < 1793 device_mem_size) { 1794 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1795 machine->maxram_size); 1796 exit(EXIT_FAILURE); 1797 } 1798 1799 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1800 "device-memory", device_mem_size); 1801 memory_region_add_subregion(system_memory, machine->device_memory->base, 1802 &machine->device_memory->mr); 1803 } 1804 1805 /* Initialize PC system firmware */ 1806 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1807 1808 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1809 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1810 &error_fatal); 1811 if (pcmc->pci_enabled) { 1812 memory_region_set_readonly(option_rom_mr, true); 1813 } 1814 memory_region_add_subregion_overlap(rom_memory, 1815 PC_ROM_MIN_VGA, 1816 option_rom_mr, 1817 1); 1818 1819 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1820 1821 rom_set_fw(fw_cfg); 1822 1823 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1824 uint64_t *val = g_malloc(sizeof(*val)); 1825 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1826 uint64_t res_mem_end = machine->device_memory->base; 1827 1828 if (!pcmc->broken_reserved_end) { 1829 res_mem_end += memory_region_size(&machine->device_memory->mr); 1830 } 1831 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1832 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1833 } 1834 1835 if (linux_boot) { 1836 load_linux(pcms, fw_cfg); 1837 } 1838 1839 for (i = 0; i < nb_option_roms; i++) { 1840 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1841 } 1842 pcms->fw_cfg = fw_cfg; 1843 1844 /* Init default IOAPIC address space */ 1845 pcms->ioapic_as = &address_space_memory; 1846 } 1847 1848 /* 1849 * The 64bit pci hole starts after "above 4G RAM" and 1850 * potentially the space reserved for memory hotplug. 1851 */ 1852 uint64_t pc_pci_hole64_start(void) 1853 { 1854 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1855 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1856 MachineState *ms = MACHINE(pcms); 1857 uint64_t hole64_start = 0; 1858 1859 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1860 hole64_start = ms->device_memory->base; 1861 if (!pcmc->broken_reserved_end) { 1862 hole64_start += memory_region_size(&ms->device_memory->mr); 1863 } 1864 } else { 1865 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1866 } 1867 1868 return ROUND_UP(hole64_start, 1 * GiB); 1869 } 1870 1871 qemu_irq pc_allocate_cpu_irq(void) 1872 { 1873 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1874 } 1875 1876 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1877 { 1878 DeviceState *dev = NULL; 1879 1880 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1881 if (pci_bus) { 1882 PCIDevice *pcidev = pci_vga_init(pci_bus); 1883 dev = pcidev ? &pcidev->qdev : NULL; 1884 } else if (isa_bus) { 1885 ISADevice *isadev = isa_vga_init(isa_bus); 1886 dev = isadev ? DEVICE(isadev) : NULL; 1887 } 1888 rom_reset_order_override(); 1889 return dev; 1890 } 1891 1892 static const MemoryRegionOps ioport80_io_ops = { 1893 .write = ioport80_write, 1894 .read = ioport80_read, 1895 .endianness = DEVICE_NATIVE_ENDIAN, 1896 .impl = { 1897 .min_access_size = 1, 1898 .max_access_size = 1, 1899 }, 1900 }; 1901 1902 static const MemoryRegionOps ioportF0_io_ops = { 1903 .write = ioportF0_write, 1904 .read = ioportF0_read, 1905 .endianness = DEVICE_NATIVE_ENDIAN, 1906 .impl = { 1907 .min_access_size = 1, 1908 .max_access_size = 1, 1909 }, 1910 }; 1911 1912 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1913 { 1914 int i; 1915 DriveInfo *fd[MAX_FD]; 1916 qemu_irq *a20_line; 1917 ISADevice *i8042, *port92, *vmmouse; 1918 1919 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1920 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1921 1922 for (i = 0; i < MAX_FD; i++) { 1923 fd[i] = drive_get(IF_FLOPPY, 0, i); 1924 create_fdctrl |= !!fd[i]; 1925 } 1926 if (create_fdctrl) { 1927 fdctrl_init_isa(isa_bus, fd); 1928 } 1929 1930 i8042 = isa_create_simple(isa_bus, "i8042"); 1931 if (!no_vmport) { 1932 vmport_init(isa_bus); 1933 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1934 } else { 1935 vmmouse = NULL; 1936 } 1937 if (vmmouse) { 1938 DeviceState *dev = DEVICE(vmmouse); 1939 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1940 qdev_init_nofail(dev); 1941 } 1942 port92 = isa_create_simple(isa_bus, "port92"); 1943 1944 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1945 i8042_setup_a20_line(i8042, a20_line[0]); 1946 port92_init(port92, a20_line[1]); 1947 g_free(a20_line); 1948 } 1949 1950 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1951 ISADevice **rtc_state, 1952 bool create_fdctrl, 1953 bool no_vmport, 1954 bool has_pit, 1955 uint32_t hpet_irqs) 1956 { 1957 int i; 1958 DeviceState *hpet = NULL; 1959 int pit_isa_irq = 0; 1960 qemu_irq pit_alt_irq = NULL; 1961 qemu_irq rtc_irq = NULL; 1962 ISADevice *pit = NULL; 1963 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1964 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1965 1966 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1967 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1968 1969 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1970 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1971 1972 /* 1973 * Check if an HPET shall be created. 1974 * 1975 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1976 * when the HPET wants to take over. Thus we have to disable the latter. 1977 */ 1978 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1979 /* In order to set property, here not using sysbus_try_create_simple */ 1980 hpet = qdev_try_create(NULL, TYPE_HPET); 1981 if (hpet) { 1982 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1983 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1984 * IRQ8 and IRQ2. 1985 */ 1986 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1987 HPET_INTCAP, NULL); 1988 if (!compat) { 1989 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1990 } 1991 qdev_init_nofail(hpet); 1992 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1993 1994 for (i = 0; i < GSI_NUM_PINS; i++) { 1995 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1996 } 1997 pit_isa_irq = -1; 1998 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1999 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 2000 } 2001 } 2002 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 2003 2004 qemu_register_boot_set(pc_boot_set, *rtc_state); 2005 2006 if (!xen_enabled() && has_pit) { 2007 if (kvm_pit_in_kernel()) { 2008 pit = kvm_pit_init(isa_bus, 0x40); 2009 } else { 2010 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 2011 } 2012 if (hpet) { 2013 /* connect PIT to output control line of the HPET */ 2014 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 2015 } 2016 pcspk_init(isa_bus, pit); 2017 } 2018 2019 i8257_dma_init(isa_bus, 0); 2020 2021 /* Super I/O */ 2022 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 2023 } 2024 2025 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 2026 { 2027 int i; 2028 2029 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 2030 for (i = 0; i < nb_nics; i++) { 2031 NICInfo *nd = &nd_table[i]; 2032 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 2033 2034 if (g_str_equal(model, "ne2k_isa")) { 2035 pc_init_ne2k_isa(isa_bus, nd); 2036 } else { 2037 pci_nic_init_nofail(nd, pci_bus, model, NULL); 2038 } 2039 } 2040 rom_reset_order_override(); 2041 } 2042 2043 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 2044 { 2045 DeviceState *dev; 2046 SysBusDevice *d; 2047 unsigned int i; 2048 2049 if (kvm_ioapic_in_kernel()) { 2050 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 2051 } else { 2052 dev = qdev_create(NULL, TYPE_IOAPIC); 2053 } 2054 if (parent_name) { 2055 object_property_add_child(object_resolve_path(parent_name, NULL), 2056 "ioapic", OBJECT(dev), NULL); 2057 } 2058 qdev_init_nofail(dev); 2059 d = SYS_BUS_DEVICE(dev); 2060 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2061 2062 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2063 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2064 } 2065 } 2066 2067 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2068 Error **errp) 2069 { 2070 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2071 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2072 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2073 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2074 2075 /* 2076 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2077 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2078 * addition to cover this case. 2079 */ 2080 if (!pcms->acpi_dev || !acpi_enabled) { 2081 error_setg(errp, 2082 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2083 return; 2084 } 2085 2086 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) { 2087 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2088 return; 2089 } 2090 2091 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2092 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2093 } 2094 2095 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2096 DeviceState *dev, Error **errp) 2097 { 2098 Error *local_err = NULL; 2099 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2100 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2101 2102 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2103 if (local_err) { 2104 goto out; 2105 } 2106 2107 if (is_nvdimm) { 2108 nvdimm_plug(&pcms->acpi_nvdimm_state); 2109 } 2110 2111 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2112 out: 2113 error_propagate(errp, local_err); 2114 } 2115 2116 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2117 DeviceState *dev, Error **errp) 2118 { 2119 Error *local_err = NULL; 2120 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2121 2122 /* 2123 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2124 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2125 * addition to cover this case. 2126 */ 2127 if (!pcms->acpi_dev || !acpi_enabled) { 2128 error_setg(&local_err, 2129 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2130 goto out; 2131 } 2132 2133 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2134 error_setg(&local_err, 2135 "nvdimm device hot unplug is not supported yet."); 2136 goto out; 2137 } 2138 2139 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2140 &local_err); 2141 out: 2142 error_propagate(errp, local_err); 2143 } 2144 2145 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2146 DeviceState *dev, Error **errp) 2147 { 2148 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2149 Error *local_err = NULL; 2150 2151 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2152 if (local_err) { 2153 goto out; 2154 } 2155 2156 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2157 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2158 out: 2159 error_propagate(errp, local_err); 2160 } 2161 2162 static int pc_apic_cmp(const void *a, const void *b) 2163 { 2164 CPUArchId *apic_a = (CPUArchId *)a; 2165 CPUArchId *apic_b = (CPUArchId *)b; 2166 2167 return apic_a->arch_id - apic_b->arch_id; 2168 } 2169 2170 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2171 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2172 * entry corresponding to CPU's apic_id returns NULL. 2173 */ 2174 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2175 { 2176 CPUArchId apic_id, *found_cpu; 2177 2178 apic_id.arch_id = id; 2179 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2180 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2181 pc_apic_cmp); 2182 if (found_cpu && idx) { 2183 *idx = found_cpu - ms->possible_cpus->cpus; 2184 } 2185 return found_cpu; 2186 } 2187 2188 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2189 DeviceState *dev, Error **errp) 2190 { 2191 CPUArchId *found_cpu; 2192 Error *local_err = NULL; 2193 X86CPU *cpu = X86_CPU(dev); 2194 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2195 2196 if (pcms->acpi_dev) { 2197 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2198 if (local_err) { 2199 goto out; 2200 } 2201 } 2202 2203 /* increment the number of CPUs */ 2204 pcms->boot_cpus++; 2205 if (pcms->rtc) { 2206 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2207 } 2208 if (pcms->fw_cfg) { 2209 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2210 } 2211 2212 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2213 found_cpu->cpu = OBJECT(dev); 2214 out: 2215 error_propagate(errp, local_err); 2216 } 2217 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2218 DeviceState *dev, Error **errp) 2219 { 2220 int idx = -1; 2221 Error *local_err = NULL; 2222 X86CPU *cpu = X86_CPU(dev); 2223 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2224 2225 if (!pcms->acpi_dev) { 2226 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2227 goto out; 2228 } 2229 2230 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2231 assert(idx != -1); 2232 if (idx == 0) { 2233 error_setg(&local_err, "Boot CPU is unpluggable"); 2234 goto out; 2235 } 2236 2237 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2238 &local_err); 2239 if (local_err) { 2240 goto out; 2241 } 2242 2243 out: 2244 error_propagate(errp, local_err); 2245 2246 } 2247 2248 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2249 DeviceState *dev, Error **errp) 2250 { 2251 CPUArchId *found_cpu; 2252 Error *local_err = NULL; 2253 X86CPU *cpu = X86_CPU(dev); 2254 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2255 2256 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2257 if (local_err) { 2258 goto out; 2259 } 2260 2261 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2262 found_cpu->cpu = NULL; 2263 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2264 2265 /* decrement the number of CPUs */ 2266 pcms->boot_cpus--; 2267 /* Update the number of CPUs in CMOS */ 2268 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2269 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2270 out: 2271 error_propagate(errp, local_err); 2272 } 2273 2274 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2275 DeviceState *dev, Error **errp) 2276 { 2277 int idx; 2278 CPUState *cs; 2279 CPUArchId *cpu_slot; 2280 X86CPUTopoInfo topo; 2281 X86CPU *cpu = X86_CPU(dev); 2282 MachineState *ms = MACHINE(hotplug_dev); 2283 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2284 2285 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2286 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2287 ms->cpu_type); 2288 return; 2289 } 2290 2291 /* if APIC ID is not set, set it based on socket/core/thread properties */ 2292 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2293 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 2294 2295 if (cpu->socket_id < 0) { 2296 error_setg(errp, "CPU socket-id is not set"); 2297 return; 2298 } else if (cpu->socket_id > max_socket) { 2299 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2300 cpu->socket_id, max_socket); 2301 return; 2302 } 2303 if (cpu->core_id < 0) { 2304 error_setg(errp, "CPU core-id is not set"); 2305 return; 2306 } else if (cpu->core_id > (smp_cores - 1)) { 2307 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2308 cpu->core_id, smp_cores - 1); 2309 return; 2310 } 2311 if (cpu->thread_id < 0) { 2312 error_setg(errp, "CPU thread-id is not set"); 2313 return; 2314 } else if (cpu->thread_id > (smp_threads - 1)) { 2315 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2316 cpu->thread_id, smp_threads - 1); 2317 return; 2318 } 2319 2320 topo.pkg_id = cpu->socket_id; 2321 topo.core_id = cpu->core_id; 2322 topo.smt_id = cpu->thread_id; 2323 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 2324 } 2325 2326 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2327 if (!cpu_slot) { 2328 MachineState *ms = MACHINE(pcms); 2329 2330 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2331 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 2332 " APIC ID %" PRIu32 ", valid index range 0:%d", 2333 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 2334 ms->possible_cpus->len - 1); 2335 return; 2336 } 2337 2338 if (cpu_slot->cpu) { 2339 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2340 idx, cpu->apic_id); 2341 return; 2342 } 2343 2344 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2345 * so that machine_query_hotpluggable_cpus would show correct values 2346 */ 2347 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2348 * once -smp refactoring is complete and there will be CPU private 2349 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2350 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2351 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2352 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2353 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2354 return; 2355 } 2356 cpu->socket_id = topo.pkg_id; 2357 2358 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2359 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2360 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2361 return; 2362 } 2363 cpu->core_id = topo.core_id; 2364 2365 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2366 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2367 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2368 return; 2369 } 2370 cpu->thread_id = topo.smt_id; 2371 2372 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) { 2373 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2374 return; 2375 } 2376 2377 cs = CPU(cpu); 2378 cs->cpu_index = idx; 2379 2380 numa_cpu_pre_plug(cpu_slot, dev, errp); 2381 } 2382 2383 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2384 DeviceState *dev, Error **errp) 2385 { 2386 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2387 pc_memory_pre_plug(hotplug_dev, dev, errp); 2388 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2389 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2390 } 2391 } 2392 2393 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2394 DeviceState *dev, Error **errp) 2395 { 2396 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2397 pc_memory_plug(hotplug_dev, dev, errp); 2398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2399 pc_cpu_plug(hotplug_dev, dev, errp); 2400 } 2401 } 2402 2403 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2404 DeviceState *dev, Error **errp) 2405 { 2406 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2407 pc_memory_unplug_request(hotplug_dev, dev, errp); 2408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2409 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2410 } else { 2411 error_setg(errp, "acpi: device unplug request for not supported device" 2412 " type: %s", object_get_typename(OBJECT(dev))); 2413 } 2414 } 2415 2416 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2417 DeviceState *dev, Error **errp) 2418 { 2419 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2420 pc_memory_unplug(hotplug_dev, dev, errp); 2421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2422 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2423 } else { 2424 error_setg(errp, "acpi: device unplug for not supported device" 2425 " type: %s", object_get_typename(OBJECT(dev))); 2426 } 2427 } 2428 2429 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2430 DeviceState *dev) 2431 { 2432 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2433 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2434 return HOTPLUG_HANDLER(machine); 2435 } 2436 2437 return NULL; 2438 } 2439 2440 static void 2441 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2442 const char *name, void *opaque, 2443 Error **errp) 2444 { 2445 MachineState *ms = MACHINE(obj); 2446 int64_t value = memory_region_size(&ms->device_memory->mr); 2447 2448 visit_type_int(v, name, &value, errp); 2449 } 2450 2451 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2452 const char *name, void *opaque, 2453 Error **errp) 2454 { 2455 PCMachineState *pcms = PC_MACHINE(obj); 2456 uint64_t value = pcms->max_ram_below_4g; 2457 2458 visit_type_size(v, name, &value, errp); 2459 } 2460 2461 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2462 const char *name, void *opaque, 2463 Error **errp) 2464 { 2465 PCMachineState *pcms = PC_MACHINE(obj); 2466 Error *error = NULL; 2467 uint64_t value; 2468 2469 visit_type_size(v, name, &value, &error); 2470 if (error) { 2471 error_propagate(errp, error); 2472 return; 2473 } 2474 if (value > 4 * GiB) { 2475 error_setg(&error, 2476 "Machine option 'max-ram-below-4g=%"PRIu64 2477 "' expects size less than or equal to 4G", value); 2478 error_propagate(errp, error); 2479 return; 2480 } 2481 2482 if (value < 1 * MiB) { 2483 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2484 "BIOS may not work with less than 1MiB", value); 2485 } 2486 2487 pcms->max_ram_below_4g = value; 2488 } 2489 2490 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2491 void *opaque, Error **errp) 2492 { 2493 PCMachineState *pcms = PC_MACHINE(obj); 2494 OnOffAuto vmport = pcms->vmport; 2495 2496 visit_type_OnOffAuto(v, name, &vmport, errp); 2497 } 2498 2499 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2500 void *opaque, Error **errp) 2501 { 2502 PCMachineState *pcms = PC_MACHINE(obj); 2503 2504 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2505 } 2506 2507 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2508 { 2509 bool smm_available = false; 2510 2511 if (pcms->smm == ON_OFF_AUTO_OFF) { 2512 return false; 2513 } 2514 2515 if (tcg_enabled() || qtest_enabled()) { 2516 smm_available = true; 2517 } else if (kvm_enabled()) { 2518 smm_available = kvm_has_smm(); 2519 } 2520 2521 if (smm_available) { 2522 return true; 2523 } 2524 2525 if (pcms->smm == ON_OFF_AUTO_ON) { 2526 error_report("System Management Mode not supported by this hypervisor."); 2527 exit(1); 2528 } 2529 return false; 2530 } 2531 2532 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2533 void *opaque, Error **errp) 2534 { 2535 PCMachineState *pcms = PC_MACHINE(obj); 2536 OnOffAuto smm = pcms->smm; 2537 2538 visit_type_OnOffAuto(v, name, &smm, errp); 2539 } 2540 2541 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2542 void *opaque, Error **errp) 2543 { 2544 PCMachineState *pcms = PC_MACHINE(obj); 2545 2546 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2547 } 2548 2549 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 2550 { 2551 PCMachineState *pcms = PC_MACHINE(obj); 2552 2553 return pcms->acpi_nvdimm_state.is_enabled; 2554 } 2555 2556 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 2557 { 2558 PCMachineState *pcms = PC_MACHINE(obj); 2559 2560 pcms->acpi_nvdimm_state.is_enabled = value; 2561 } 2562 2563 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp) 2564 { 2565 PCMachineState *pcms = PC_MACHINE(obj); 2566 2567 return g_strdup(pcms->acpi_nvdimm_state.persistence_string); 2568 } 2569 2570 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value, 2571 Error **errp) 2572 { 2573 PCMachineState *pcms = PC_MACHINE(obj); 2574 AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state; 2575 2576 if (strcmp(value, "cpu") == 0) 2577 nvdimm_state->persistence = 3; 2578 else if (strcmp(value, "mem-ctrl") == 0) 2579 nvdimm_state->persistence = 2; 2580 else { 2581 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 2582 value); 2583 return; 2584 } 2585 2586 g_free(nvdimm_state->persistence_string); 2587 nvdimm_state->persistence_string = g_strdup(value); 2588 } 2589 2590 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2591 { 2592 PCMachineState *pcms = PC_MACHINE(obj); 2593 2594 return pcms->smbus_enabled; 2595 } 2596 2597 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2598 { 2599 PCMachineState *pcms = PC_MACHINE(obj); 2600 2601 pcms->smbus_enabled = value; 2602 } 2603 2604 static bool pc_machine_get_sata(Object *obj, Error **errp) 2605 { 2606 PCMachineState *pcms = PC_MACHINE(obj); 2607 2608 return pcms->sata_enabled; 2609 } 2610 2611 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2612 { 2613 PCMachineState *pcms = PC_MACHINE(obj); 2614 2615 pcms->sata_enabled = value; 2616 } 2617 2618 static bool pc_machine_get_pit(Object *obj, Error **errp) 2619 { 2620 PCMachineState *pcms = PC_MACHINE(obj); 2621 2622 return pcms->pit_enabled; 2623 } 2624 2625 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2626 { 2627 PCMachineState *pcms = PC_MACHINE(obj); 2628 2629 pcms->pit_enabled = value; 2630 } 2631 2632 static void pc_machine_initfn(Object *obj) 2633 { 2634 PCMachineState *pcms = PC_MACHINE(obj); 2635 2636 pcms->max_ram_below_4g = 0; /* use default */ 2637 pcms->smm = ON_OFF_AUTO_AUTO; 2638 pcms->vmport = ON_OFF_AUTO_AUTO; 2639 /* nvdimm is disabled on default. */ 2640 pcms->acpi_nvdimm_state.is_enabled = false; 2641 /* acpi build is enabled by default if machine supports it */ 2642 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2643 pcms->smbus_enabled = true; 2644 pcms->sata_enabled = true; 2645 pcms->pit_enabled = true; 2646 } 2647 2648 static void pc_machine_reset(void) 2649 { 2650 CPUState *cs; 2651 X86CPU *cpu; 2652 2653 qemu_devices_reset(); 2654 2655 /* Reset APIC after devices have been reset to cancel 2656 * any changes that qemu_devices_reset() might have done. 2657 */ 2658 CPU_FOREACH(cs) { 2659 cpu = X86_CPU(cs); 2660 2661 if (cpu->apic_state) { 2662 device_reset(cpu->apic_state); 2663 } 2664 } 2665 } 2666 2667 static CpuInstanceProperties 2668 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2669 { 2670 MachineClass *mc = MACHINE_GET_CLASS(ms); 2671 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2672 2673 assert(cpu_index < possible_cpus->len); 2674 return possible_cpus->cpus[cpu_index].props; 2675 } 2676 2677 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2678 { 2679 X86CPUTopoInfo topo; 2680 2681 assert(idx < ms->possible_cpus->len); 2682 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2683 smp_cores, smp_threads, &topo); 2684 return topo.pkg_id % nb_numa_nodes; 2685 } 2686 2687 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2688 { 2689 int i; 2690 2691 if (ms->possible_cpus) { 2692 /* 2693 * make sure that max_cpus hasn't changed since the first use, i.e. 2694 * -smp hasn't been parsed after it 2695 */ 2696 assert(ms->possible_cpus->len == max_cpus); 2697 return ms->possible_cpus; 2698 } 2699 2700 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2701 sizeof(CPUArchId) * max_cpus); 2702 ms->possible_cpus->len = max_cpus; 2703 for (i = 0; i < ms->possible_cpus->len; i++) { 2704 X86CPUTopoInfo topo; 2705 2706 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2707 ms->possible_cpus->cpus[i].vcpus_count = 1; 2708 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 2709 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2710 smp_cores, smp_threads, &topo); 2711 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2712 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2713 ms->possible_cpus->cpus[i].props.has_core_id = true; 2714 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2715 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2716 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2717 } 2718 return ms->possible_cpus; 2719 } 2720 2721 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2722 { 2723 /* cpu index isn't used */ 2724 CPUState *cs; 2725 2726 CPU_FOREACH(cs) { 2727 X86CPU *cpu = X86_CPU(cs); 2728 2729 if (!cpu->apic_state) { 2730 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2731 } else { 2732 apic_deliver_nmi(cpu->apic_state); 2733 } 2734 } 2735 } 2736 2737 static void pc_machine_class_init(ObjectClass *oc, void *data) 2738 { 2739 MachineClass *mc = MACHINE_CLASS(oc); 2740 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2741 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2742 NMIClass *nc = NMI_CLASS(oc); 2743 2744 pcmc->pci_enabled = true; 2745 pcmc->has_acpi_build = true; 2746 pcmc->rsdp_in_ram = true; 2747 pcmc->smbios_defaults = true; 2748 pcmc->smbios_uuid_encoded = true; 2749 pcmc->gigabyte_align = true; 2750 pcmc->has_reserved_memory = true; 2751 pcmc->kvmclock_enabled = true; 2752 pcmc->enforce_aligned_dimm = true; 2753 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2754 * to be used at the moment, 32K should be enough for a while. */ 2755 pcmc->acpi_data_size = 0x20000 + 0x8000; 2756 pcmc->save_tsc_khz = true; 2757 pcmc->linuxboot_dma_enabled = true; 2758 pcmc->pvh_enabled = true; 2759 assert(!mc->get_hotplug_handler); 2760 mc->get_hotplug_handler = pc_get_hotplug_handler; 2761 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2762 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2763 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2764 mc->auto_enable_numa_with_memhp = true; 2765 mc->has_hotpluggable_cpus = true; 2766 mc->default_boot_order = "cad"; 2767 mc->hot_add_cpu = pc_hot_add_cpu; 2768 mc->block_default_type = IF_IDE; 2769 mc->max_cpus = 255; 2770 mc->reset = pc_machine_reset; 2771 hc->pre_plug = pc_machine_device_pre_plug_cb; 2772 hc->plug = pc_machine_device_plug_cb; 2773 hc->unplug_request = pc_machine_device_unplug_request_cb; 2774 hc->unplug = pc_machine_device_unplug_cb; 2775 nc->nmi_monitor_handler = x86_nmi; 2776 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2777 2778 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2779 pc_machine_get_device_memory_region_size, NULL, 2780 NULL, NULL, &error_abort); 2781 2782 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2783 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2784 NULL, NULL, &error_abort); 2785 2786 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2787 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2788 2789 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2790 pc_machine_get_smm, pc_machine_set_smm, 2791 NULL, NULL, &error_abort); 2792 object_class_property_set_description(oc, PC_MACHINE_SMM, 2793 "Enable SMM (pc & q35)", &error_abort); 2794 2795 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2796 pc_machine_get_vmport, pc_machine_set_vmport, 2797 NULL, NULL, &error_abort); 2798 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2799 "Enable vmport (pc & q35)", &error_abort); 2800 2801 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, 2802 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); 2803 2804 object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST, 2805 pc_machine_get_nvdimm_persistence, 2806 pc_machine_set_nvdimm_persistence, &error_abort); 2807 2808 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2809 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2810 2811 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2812 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2813 2814 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2815 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2816 } 2817 2818 static const TypeInfo pc_machine_info = { 2819 .name = TYPE_PC_MACHINE, 2820 .parent = TYPE_MACHINE, 2821 .abstract = true, 2822 .instance_size = sizeof(PCMachineState), 2823 .instance_init = pc_machine_initfn, 2824 .class_size = sizeof(PCMachineClass), 2825 .class_init = pc_machine_class_init, 2826 .interfaces = (InterfaceInfo[]) { 2827 { TYPE_HOTPLUG_HANDLER }, 2828 { TYPE_NMI }, 2829 { } 2830 }, 2831 }; 2832 2833 static void pc_machine_register_types(void) 2834 { 2835 type_register_static(&pc_machine_info); 2836 } 2837 2838 type_init(pc_machine_register_types) 2839