1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/i386/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/cpu/icc_bus.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 81 * (128K) and other BIOS datastructures (less than 4K reported to be used at 82 * the moment, 32K should be enough for a while). */ 83 static unsigned acpi_data_size = 0x20000 + 0x8000; 84 void pc_set_legacy_acpi_data_size(void) 85 { 86 acpi_data_size = 0x10000; 87 } 88 89 #define BIOS_CFG_IOPORT 0x510 90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 95 96 #define E820_NR_ENTRIES 16 97 98 struct e820_entry { 99 uint64_t address; 100 uint64_t length; 101 uint32_t type; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 struct e820_table { 105 uint32_t count; 106 struct e820_entry entry[E820_NR_ENTRIES]; 107 } QEMU_PACKED __attribute((__aligned__(4))); 108 109 static struct e820_table e820_reserve; 110 static struct e820_entry *e820_table; 111 static unsigned e820_entries; 112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 113 114 void gsi_handler(void *opaque, int n, int level) 115 { 116 GSIState *s = opaque; 117 118 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 119 if (n < ISA_NUM_IRQS) { 120 qemu_set_irq(s->i8259_irq[n], level); 121 } 122 qemu_set_irq(s->ioapic_irq[n], level); 123 } 124 125 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 126 unsigned size) 127 { 128 } 129 130 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 131 { 132 return 0xffffffffffffffffULL; 133 } 134 135 /* MSDOS compatibility mode FPU exception support */ 136 static qemu_irq ferr_irq; 137 138 void pc_register_ferr_irq(qemu_irq irq) 139 { 140 ferr_irq = irq; 141 } 142 143 /* XXX: add IGNNE support */ 144 void cpu_set_ferr(CPUX86State *s) 145 { 146 qemu_irq_raise(ferr_irq); 147 } 148 149 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 150 unsigned size) 151 { 152 qemu_irq_lower(ferr_irq); 153 } 154 155 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 156 { 157 return 0xffffffffffffffffULL; 158 } 159 160 /* TSC handling */ 161 uint64_t cpu_get_tsc(CPUX86State *env) 162 { 163 return cpu_get_ticks(); 164 } 165 166 /* IRQ handling */ 167 int cpu_get_pic_interrupt(CPUX86State *env) 168 { 169 X86CPU *cpu = x86_env_get_cpu(env); 170 int intno; 171 172 intno = apic_get_interrupt(cpu->apic_state); 173 if (intno >= 0) { 174 return intno; 175 } 176 /* read the irq from the PIC */ 177 if (!apic_accept_pic_intr(cpu->apic_state)) { 178 return -1; 179 } 180 181 intno = pic_read_irq(isa_pic); 182 return intno; 183 } 184 185 static void pic_irq_request(void *opaque, int irq, int level) 186 { 187 CPUState *cs = first_cpu; 188 X86CPU *cpu = X86_CPU(cs); 189 190 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 191 if (cpu->apic_state) { 192 CPU_FOREACH(cs) { 193 cpu = X86_CPU(cs); 194 if (apic_accept_pic_intr(cpu->apic_state)) { 195 apic_deliver_pic_intr(cpu->apic_state, level); 196 } 197 } 198 } else { 199 if (level) { 200 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 201 } else { 202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 203 } 204 } 205 } 206 207 /* PC cmos mappings */ 208 209 #define REG_EQUIPMENT_BYTE 0x14 210 211 static int cmos_get_fd_drive_type(FDriveType fd0) 212 { 213 int val; 214 215 switch (fd0) { 216 case FDRIVE_DRV_144: 217 /* 1.44 Mb 3"5 drive */ 218 val = 4; 219 break; 220 case FDRIVE_DRV_288: 221 /* 2.88 Mb 3"5 drive */ 222 val = 5; 223 break; 224 case FDRIVE_DRV_120: 225 /* 1.2 Mb 5"5 drive */ 226 val = 2; 227 break; 228 case FDRIVE_DRV_NONE: 229 default: 230 val = 0; 231 break; 232 } 233 return val; 234 } 235 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 237 int16_t cylinders, int8_t heads, int8_t sectors) 238 { 239 rtc_set_memory(s, type_ofs, 47); 240 rtc_set_memory(s, info_ofs, cylinders); 241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 242 rtc_set_memory(s, info_ofs + 2, heads); 243 rtc_set_memory(s, info_ofs + 3, 0xff); 244 rtc_set_memory(s, info_ofs + 4, 0xff); 245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 246 rtc_set_memory(s, info_ofs + 6, cylinders); 247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 8, sectors); 249 } 250 251 /* convert boot_device letter to something recognizable by the bios */ 252 static int boot_device2nibble(char boot_device) 253 { 254 switch(boot_device) { 255 case 'a': 256 case 'b': 257 return 0x01; /* floppy boot */ 258 case 'c': 259 return 0x02; /* hard drive boot */ 260 case 'd': 261 return 0x03; /* CD-ROM boot */ 262 case 'n': 263 return 0x04; /* Network boot */ 264 } 265 return 0; 266 } 267 268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 269 { 270 #define PC_MAX_BOOT_DEVICES 3 271 int nbds, bds[3] = { 0, }; 272 int i; 273 274 nbds = strlen(boot_device); 275 if (nbds > PC_MAX_BOOT_DEVICES) { 276 error_setg(errp, "Too many boot devices for PC"); 277 return; 278 } 279 for (i = 0; i < nbds; i++) { 280 bds[i] = boot_device2nibble(boot_device[i]); 281 if (bds[i] == 0) { 282 error_setg(errp, "Invalid boot device for PC: '%c'", 283 boot_device[i]); 284 return; 285 } 286 } 287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 289 } 290 291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 292 { 293 set_boot_dev(opaque, boot_device, errp); 294 } 295 296 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 297 { 298 int val, nb, i; 299 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 300 301 /* floppy type */ 302 if (floppy) { 303 for (i = 0; i < 2; i++) { 304 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 305 } 306 } 307 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 308 cmos_get_fd_drive_type(fd_type[1]); 309 rtc_set_memory(rtc_state, 0x10, val); 310 311 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 312 nb = 0; 313 if (fd_type[0] < FDRIVE_DRV_NONE) { 314 nb++; 315 } 316 if (fd_type[1] < FDRIVE_DRV_NONE) { 317 nb++; 318 } 319 switch (nb) { 320 case 0: 321 break; 322 case 1: 323 val |= 0x01; /* 1 drive, ready for boot */ 324 break; 325 case 2: 326 val |= 0x41; /* 2 drives, ready for boot */ 327 break; 328 } 329 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 330 } 331 332 typedef struct pc_cmos_init_late_arg { 333 ISADevice *rtc_state; 334 BusState *idebus[2]; 335 } pc_cmos_init_late_arg; 336 337 typedef struct check_fdc_state { 338 ISADevice *floppy; 339 bool multiple; 340 } CheckFdcState; 341 342 static int check_fdc(Object *obj, void *opaque) 343 { 344 CheckFdcState *state = opaque; 345 Object *fdc; 346 uint32_t iobase; 347 Error *local_err = NULL; 348 349 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 350 if (!fdc) { 351 return 0; 352 } 353 354 iobase = object_property_get_int(obj, "iobase", &local_err); 355 if (local_err || iobase != 0x3f0) { 356 error_free(local_err); 357 return 0; 358 } 359 360 if (state->floppy) { 361 state->multiple = true; 362 } else { 363 state->floppy = ISA_DEVICE(obj); 364 } 365 return 0; 366 } 367 368 static const char * const fdc_container_path[] = { 369 "/unattached", "/peripheral", "/peripheral-anon" 370 }; 371 372 static void pc_cmos_init_late(void *opaque) 373 { 374 pc_cmos_init_late_arg *arg = opaque; 375 ISADevice *s = arg->rtc_state; 376 int16_t cylinders; 377 int8_t heads, sectors; 378 int val; 379 int i, trans; 380 Object *container; 381 CheckFdcState state = { 0 }; 382 383 val = 0; 384 if (ide_get_geometry(arg->idebus[0], 0, 385 &cylinders, &heads, §ors) >= 0) { 386 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 387 val |= 0xf0; 388 } 389 if (ide_get_geometry(arg->idebus[0], 1, 390 &cylinders, &heads, §ors) >= 0) { 391 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 392 val |= 0x0f; 393 } 394 rtc_set_memory(s, 0x12, val); 395 396 val = 0; 397 for (i = 0; i < 4; i++) { 398 /* NOTE: ide_get_geometry() returns the physical 399 geometry. It is always such that: 1 <= sects <= 63, 1 400 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 401 geometry can be different if a translation is done. */ 402 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 403 &cylinders, &heads, §ors) >= 0) { 404 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 405 assert((trans & ~3) == 0); 406 val |= trans << (i * 2); 407 } 408 } 409 rtc_set_memory(s, 0x39, val); 410 411 /* 412 * Locate the FDC at IO address 0x3f0, and configure the CMOS registers 413 * accordingly. 414 */ 415 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 416 container = container_get(qdev_get_machine(), fdc_container_path[i]); 417 object_child_foreach(container, check_fdc, &state); 418 } 419 420 if (state.multiple) { 421 error_report("warning: multiple floppy disk controllers with " 422 "iobase=0x3f0 have been found;\n" 423 "the one being picked for CMOS setup might not reflect " 424 "your intent"); 425 } 426 pc_cmos_init_floppy(s, state.floppy); 427 428 qemu_unregister_reset(pc_cmos_init_late, opaque); 429 } 430 431 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 432 const char *boot_device, MachineState *machine, 433 BusState *idebus0, BusState *idebus1, 434 ISADevice *s) 435 { 436 int val; 437 static pc_cmos_init_late_arg arg; 438 PCMachineState *pc_machine = PC_MACHINE(machine); 439 Error *local_err = NULL; 440 441 /* various important CMOS locations needed by PC/Bochs bios */ 442 443 /* memory size */ 444 /* base memory (first MiB) */ 445 val = MIN(ram_size / 1024, 640); 446 rtc_set_memory(s, 0x15, val); 447 rtc_set_memory(s, 0x16, val >> 8); 448 /* extended memory (next 64MiB) */ 449 if (ram_size > 1024 * 1024) { 450 val = (ram_size - 1024 * 1024) / 1024; 451 } else { 452 val = 0; 453 } 454 if (val > 65535) 455 val = 65535; 456 rtc_set_memory(s, 0x17, val); 457 rtc_set_memory(s, 0x18, val >> 8); 458 rtc_set_memory(s, 0x30, val); 459 rtc_set_memory(s, 0x31, val >> 8); 460 /* memory between 16MiB and 4GiB */ 461 if (ram_size > 16 * 1024 * 1024) { 462 val = (ram_size - 16 * 1024 * 1024) / 65536; 463 } else { 464 val = 0; 465 } 466 if (val > 65535) 467 val = 65535; 468 rtc_set_memory(s, 0x34, val); 469 rtc_set_memory(s, 0x35, val >> 8); 470 /* memory above 4GiB */ 471 val = above_4g_mem_size / 65536; 472 rtc_set_memory(s, 0x5b, val); 473 rtc_set_memory(s, 0x5c, val >> 8); 474 rtc_set_memory(s, 0x5d, val >> 16); 475 476 /* set the number of CPU */ 477 rtc_set_memory(s, 0x5f, smp_cpus - 1); 478 479 object_property_add_link(OBJECT(machine), "rtc_state", 480 TYPE_ISA_DEVICE, 481 (Object **)&pc_machine->rtc, 482 object_property_allow_set_link, 483 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 484 object_property_set_link(OBJECT(machine), OBJECT(s), 485 "rtc_state", &error_abort); 486 487 set_boot_dev(s, boot_device, &local_err); 488 if (local_err) { 489 error_report_err(local_err); 490 exit(1); 491 } 492 493 val = 0; 494 val |= 0x02; /* FPU is there */ 495 val |= 0x04; /* PS/2 mouse installed */ 496 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 497 498 /* hard drives and FDC */ 499 arg.rtc_state = s; 500 arg.idebus[0] = idebus0; 501 arg.idebus[1] = idebus1; 502 qemu_register_reset(pc_cmos_init_late, &arg); 503 } 504 505 #define TYPE_PORT92 "port92" 506 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 507 508 /* port 92 stuff: could be split off */ 509 typedef struct Port92State { 510 ISADevice parent_obj; 511 512 MemoryRegion io; 513 uint8_t outport; 514 qemu_irq *a20_out; 515 } Port92State; 516 517 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 518 unsigned size) 519 { 520 Port92State *s = opaque; 521 int oldval = s->outport; 522 523 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 524 s->outport = val; 525 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 526 if ((val & 1) && !(oldval & 1)) { 527 qemu_system_reset_request(); 528 } 529 } 530 531 static uint64_t port92_read(void *opaque, hwaddr addr, 532 unsigned size) 533 { 534 Port92State *s = opaque; 535 uint32_t ret; 536 537 ret = s->outport; 538 DPRINTF("port92: read 0x%02x\n", ret); 539 return ret; 540 } 541 542 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 543 { 544 Port92State *s = PORT92(dev); 545 546 s->a20_out = a20_out; 547 } 548 549 static const VMStateDescription vmstate_port92_isa = { 550 .name = "port92", 551 .version_id = 1, 552 .minimum_version_id = 1, 553 .fields = (VMStateField[]) { 554 VMSTATE_UINT8(outport, Port92State), 555 VMSTATE_END_OF_LIST() 556 } 557 }; 558 559 static void port92_reset(DeviceState *d) 560 { 561 Port92State *s = PORT92(d); 562 563 s->outport &= ~1; 564 } 565 566 static const MemoryRegionOps port92_ops = { 567 .read = port92_read, 568 .write = port92_write, 569 .impl = { 570 .min_access_size = 1, 571 .max_access_size = 1, 572 }, 573 .endianness = DEVICE_LITTLE_ENDIAN, 574 }; 575 576 static void port92_initfn(Object *obj) 577 { 578 Port92State *s = PORT92(obj); 579 580 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 581 582 s->outport = 0; 583 } 584 585 static void port92_realizefn(DeviceState *dev, Error **errp) 586 { 587 ISADevice *isadev = ISA_DEVICE(dev); 588 Port92State *s = PORT92(dev); 589 590 isa_register_ioport(isadev, &s->io, 0x92); 591 } 592 593 static void port92_class_initfn(ObjectClass *klass, void *data) 594 { 595 DeviceClass *dc = DEVICE_CLASS(klass); 596 597 dc->realize = port92_realizefn; 598 dc->reset = port92_reset; 599 dc->vmsd = &vmstate_port92_isa; 600 /* 601 * Reason: unlike ordinary ISA devices, this one needs additional 602 * wiring: its A20 output line needs to be wired up by 603 * port92_init(). 604 */ 605 dc->cannot_instantiate_with_device_add_yet = true; 606 } 607 608 static const TypeInfo port92_info = { 609 .name = TYPE_PORT92, 610 .parent = TYPE_ISA_DEVICE, 611 .instance_size = sizeof(Port92State), 612 .instance_init = port92_initfn, 613 .class_init = port92_class_initfn, 614 }; 615 616 static void port92_register_types(void) 617 { 618 type_register_static(&port92_info); 619 } 620 621 type_init(port92_register_types) 622 623 static void handle_a20_line_change(void *opaque, int irq, int level) 624 { 625 X86CPU *cpu = opaque; 626 627 /* XXX: send to all CPUs ? */ 628 /* XXX: add logic to handle multiple A20 line sources */ 629 x86_cpu_set_a20(cpu, level); 630 } 631 632 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 633 { 634 int index = le32_to_cpu(e820_reserve.count); 635 struct e820_entry *entry; 636 637 if (type != E820_RAM) { 638 /* old FW_CFG_E820_TABLE entry -- reservations only */ 639 if (index >= E820_NR_ENTRIES) { 640 return -EBUSY; 641 } 642 entry = &e820_reserve.entry[index++]; 643 644 entry->address = cpu_to_le64(address); 645 entry->length = cpu_to_le64(length); 646 entry->type = cpu_to_le32(type); 647 648 e820_reserve.count = cpu_to_le32(index); 649 } 650 651 /* new "etc/e820" file -- include ram too */ 652 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 653 e820_table[e820_entries].address = cpu_to_le64(address); 654 e820_table[e820_entries].length = cpu_to_le64(length); 655 e820_table[e820_entries].type = cpu_to_le32(type); 656 e820_entries++; 657 658 return e820_entries; 659 } 660 661 int e820_get_num_entries(void) 662 { 663 return e820_entries; 664 } 665 666 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 667 { 668 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 669 *address = le64_to_cpu(e820_table[idx].address); 670 *length = le64_to_cpu(e820_table[idx].length); 671 return true; 672 } 673 return false; 674 } 675 676 /* Enables contiguous-apic-ID mode, for compatibility */ 677 static bool compat_apic_id_mode; 678 679 void enable_compat_apic_id_mode(void) 680 { 681 compat_apic_id_mode = true; 682 } 683 684 /* Calculates initial APIC ID for a specific CPU index 685 * 686 * Currently we need to be able to calculate the APIC ID from the CPU index 687 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 688 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 689 * all CPUs up to max_cpus. 690 */ 691 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 692 { 693 uint32_t correct_id; 694 static bool warned; 695 696 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 697 if (compat_apic_id_mode) { 698 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 699 error_report("APIC IDs set in compatibility mode, " 700 "CPU topology won't match the configuration"); 701 warned = true; 702 } 703 return cpu_index; 704 } else { 705 return correct_id; 706 } 707 } 708 709 /* Calculates the limit to CPU APIC ID values 710 * 711 * This function returns the limit for the APIC ID value, so that all 712 * CPU APIC IDs are < pc_apic_id_limit(). 713 * 714 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 715 */ 716 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 717 { 718 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 719 } 720 721 static FWCfgState *bochs_bios_init(void) 722 { 723 FWCfgState *fw_cfg; 724 uint8_t *smbios_tables, *smbios_anchor; 725 size_t smbios_tables_len, smbios_anchor_len; 726 uint64_t *numa_fw_cfg; 727 int i, j; 728 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 729 730 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 731 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 732 * 733 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 734 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 735 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 736 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 737 * may see". 738 * 739 * So, this means we must not use max_cpus, here, but the maximum possible 740 * APIC ID value, plus one. 741 * 742 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 743 * the APIC ID, not the "CPU index" 744 */ 745 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 746 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 747 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 748 acpi_tables, acpi_tables_len); 749 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 750 751 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 752 if (smbios_tables) { 753 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 754 smbios_tables, smbios_tables_len); 755 } 756 757 smbios_get_tables(&smbios_tables, &smbios_tables_len, 758 &smbios_anchor, &smbios_anchor_len); 759 if (smbios_anchor) { 760 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 761 smbios_tables, smbios_tables_len); 762 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 763 smbios_anchor, smbios_anchor_len); 764 } 765 766 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 767 &e820_reserve, sizeof(e820_reserve)); 768 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 769 sizeof(struct e820_entry) * e820_entries); 770 771 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 772 /* allocate memory for the NUMA channel: one (64bit) word for the number 773 * of nodes, one word for each VCPU->node and one word for each node to 774 * hold the amount of memory. 775 */ 776 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 777 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 778 for (i = 0; i < max_cpus; i++) { 779 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 780 assert(apic_id < apic_id_limit); 781 for (j = 0; j < nb_numa_nodes; j++) { 782 if (test_bit(i, numa_info[j].node_cpu)) { 783 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 784 break; 785 } 786 } 787 } 788 for (i = 0; i < nb_numa_nodes; i++) { 789 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 790 } 791 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 792 (1 + apic_id_limit + nb_numa_nodes) * 793 sizeof(*numa_fw_cfg)); 794 795 return fw_cfg; 796 } 797 798 static long get_file_size(FILE *f) 799 { 800 long where, size; 801 802 /* XXX: on Unix systems, using fstat() probably makes more sense */ 803 804 where = ftell(f); 805 fseek(f, 0, SEEK_END); 806 size = ftell(f); 807 fseek(f, where, SEEK_SET); 808 809 return size; 810 } 811 812 static void load_linux(FWCfgState *fw_cfg, 813 const char *kernel_filename, 814 const char *initrd_filename, 815 const char *kernel_cmdline, 816 hwaddr max_ram_size) 817 { 818 uint16_t protocol; 819 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 820 uint32_t initrd_max; 821 uint8_t header[8192], *setup, *kernel, *initrd_data; 822 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 823 FILE *f; 824 char *vmode; 825 826 /* Align to 16 bytes as a paranoia measure */ 827 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 828 829 /* load the kernel header */ 830 f = fopen(kernel_filename, "rb"); 831 if (!f || !(kernel_size = get_file_size(f)) || 832 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 833 MIN(ARRAY_SIZE(header), kernel_size)) { 834 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 835 kernel_filename, strerror(errno)); 836 exit(1); 837 } 838 839 /* kernel protocol version */ 840 #if 0 841 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 842 #endif 843 if (ldl_p(header+0x202) == 0x53726448) { 844 protocol = lduw_p(header+0x206); 845 } else { 846 /* This looks like a multiboot kernel. If it is, let's stop 847 treating it like a Linux kernel. */ 848 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 849 kernel_cmdline, kernel_size, header)) { 850 return; 851 } 852 protocol = 0; 853 } 854 855 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 856 /* Low kernel */ 857 real_addr = 0x90000; 858 cmdline_addr = 0x9a000 - cmdline_size; 859 prot_addr = 0x10000; 860 } else if (protocol < 0x202) { 861 /* High but ancient kernel */ 862 real_addr = 0x90000; 863 cmdline_addr = 0x9a000 - cmdline_size; 864 prot_addr = 0x100000; 865 } else { 866 /* High and recent kernel */ 867 real_addr = 0x10000; 868 cmdline_addr = 0x20000; 869 prot_addr = 0x100000; 870 } 871 872 #if 0 873 fprintf(stderr, 874 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 875 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 876 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 877 real_addr, 878 cmdline_addr, 879 prot_addr); 880 #endif 881 882 /* highest address for loading the initrd */ 883 if (protocol >= 0x203) { 884 initrd_max = ldl_p(header+0x22c); 885 } else { 886 initrd_max = 0x37ffffff; 887 } 888 889 if (initrd_max >= max_ram_size - acpi_data_size) { 890 initrd_max = max_ram_size - acpi_data_size - 1; 891 } 892 893 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 894 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 895 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 896 897 if (protocol >= 0x202) { 898 stl_p(header+0x228, cmdline_addr); 899 } else { 900 stw_p(header+0x20, 0xA33F); 901 stw_p(header+0x22, cmdline_addr-real_addr); 902 } 903 904 /* handle vga= parameter */ 905 vmode = strstr(kernel_cmdline, "vga="); 906 if (vmode) { 907 unsigned int video_mode; 908 /* skip "vga=" */ 909 vmode += 4; 910 if (!strncmp(vmode, "normal", 6)) { 911 video_mode = 0xffff; 912 } else if (!strncmp(vmode, "ext", 3)) { 913 video_mode = 0xfffe; 914 } else if (!strncmp(vmode, "ask", 3)) { 915 video_mode = 0xfffd; 916 } else { 917 video_mode = strtol(vmode, NULL, 0); 918 } 919 stw_p(header+0x1fa, video_mode); 920 } 921 922 /* loader type */ 923 /* High nybble = B reserved for QEMU; low nybble is revision number. 924 If this code is substantially changed, you may want to consider 925 incrementing the revision. */ 926 if (protocol >= 0x200) { 927 header[0x210] = 0xB0; 928 } 929 /* heap */ 930 if (protocol >= 0x201) { 931 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 932 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 933 } 934 935 /* load initrd */ 936 if (initrd_filename) { 937 if (protocol < 0x200) { 938 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 939 exit(1); 940 } 941 942 initrd_size = get_image_size(initrd_filename); 943 if (initrd_size < 0) { 944 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 945 initrd_filename, strerror(errno)); 946 exit(1); 947 } 948 949 initrd_addr = (initrd_max-initrd_size) & ~4095; 950 951 initrd_data = g_malloc(initrd_size); 952 load_image(initrd_filename, initrd_data); 953 954 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 955 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 956 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 957 958 stl_p(header+0x218, initrd_addr); 959 stl_p(header+0x21c, initrd_size); 960 } 961 962 /* load kernel and setup */ 963 setup_size = header[0x1f1]; 964 if (setup_size == 0) { 965 setup_size = 4; 966 } 967 setup_size = (setup_size+1)*512; 968 kernel_size -= setup_size; 969 970 setup = g_malloc(setup_size); 971 kernel = g_malloc(kernel_size); 972 fseek(f, 0, SEEK_SET); 973 if (fread(setup, 1, setup_size, f) != setup_size) { 974 fprintf(stderr, "fread() failed\n"); 975 exit(1); 976 } 977 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 978 fprintf(stderr, "fread() failed\n"); 979 exit(1); 980 } 981 fclose(f); 982 memcpy(setup, header, MIN(sizeof(header), setup_size)); 983 984 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 985 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 986 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 987 988 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 989 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 990 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 991 992 option_rom[nb_option_roms].name = "linuxboot.bin"; 993 option_rom[nb_option_roms].bootindex = 0; 994 nb_option_roms++; 995 } 996 997 #define NE2000_NB_MAX 6 998 999 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1000 0x280, 0x380 }; 1001 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1002 1003 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1004 { 1005 static int nb_ne2k = 0; 1006 1007 if (nb_ne2k == NE2000_NB_MAX) 1008 return; 1009 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1010 ne2000_irq[nb_ne2k], nd); 1011 nb_ne2k++; 1012 } 1013 1014 DeviceState *cpu_get_current_apic(void) 1015 { 1016 if (current_cpu) { 1017 X86CPU *cpu = X86_CPU(current_cpu); 1018 return cpu->apic_state; 1019 } else { 1020 return NULL; 1021 } 1022 } 1023 1024 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1025 { 1026 X86CPU *cpu = opaque; 1027 1028 if (level) { 1029 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1030 } 1031 } 1032 1033 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1034 DeviceState *icc_bridge, Error **errp) 1035 { 1036 X86CPU *cpu = NULL; 1037 Error *local_err = NULL; 1038 1039 if (icc_bridge == NULL) { 1040 error_setg(&local_err, "Invalid icc-bridge value"); 1041 goto out; 1042 } 1043 1044 cpu = cpu_x86_create(cpu_model, &local_err); 1045 if (local_err != NULL) { 1046 goto out; 1047 } 1048 1049 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); 1050 1051 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1052 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1053 1054 out: 1055 if (local_err) { 1056 error_propagate(errp, local_err); 1057 object_unref(OBJECT(cpu)); 1058 cpu = NULL; 1059 } 1060 return cpu; 1061 } 1062 1063 static const char *current_cpu_model; 1064 1065 void pc_hot_add_cpu(const int64_t id, Error **errp) 1066 { 1067 DeviceState *icc_bridge; 1068 X86CPU *cpu; 1069 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1070 Error *local_err = NULL; 1071 1072 if (id < 0) { 1073 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1074 return; 1075 } 1076 1077 if (cpu_exists(apic_id)) { 1078 error_setg(errp, "Unable to add CPU: %" PRIi64 1079 ", it already exists", id); 1080 return; 1081 } 1082 1083 if (id >= max_cpus) { 1084 error_setg(errp, "Unable to add CPU: %" PRIi64 1085 ", max allowed: %d", id, max_cpus - 1); 1086 return; 1087 } 1088 1089 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1090 error_setg(errp, "Unable to add CPU: %" PRIi64 1091 ", resulting APIC ID (%" PRIi64 ") is too large", 1092 id, apic_id); 1093 return; 1094 } 1095 1096 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1097 TYPE_ICC_BRIDGE, NULL)); 1098 cpu = pc_new_cpu(current_cpu_model, apic_id, icc_bridge, &local_err); 1099 if (local_err) { 1100 error_propagate(errp, local_err); 1101 return; 1102 } 1103 object_unref(OBJECT(cpu)); 1104 } 1105 1106 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1107 { 1108 int i; 1109 X86CPU *cpu = NULL; 1110 Error *error = NULL; 1111 unsigned long apic_id_limit; 1112 1113 /* init CPUs */ 1114 if (cpu_model == NULL) { 1115 #ifdef TARGET_X86_64 1116 cpu_model = "qemu64"; 1117 #else 1118 cpu_model = "qemu32"; 1119 #endif 1120 } 1121 current_cpu_model = cpu_model; 1122 1123 apic_id_limit = pc_apic_id_limit(max_cpus); 1124 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1125 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1126 apic_id_limit - 1); 1127 exit(1); 1128 } 1129 1130 for (i = 0; i < smp_cpus; i++) { 1131 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1132 icc_bridge, &error); 1133 if (error) { 1134 error_report_err(error); 1135 exit(1); 1136 } 1137 object_unref(OBJECT(cpu)); 1138 } 1139 1140 /* map APIC MMIO area if CPU has APIC */ 1141 if (cpu && cpu->apic_state) { 1142 /* XXX: what if the base changes? */ 1143 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1144 APIC_DEFAULT_ADDRESS, 0x1000); 1145 } 1146 1147 /* tell smbios about cpuid version and features */ 1148 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1149 } 1150 1151 /* pci-info ROM file. Little endian format */ 1152 typedef struct PcRomPciInfo { 1153 uint64_t w32_min; 1154 uint64_t w32_max; 1155 uint64_t w64_min; 1156 uint64_t w64_max; 1157 } PcRomPciInfo; 1158 1159 typedef struct PcGuestInfoState { 1160 PcGuestInfo info; 1161 Notifier machine_done; 1162 } PcGuestInfoState; 1163 1164 static 1165 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1166 { 1167 PcGuestInfoState *guest_info_state = container_of(notifier, 1168 PcGuestInfoState, 1169 machine_done); 1170 PCIBus *bus = find_i440fx(); 1171 1172 if (bus) { 1173 int extra_hosts = 0; 1174 1175 QLIST_FOREACH(bus, &bus->child, sibling) { 1176 /* look for expander root buses */ 1177 if (pci_bus_is_root(bus)) { 1178 extra_hosts++; 1179 } 1180 } 1181 if (extra_hosts && guest_info_state->info.fw_cfg) { 1182 uint64_t *val = g_malloc(sizeof(*val)); 1183 *val = cpu_to_le64(extra_hosts); 1184 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1185 "etc/extra-pci-roots", val, sizeof(*val)); 1186 } 1187 } 1188 1189 acpi_setup(&guest_info_state->info); 1190 } 1191 1192 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1193 ram_addr_t above_4g_mem_size) 1194 { 1195 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1196 PcGuestInfo *guest_info = &guest_info_state->info; 1197 int i, j; 1198 1199 guest_info->ram_size_below_4g = below_4g_mem_size; 1200 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1201 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1202 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1203 guest_info->numa_nodes = nb_numa_nodes; 1204 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1205 sizeof *guest_info->node_mem); 1206 for (i = 0; i < nb_numa_nodes; i++) { 1207 guest_info->node_mem[i] = numa_info[i].node_mem; 1208 } 1209 1210 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1211 sizeof *guest_info->node_cpu); 1212 1213 for (i = 0; i < max_cpus; i++) { 1214 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1215 assert(apic_id < guest_info->apic_id_limit); 1216 for (j = 0; j < nb_numa_nodes; j++) { 1217 if (test_bit(i, numa_info[j].node_cpu)) { 1218 guest_info->node_cpu[apic_id] = j; 1219 break; 1220 } 1221 } 1222 } 1223 1224 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1225 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1226 return guest_info; 1227 } 1228 1229 /* setup pci memory address space mapping into system address space */ 1230 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1231 MemoryRegion *pci_address_space) 1232 { 1233 /* Set to lower priority than RAM */ 1234 memory_region_add_subregion_overlap(system_memory, 0x0, 1235 pci_address_space, -1); 1236 } 1237 1238 void pc_acpi_init(const char *default_dsdt) 1239 { 1240 char *filename; 1241 1242 if (acpi_tables != NULL) { 1243 /* manually set via -acpitable, leave it alone */ 1244 return; 1245 } 1246 1247 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1248 if (filename == NULL) { 1249 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1250 } else { 1251 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1252 &error_abort); 1253 Error *err = NULL; 1254 1255 qemu_opt_set(opts, "file", filename, &error_abort); 1256 1257 acpi_table_add_builtin(opts, &err); 1258 if (err) { 1259 error_report("WARNING: failed to load %s: %s", filename, 1260 error_get_pretty(err)); 1261 error_free(err); 1262 } 1263 g_free(filename); 1264 } 1265 } 1266 1267 FWCfgState *xen_load_linux(const char *kernel_filename, 1268 const char *kernel_cmdline, 1269 const char *initrd_filename, 1270 ram_addr_t below_4g_mem_size, 1271 PcGuestInfo *guest_info) 1272 { 1273 int i; 1274 FWCfgState *fw_cfg; 1275 1276 assert(kernel_filename != NULL); 1277 1278 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1279 rom_set_fw(fw_cfg); 1280 1281 load_linux(fw_cfg, kernel_filename, initrd_filename, 1282 kernel_cmdline, below_4g_mem_size); 1283 for (i = 0; i < nb_option_roms; i++) { 1284 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1285 !strcmp(option_rom[i].name, "multiboot.bin")); 1286 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1287 } 1288 guest_info->fw_cfg = fw_cfg; 1289 return fw_cfg; 1290 } 1291 1292 FWCfgState *pc_memory_init(MachineState *machine, 1293 MemoryRegion *system_memory, 1294 ram_addr_t below_4g_mem_size, 1295 ram_addr_t above_4g_mem_size, 1296 MemoryRegion *rom_memory, 1297 MemoryRegion **ram_memory, 1298 PcGuestInfo *guest_info) 1299 { 1300 int linux_boot, i; 1301 MemoryRegion *ram, *option_rom_mr; 1302 MemoryRegion *ram_below_4g, *ram_above_4g; 1303 FWCfgState *fw_cfg; 1304 PCMachineState *pcms = PC_MACHINE(machine); 1305 1306 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1307 1308 linux_boot = (machine->kernel_filename != NULL); 1309 1310 /* Allocate RAM. We allocate it as a single memory region and use 1311 * aliases to address portions of it, mostly for backwards compatibility 1312 * with older qemus that used qemu_ram_alloc(). 1313 */ 1314 ram = g_malloc(sizeof(*ram)); 1315 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1316 machine->ram_size); 1317 *ram_memory = ram; 1318 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1319 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1320 0, below_4g_mem_size); 1321 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1322 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1323 if (above_4g_mem_size > 0) { 1324 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1325 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1326 below_4g_mem_size, above_4g_mem_size); 1327 memory_region_add_subregion(system_memory, 0x100000000ULL, 1328 ram_above_4g); 1329 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1330 } 1331 1332 if (!guest_info->has_reserved_memory && 1333 (machine->ram_slots || 1334 (machine->maxram_size > machine->ram_size))) { 1335 MachineClass *mc = MACHINE_GET_CLASS(machine); 1336 1337 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1338 mc->name); 1339 exit(EXIT_FAILURE); 1340 } 1341 1342 /* initialize hotplug memory address space */ 1343 if (guest_info->has_reserved_memory && 1344 (machine->ram_size < machine->maxram_size)) { 1345 ram_addr_t hotplug_mem_size = 1346 machine->maxram_size - machine->ram_size; 1347 1348 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1349 error_report("unsupported amount of memory slots: %"PRIu64, 1350 machine->ram_slots); 1351 exit(EXIT_FAILURE); 1352 } 1353 1354 if (QEMU_ALIGN_UP(machine->maxram_size, 1355 TARGET_PAGE_SIZE) != machine->maxram_size) { 1356 error_report("maximum memory size must by aligned to multiple of " 1357 "%d bytes", TARGET_PAGE_SIZE); 1358 exit(EXIT_FAILURE); 1359 } 1360 1361 pcms->hotplug_memory.base = 1362 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1363 1364 if (pcms->enforce_aligned_dimm) { 1365 /* size hotplug region assuming 1G page max alignment per slot */ 1366 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1367 } 1368 1369 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1370 hotplug_mem_size) { 1371 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1372 machine->maxram_size); 1373 exit(EXIT_FAILURE); 1374 } 1375 1376 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1377 "hotplug-memory", hotplug_mem_size); 1378 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1379 &pcms->hotplug_memory.mr); 1380 } 1381 1382 /* Initialize PC system firmware */ 1383 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1384 1385 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1386 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1387 &error_abort); 1388 vmstate_register_ram_global(option_rom_mr); 1389 memory_region_add_subregion_overlap(rom_memory, 1390 PC_ROM_MIN_VGA, 1391 option_rom_mr, 1392 1); 1393 1394 fw_cfg = bochs_bios_init(); 1395 rom_set_fw(fw_cfg); 1396 1397 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1398 uint64_t *val = g_malloc(sizeof(*val)); 1399 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory.base, 0x1ULL << 30)); 1400 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1401 } 1402 1403 if (linux_boot) { 1404 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1405 machine->kernel_cmdline, below_4g_mem_size); 1406 } 1407 1408 for (i = 0; i < nb_option_roms; i++) { 1409 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1410 } 1411 guest_info->fw_cfg = fw_cfg; 1412 return fw_cfg; 1413 } 1414 1415 qemu_irq pc_allocate_cpu_irq(void) 1416 { 1417 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1418 } 1419 1420 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1421 { 1422 DeviceState *dev = NULL; 1423 1424 if (pci_bus) { 1425 PCIDevice *pcidev = pci_vga_init(pci_bus); 1426 dev = pcidev ? &pcidev->qdev : NULL; 1427 } else if (isa_bus) { 1428 ISADevice *isadev = isa_vga_init(isa_bus); 1429 dev = isadev ? DEVICE(isadev) : NULL; 1430 } 1431 return dev; 1432 } 1433 1434 static void cpu_request_exit(void *opaque, int irq, int level) 1435 { 1436 CPUState *cpu = current_cpu; 1437 1438 if (cpu && level) { 1439 cpu_exit(cpu); 1440 } 1441 } 1442 1443 static const MemoryRegionOps ioport80_io_ops = { 1444 .write = ioport80_write, 1445 .read = ioport80_read, 1446 .endianness = DEVICE_NATIVE_ENDIAN, 1447 .impl = { 1448 .min_access_size = 1, 1449 .max_access_size = 1, 1450 }, 1451 }; 1452 1453 static const MemoryRegionOps ioportF0_io_ops = { 1454 .write = ioportF0_write, 1455 .read = ioportF0_read, 1456 .endianness = DEVICE_NATIVE_ENDIAN, 1457 .impl = { 1458 .min_access_size = 1, 1459 .max_access_size = 1, 1460 }, 1461 }; 1462 1463 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1464 ISADevice **rtc_state, 1465 bool create_fdctrl, 1466 bool no_vmport, 1467 uint32 hpet_irqs) 1468 { 1469 int i; 1470 DriveInfo *fd[MAX_FD]; 1471 DeviceState *hpet = NULL; 1472 int pit_isa_irq = 0; 1473 qemu_irq pit_alt_irq = NULL; 1474 qemu_irq rtc_irq = NULL; 1475 qemu_irq *a20_line; 1476 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1477 qemu_irq *cpu_exit_irq; 1478 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1479 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1480 1481 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1482 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1483 1484 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1485 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1486 1487 /* 1488 * Check if an HPET shall be created. 1489 * 1490 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1491 * when the HPET wants to take over. Thus we have to disable the latter. 1492 */ 1493 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1494 /* In order to set property, here not using sysbus_try_create_simple */ 1495 hpet = qdev_try_create(NULL, TYPE_HPET); 1496 if (hpet) { 1497 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1498 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1499 * IRQ8 and IRQ2. 1500 */ 1501 uint8_t compat = object_property_get_int(OBJECT(hpet), 1502 HPET_INTCAP, NULL); 1503 if (!compat) { 1504 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1505 } 1506 qdev_init_nofail(hpet); 1507 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1508 1509 for (i = 0; i < GSI_NUM_PINS; i++) { 1510 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1511 } 1512 pit_isa_irq = -1; 1513 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1514 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1515 } 1516 } 1517 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1518 1519 qemu_register_boot_set(pc_boot_set, *rtc_state); 1520 1521 if (!xen_enabled()) { 1522 if (kvm_irqchip_in_kernel()) { 1523 pit = kvm_pit_init(isa_bus, 0x40); 1524 } else { 1525 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1526 } 1527 if (hpet) { 1528 /* connect PIT to output control line of the HPET */ 1529 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1530 } 1531 pcspk_init(isa_bus, pit); 1532 } 1533 1534 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1535 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1536 1537 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1538 i8042 = isa_create_simple(isa_bus, "i8042"); 1539 i8042_setup_a20_line(i8042, &a20_line[0]); 1540 if (!no_vmport) { 1541 vmport_init(isa_bus); 1542 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1543 } else { 1544 vmmouse = NULL; 1545 } 1546 if (vmmouse) { 1547 DeviceState *dev = DEVICE(vmmouse); 1548 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1549 qdev_init_nofail(dev); 1550 } 1551 port92 = isa_create_simple(isa_bus, "port92"); 1552 port92_init(port92, &a20_line[1]); 1553 1554 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1555 DMA_init(0, cpu_exit_irq); 1556 1557 for(i = 0; i < MAX_FD; i++) { 1558 fd[i] = drive_get(IF_FLOPPY, 0, i); 1559 create_fdctrl |= !!fd[i]; 1560 } 1561 if (create_fdctrl) { 1562 fdctrl_init_isa(isa_bus, fd); 1563 } 1564 } 1565 1566 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1567 { 1568 int i; 1569 1570 for (i = 0; i < nb_nics; i++) { 1571 NICInfo *nd = &nd_table[i]; 1572 1573 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1574 pc_init_ne2k_isa(isa_bus, nd); 1575 } else { 1576 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1577 } 1578 } 1579 } 1580 1581 void pc_pci_device_init(PCIBus *pci_bus) 1582 { 1583 int max_bus; 1584 int bus; 1585 1586 max_bus = drive_get_max_bus(IF_SCSI); 1587 for (bus = 0; bus <= max_bus; bus++) { 1588 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1589 } 1590 } 1591 1592 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1593 { 1594 DeviceState *dev; 1595 SysBusDevice *d; 1596 unsigned int i; 1597 1598 if (kvm_irqchip_in_kernel()) { 1599 dev = qdev_create(NULL, "kvm-ioapic"); 1600 } else { 1601 dev = qdev_create(NULL, "ioapic"); 1602 } 1603 if (parent_name) { 1604 object_property_add_child(object_resolve_path(parent_name, NULL), 1605 "ioapic", OBJECT(dev), NULL); 1606 } 1607 qdev_init_nofail(dev); 1608 d = SYS_BUS_DEVICE(dev); 1609 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1610 1611 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1612 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1613 } 1614 } 1615 1616 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1617 DeviceState *dev, Error **errp) 1618 { 1619 HotplugHandlerClass *hhc; 1620 Error *local_err = NULL; 1621 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1622 PCDIMMDevice *dimm = PC_DIMM(dev); 1623 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1624 MemoryRegion *mr = ddc->get_memory_region(dimm); 1625 uint64_t align = TARGET_PAGE_SIZE; 1626 1627 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1628 align = memory_region_get_alignment(mr); 1629 } 1630 1631 if (!pcms->acpi_dev) { 1632 error_setg(&local_err, 1633 "memory hotplug is not enabled: missing acpi device"); 1634 goto out; 1635 } 1636 1637 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1638 if (local_err) { 1639 goto out; 1640 } 1641 1642 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1643 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1644 out: 1645 error_propagate(errp, local_err); 1646 } 1647 1648 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1649 DeviceState *dev, Error **errp) 1650 { 1651 HotplugHandlerClass *hhc; 1652 Error *local_err = NULL; 1653 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1654 1655 if (!pcms->acpi_dev) { 1656 error_setg(&local_err, 1657 "memory hotplug is not enabled: missing acpi device"); 1658 goto out; 1659 } 1660 1661 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1662 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1663 1664 out: 1665 error_propagate(errp, local_err); 1666 } 1667 1668 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1669 DeviceState *dev, Error **errp) 1670 { 1671 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1672 PCDIMMDevice *dimm = PC_DIMM(dev); 1673 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1674 MemoryRegion *mr = ddc->get_memory_region(dimm); 1675 HotplugHandlerClass *hhc; 1676 Error *local_err = NULL; 1677 1678 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1679 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1680 1681 if (local_err) { 1682 goto out; 1683 } 1684 1685 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1686 object_unparent(OBJECT(dev)); 1687 1688 out: 1689 error_propagate(errp, local_err); 1690 } 1691 1692 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1693 DeviceState *dev, Error **errp) 1694 { 1695 HotplugHandlerClass *hhc; 1696 Error *local_err = NULL; 1697 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1698 1699 if (!dev->hotplugged) { 1700 goto out; 1701 } 1702 1703 if (!pcms->acpi_dev) { 1704 error_setg(&local_err, 1705 "cpu hotplug is not enabled: missing acpi device"); 1706 goto out; 1707 } 1708 1709 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1710 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1711 if (local_err) { 1712 goto out; 1713 } 1714 1715 /* increment the number of CPUs */ 1716 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1717 out: 1718 error_propagate(errp, local_err); 1719 } 1720 1721 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1722 DeviceState *dev, Error **errp) 1723 { 1724 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1725 pc_dimm_plug(hotplug_dev, dev, errp); 1726 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1727 pc_cpu_plug(hotplug_dev, dev, errp); 1728 } 1729 } 1730 1731 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1732 DeviceState *dev, Error **errp) 1733 { 1734 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1735 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1736 } else { 1737 error_setg(errp, "acpi: device unplug request for not supported device" 1738 " type: %s", object_get_typename(OBJECT(dev))); 1739 } 1740 } 1741 1742 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1743 DeviceState *dev, Error **errp) 1744 { 1745 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1746 pc_dimm_unplug(hotplug_dev, dev, errp); 1747 } else { 1748 error_setg(errp, "acpi: device unplug for not supported device" 1749 " type: %s", object_get_typename(OBJECT(dev))); 1750 } 1751 } 1752 1753 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1754 DeviceState *dev) 1755 { 1756 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1757 1758 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1759 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1760 return HOTPLUG_HANDLER(machine); 1761 } 1762 1763 return pcmc->get_hotplug_handler ? 1764 pcmc->get_hotplug_handler(machine, dev) : NULL; 1765 } 1766 1767 static void 1768 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1769 const char *name, Error **errp) 1770 { 1771 PCMachineState *pcms = PC_MACHINE(obj); 1772 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1773 1774 visit_type_int(v, &value, name, errp); 1775 } 1776 1777 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1778 void *opaque, const char *name, 1779 Error **errp) 1780 { 1781 PCMachineState *pcms = PC_MACHINE(obj); 1782 uint64_t value = pcms->max_ram_below_4g; 1783 1784 visit_type_size(v, &value, name, errp); 1785 } 1786 1787 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1788 void *opaque, const char *name, 1789 Error **errp) 1790 { 1791 PCMachineState *pcms = PC_MACHINE(obj); 1792 Error *error = NULL; 1793 uint64_t value; 1794 1795 visit_type_size(v, &value, name, &error); 1796 if (error) { 1797 error_propagate(errp, error); 1798 return; 1799 } 1800 if (value > (1ULL << 32)) { 1801 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1802 "Machine option 'max-ram-below-4g=%"PRIu64 1803 "' expects size less than or equal to 4G", value); 1804 error_propagate(errp, error); 1805 return; 1806 } 1807 1808 if (value < (1ULL << 20)) { 1809 error_report("Warning: small max_ram_below_4g(%"PRIu64 1810 ") less than 1M. BIOS may not work..", 1811 value); 1812 } 1813 1814 pcms->max_ram_below_4g = value; 1815 } 1816 1817 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1818 const char *name, Error **errp) 1819 { 1820 PCMachineState *pcms = PC_MACHINE(obj); 1821 OnOffAuto vmport = pcms->vmport; 1822 1823 visit_type_OnOffAuto(v, &vmport, name, errp); 1824 } 1825 1826 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1827 const char *name, Error **errp) 1828 { 1829 PCMachineState *pcms = PC_MACHINE(obj); 1830 1831 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1832 } 1833 1834 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1835 { 1836 bool smm_available = false; 1837 1838 if (pcms->smm == ON_OFF_AUTO_OFF) { 1839 return false; 1840 } 1841 1842 if (tcg_enabled() || qtest_enabled()) { 1843 smm_available = true; 1844 } else if (kvm_enabled()) { 1845 smm_available = kvm_has_smm(); 1846 } 1847 1848 if (smm_available) { 1849 return true; 1850 } 1851 1852 if (pcms->smm == ON_OFF_AUTO_ON) { 1853 error_report("System Management Mode not supported by this hypervisor."); 1854 exit(1); 1855 } 1856 return false; 1857 } 1858 1859 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1860 const char *name, Error **errp) 1861 { 1862 PCMachineState *pcms = PC_MACHINE(obj); 1863 OnOffAuto smm = pcms->smm; 1864 1865 visit_type_OnOffAuto(v, &smm, name, errp); 1866 } 1867 1868 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1869 const char *name, Error **errp) 1870 { 1871 PCMachineState *pcms = PC_MACHINE(obj); 1872 1873 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1874 } 1875 1876 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1877 { 1878 PCMachineState *pcms = PC_MACHINE(obj); 1879 1880 return pcms->enforce_aligned_dimm; 1881 } 1882 1883 static void pc_machine_initfn(Object *obj) 1884 { 1885 PCMachineState *pcms = PC_MACHINE(obj); 1886 1887 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1888 pc_machine_get_hotplug_memory_region_size, 1889 NULL, NULL, NULL, NULL); 1890 1891 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1892 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1893 pc_machine_get_max_ram_below_4g, 1894 pc_machine_set_max_ram_below_4g, 1895 NULL, NULL, NULL); 1896 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1897 "Maximum ram below the 4G boundary (32bit boundary)", 1898 NULL); 1899 1900 pcms->smm = ON_OFF_AUTO_AUTO; 1901 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1902 pc_machine_get_smm, 1903 pc_machine_set_smm, 1904 NULL, NULL, NULL); 1905 object_property_set_description(obj, PC_MACHINE_SMM, 1906 "Enable SMM (pc & q35)", 1907 NULL); 1908 1909 pcms->vmport = ON_OFF_AUTO_AUTO; 1910 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1911 pc_machine_get_vmport, 1912 pc_machine_set_vmport, 1913 NULL, NULL, NULL); 1914 object_property_set_description(obj, PC_MACHINE_VMPORT, 1915 "Enable vmport (pc & q35)", 1916 NULL); 1917 1918 pcms->enforce_aligned_dimm = true; 1919 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1920 pc_machine_get_aligned_dimm, 1921 NULL, NULL); 1922 } 1923 1924 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1925 { 1926 unsigned pkg_id, core_id, smt_id; 1927 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1928 &pkg_id, &core_id, &smt_id); 1929 return pkg_id; 1930 } 1931 1932 static void pc_machine_class_init(ObjectClass *oc, void *data) 1933 { 1934 MachineClass *mc = MACHINE_CLASS(oc); 1935 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1936 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1937 1938 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1939 mc->get_hotplug_handler = pc_get_hotpug_handler; 1940 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1941 hc->plug = pc_machine_device_plug_cb; 1942 hc->unplug_request = pc_machine_device_unplug_request_cb; 1943 hc->unplug = pc_machine_device_unplug_cb; 1944 } 1945 1946 static const TypeInfo pc_machine_info = { 1947 .name = TYPE_PC_MACHINE, 1948 .parent = TYPE_MACHINE, 1949 .abstract = true, 1950 .instance_size = sizeof(PCMachineState), 1951 .instance_init = pc_machine_initfn, 1952 .class_size = sizeof(PCMachineClass), 1953 .class_init = pc_machine_class_init, 1954 .interfaces = (InterfaceInfo[]) { 1955 { TYPE_HOTPLUG_HANDLER }, 1956 { } 1957 }, 1958 }; 1959 1960 static void pc_machine_register_types(void) 1961 { 1962 type_register_static(&pc_machine_info); 1963 } 1964 1965 type_init(pc_machine_register_types) 1966