1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/topology.h" 30 #include "sysemu/cpus.h" 31 #include "hw/block/fdc.h" 32 #include "hw/ide.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_bus.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/smbios/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "hw/acpi/acpi.h" 62 #include "hw/acpi/cpu_hotplug.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 #include "qom/cpu.h" 70 #include "hw/nmi.h" 71 72 /* debug PC/ISA interrupts */ 73 //#define DEBUG_IRQ 74 75 #ifdef DEBUG_IRQ 76 #define DPRINTF(fmt, ...) \ 77 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 78 #else 79 #define DPRINTF(fmt, ...) 80 #endif 81 82 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 83 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 84 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 85 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 86 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 87 88 #define E820_NR_ENTRIES 16 89 90 struct e820_entry { 91 uint64_t address; 92 uint64_t length; 93 uint32_t type; 94 } QEMU_PACKED __attribute((__aligned__(4))); 95 96 struct e820_table { 97 uint32_t count; 98 struct e820_entry entry[E820_NR_ENTRIES]; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 static struct e820_table e820_reserve; 102 static struct e820_entry *e820_table; 103 static unsigned e820_entries; 104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 105 106 void gsi_handler(void *opaque, int n, int level) 107 { 108 GSIState *s = opaque; 109 110 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 111 if (n < ISA_NUM_IRQS) { 112 qemu_set_irq(s->i8259_irq[n], level); 113 } 114 qemu_set_irq(s->ioapic_irq[n], level); 115 } 116 117 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 118 unsigned size) 119 { 120 } 121 122 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 123 { 124 return 0xffffffffffffffffULL; 125 } 126 127 /* MSDOS compatibility mode FPU exception support */ 128 static qemu_irq ferr_irq; 129 130 void pc_register_ferr_irq(qemu_irq irq) 131 { 132 ferr_irq = irq; 133 } 134 135 /* XXX: add IGNNE support */ 136 void cpu_set_ferr(CPUX86State *s) 137 { 138 qemu_irq_raise(ferr_irq); 139 } 140 141 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 142 unsigned size) 143 { 144 qemu_irq_lower(ferr_irq); 145 } 146 147 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 148 { 149 return 0xffffffffffffffffULL; 150 } 151 152 /* TSC handling */ 153 uint64_t cpu_get_tsc(CPUX86State *env) 154 { 155 return cpu_get_ticks(); 156 } 157 158 /* IRQ handling */ 159 int cpu_get_pic_interrupt(CPUX86State *env) 160 { 161 X86CPU *cpu = x86_env_get_cpu(env); 162 int intno; 163 164 if (!kvm_irqchip_in_kernel()) { 165 intno = apic_get_interrupt(cpu->apic_state); 166 if (intno >= 0) { 167 return intno; 168 } 169 /* read the irq from the PIC */ 170 if (!apic_accept_pic_intr(cpu->apic_state)) { 171 return -1; 172 } 173 } 174 175 intno = pic_read_irq(isa_pic); 176 return intno; 177 } 178 179 static void pic_irq_request(void *opaque, int irq, int level) 180 { 181 CPUState *cs = first_cpu; 182 X86CPU *cpu = X86_CPU(cs); 183 184 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 185 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 186 CPU_FOREACH(cs) { 187 cpu = X86_CPU(cs); 188 if (apic_accept_pic_intr(cpu->apic_state)) { 189 apic_deliver_pic_intr(cpu->apic_state, level); 190 } 191 } 192 } else { 193 if (level) { 194 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 195 } else { 196 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 197 } 198 } 199 } 200 201 /* PC cmos mappings */ 202 203 #define REG_EQUIPMENT_BYTE 0x14 204 205 int cmos_get_fd_drive_type(FloppyDriveType fd0) 206 { 207 int val; 208 209 switch (fd0) { 210 case FLOPPY_DRIVE_TYPE_144: 211 /* 1.44 Mb 3"5 drive */ 212 val = 4; 213 break; 214 case FLOPPY_DRIVE_TYPE_288: 215 /* 2.88 Mb 3"5 drive */ 216 val = 5; 217 break; 218 case FLOPPY_DRIVE_TYPE_120: 219 /* 1.2 Mb 5"5 drive */ 220 val = 2; 221 break; 222 case FLOPPY_DRIVE_TYPE_NONE: 223 default: 224 val = 0; 225 break; 226 } 227 return val; 228 } 229 230 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 231 int16_t cylinders, int8_t heads, int8_t sectors) 232 { 233 rtc_set_memory(s, type_ofs, 47); 234 rtc_set_memory(s, info_ofs, cylinders); 235 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 236 rtc_set_memory(s, info_ofs + 2, heads); 237 rtc_set_memory(s, info_ofs + 3, 0xff); 238 rtc_set_memory(s, info_ofs + 4, 0xff); 239 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 240 rtc_set_memory(s, info_ofs + 6, cylinders); 241 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 242 rtc_set_memory(s, info_ofs + 8, sectors); 243 } 244 245 /* convert boot_device letter to something recognizable by the bios */ 246 static int boot_device2nibble(char boot_device) 247 { 248 switch(boot_device) { 249 case 'a': 250 case 'b': 251 return 0x01; /* floppy boot */ 252 case 'c': 253 return 0x02; /* hard drive boot */ 254 case 'd': 255 return 0x03; /* CD-ROM boot */ 256 case 'n': 257 return 0x04; /* Network boot */ 258 } 259 return 0; 260 } 261 262 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 263 { 264 #define PC_MAX_BOOT_DEVICES 3 265 int nbds, bds[3] = { 0, }; 266 int i; 267 268 nbds = strlen(boot_device); 269 if (nbds > PC_MAX_BOOT_DEVICES) { 270 error_setg(errp, "Too many boot devices for PC"); 271 return; 272 } 273 for (i = 0; i < nbds; i++) { 274 bds[i] = boot_device2nibble(boot_device[i]); 275 if (bds[i] == 0) { 276 error_setg(errp, "Invalid boot device for PC: '%c'", 277 boot_device[i]); 278 return; 279 } 280 } 281 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 282 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 283 } 284 285 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 286 { 287 set_boot_dev(opaque, boot_device, errp); 288 } 289 290 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 291 { 292 int val, nb, i; 293 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 294 FLOPPY_DRIVE_TYPE_NONE }; 295 296 /* floppy type */ 297 if (floppy) { 298 for (i = 0; i < 2; i++) { 299 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 300 } 301 } 302 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 303 cmos_get_fd_drive_type(fd_type[1]); 304 rtc_set_memory(rtc_state, 0x10, val); 305 306 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 307 nb = 0; 308 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 309 nb++; 310 } 311 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 312 nb++; 313 } 314 switch (nb) { 315 case 0: 316 break; 317 case 1: 318 val |= 0x01; /* 1 drive, ready for boot */ 319 break; 320 case 2: 321 val |= 0x41; /* 2 drives, ready for boot */ 322 break; 323 } 324 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 325 } 326 327 typedef struct pc_cmos_init_late_arg { 328 ISADevice *rtc_state; 329 BusState *idebus[2]; 330 } pc_cmos_init_late_arg; 331 332 typedef struct check_fdc_state { 333 ISADevice *floppy; 334 bool multiple; 335 } CheckFdcState; 336 337 static int check_fdc(Object *obj, void *opaque) 338 { 339 CheckFdcState *state = opaque; 340 Object *fdc; 341 uint32_t iobase; 342 Error *local_err = NULL; 343 344 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 345 if (!fdc) { 346 return 0; 347 } 348 349 iobase = object_property_get_int(obj, "iobase", &local_err); 350 if (local_err || iobase != 0x3f0) { 351 error_free(local_err); 352 return 0; 353 } 354 355 if (state->floppy) { 356 state->multiple = true; 357 } else { 358 state->floppy = ISA_DEVICE(obj); 359 } 360 return 0; 361 } 362 363 static const char * const fdc_container_path[] = { 364 "/unattached", "/peripheral", "/peripheral-anon" 365 }; 366 367 /* 368 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 369 * and ACPI objects. 370 */ 371 ISADevice *pc_find_fdc0(void) 372 { 373 int i; 374 Object *container; 375 CheckFdcState state = { 0 }; 376 377 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 378 container = container_get(qdev_get_machine(), fdc_container_path[i]); 379 object_child_foreach(container, check_fdc, &state); 380 } 381 382 if (state.multiple) { 383 error_report("warning: multiple floppy disk controllers with " 384 "iobase=0x3f0 have been found"); 385 error_printf("the one being picked for CMOS setup might not reflect " 386 "your intent\n"); 387 } 388 389 return state.floppy; 390 } 391 392 static void pc_cmos_init_late(void *opaque) 393 { 394 pc_cmos_init_late_arg *arg = opaque; 395 ISADevice *s = arg->rtc_state; 396 int16_t cylinders; 397 int8_t heads, sectors; 398 int val; 399 int i, trans; 400 401 val = 0; 402 if (ide_get_geometry(arg->idebus[0], 0, 403 &cylinders, &heads, §ors) >= 0) { 404 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 405 val |= 0xf0; 406 } 407 if (ide_get_geometry(arg->idebus[0], 1, 408 &cylinders, &heads, §ors) >= 0) { 409 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 410 val |= 0x0f; 411 } 412 rtc_set_memory(s, 0x12, val); 413 414 val = 0; 415 for (i = 0; i < 4; i++) { 416 /* NOTE: ide_get_geometry() returns the physical 417 geometry. It is always such that: 1 <= sects <= 63, 1 418 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 419 geometry can be different if a translation is done. */ 420 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 421 &cylinders, &heads, §ors) >= 0) { 422 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 423 assert((trans & ~3) == 0); 424 val |= trans << (i * 2); 425 } 426 } 427 rtc_set_memory(s, 0x39, val); 428 429 pc_cmos_init_floppy(s, pc_find_fdc0()); 430 431 qemu_unregister_reset(pc_cmos_init_late, opaque); 432 } 433 434 void pc_cmos_init(PCMachineState *pcms, 435 BusState *idebus0, BusState *idebus1, 436 ISADevice *s) 437 { 438 int val; 439 static pc_cmos_init_late_arg arg; 440 441 /* various important CMOS locations needed by PC/Bochs bios */ 442 443 /* memory size */ 444 /* base memory (first MiB) */ 445 val = MIN(pcms->below_4g_mem_size / 1024, 640); 446 rtc_set_memory(s, 0x15, val); 447 rtc_set_memory(s, 0x16, val >> 8); 448 /* extended memory (next 64MiB) */ 449 if (pcms->below_4g_mem_size > 1024 * 1024) { 450 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 451 } else { 452 val = 0; 453 } 454 if (val > 65535) 455 val = 65535; 456 rtc_set_memory(s, 0x17, val); 457 rtc_set_memory(s, 0x18, val >> 8); 458 rtc_set_memory(s, 0x30, val); 459 rtc_set_memory(s, 0x31, val >> 8); 460 /* memory between 16MiB and 4GiB */ 461 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 462 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 463 } else { 464 val = 0; 465 } 466 if (val > 65535) 467 val = 65535; 468 rtc_set_memory(s, 0x34, val); 469 rtc_set_memory(s, 0x35, val >> 8); 470 /* memory above 4GiB */ 471 val = pcms->above_4g_mem_size / 65536; 472 rtc_set_memory(s, 0x5b, val); 473 rtc_set_memory(s, 0x5c, val >> 8); 474 rtc_set_memory(s, 0x5d, val >> 16); 475 476 object_property_add_link(OBJECT(pcms), "rtc_state", 477 TYPE_ISA_DEVICE, 478 (Object **)&pcms->rtc, 479 object_property_allow_set_link, 480 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 481 object_property_set_link(OBJECT(pcms), OBJECT(s), 482 "rtc_state", &error_abort); 483 484 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 485 486 val = 0; 487 val |= 0x02; /* FPU is there */ 488 val |= 0x04; /* PS/2 mouse installed */ 489 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 490 491 /* hard drives and FDC */ 492 arg.rtc_state = s; 493 arg.idebus[0] = idebus0; 494 arg.idebus[1] = idebus1; 495 qemu_register_reset(pc_cmos_init_late, &arg); 496 } 497 498 #define TYPE_PORT92 "port92" 499 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 500 501 /* port 92 stuff: could be split off */ 502 typedef struct Port92State { 503 ISADevice parent_obj; 504 505 MemoryRegion io; 506 uint8_t outport; 507 qemu_irq a20_out; 508 } Port92State; 509 510 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 511 unsigned size) 512 { 513 Port92State *s = opaque; 514 int oldval = s->outport; 515 516 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 517 s->outport = val; 518 qemu_set_irq(s->a20_out, (val >> 1) & 1); 519 if ((val & 1) && !(oldval & 1)) { 520 qemu_system_reset_request(); 521 } 522 } 523 524 static uint64_t port92_read(void *opaque, hwaddr addr, 525 unsigned size) 526 { 527 Port92State *s = opaque; 528 uint32_t ret; 529 530 ret = s->outport; 531 DPRINTF("port92: read 0x%02x\n", ret); 532 return ret; 533 } 534 535 static void port92_init(ISADevice *dev, qemu_irq a20_out) 536 { 537 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 538 } 539 540 static const VMStateDescription vmstate_port92_isa = { 541 .name = "port92", 542 .version_id = 1, 543 .minimum_version_id = 1, 544 .fields = (VMStateField[]) { 545 VMSTATE_UINT8(outport, Port92State), 546 VMSTATE_END_OF_LIST() 547 } 548 }; 549 550 static void port92_reset(DeviceState *d) 551 { 552 Port92State *s = PORT92(d); 553 554 s->outport &= ~1; 555 } 556 557 static const MemoryRegionOps port92_ops = { 558 .read = port92_read, 559 .write = port92_write, 560 .impl = { 561 .min_access_size = 1, 562 .max_access_size = 1, 563 }, 564 .endianness = DEVICE_LITTLE_ENDIAN, 565 }; 566 567 static void port92_initfn(Object *obj) 568 { 569 Port92State *s = PORT92(obj); 570 571 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 572 573 s->outport = 0; 574 575 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 576 } 577 578 static void port92_realizefn(DeviceState *dev, Error **errp) 579 { 580 ISADevice *isadev = ISA_DEVICE(dev); 581 Port92State *s = PORT92(dev); 582 583 isa_register_ioport(isadev, &s->io, 0x92); 584 } 585 586 static void port92_class_initfn(ObjectClass *klass, void *data) 587 { 588 DeviceClass *dc = DEVICE_CLASS(klass); 589 590 dc->realize = port92_realizefn; 591 dc->reset = port92_reset; 592 dc->vmsd = &vmstate_port92_isa; 593 /* 594 * Reason: unlike ordinary ISA devices, this one needs additional 595 * wiring: its A20 output line needs to be wired up by 596 * port92_init(). 597 */ 598 dc->cannot_instantiate_with_device_add_yet = true; 599 } 600 601 static const TypeInfo port92_info = { 602 .name = TYPE_PORT92, 603 .parent = TYPE_ISA_DEVICE, 604 .instance_size = sizeof(Port92State), 605 .instance_init = port92_initfn, 606 .class_init = port92_class_initfn, 607 }; 608 609 static void port92_register_types(void) 610 { 611 type_register_static(&port92_info); 612 } 613 614 type_init(port92_register_types) 615 616 static void handle_a20_line_change(void *opaque, int irq, int level) 617 { 618 X86CPU *cpu = opaque; 619 620 /* XXX: send to all CPUs ? */ 621 /* XXX: add logic to handle multiple A20 line sources */ 622 x86_cpu_set_a20(cpu, level); 623 } 624 625 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 626 { 627 int index = le32_to_cpu(e820_reserve.count); 628 struct e820_entry *entry; 629 630 if (type != E820_RAM) { 631 /* old FW_CFG_E820_TABLE entry -- reservations only */ 632 if (index >= E820_NR_ENTRIES) { 633 return -EBUSY; 634 } 635 entry = &e820_reserve.entry[index++]; 636 637 entry->address = cpu_to_le64(address); 638 entry->length = cpu_to_le64(length); 639 entry->type = cpu_to_le32(type); 640 641 e820_reserve.count = cpu_to_le32(index); 642 } 643 644 /* new "etc/e820" file -- include ram too */ 645 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 646 e820_table[e820_entries].address = cpu_to_le64(address); 647 e820_table[e820_entries].length = cpu_to_le64(length); 648 e820_table[e820_entries].type = cpu_to_le32(type); 649 e820_entries++; 650 651 return e820_entries; 652 } 653 654 int e820_get_num_entries(void) 655 { 656 return e820_entries; 657 } 658 659 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 660 { 661 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 662 *address = le64_to_cpu(e820_table[idx].address); 663 *length = le64_to_cpu(e820_table[idx].length); 664 return true; 665 } 666 return false; 667 } 668 669 /* Enables contiguous-apic-ID mode, for compatibility */ 670 static bool compat_apic_id_mode; 671 672 void enable_compat_apic_id_mode(void) 673 { 674 compat_apic_id_mode = true; 675 } 676 677 /* Calculates initial APIC ID for a specific CPU index 678 * 679 * Currently we need to be able to calculate the APIC ID from the CPU index 680 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 681 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 682 * all CPUs up to max_cpus. 683 */ 684 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 685 { 686 uint32_t correct_id; 687 static bool warned; 688 689 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 690 if (compat_apic_id_mode) { 691 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 692 error_report("APIC IDs set in compatibility mode, " 693 "CPU topology won't match the configuration"); 694 warned = true; 695 } 696 return cpu_index; 697 } else { 698 return correct_id; 699 } 700 } 701 702 static void pc_build_smbios(FWCfgState *fw_cfg) 703 { 704 uint8_t *smbios_tables, *smbios_anchor; 705 size_t smbios_tables_len, smbios_anchor_len; 706 struct smbios_phys_mem_area *mem_array; 707 unsigned i, array_count; 708 709 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 710 if (smbios_tables) { 711 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 712 smbios_tables, smbios_tables_len); 713 } 714 715 /* build the array of physical mem area from e820 table */ 716 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 717 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 718 uint64_t addr, len; 719 720 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 721 mem_array[array_count].address = addr; 722 mem_array[array_count].length = len; 723 array_count++; 724 } 725 } 726 smbios_get_tables(mem_array, array_count, 727 &smbios_tables, &smbios_tables_len, 728 &smbios_anchor, &smbios_anchor_len); 729 g_free(mem_array); 730 731 if (smbios_anchor) { 732 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 733 smbios_tables, smbios_tables_len); 734 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 735 smbios_anchor, smbios_anchor_len); 736 } 737 } 738 739 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 740 { 741 FWCfgState *fw_cfg; 742 uint64_t *numa_fw_cfg; 743 int i, j; 744 745 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 746 747 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 748 * 749 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 750 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 751 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 752 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 753 * may see". 754 * 755 * So, this means we must not use max_cpus, here, but the maximum possible 756 * APIC ID value, plus one. 757 * 758 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 759 * the APIC ID, not the "CPU index" 760 */ 761 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 762 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 763 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 764 acpi_tables, acpi_tables_len); 765 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 766 767 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 768 &e820_reserve, sizeof(e820_reserve)); 769 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 770 sizeof(struct e820_entry) * e820_entries); 771 772 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 773 /* allocate memory for the NUMA channel: one (64bit) word for the number 774 * of nodes, one word for each VCPU->node and one word for each node to 775 * hold the amount of memory. 776 */ 777 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 778 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 779 for (i = 0; i < max_cpus; i++) { 780 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 781 assert(apic_id < pcms->apic_id_limit); 782 for (j = 0; j < nb_numa_nodes; j++) { 783 if (test_bit(i, numa_info[j].node_cpu)) { 784 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 785 break; 786 } 787 } 788 } 789 for (i = 0; i < nb_numa_nodes; i++) { 790 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 791 cpu_to_le64(numa_info[i].node_mem); 792 } 793 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 794 (1 + pcms->apic_id_limit + nb_numa_nodes) * 795 sizeof(*numa_fw_cfg)); 796 797 return fw_cfg; 798 } 799 800 static long get_file_size(FILE *f) 801 { 802 long where, size; 803 804 /* XXX: on Unix systems, using fstat() probably makes more sense */ 805 806 where = ftell(f); 807 fseek(f, 0, SEEK_END); 808 size = ftell(f); 809 fseek(f, where, SEEK_SET); 810 811 return size; 812 } 813 814 /* setup_data types */ 815 #define SETUP_NONE 0 816 #define SETUP_E820_EXT 1 817 #define SETUP_DTB 2 818 #define SETUP_PCI 3 819 #define SETUP_EFI 4 820 821 struct setup_data { 822 uint64_t next; 823 uint32_t type; 824 uint32_t len; 825 uint8_t data[0]; 826 } __attribute__((packed)); 827 828 static void load_linux(PCMachineState *pcms, 829 FWCfgState *fw_cfg) 830 { 831 uint16_t protocol; 832 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 833 int dtb_size, setup_data_offset; 834 uint32_t initrd_max; 835 uint8_t header[8192], *setup, *kernel, *initrd_data; 836 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 837 FILE *f; 838 char *vmode; 839 MachineState *machine = MACHINE(pcms); 840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 841 struct setup_data *setup_data; 842 const char *kernel_filename = machine->kernel_filename; 843 const char *initrd_filename = machine->initrd_filename; 844 const char *dtb_filename = machine->dtb; 845 const char *kernel_cmdline = machine->kernel_cmdline; 846 847 /* Align to 16 bytes as a paranoia measure */ 848 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 849 850 /* load the kernel header */ 851 f = fopen(kernel_filename, "rb"); 852 if (!f || !(kernel_size = get_file_size(f)) || 853 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 854 MIN(ARRAY_SIZE(header), kernel_size)) { 855 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 856 kernel_filename, strerror(errno)); 857 exit(1); 858 } 859 860 /* kernel protocol version */ 861 #if 0 862 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 863 #endif 864 if (ldl_p(header+0x202) == 0x53726448) { 865 protocol = lduw_p(header+0x206); 866 } else { 867 /* This looks like a multiboot kernel. If it is, let's stop 868 treating it like a Linux kernel. */ 869 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 870 kernel_cmdline, kernel_size, header)) { 871 return; 872 } 873 protocol = 0; 874 } 875 876 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 877 /* Low kernel */ 878 real_addr = 0x90000; 879 cmdline_addr = 0x9a000 - cmdline_size; 880 prot_addr = 0x10000; 881 } else if (protocol < 0x202) { 882 /* High but ancient kernel */ 883 real_addr = 0x90000; 884 cmdline_addr = 0x9a000 - cmdline_size; 885 prot_addr = 0x100000; 886 } else { 887 /* High and recent kernel */ 888 real_addr = 0x10000; 889 cmdline_addr = 0x20000; 890 prot_addr = 0x100000; 891 } 892 893 #if 0 894 fprintf(stderr, 895 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 896 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 897 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 898 real_addr, 899 cmdline_addr, 900 prot_addr); 901 #endif 902 903 /* highest address for loading the initrd */ 904 if (protocol >= 0x203) { 905 initrd_max = ldl_p(header+0x22c); 906 } else { 907 initrd_max = 0x37ffffff; 908 } 909 910 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 911 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 912 } 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 916 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 917 918 if (protocol >= 0x202) { 919 stl_p(header+0x228, cmdline_addr); 920 } else { 921 stw_p(header+0x20, 0xA33F); 922 stw_p(header+0x22, cmdline_addr-real_addr); 923 } 924 925 /* handle vga= parameter */ 926 vmode = strstr(kernel_cmdline, "vga="); 927 if (vmode) { 928 unsigned int video_mode; 929 /* skip "vga=" */ 930 vmode += 4; 931 if (!strncmp(vmode, "normal", 6)) { 932 video_mode = 0xffff; 933 } else if (!strncmp(vmode, "ext", 3)) { 934 video_mode = 0xfffe; 935 } else if (!strncmp(vmode, "ask", 3)) { 936 video_mode = 0xfffd; 937 } else { 938 video_mode = strtol(vmode, NULL, 0); 939 } 940 stw_p(header+0x1fa, video_mode); 941 } 942 943 /* loader type */ 944 /* High nybble = B reserved for QEMU; low nybble is revision number. 945 If this code is substantially changed, you may want to consider 946 incrementing the revision. */ 947 if (protocol >= 0x200) { 948 header[0x210] = 0xB0; 949 } 950 /* heap */ 951 if (protocol >= 0x201) { 952 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 953 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 954 } 955 956 /* load initrd */ 957 if (initrd_filename) { 958 if (protocol < 0x200) { 959 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 960 exit(1); 961 } 962 963 initrd_size = get_image_size(initrd_filename); 964 if (initrd_size < 0) { 965 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 966 initrd_filename, strerror(errno)); 967 exit(1); 968 } 969 970 initrd_addr = (initrd_max-initrd_size) & ~4095; 971 972 initrd_data = g_malloc(initrd_size); 973 load_image(initrd_filename, initrd_data); 974 975 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 976 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 977 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 978 979 stl_p(header+0x218, initrd_addr); 980 stl_p(header+0x21c, initrd_size); 981 } 982 983 /* load kernel and setup */ 984 setup_size = header[0x1f1]; 985 if (setup_size == 0) { 986 setup_size = 4; 987 } 988 setup_size = (setup_size+1)*512; 989 if (setup_size > kernel_size) { 990 fprintf(stderr, "qemu: invalid kernel header\n"); 991 exit(1); 992 } 993 kernel_size -= setup_size; 994 995 setup = g_malloc(setup_size); 996 kernel = g_malloc(kernel_size); 997 fseek(f, 0, SEEK_SET); 998 if (fread(setup, 1, setup_size, f) != setup_size) { 999 fprintf(stderr, "fread() failed\n"); 1000 exit(1); 1001 } 1002 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1003 fprintf(stderr, "fread() failed\n"); 1004 exit(1); 1005 } 1006 fclose(f); 1007 1008 /* append dtb to kernel */ 1009 if (dtb_filename) { 1010 if (protocol < 0x209) { 1011 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1012 exit(1); 1013 } 1014 1015 dtb_size = get_image_size(dtb_filename); 1016 if (dtb_size <= 0) { 1017 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1018 dtb_filename, strerror(errno)); 1019 exit(1); 1020 } 1021 1022 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1023 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1024 kernel = g_realloc(kernel, kernel_size); 1025 1026 stq_p(header+0x250, prot_addr + setup_data_offset); 1027 1028 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1029 setup_data->next = 0; 1030 setup_data->type = cpu_to_le32(SETUP_DTB); 1031 setup_data->len = cpu_to_le32(dtb_size); 1032 1033 load_image_size(dtb_filename, setup_data->data, dtb_size); 1034 } 1035 1036 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1037 1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1040 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1041 1042 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1043 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1044 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1045 1046 if (fw_cfg_dma_enabled(fw_cfg)) { 1047 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1048 option_rom[nb_option_roms].bootindex = 0; 1049 } else { 1050 option_rom[nb_option_roms].name = "linuxboot.bin"; 1051 option_rom[nb_option_roms].bootindex = 0; 1052 } 1053 nb_option_roms++; 1054 } 1055 1056 #define NE2000_NB_MAX 6 1057 1058 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1059 0x280, 0x380 }; 1060 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1061 1062 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1063 { 1064 static int nb_ne2k = 0; 1065 1066 if (nb_ne2k == NE2000_NB_MAX) 1067 return; 1068 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1069 ne2000_irq[nb_ne2k], nd); 1070 nb_ne2k++; 1071 } 1072 1073 DeviceState *cpu_get_current_apic(void) 1074 { 1075 if (current_cpu) { 1076 X86CPU *cpu = X86_CPU(current_cpu); 1077 return cpu->apic_state; 1078 } else { 1079 return NULL; 1080 } 1081 } 1082 1083 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1084 { 1085 X86CPU *cpu = opaque; 1086 1087 if (level) { 1088 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1089 } 1090 } 1091 1092 static int pc_present_cpus_count(PCMachineState *pcms) 1093 { 1094 int i, boot_cpus = 0; 1095 for (i = 0; i < pcms->possible_cpus->len; i++) { 1096 if (pcms->possible_cpus->cpus[i].cpu) { 1097 boot_cpus++; 1098 } 1099 } 1100 return boot_cpus; 1101 } 1102 1103 static X86CPU *pc_new_cpu(const char *typename, int64_t apic_id, 1104 Error **errp) 1105 { 1106 X86CPU *cpu = NULL; 1107 Error *local_err = NULL; 1108 1109 cpu = X86_CPU(object_new(typename)); 1110 1111 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1112 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1113 1114 if (local_err) { 1115 error_propagate(errp, local_err); 1116 object_unref(OBJECT(cpu)); 1117 cpu = NULL; 1118 } 1119 return cpu; 1120 } 1121 1122 void pc_hot_add_cpu(const int64_t id, Error **errp) 1123 { 1124 X86CPU *cpu; 1125 ObjectClass *oc; 1126 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1127 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1128 Error *local_err = NULL; 1129 1130 if (id < 0) { 1131 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1132 return; 1133 } 1134 1135 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1136 error_setg(errp, "Unable to add CPU: %" PRIi64 1137 ", resulting APIC ID (%" PRIi64 ") is too large", 1138 id, apic_id); 1139 return; 1140 } 1141 1142 assert(pcms->possible_cpus->cpus[0].cpu); /* BSP is always present */ 1143 oc = OBJECT_CLASS(CPU_GET_CLASS(pcms->possible_cpus->cpus[0].cpu)); 1144 cpu = pc_new_cpu(object_class_get_name(oc), apic_id, &local_err); 1145 if (local_err) { 1146 error_propagate(errp, local_err); 1147 return; 1148 } 1149 object_unref(OBJECT(cpu)); 1150 } 1151 1152 void pc_cpus_init(PCMachineState *pcms) 1153 { 1154 int i; 1155 CPUClass *cc; 1156 ObjectClass *oc; 1157 const char *typename; 1158 gchar **model_pieces; 1159 X86CPU *cpu = NULL; 1160 MachineState *machine = MACHINE(pcms); 1161 1162 /* init CPUs */ 1163 if (machine->cpu_model == NULL) { 1164 #ifdef TARGET_X86_64 1165 machine->cpu_model = "qemu64"; 1166 #else 1167 machine->cpu_model = "qemu32"; 1168 #endif 1169 } 1170 1171 model_pieces = g_strsplit(machine->cpu_model, ",", 2); 1172 if (!model_pieces[0]) { 1173 error_report("Invalid/empty CPU model name"); 1174 exit(1); 1175 } 1176 1177 oc = cpu_class_by_name(TYPE_X86_CPU, model_pieces[0]); 1178 if (oc == NULL) { 1179 error_report("Unable to find CPU definition: %s", model_pieces[0]); 1180 exit(1); 1181 } 1182 typename = object_class_get_name(oc); 1183 cc = CPU_CLASS(oc); 1184 cc->parse_features(typename, model_pieces[1], &error_fatal); 1185 g_strfreev(model_pieces); 1186 1187 /* Calculates the limit to CPU APIC ID values 1188 * 1189 * Limit for the APIC ID value, so that all 1190 * CPU APIC IDs are < pcms->apic_id_limit. 1191 * 1192 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1193 */ 1194 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1195 if (pcms->apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1196 error_report("max_cpus is too large. APIC ID of last CPU is %u", 1197 pcms->apic_id_limit - 1); 1198 exit(1); 1199 } 1200 1201 pcms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1202 sizeof(CPUArchId) * max_cpus); 1203 for (i = 0; i < max_cpus; i++) { 1204 pcms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 1205 pcms->possible_cpus->len++; 1206 if (i < smp_cpus) { 1207 cpu = pc_new_cpu(typename, x86_cpu_apic_id_from_index(i), 1208 &error_fatal); 1209 object_unref(OBJECT(cpu)); 1210 } 1211 } 1212 1213 /* tell smbios about cpuid version and features */ 1214 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1215 } 1216 1217 static void pc_build_feature_control_file(PCMachineState *pcms) 1218 { 1219 X86CPU *cpu = X86_CPU(pcms->possible_cpus->cpus[0].cpu); 1220 CPUX86State *env = &cpu->env; 1221 uint32_t unused, ecx, edx; 1222 uint64_t feature_control_bits = 0; 1223 uint64_t *val; 1224 1225 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1226 if (ecx & CPUID_EXT_VMX) { 1227 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1228 } 1229 1230 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1231 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1232 (env->mcg_cap & MCG_LMCE_P)) { 1233 feature_control_bits |= FEATURE_CONTROL_LMCE; 1234 } 1235 1236 if (!feature_control_bits) { 1237 return; 1238 } 1239 1240 val = g_malloc(sizeof(*val)); 1241 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1242 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1243 } 1244 1245 static 1246 void pc_machine_done(Notifier *notifier, void *data) 1247 { 1248 PCMachineState *pcms = container_of(notifier, 1249 PCMachineState, machine_done); 1250 PCIBus *bus = pcms->bus; 1251 1252 /* set the number of CPUs */ 1253 rtc_set_memory(pcms->rtc, 0x5f, pc_present_cpus_count(pcms) - 1); 1254 1255 if (bus) { 1256 int extra_hosts = 0; 1257 1258 QLIST_FOREACH(bus, &bus->child, sibling) { 1259 /* look for expander root buses */ 1260 if (pci_bus_is_root(bus)) { 1261 extra_hosts++; 1262 } 1263 } 1264 if (extra_hosts && pcms->fw_cfg) { 1265 uint64_t *val = g_malloc(sizeof(*val)); 1266 *val = cpu_to_le64(extra_hosts); 1267 fw_cfg_add_file(pcms->fw_cfg, 1268 "etc/extra-pci-roots", val, sizeof(*val)); 1269 } 1270 } 1271 1272 acpi_setup(); 1273 if (pcms->fw_cfg) { 1274 pc_build_smbios(pcms->fw_cfg); 1275 pc_build_feature_control_file(pcms); 1276 } 1277 } 1278 1279 void pc_guest_info_init(PCMachineState *pcms) 1280 { 1281 int i; 1282 1283 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1284 pcms->numa_nodes = nb_numa_nodes; 1285 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1286 sizeof *pcms->node_mem); 1287 for (i = 0; i < nb_numa_nodes; i++) { 1288 pcms->node_mem[i] = numa_info[i].node_mem; 1289 } 1290 1291 pcms->machine_done.notify = pc_machine_done; 1292 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1293 } 1294 1295 /* setup pci memory address space mapping into system address space */ 1296 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1297 MemoryRegion *pci_address_space) 1298 { 1299 /* Set to lower priority than RAM */ 1300 memory_region_add_subregion_overlap(system_memory, 0x0, 1301 pci_address_space, -1); 1302 } 1303 1304 void pc_acpi_init(const char *default_dsdt) 1305 { 1306 char *filename; 1307 1308 if (acpi_tables != NULL) { 1309 /* manually set via -acpitable, leave it alone */ 1310 return; 1311 } 1312 1313 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1314 if (filename == NULL) { 1315 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1316 } else { 1317 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1318 &error_abort); 1319 Error *err = NULL; 1320 1321 qemu_opt_set(opts, "file", filename, &error_abort); 1322 1323 acpi_table_add_builtin(opts, &err); 1324 if (err) { 1325 error_reportf_err(err, "WARNING: failed to load %s: ", 1326 filename); 1327 } 1328 g_free(filename); 1329 } 1330 } 1331 1332 void xen_load_linux(PCMachineState *pcms) 1333 { 1334 int i; 1335 FWCfgState *fw_cfg; 1336 1337 assert(MACHINE(pcms)->kernel_filename != NULL); 1338 1339 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1340 rom_set_fw(fw_cfg); 1341 1342 load_linux(pcms, fw_cfg); 1343 for (i = 0; i < nb_option_roms; i++) { 1344 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1345 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1346 !strcmp(option_rom[i].name, "multiboot.bin")); 1347 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1348 } 1349 pcms->fw_cfg = fw_cfg; 1350 } 1351 1352 void pc_memory_init(PCMachineState *pcms, 1353 MemoryRegion *system_memory, 1354 MemoryRegion *rom_memory, 1355 MemoryRegion **ram_memory) 1356 { 1357 int linux_boot, i; 1358 MemoryRegion *ram, *option_rom_mr; 1359 MemoryRegion *ram_below_4g, *ram_above_4g; 1360 FWCfgState *fw_cfg; 1361 MachineState *machine = MACHINE(pcms); 1362 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1363 1364 assert(machine->ram_size == pcms->below_4g_mem_size + 1365 pcms->above_4g_mem_size); 1366 1367 linux_boot = (machine->kernel_filename != NULL); 1368 1369 /* Allocate RAM. We allocate it as a single memory region and use 1370 * aliases to address portions of it, mostly for backwards compatibility 1371 * with older qemus that used qemu_ram_alloc(). 1372 */ 1373 ram = g_malloc(sizeof(*ram)); 1374 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1375 machine->ram_size); 1376 *ram_memory = ram; 1377 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1378 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1379 0, pcms->below_4g_mem_size); 1380 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1381 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1382 if (pcms->above_4g_mem_size > 0) { 1383 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1384 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1385 pcms->below_4g_mem_size, 1386 pcms->above_4g_mem_size); 1387 memory_region_add_subregion(system_memory, 0x100000000ULL, 1388 ram_above_4g); 1389 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1390 } 1391 1392 if (!pcmc->has_reserved_memory && 1393 (machine->ram_slots || 1394 (machine->maxram_size > machine->ram_size))) { 1395 MachineClass *mc = MACHINE_GET_CLASS(machine); 1396 1397 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1398 mc->name); 1399 exit(EXIT_FAILURE); 1400 } 1401 1402 /* initialize hotplug memory address space */ 1403 if (pcmc->has_reserved_memory && 1404 (machine->ram_size < machine->maxram_size)) { 1405 ram_addr_t hotplug_mem_size = 1406 machine->maxram_size - machine->ram_size; 1407 1408 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1409 error_report("unsupported amount of memory slots: %"PRIu64, 1410 machine->ram_slots); 1411 exit(EXIT_FAILURE); 1412 } 1413 1414 if (QEMU_ALIGN_UP(machine->maxram_size, 1415 TARGET_PAGE_SIZE) != machine->maxram_size) { 1416 error_report("maximum memory size must by aligned to multiple of " 1417 "%d bytes", TARGET_PAGE_SIZE); 1418 exit(EXIT_FAILURE); 1419 } 1420 1421 pcms->hotplug_memory.base = 1422 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1423 1424 if (pcmc->enforce_aligned_dimm) { 1425 /* size hotplug region assuming 1G page max alignment per slot */ 1426 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1427 } 1428 1429 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1430 hotplug_mem_size) { 1431 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1432 machine->maxram_size); 1433 exit(EXIT_FAILURE); 1434 } 1435 1436 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1437 "hotplug-memory", hotplug_mem_size); 1438 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1439 &pcms->hotplug_memory.mr); 1440 } 1441 1442 /* Initialize PC system firmware */ 1443 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1444 1445 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1446 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1447 &error_fatal); 1448 vmstate_register_ram_global(option_rom_mr); 1449 memory_region_add_subregion_overlap(rom_memory, 1450 PC_ROM_MIN_VGA, 1451 option_rom_mr, 1452 1); 1453 1454 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1455 1456 rom_set_fw(fw_cfg); 1457 1458 if (pcmc->has_reserved_memory && pcms->hotplug_memory.base) { 1459 uint64_t *val = g_malloc(sizeof(*val)); 1460 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1461 uint64_t res_mem_end = pcms->hotplug_memory.base; 1462 1463 if (!pcmc->broken_reserved_end) { 1464 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1465 } 1466 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1467 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1468 } 1469 1470 if (linux_boot) { 1471 load_linux(pcms, fw_cfg); 1472 } 1473 1474 for (i = 0; i < nb_option_roms; i++) { 1475 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1476 } 1477 pcms->fw_cfg = fw_cfg; 1478 1479 /* Init default IOAPIC address space */ 1480 pcms->ioapic_as = &address_space_memory; 1481 } 1482 1483 qemu_irq pc_allocate_cpu_irq(void) 1484 { 1485 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1486 } 1487 1488 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1489 { 1490 DeviceState *dev = NULL; 1491 1492 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1493 if (pci_bus) { 1494 PCIDevice *pcidev = pci_vga_init(pci_bus); 1495 dev = pcidev ? &pcidev->qdev : NULL; 1496 } else if (isa_bus) { 1497 ISADevice *isadev = isa_vga_init(isa_bus); 1498 dev = isadev ? DEVICE(isadev) : NULL; 1499 } 1500 rom_reset_order_override(); 1501 return dev; 1502 } 1503 1504 static const MemoryRegionOps ioport80_io_ops = { 1505 .write = ioport80_write, 1506 .read = ioport80_read, 1507 .endianness = DEVICE_NATIVE_ENDIAN, 1508 .impl = { 1509 .min_access_size = 1, 1510 .max_access_size = 1, 1511 }, 1512 }; 1513 1514 static const MemoryRegionOps ioportF0_io_ops = { 1515 .write = ioportF0_write, 1516 .read = ioportF0_read, 1517 .endianness = DEVICE_NATIVE_ENDIAN, 1518 .impl = { 1519 .min_access_size = 1, 1520 .max_access_size = 1, 1521 }, 1522 }; 1523 1524 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1525 ISADevice **rtc_state, 1526 bool create_fdctrl, 1527 bool no_vmport, 1528 uint32_t hpet_irqs) 1529 { 1530 int i; 1531 DriveInfo *fd[MAX_FD]; 1532 DeviceState *hpet = NULL; 1533 int pit_isa_irq = 0; 1534 qemu_irq pit_alt_irq = NULL; 1535 qemu_irq rtc_irq = NULL; 1536 qemu_irq *a20_line; 1537 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1538 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1539 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1540 1541 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1542 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1543 1544 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1545 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1546 1547 /* 1548 * Check if an HPET shall be created. 1549 * 1550 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1551 * when the HPET wants to take over. Thus we have to disable the latter. 1552 */ 1553 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1554 /* In order to set property, here not using sysbus_try_create_simple */ 1555 hpet = qdev_try_create(NULL, TYPE_HPET); 1556 if (hpet) { 1557 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1558 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1559 * IRQ8 and IRQ2. 1560 */ 1561 uint8_t compat = object_property_get_int(OBJECT(hpet), 1562 HPET_INTCAP, NULL); 1563 if (!compat) { 1564 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1565 } 1566 qdev_init_nofail(hpet); 1567 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1568 1569 for (i = 0; i < GSI_NUM_PINS; i++) { 1570 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1571 } 1572 pit_isa_irq = -1; 1573 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1574 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1575 } 1576 } 1577 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1578 1579 qemu_register_boot_set(pc_boot_set, *rtc_state); 1580 1581 if (!xen_enabled()) { 1582 if (kvm_pit_in_kernel()) { 1583 pit = kvm_pit_init(isa_bus, 0x40); 1584 } else { 1585 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1586 } 1587 if (hpet) { 1588 /* connect PIT to output control line of the HPET */ 1589 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1590 } 1591 pcspk_init(isa_bus, pit); 1592 } 1593 1594 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1595 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1596 1597 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1598 i8042 = isa_create_simple(isa_bus, "i8042"); 1599 i8042_setup_a20_line(i8042, a20_line[0]); 1600 if (!no_vmport) { 1601 vmport_init(isa_bus); 1602 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1603 } else { 1604 vmmouse = NULL; 1605 } 1606 if (vmmouse) { 1607 DeviceState *dev = DEVICE(vmmouse); 1608 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1609 qdev_init_nofail(dev); 1610 } 1611 port92 = isa_create_simple(isa_bus, "port92"); 1612 port92_init(port92, a20_line[1]); 1613 g_free(a20_line); 1614 1615 DMA_init(isa_bus, 0); 1616 1617 for(i = 0; i < MAX_FD; i++) { 1618 fd[i] = drive_get(IF_FLOPPY, 0, i); 1619 create_fdctrl |= !!fd[i]; 1620 } 1621 if (create_fdctrl) { 1622 fdctrl_init_isa(isa_bus, fd); 1623 } 1624 } 1625 1626 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1627 { 1628 int i; 1629 1630 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1631 for (i = 0; i < nb_nics; i++) { 1632 NICInfo *nd = &nd_table[i]; 1633 1634 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1635 pc_init_ne2k_isa(isa_bus, nd); 1636 } else { 1637 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1638 } 1639 } 1640 rom_reset_order_override(); 1641 } 1642 1643 void pc_pci_device_init(PCIBus *pci_bus) 1644 { 1645 int max_bus; 1646 int bus; 1647 1648 max_bus = drive_get_max_bus(IF_SCSI); 1649 for (bus = 0; bus <= max_bus; bus++) { 1650 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1651 } 1652 } 1653 1654 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1655 { 1656 DeviceState *dev; 1657 SysBusDevice *d; 1658 unsigned int i; 1659 1660 if (kvm_ioapic_in_kernel()) { 1661 dev = qdev_create(NULL, "kvm-ioapic"); 1662 } else { 1663 dev = qdev_create(NULL, "ioapic"); 1664 } 1665 if (parent_name) { 1666 object_property_add_child(object_resolve_path(parent_name, NULL), 1667 "ioapic", OBJECT(dev), NULL); 1668 } 1669 qdev_init_nofail(dev); 1670 d = SYS_BUS_DEVICE(dev); 1671 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1672 1673 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1674 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1675 } 1676 } 1677 1678 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1679 DeviceState *dev, Error **errp) 1680 { 1681 HotplugHandlerClass *hhc; 1682 Error *local_err = NULL; 1683 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1684 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1685 PCDIMMDevice *dimm = PC_DIMM(dev); 1686 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1687 MemoryRegion *mr = ddc->get_memory_region(dimm); 1688 uint64_t align = TARGET_PAGE_SIZE; 1689 1690 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1691 align = memory_region_get_alignment(mr); 1692 } 1693 1694 if (!pcms->acpi_dev) { 1695 error_setg(&local_err, 1696 "memory hotplug is not enabled: missing acpi device"); 1697 goto out; 1698 } 1699 1700 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1701 if (local_err) { 1702 goto out; 1703 } 1704 1705 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1706 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1707 out: 1708 error_propagate(errp, local_err); 1709 } 1710 1711 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1712 DeviceState *dev, Error **errp) 1713 { 1714 HotplugHandlerClass *hhc; 1715 Error *local_err = NULL; 1716 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1717 1718 if (!pcms->acpi_dev) { 1719 error_setg(&local_err, 1720 "memory hotplug is not enabled: missing acpi device"); 1721 goto out; 1722 } 1723 1724 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1725 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1726 1727 out: 1728 error_propagate(errp, local_err); 1729 } 1730 1731 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1732 DeviceState *dev, Error **errp) 1733 { 1734 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1735 PCDIMMDevice *dimm = PC_DIMM(dev); 1736 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1737 MemoryRegion *mr = ddc->get_memory_region(dimm); 1738 HotplugHandlerClass *hhc; 1739 Error *local_err = NULL; 1740 1741 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1742 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1743 1744 if (local_err) { 1745 goto out; 1746 } 1747 1748 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1749 object_unparent(OBJECT(dev)); 1750 1751 out: 1752 error_propagate(errp, local_err); 1753 } 1754 1755 static int pc_apic_cmp(const void *a, const void *b) 1756 { 1757 CPUArchId *apic_a = (CPUArchId *)a; 1758 CPUArchId *apic_b = (CPUArchId *)b; 1759 1760 return apic_a->arch_id - apic_b->arch_id; 1761 } 1762 1763 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1764 * in pcms->possible_cpus->cpus, if pcms->possible_cpus->cpus has no 1765 * entry correponding to CPU's apic_id returns NULL. 1766 */ 1767 static CPUArchId *pc_find_cpu_slot(PCMachineState *pcms, CPUState *cpu, 1768 int *idx) 1769 { 1770 CPUClass *cc = CPU_GET_CLASS(cpu); 1771 CPUArchId apic_id, *found_cpu; 1772 1773 apic_id.arch_id = cc->get_arch_id(CPU(cpu)); 1774 found_cpu = bsearch(&apic_id, pcms->possible_cpus->cpus, 1775 pcms->possible_cpus->len, sizeof(*pcms->possible_cpus->cpus), 1776 pc_apic_cmp); 1777 if (found_cpu && idx) { 1778 *idx = found_cpu - pcms->possible_cpus->cpus; 1779 } 1780 return found_cpu; 1781 } 1782 1783 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1784 DeviceState *dev, Error **errp) 1785 { 1786 CPUArchId *found_cpu; 1787 HotplugHandlerClass *hhc; 1788 Error *local_err = NULL; 1789 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1790 1791 if (pcms->acpi_dev) { 1792 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1793 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1794 if (local_err) { 1795 goto out; 1796 } 1797 } 1798 1799 if (dev->hotplugged) { 1800 /* increment the number of CPUs */ 1801 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1802 } 1803 1804 found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); 1805 found_cpu->cpu = CPU(dev); 1806 out: 1807 error_propagate(errp, local_err); 1808 } 1809 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1810 DeviceState *dev, Error **errp) 1811 { 1812 int idx = -1; 1813 HotplugHandlerClass *hhc; 1814 Error *local_err = NULL; 1815 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1816 1817 pc_find_cpu_slot(pcms, CPU(dev), &idx); 1818 assert(idx != -1); 1819 if (idx == 0) { 1820 error_setg(&local_err, "Boot CPU is unpluggable"); 1821 goto out; 1822 } 1823 1824 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1825 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1826 1827 if (local_err) { 1828 goto out; 1829 } 1830 1831 out: 1832 error_propagate(errp, local_err); 1833 1834 } 1835 1836 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1837 DeviceState *dev, Error **errp) 1838 { 1839 CPUArchId *found_cpu; 1840 HotplugHandlerClass *hhc; 1841 Error *local_err = NULL; 1842 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1843 1844 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1845 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1846 1847 if (local_err) { 1848 goto out; 1849 } 1850 1851 found_cpu = pc_find_cpu_slot(pcms, CPU(dev), NULL); 1852 found_cpu->cpu = NULL; 1853 object_unparent(OBJECT(dev)); 1854 1855 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) - 1); 1856 out: 1857 error_propagate(errp, local_err); 1858 } 1859 1860 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1861 DeviceState *dev, Error **errp) 1862 { 1863 int idx; 1864 CPUState *cs; 1865 CPUArchId *cpu_slot; 1866 X86CPUTopoInfo topo; 1867 X86CPU *cpu = X86_CPU(dev); 1868 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1869 1870 /* if APIC ID is not set, set it based on socket/core/thread properties */ 1871 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1872 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 1873 1874 if (cpu->socket_id < 0) { 1875 error_setg(errp, "CPU socket-id is not set"); 1876 return; 1877 } else if (cpu->socket_id > max_socket) { 1878 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1879 cpu->socket_id, max_socket); 1880 return; 1881 } 1882 if (cpu->core_id < 0) { 1883 error_setg(errp, "CPU core-id is not set"); 1884 return; 1885 } else if (cpu->core_id > (smp_cores - 1)) { 1886 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1887 cpu->core_id, smp_cores - 1); 1888 return; 1889 } 1890 if (cpu->thread_id < 0) { 1891 error_setg(errp, "CPU thread-id is not set"); 1892 return; 1893 } else if (cpu->thread_id > (smp_threads - 1)) { 1894 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1895 cpu->thread_id, smp_threads - 1); 1896 return; 1897 } 1898 1899 topo.pkg_id = cpu->socket_id; 1900 topo.core_id = cpu->core_id; 1901 topo.smt_id = cpu->thread_id; 1902 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 1903 } 1904 1905 cpu_slot = pc_find_cpu_slot(pcms, CPU(dev), &idx); 1906 if (!cpu_slot) { 1907 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1908 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 1909 " APIC ID %" PRIu32 ", valid index range 0:%d", 1910 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 1911 pcms->possible_cpus->len - 1); 1912 return; 1913 } 1914 1915 if (cpu_slot->cpu) { 1916 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1917 idx, cpu->apic_id); 1918 return; 1919 } 1920 1921 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1922 * so that query_hotpluggable_cpus would show correct values 1923 */ 1924 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1925 * once -smp refactoring is complete and there will be CPU private 1926 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1927 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1928 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1929 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1930 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1931 return; 1932 } 1933 cpu->socket_id = topo.pkg_id; 1934 1935 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1936 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1937 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1938 return; 1939 } 1940 cpu->core_id = topo.core_id; 1941 1942 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1943 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1944 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1945 return; 1946 } 1947 cpu->thread_id = topo.smt_id; 1948 1949 cs = CPU(cpu); 1950 cs->cpu_index = idx; 1951 } 1952 1953 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1954 DeviceState *dev, Error **errp) 1955 { 1956 if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1957 pc_cpu_pre_plug(hotplug_dev, dev, errp); 1958 } 1959 } 1960 1961 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1962 DeviceState *dev, Error **errp) 1963 { 1964 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1965 pc_dimm_plug(hotplug_dev, dev, errp); 1966 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1967 pc_cpu_plug(hotplug_dev, dev, errp); 1968 } 1969 } 1970 1971 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1972 DeviceState *dev, Error **errp) 1973 { 1974 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1975 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1976 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1977 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1978 } else { 1979 error_setg(errp, "acpi: device unplug request for not supported device" 1980 " type: %s", object_get_typename(OBJECT(dev))); 1981 } 1982 } 1983 1984 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1985 DeviceState *dev, Error **errp) 1986 { 1987 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1988 pc_dimm_unplug(hotplug_dev, dev, errp); 1989 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1990 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 1991 } else { 1992 error_setg(errp, "acpi: device unplug for not supported device" 1993 " type: %s", object_get_typename(OBJECT(dev))); 1994 } 1995 } 1996 1997 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1998 DeviceState *dev) 1999 { 2000 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 2001 2002 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2003 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2004 return HOTPLUG_HANDLER(machine); 2005 } 2006 2007 return pcmc->get_hotplug_handler ? 2008 pcmc->get_hotplug_handler(machine, dev) : NULL; 2009 } 2010 2011 static void 2012 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, 2013 const char *name, void *opaque, 2014 Error **errp) 2015 { 2016 PCMachineState *pcms = PC_MACHINE(obj); 2017 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 2018 2019 visit_type_int(v, name, &value, errp); 2020 } 2021 2022 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2023 const char *name, void *opaque, 2024 Error **errp) 2025 { 2026 PCMachineState *pcms = PC_MACHINE(obj); 2027 uint64_t value = pcms->max_ram_below_4g; 2028 2029 visit_type_size(v, name, &value, errp); 2030 } 2031 2032 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2033 const char *name, void *opaque, 2034 Error **errp) 2035 { 2036 PCMachineState *pcms = PC_MACHINE(obj); 2037 Error *error = NULL; 2038 uint64_t value; 2039 2040 visit_type_size(v, name, &value, &error); 2041 if (error) { 2042 error_propagate(errp, error); 2043 return; 2044 } 2045 if (value > (1ULL << 32)) { 2046 error_setg(&error, 2047 "Machine option 'max-ram-below-4g=%"PRIu64 2048 "' expects size less than or equal to 4G", value); 2049 error_propagate(errp, error); 2050 return; 2051 } 2052 2053 if (value < (1ULL << 20)) { 2054 error_report("Warning: small max_ram_below_4g(%"PRIu64 2055 ") less than 1M. BIOS may not work..", 2056 value); 2057 } 2058 2059 pcms->max_ram_below_4g = value; 2060 } 2061 2062 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2063 void *opaque, Error **errp) 2064 { 2065 PCMachineState *pcms = PC_MACHINE(obj); 2066 OnOffAuto vmport = pcms->vmport; 2067 2068 visit_type_OnOffAuto(v, name, &vmport, errp); 2069 } 2070 2071 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2072 void *opaque, Error **errp) 2073 { 2074 PCMachineState *pcms = PC_MACHINE(obj); 2075 2076 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2077 } 2078 2079 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2080 { 2081 bool smm_available = false; 2082 2083 if (pcms->smm == ON_OFF_AUTO_OFF) { 2084 return false; 2085 } 2086 2087 if (tcg_enabled() || qtest_enabled()) { 2088 smm_available = true; 2089 } else if (kvm_enabled()) { 2090 smm_available = kvm_has_smm(); 2091 } 2092 2093 if (smm_available) { 2094 return true; 2095 } 2096 2097 if (pcms->smm == ON_OFF_AUTO_ON) { 2098 error_report("System Management Mode not supported by this hypervisor."); 2099 exit(1); 2100 } 2101 return false; 2102 } 2103 2104 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2105 void *opaque, Error **errp) 2106 { 2107 PCMachineState *pcms = PC_MACHINE(obj); 2108 OnOffAuto smm = pcms->smm; 2109 2110 visit_type_OnOffAuto(v, name, &smm, errp); 2111 } 2112 2113 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2114 void *opaque, Error **errp) 2115 { 2116 PCMachineState *pcms = PC_MACHINE(obj); 2117 2118 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2119 } 2120 2121 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 2122 { 2123 PCMachineState *pcms = PC_MACHINE(obj); 2124 2125 return pcms->acpi_nvdimm_state.is_enabled; 2126 } 2127 2128 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 2129 { 2130 PCMachineState *pcms = PC_MACHINE(obj); 2131 2132 pcms->acpi_nvdimm_state.is_enabled = value; 2133 } 2134 2135 static void pc_machine_initfn(Object *obj) 2136 { 2137 PCMachineState *pcms = PC_MACHINE(obj); 2138 2139 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 2140 pc_machine_get_hotplug_memory_region_size, 2141 NULL, NULL, NULL, &error_abort); 2142 2143 pcms->max_ram_below_4g = 0; /* use default */ 2144 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2145 pc_machine_get_max_ram_below_4g, 2146 pc_machine_set_max_ram_below_4g, 2147 NULL, NULL, &error_abort); 2148 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 2149 "Maximum ram below the 4G boundary (32bit boundary)", 2150 &error_abort); 2151 2152 pcms->smm = ON_OFF_AUTO_AUTO; 2153 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 2154 pc_machine_get_smm, 2155 pc_machine_set_smm, 2156 NULL, NULL, &error_abort); 2157 object_property_set_description(obj, PC_MACHINE_SMM, 2158 "Enable SMM (pc & q35)", 2159 &error_abort); 2160 2161 pcms->vmport = ON_OFF_AUTO_AUTO; 2162 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 2163 pc_machine_get_vmport, 2164 pc_machine_set_vmport, 2165 NULL, NULL, &error_abort); 2166 object_property_set_description(obj, PC_MACHINE_VMPORT, 2167 "Enable vmport (pc & q35)", 2168 &error_abort); 2169 2170 /* nvdimm is disabled on default. */ 2171 pcms->acpi_nvdimm_state.is_enabled = false; 2172 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, 2173 pc_machine_set_nvdimm, &error_abort); 2174 } 2175 2176 static void pc_machine_reset(void) 2177 { 2178 CPUState *cs; 2179 X86CPU *cpu; 2180 2181 qemu_devices_reset(); 2182 2183 /* Reset APIC after devices have been reset to cancel 2184 * any changes that qemu_devices_reset() might have done. 2185 */ 2186 CPU_FOREACH(cs) { 2187 cpu = X86_CPU(cs); 2188 2189 if (cpu->apic_state) { 2190 device_reset(cpu->apic_state); 2191 } 2192 } 2193 } 2194 2195 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 2196 { 2197 X86CPUTopoInfo topo; 2198 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 2199 &topo); 2200 return topo.pkg_id; 2201 } 2202 2203 static CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *machine) 2204 { 2205 PCMachineState *pcms = PC_MACHINE(machine); 2206 int len = sizeof(CPUArchIdList) + 2207 sizeof(CPUArchId) * (pcms->possible_cpus->len); 2208 CPUArchIdList *list = g_malloc(len); 2209 2210 memcpy(list, pcms->possible_cpus, len); 2211 return list; 2212 } 2213 2214 static HotpluggableCPUList *pc_query_hotpluggable_cpus(MachineState *machine) 2215 { 2216 int i; 2217 CPUState *cpu; 2218 HotpluggableCPUList *head = NULL; 2219 PCMachineState *pcms = PC_MACHINE(machine); 2220 const char *cpu_type; 2221 2222 cpu = pcms->possible_cpus->cpus[0].cpu; 2223 assert(cpu); /* BSP is always present */ 2224 cpu_type = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(cpu))); 2225 2226 for (i = 0; i < pcms->possible_cpus->len; i++) { 2227 X86CPUTopoInfo topo; 2228 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); 2229 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 2230 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); 2231 const uint32_t apic_id = pcms->possible_cpus->cpus[i].arch_id; 2232 2233 x86_topo_ids_from_apicid(apic_id, smp_cores, smp_threads, &topo); 2234 2235 cpu_item->type = g_strdup(cpu_type); 2236 cpu_item->vcpus_count = 1; 2237 cpu_props->has_socket_id = true; 2238 cpu_props->socket_id = topo.pkg_id; 2239 cpu_props->has_core_id = true; 2240 cpu_props->core_id = topo.core_id; 2241 cpu_props->has_thread_id = true; 2242 cpu_props->thread_id = topo.smt_id; 2243 cpu_item->props = cpu_props; 2244 2245 cpu = pcms->possible_cpus->cpus[i].cpu; 2246 if (cpu) { 2247 cpu_item->has_qom_path = true; 2248 cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); 2249 } 2250 2251 list_item->value = cpu_item; 2252 list_item->next = head; 2253 head = list_item; 2254 } 2255 return head; 2256 } 2257 2258 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2259 { 2260 /* cpu index isn't used */ 2261 CPUState *cs; 2262 2263 CPU_FOREACH(cs) { 2264 X86CPU *cpu = X86_CPU(cs); 2265 2266 if (!cpu->apic_state) { 2267 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2268 } else { 2269 apic_deliver_nmi(cpu->apic_state); 2270 } 2271 } 2272 } 2273 2274 static void pc_machine_class_init(ObjectClass *oc, void *data) 2275 { 2276 MachineClass *mc = MACHINE_CLASS(oc); 2277 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2278 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2279 NMIClass *nc = NMI_CLASS(oc); 2280 2281 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 2282 pcmc->pci_enabled = true; 2283 pcmc->has_acpi_build = true; 2284 pcmc->rsdp_in_ram = true; 2285 pcmc->smbios_defaults = true; 2286 pcmc->smbios_uuid_encoded = true; 2287 pcmc->gigabyte_align = true; 2288 pcmc->has_reserved_memory = true; 2289 pcmc->kvmclock_enabled = true; 2290 pcmc->enforce_aligned_dimm = true; 2291 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2292 * to be used at the moment, 32K should be enough for a while. */ 2293 pcmc->acpi_data_size = 0x20000 + 0x8000; 2294 pcmc->save_tsc_khz = true; 2295 mc->get_hotplug_handler = pc_get_hotpug_handler; 2296 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 2297 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2298 mc->query_hotpluggable_cpus = pc_query_hotpluggable_cpus; 2299 mc->default_boot_order = "cad"; 2300 mc->hot_add_cpu = pc_hot_add_cpu; 2301 mc->max_cpus = 255; 2302 mc->reset = pc_machine_reset; 2303 hc->pre_plug = pc_machine_device_pre_plug_cb; 2304 hc->plug = pc_machine_device_plug_cb; 2305 hc->unplug_request = pc_machine_device_unplug_request_cb; 2306 hc->unplug = pc_machine_device_unplug_cb; 2307 nc->nmi_monitor_handler = x86_nmi; 2308 } 2309 2310 static const TypeInfo pc_machine_info = { 2311 .name = TYPE_PC_MACHINE, 2312 .parent = TYPE_MACHINE, 2313 .abstract = true, 2314 .instance_size = sizeof(PCMachineState), 2315 .instance_init = pc_machine_initfn, 2316 .class_size = sizeof(PCMachineClass), 2317 .class_init = pc_machine_class_init, 2318 .interfaces = (InterfaceInfo[]) { 2319 { TYPE_HOTPLUG_HANDLER }, 2320 { TYPE_NMI }, 2321 { } 2322 }, 2323 }; 2324 2325 static void pc_machine_register_types(void) 2326 { 2327 type_register_static(&pc_machine_info); 2328 } 2329 2330 type_init(pc_machine_register_types) 2331