1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "migration/vmstate.h" 45 #include "multiboot.h" 46 #include "hw/timer/mc146818rtc.h" 47 #include "hw/dma/i8257.h" 48 #include "hw/timer/i8254.h" 49 #include "hw/input/i8042.h" 50 #include "hw/irq.h" 51 #include "hw/audio/pcspk.h" 52 #include "hw/pci/msi.h" 53 #include "hw/sysbus.h" 54 #include "sysemu/sysemu.h" 55 #include "sysemu/tcg.h" 56 #include "sysemu/numa.h" 57 #include "sysemu/kvm.h" 58 #include "sysemu/qtest.h" 59 #include "sysemu/reset.h" 60 #include "sysemu/runstate.h" 61 #include "kvm_i386.h" 62 #include "hw/xen/xen.h" 63 #include "hw/xen/start_info.h" 64 #include "ui/qemu-spice.h" 65 #include "exec/memory.h" 66 #include "exec/address-spaces.h" 67 #include "sysemu/arch_init.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "hw/boards.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/visitor.h" 81 #include "hw/core/cpu.h" 82 #include "hw/usb.h" 83 #include "hw/i386/intel_iommu.h" 84 #include "hw/net/ne2000-isa.h" 85 #include "standard-headers/asm-x86/bootparam.h" 86 #include "hw/virtio/virtio-pmem-pci.h" 87 #include "hw/mem/memory-device.h" 88 #include "sysemu/replay.h" 89 #include "qapi/qmp/qerror.h" 90 #include "config-devices.h" 91 #include "e820_memory_layout.h" 92 #include "fw_cfg.h" 93 94 /* debug PC/ISA interrupts */ 95 //#define DEBUG_IRQ 96 97 #ifdef DEBUG_IRQ 98 #define DPRINTF(fmt, ...) \ 99 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 100 #else 101 #define DPRINTF(fmt, ...) 102 #endif 103 104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 105 106 GlobalProperty pc_compat_4_1[] = {}; 107 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 108 109 GlobalProperty pc_compat_4_0[] = {}; 110 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 111 112 GlobalProperty pc_compat_3_1[] = { 113 { "intel-iommu", "dma-drain", "off" }, 114 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 115 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 116 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 117 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 118 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 119 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 120 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 121 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 122 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 123 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 124 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 125 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 126 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 127 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 128 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 129 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 130 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 131 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 132 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 133 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 134 }; 135 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 136 137 GlobalProperty pc_compat_3_0[] = { 138 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 139 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 140 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 141 }; 142 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 143 144 GlobalProperty pc_compat_2_12[] = { 145 { TYPE_X86_CPU, "legacy-cache", "on" }, 146 { TYPE_X86_CPU, "topoext", "off" }, 147 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 148 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 149 }; 150 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 151 152 GlobalProperty pc_compat_2_11[] = { 153 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 154 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 155 }; 156 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 157 158 GlobalProperty pc_compat_2_10[] = { 159 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 160 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 161 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 162 }; 163 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 164 165 GlobalProperty pc_compat_2_9[] = { 166 { "mch", "extended-tseg-mbytes", "0" }, 167 }; 168 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 169 170 GlobalProperty pc_compat_2_8[] = { 171 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 172 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 173 { "ICH9-LPC", "x-smi-broadcast", "off" }, 174 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 175 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 176 }; 177 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 178 179 GlobalProperty pc_compat_2_7[] = { 180 { TYPE_X86_CPU, "l3-cache", "off" }, 181 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 182 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 183 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 184 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 185 { "isa-pcspk", "migrate", "off" }, 186 }; 187 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 188 189 GlobalProperty pc_compat_2_6[] = { 190 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 191 { "vmxnet3", "romfile", "" }, 192 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 193 { "apic-common", "legacy-instance-id", "on", } 194 }; 195 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 196 197 GlobalProperty pc_compat_2_5[] = {}; 198 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 199 200 GlobalProperty pc_compat_2_4[] = { 201 PC_CPU_MODEL_IDS("2.4.0") 202 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 203 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 204 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 205 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 206 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 207 { TYPE_X86_CPU, "check", "off" }, 208 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 209 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 210 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 211 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 212 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 213 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 214 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 215 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 216 }; 217 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 218 219 GlobalProperty pc_compat_2_3[] = { 220 PC_CPU_MODEL_IDS("2.3.0") 221 { TYPE_X86_CPU, "arat", "off" }, 222 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 223 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 224 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 225 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 226 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 227 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 228 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 229 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 230 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 231 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 232 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 233 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 234 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 235 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 236 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 241 }; 242 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 243 244 GlobalProperty pc_compat_2_2[] = { 245 PC_CPU_MODEL_IDS("2.2.0") 246 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 247 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 248 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 249 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 250 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 251 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 252 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 261 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 262 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 263 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 264 }; 265 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 266 267 GlobalProperty pc_compat_2_1[] = { 268 PC_CPU_MODEL_IDS("2.1.0") 269 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 270 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 271 }; 272 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 273 274 GlobalProperty pc_compat_2_0[] = { 275 PC_CPU_MODEL_IDS("2.0.0") 276 { "virtio-scsi-pci", "any_layout", "off" }, 277 { "PIIX4_PM", "memory-hotplug-support", "off" }, 278 { "apic", "version", "0x11" }, 279 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 280 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 281 { "pci-serial", "prog_if", "0" }, 282 { "pci-serial-2x", "prog_if", "0" }, 283 { "pci-serial-4x", "prog_if", "0" }, 284 { "virtio-net-pci", "guest_announce", "off" }, 285 { "ICH9-LPC", "memory-hotplug-support", "off" }, 286 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 287 { "ioh3420", COMPAT_PROP_PCP, "off" }, 288 }; 289 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 290 291 GlobalProperty pc_compat_1_7[] = { 292 PC_CPU_MODEL_IDS("1.7.0") 293 { TYPE_USB_DEVICE, "msos-desc", "no" }, 294 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 295 { "hpet", HPET_INTCAP, "4" }, 296 }; 297 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 298 299 GlobalProperty pc_compat_1_6[] = { 300 PC_CPU_MODEL_IDS("1.6.0") 301 { "e1000", "mitigation", "off" }, 302 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 303 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 304 { "i440FX-pcihost", "short_root_bus", "1" }, 305 { "q35-pcihost", "short_root_bus", "1" }, 306 }; 307 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 308 309 GlobalProperty pc_compat_1_5[] = { 310 PC_CPU_MODEL_IDS("1.5.0") 311 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 312 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 313 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 314 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 315 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 316 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 317 { "virtio-net-pci", "any_layout", "off" }, 318 { TYPE_X86_CPU, "pmu", "on" }, 319 { "i440FX-pcihost", "short_root_bus", "0" }, 320 { "q35-pcihost", "short_root_bus", "0" }, 321 }; 322 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 323 324 GlobalProperty pc_compat_1_4[] = { 325 PC_CPU_MODEL_IDS("1.4.0") 326 { "scsi-hd", "discard_granularity", "0" }, 327 { "scsi-cd", "discard_granularity", "0" }, 328 { "scsi-disk", "discard_granularity", "0" }, 329 { "ide-hd", "discard_granularity", "0" }, 330 { "ide-cd", "discard_granularity", "0" }, 331 { "ide-drive", "discard_granularity", "0" }, 332 { "virtio-blk-pci", "discard_granularity", "0" }, 333 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 334 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 335 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 336 { "e1000", "romfile", "pxe-e1000.rom" }, 337 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 338 { "pcnet", "romfile", "pxe-pcnet.rom" }, 339 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 340 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 341 { "486-" TYPE_X86_CPU, "model", "0" }, 342 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 343 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 344 }; 345 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 346 347 void gsi_handler(void *opaque, int n, int level) 348 { 349 GSIState *s = opaque; 350 351 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 352 if (n < ISA_NUM_IRQS) { 353 qemu_set_irq(s->i8259_irq[n], level); 354 } 355 qemu_set_irq(s->ioapic_irq[n], level); 356 } 357 358 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 359 unsigned size) 360 { 361 } 362 363 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 364 { 365 return 0xffffffffffffffffULL; 366 } 367 368 /* MSDOS compatibility mode FPU exception support */ 369 static qemu_irq ferr_irq; 370 371 void pc_register_ferr_irq(qemu_irq irq) 372 { 373 ferr_irq = irq; 374 } 375 376 /* XXX: add IGNNE support */ 377 void cpu_set_ferr(CPUX86State *s) 378 { 379 qemu_irq_raise(ferr_irq); 380 } 381 382 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 383 unsigned size) 384 { 385 qemu_irq_lower(ferr_irq); 386 } 387 388 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 389 { 390 return 0xffffffffffffffffULL; 391 } 392 393 /* TSC handling */ 394 uint64_t cpu_get_tsc(CPUX86State *env) 395 { 396 return cpu_get_ticks(); 397 } 398 399 /* IRQ handling */ 400 int cpu_get_pic_interrupt(CPUX86State *env) 401 { 402 X86CPU *cpu = env_archcpu(env); 403 int intno; 404 405 if (!kvm_irqchip_in_kernel()) { 406 intno = apic_get_interrupt(cpu->apic_state); 407 if (intno >= 0) { 408 return intno; 409 } 410 /* read the irq from the PIC */ 411 if (!apic_accept_pic_intr(cpu->apic_state)) { 412 return -1; 413 } 414 } 415 416 intno = pic_read_irq(isa_pic); 417 return intno; 418 } 419 420 static void pic_irq_request(void *opaque, int irq, int level) 421 { 422 CPUState *cs = first_cpu; 423 X86CPU *cpu = X86_CPU(cs); 424 425 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 426 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 427 CPU_FOREACH(cs) { 428 cpu = X86_CPU(cs); 429 if (apic_accept_pic_intr(cpu->apic_state)) { 430 apic_deliver_pic_intr(cpu->apic_state, level); 431 } 432 } 433 } else { 434 if (level) { 435 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 436 } else { 437 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 438 } 439 } 440 } 441 442 /* PC cmos mappings */ 443 444 #define REG_EQUIPMENT_BYTE 0x14 445 446 int cmos_get_fd_drive_type(FloppyDriveType fd0) 447 { 448 int val; 449 450 switch (fd0) { 451 case FLOPPY_DRIVE_TYPE_144: 452 /* 1.44 Mb 3"5 drive */ 453 val = 4; 454 break; 455 case FLOPPY_DRIVE_TYPE_288: 456 /* 2.88 Mb 3"5 drive */ 457 val = 5; 458 break; 459 case FLOPPY_DRIVE_TYPE_120: 460 /* 1.2 Mb 5"5 drive */ 461 val = 2; 462 break; 463 case FLOPPY_DRIVE_TYPE_NONE: 464 default: 465 val = 0; 466 break; 467 } 468 return val; 469 } 470 471 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 472 int16_t cylinders, int8_t heads, int8_t sectors) 473 { 474 rtc_set_memory(s, type_ofs, 47); 475 rtc_set_memory(s, info_ofs, cylinders); 476 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 477 rtc_set_memory(s, info_ofs + 2, heads); 478 rtc_set_memory(s, info_ofs + 3, 0xff); 479 rtc_set_memory(s, info_ofs + 4, 0xff); 480 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 481 rtc_set_memory(s, info_ofs + 6, cylinders); 482 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 483 rtc_set_memory(s, info_ofs + 8, sectors); 484 } 485 486 /* convert boot_device letter to something recognizable by the bios */ 487 static int boot_device2nibble(char boot_device) 488 { 489 switch(boot_device) { 490 case 'a': 491 case 'b': 492 return 0x01; /* floppy boot */ 493 case 'c': 494 return 0x02; /* hard drive boot */ 495 case 'd': 496 return 0x03; /* CD-ROM boot */ 497 case 'n': 498 return 0x04; /* Network boot */ 499 } 500 return 0; 501 } 502 503 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 504 { 505 #define PC_MAX_BOOT_DEVICES 3 506 int nbds, bds[3] = { 0, }; 507 int i; 508 509 nbds = strlen(boot_device); 510 if (nbds > PC_MAX_BOOT_DEVICES) { 511 error_setg(errp, "Too many boot devices for PC"); 512 return; 513 } 514 for (i = 0; i < nbds; i++) { 515 bds[i] = boot_device2nibble(boot_device[i]); 516 if (bds[i] == 0) { 517 error_setg(errp, "Invalid boot device for PC: '%c'", 518 boot_device[i]); 519 return; 520 } 521 } 522 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 523 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 524 } 525 526 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 527 { 528 set_boot_dev(opaque, boot_device, errp); 529 } 530 531 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 532 { 533 int val, nb, i; 534 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 535 FLOPPY_DRIVE_TYPE_NONE }; 536 537 /* floppy type */ 538 if (floppy) { 539 for (i = 0; i < 2; i++) { 540 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 541 } 542 } 543 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 544 cmos_get_fd_drive_type(fd_type[1]); 545 rtc_set_memory(rtc_state, 0x10, val); 546 547 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 548 nb = 0; 549 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 550 nb++; 551 } 552 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 553 nb++; 554 } 555 switch (nb) { 556 case 0: 557 break; 558 case 1: 559 val |= 0x01; /* 1 drive, ready for boot */ 560 break; 561 case 2: 562 val |= 0x41; /* 2 drives, ready for boot */ 563 break; 564 } 565 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 566 } 567 568 typedef struct pc_cmos_init_late_arg { 569 ISADevice *rtc_state; 570 BusState *idebus[2]; 571 } pc_cmos_init_late_arg; 572 573 typedef struct check_fdc_state { 574 ISADevice *floppy; 575 bool multiple; 576 } CheckFdcState; 577 578 static int check_fdc(Object *obj, void *opaque) 579 { 580 CheckFdcState *state = opaque; 581 Object *fdc; 582 uint32_t iobase; 583 Error *local_err = NULL; 584 585 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 586 if (!fdc) { 587 return 0; 588 } 589 590 iobase = object_property_get_uint(obj, "iobase", &local_err); 591 if (local_err || iobase != 0x3f0) { 592 error_free(local_err); 593 return 0; 594 } 595 596 if (state->floppy) { 597 state->multiple = true; 598 } else { 599 state->floppy = ISA_DEVICE(obj); 600 } 601 return 0; 602 } 603 604 static const char * const fdc_container_path[] = { 605 "/unattached", "/peripheral", "/peripheral-anon" 606 }; 607 608 /* 609 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 610 * and ACPI objects. 611 */ 612 ISADevice *pc_find_fdc0(void) 613 { 614 int i; 615 Object *container; 616 CheckFdcState state = { 0 }; 617 618 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 619 container = container_get(qdev_get_machine(), fdc_container_path[i]); 620 object_child_foreach(container, check_fdc, &state); 621 } 622 623 if (state.multiple) { 624 warn_report("multiple floppy disk controllers with " 625 "iobase=0x3f0 have been found"); 626 error_printf("the one being picked for CMOS setup might not reflect " 627 "your intent"); 628 } 629 630 return state.floppy; 631 } 632 633 static void pc_cmos_init_late(void *opaque) 634 { 635 pc_cmos_init_late_arg *arg = opaque; 636 ISADevice *s = arg->rtc_state; 637 int16_t cylinders; 638 int8_t heads, sectors; 639 int val; 640 int i, trans; 641 642 val = 0; 643 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 644 &cylinders, &heads, §ors) >= 0) { 645 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 646 val |= 0xf0; 647 } 648 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 649 &cylinders, &heads, §ors) >= 0) { 650 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 651 val |= 0x0f; 652 } 653 rtc_set_memory(s, 0x12, val); 654 655 val = 0; 656 for (i = 0; i < 4; i++) { 657 /* NOTE: ide_get_geometry() returns the physical 658 geometry. It is always such that: 1 <= sects <= 63, 1 659 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 660 geometry can be different if a translation is done. */ 661 if (arg->idebus[i / 2] && 662 ide_get_geometry(arg->idebus[i / 2], i % 2, 663 &cylinders, &heads, §ors) >= 0) { 664 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 665 assert((trans & ~3) == 0); 666 val |= trans << (i * 2); 667 } 668 } 669 rtc_set_memory(s, 0x39, val); 670 671 pc_cmos_init_floppy(s, pc_find_fdc0()); 672 673 qemu_unregister_reset(pc_cmos_init_late, opaque); 674 } 675 676 void pc_cmos_init(PCMachineState *pcms, 677 BusState *idebus0, BusState *idebus1, 678 ISADevice *s) 679 { 680 int val; 681 static pc_cmos_init_late_arg arg; 682 X86MachineState *x86ms = X86_MACHINE(pcms); 683 684 /* various important CMOS locations needed by PC/Bochs bios */ 685 686 /* memory size */ 687 /* base memory (first MiB) */ 688 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 689 rtc_set_memory(s, 0x15, val); 690 rtc_set_memory(s, 0x16, val >> 8); 691 /* extended memory (next 64MiB) */ 692 if (x86ms->below_4g_mem_size > 1 * MiB) { 693 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 694 } else { 695 val = 0; 696 } 697 if (val > 65535) 698 val = 65535; 699 rtc_set_memory(s, 0x17, val); 700 rtc_set_memory(s, 0x18, val >> 8); 701 rtc_set_memory(s, 0x30, val); 702 rtc_set_memory(s, 0x31, val >> 8); 703 /* memory between 16MiB and 4GiB */ 704 if (x86ms->below_4g_mem_size > 16 * MiB) { 705 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 706 } else { 707 val = 0; 708 } 709 if (val > 65535) 710 val = 65535; 711 rtc_set_memory(s, 0x34, val); 712 rtc_set_memory(s, 0x35, val >> 8); 713 /* memory above 4GiB */ 714 val = x86ms->above_4g_mem_size / 65536; 715 rtc_set_memory(s, 0x5b, val); 716 rtc_set_memory(s, 0x5c, val >> 8); 717 rtc_set_memory(s, 0x5d, val >> 16); 718 719 object_property_add_link(OBJECT(pcms), "rtc_state", 720 TYPE_ISA_DEVICE, 721 (Object **)&x86ms->rtc, 722 object_property_allow_set_link, 723 OBJ_PROP_LINK_STRONG, &error_abort); 724 object_property_set_link(OBJECT(pcms), OBJECT(s), 725 "rtc_state", &error_abort); 726 727 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 728 729 val = 0; 730 val |= 0x02; /* FPU is there */ 731 val |= 0x04; /* PS/2 mouse installed */ 732 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 733 734 /* hard drives and FDC */ 735 arg.rtc_state = s; 736 arg.idebus[0] = idebus0; 737 arg.idebus[1] = idebus1; 738 qemu_register_reset(pc_cmos_init_late, &arg); 739 } 740 741 #define TYPE_PORT92 "port92" 742 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 743 744 /* port 92 stuff: could be split off */ 745 typedef struct Port92State { 746 ISADevice parent_obj; 747 748 MemoryRegion io; 749 uint8_t outport; 750 qemu_irq a20_out; 751 } Port92State; 752 753 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 754 unsigned size) 755 { 756 Port92State *s = opaque; 757 int oldval = s->outport; 758 759 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 760 s->outport = val; 761 qemu_set_irq(s->a20_out, (val >> 1) & 1); 762 if ((val & 1) && !(oldval & 1)) { 763 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 764 } 765 } 766 767 static uint64_t port92_read(void *opaque, hwaddr addr, 768 unsigned size) 769 { 770 Port92State *s = opaque; 771 uint32_t ret; 772 773 ret = s->outport; 774 DPRINTF("port92: read 0x%02x\n", ret); 775 return ret; 776 } 777 778 static void port92_init(ISADevice *dev, qemu_irq a20_out) 779 { 780 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 781 } 782 783 static const VMStateDescription vmstate_port92_isa = { 784 .name = "port92", 785 .version_id = 1, 786 .minimum_version_id = 1, 787 .fields = (VMStateField[]) { 788 VMSTATE_UINT8(outport, Port92State), 789 VMSTATE_END_OF_LIST() 790 } 791 }; 792 793 static void port92_reset(DeviceState *d) 794 { 795 Port92State *s = PORT92(d); 796 797 s->outport &= ~1; 798 } 799 800 static const MemoryRegionOps port92_ops = { 801 .read = port92_read, 802 .write = port92_write, 803 .impl = { 804 .min_access_size = 1, 805 .max_access_size = 1, 806 }, 807 .endianness = DEVICE_LITTLE_ENDIAN, 808 }; 809 810 static void port92_initfn(Object *obj) 811 { 812 Port92State *s = PORT92(obj); 813 814 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 815 816 s->outport = 0; 817 818 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 819 } 820 821 static void port92_realizefn(DeviceState *dev, Error **errp) 822 { 823 ISADevice *isadev = ISA_DEVICE(dev); 824 Port92State *s = PORT92(dev); 825 826 isa_register_ioport(isadev, &s->io, 0x92); 827 } 828 829 static void port92_class_initfn(ObjectClass *klass, void *data) 830 { 831 DeviceClass *dc = DEVICE_CLASS(klass); 832 833 dc->realize = port92_realizefn; 834 dc->reset = port92_reset; 835 dc->vmsd = &vmstate_port92_isa; 836 /* 837 * Reason: unlike ordinary ISA devices, this one needs additional 838 * wiring: its A20 output line needs to be wired up by 839 * port92_init(). 840 */ 841 dc->user_creatable = false; 842 } 843 844 static const TypeInfo port92_info = { 845 .name = TYPE_PORT92, 846 .parent = TYPE_ISA_DEVICE, 847 .instance_size = sizeof(Port92State), 848 .instance_init = port92_initfn, 849 .class_init = port92_class_initfn, 850 }; 851 852 static void port92_register_types(void) 853 { 854 type_register_static(&port92_info); 855 } 856 857 type_init(port92_register_types) 858 859 static void handle_a20_line_change(void *opaque, int irq, int level) 860 { 861 X86CPU *cpu = opaque; 862 863 /* XXX: send to all CPUs ? */ 864 /* XXX: add logic to handle multiple A20 line sources */ 865 x86_cpu_set_a20(cpu, level); 866 } 867 868 #define NE2000_NB_MAX 6 869 870 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 871 0x280, 0x380 }; 872 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 873 874 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 875 { 876 static int nb_ne2k = 0; 877 878 if (nb_ne2k == NE2000_NB_MAX) 879 return; 880 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 881 ne2000_irq[nb_ne2k], nd); 882 nb_ne2k++; 883 } 884 885 DeviceState *cpu_get_current_apic(void) 886 { 887 if (current_cpu) { 888 X86CPU *cpu = X86_CPU(current_cpu); 889 return cpu->apic_state; 890 } else { 891 return NULL; 892 } 893 } 894 895 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 896 { 897 X86CPU *cpu = opaque; 898 899 if (level) { 900 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 901 } 902 } 903 904 /* 905 * This function is very similar to smp_parse() 906 * in hw/core/machine.c but includes CPU die support. 907 */ 908 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 909 { 910 X86MachineState *x86ms = X86_MACHINE(ms); 911 912 if (opts) { 913 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 914 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 915 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 916 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 917 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 918 919 /* compute missing values, prefer sockets over cores over threads */ 920 if (cpus == 0 || sockets == 0) { 921 cores = cores > 0 ? cores : 1; 922 threads = threads > 0 ? threads : 1; 923 if (cpus == 0) { 924 sockets = sockets > 0 ? sockets : 1; 925 cpus = cores * threads * dies * sockets; 926 } else { 927 ms->smp.max_cpus = 928 qemu_opt_get_number(opts, "maxcpus", cpus); 929 sockets = ms->smp.max_cpus / (cores * threads * dies); 930 } 931 } else if (cores == 0) { 932 threads = threads > 0 ? threads : 1; 933 cores = cpus / (sockets * dies * threads); 934 cores = cores > 0 ? cores : 1; 935 } else if (threads == 0) { 936 threads = cpus / (cores * dies * sockets); 937 threads = threads > 0 ? threads : 1; 938 } else if (sockets * dies * cores * threads < cpus) { 939 error_report("cpu topology: " 940 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 941 "smp_cpus (%u)", 942 sockets, dies, cores, threads, cpus); 943 exit(1); 944 } 945 946 ms->smp.max_cpus = 947 qemu_opt_get_number(opts, "maxcpus", cpus); 948 949 if (ms->smp.max_cpus < cpus) { 950 error_report("maxcpus must be equal to or greater than smp"); 951 exit(1); 952 } 953 954 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 955 error_report("cpu topology: " 956 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 957 "maxcpus (%u)", 958 sockets, dies, cores, threads, 959 ms->smp.max_cpus); 960 exit(1); 961 } 962 963 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 964 warn_report("Invalid CPU topology deprecated: " 965 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 966 "!= maxcpus (%u)", 967 sockets, dies, cores, threads, 968 ms->smp.max_cpus); 969 } 970 971 ms->smp.cpus = cpus; 972 ms->smp.cores = cores; 973 ms->smp.threads = threads; 974 x86ms->smp_dies = dies; 975 } 976 977 if (ms->smp.cpus > 1) { 978 Error *blocker = NULL; 979 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 980 replay_add_blocker(blocker); 981 } 982 } 983 984 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 985 { 986 PCMachineState *pcms = PC_MACHINE(ms); 987 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); 988 Error *local_err = NULL; 989 990 if (id < 0) { 991 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 992 return; 993 } 994 995 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 996 error_setg(errp, "Unable to add CPU: %" PRIi64 997 ", resulting APIC ID (%" PRIi64 ") is too large", 998 id, apic_id); 999 return; 1000 } 1001 1002 x86_cpu_new(PC_MACHINE(ms), apic_id, &local_err); 1003 if (local_err) { 1004 error_propagate(errp, local_err); 1005 return; 1006 } 1007 } 1008 1009 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1010 { 1011 if (cpus_count > 0xff) { 1012 /* If the number of CPUs can't be represented in 8 bits, the 1013 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1014 * to make old BIOSes fail more predictably. 1015 */ 1016 rtc_set_memory(rtc, 0x5f, 0); 1017 } else { 1018 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1019 } 1020 } 1021 1022 static 1023 void pc_machine_done(Notifier *notifier, void *data) 1024 { 1025 PCMachineState *pcms = container_of(notifier, 1026 PCMachineState, machine_done); 1027 X86MachineState *x86ms = X86_MACHINE(pcms); 1028 PCIBus *bus = pcms->bus; 1029 1030 /* set the number of CPUs */ 1031 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1032 1033 if (bus) { 1034 int extra_hosts = 0; 1035 1036 QLIST_FOREACH(bus, &bus->child, sibling) { 1037 /* look for expander root buses */ 1038 if (pci_bus_is_root(bus)) { 1039 extra_hosts++; 1040 } 1041 } 1042 if (extra_hosts && x86ms->fw_cfg) { 1043 uint64_t *val = g_malloc(sizeof(*val)); 1044 *val = cpu_to_le64(extra_hosts); 1045 fw_cfg_add_file(x86ms->fw_cfg, 1046 "etc/extra-pci-roots", val, sizeof(*val)); 1047 } 1048 } 1049 1050 acpi_setup(); 1051 if (x86ms->fw_cfg) { 1052 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 1053 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 1054 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1055 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1056 } 1057 1058 if (x86ms->apic_id_limit > 255 && !xen_enabled()) { 1059 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1060 1061 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1062 iommu->intr_eim != ON_OFF_AUTO_ON) { 1063 error_report("current -smp configuration requires " 1064 "Extended Interrupt Mode enabled. " 1065 "You can add an IOMMU using: " 1066 "-device intel-iommu,intremap=on,eim=on"); 1067 exit(EXIT_FAILURE); 1068 } 1069 } 1070 } 1071 1072 void pc_guest_info_init(PCMachineState *pcms) 1073 { 1074 int i; 1075 MachineState *ms = MACHINE(pcms); 1076 X86MachineState *x86ms = X86_MACHINE(pcms); 1077 1078 x86ms->apic_xrupt_override = kvm_allows_irq0_override(); 1079 pcms->numa_nodes = ms->numa_state->num_nodes; 1080 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1081 sizeof *pcms->node_mem); 1082 for (i = 0; i < ms->numa_state->num_nodes; i++) { 1083 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 1084 } 1085 1086 pcms->machine_done.notify = pc_machine_done; 1087 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1088 } 1089 1090 /* setup pci memory address space mapping into system address space */ 1091 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1092 MemoryRegion *pci_address_space) 1093 { 1094 /* Set to lower priority than RAM */ 1095 memory_region_add_subregion_overlap(system_memory, 0x0, 1096 pci_address_space, -1); 1097 } 1098 1099 void xen_load_linux(PCMachineState *pcms) 1100 { 1101 int i; 1102 FWCfgState *fw_cfg; 1103 X86MachineState *x86ms = X86_MACHINE(pcms); 1104 1105 assert(MACHINE(pcms)->kernel_filename != NULL); 1106 1107 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1108 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1109 rom_set_fw(fw_cfg); 1110 1111 x86_load_linux(pcms, fw_cfg); 1112 for (i = 0; i < nb_option_roms; i++) { 1113 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1114 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1115 !strcmp(option_rom[i].name, "pvh.bin") || 1116 !strcmp(option_rom[i].name, "multiboot.bin")); 1117 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1118 } 1119 x86ms->fw_cfg = fw_cfg; 1120 } 1121 1122 void pc_memory_init(PCMachineState *pcms, 1123 MemoryRegion *system_memory, 1124 MemoryRegion *rom_memory, 1125 MemoryRegion **ram_memory) 1126 { 1127 int linux_boot, i; 1128 MemoryRegion *ram, *option_rom_mr; 1129 MemoryRegion *ram_below_4g, *ram_above_4g; 1130 FWCfgState *fw_cfg; 1131 MachineState *machine = MACHINE(pcms); 1132 MachineClass *mc = MACHINE_GET_CLASS(machine); 1133 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1134 X86MachineState *x86ms = X86_MACHINE(pcms); 1135 1136 assert(machine->ram_size == x86ms->below_4g_mem_size + 1137 x86ms->above_4g_mem_size); 1138 1139 linux_boot = (machine->kernel_filename != NULL); 1140 1141 /* Allocate RAM. We allocate it as a single memory region and use 1142 * aliases to address portions of it, mostly for backwards compatibility 1143 * with older qemus that used qemu_ram_alloc(). 1144 */ 1145 ram = g_malloc(sizeof(*ram)); 1146 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1147 machine->ram_size); 1148 *ram_memory = ram; 1149 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1150 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1151 0, x86ms->below_4g_mem_size); 1152 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1153 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1154 if (x86ms->above_4g_mem_size > 0) { 1155 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1156 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1157 x86ms->below_4g_mem_size, 1158 x86ms->above_4g_mem_size); 1159 memory_region_add_subregion(system_memory, 0x100000000ULL, 1160 ram_above_4g); 1161 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 1162 } 1163 1164 if (!pcmc->has_reserved_memory && 1165 (machine->ram_slots || 1166 (machine->maxram_size > machine->ram_size))) { 1167 1168 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1169 mc->name); 1170 exit(EXIT_FAILURE); 1171 } 1172 1173 /* always allocate the device memory information */ 1174 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1175 1176 /* initialize device memory address space */ 1177 if (pcmc->has_reserved_memory && 1178 (machine->ram_size < machine->maxram_size)) { 1179 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1180 1181 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1182 error_report("unsupported amount of memory slots: %"PRIu64, 1183 machine->ram_slots); 1184 exit(EXIT_FAILURE); 1185 } 1186 1187 if (QEMU_ALIGN_UP(machine->maxram_size, 1188 TARGET_PAGE_SIZE) != machine->maxram_size) { 1189 error_report("maximum memory size must by aligned to multiple of " 1190 "%d bytes", TARGET_PAGE_SIZE); 1191 exit(EXIT_FAILURE); 1192 } 1193 1194 machine->device_memory->base = 1195 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 1196 1197 if (pcmc->enforce_aligned_dimm) { 1198 /* size device region assuming 1G page max alignment per slot */ 1199 device_mem_size += (1 * GiB) * machine->ram_slots; 1200 } 1201 1202 if ((machine->device_memory->base + device_mem_size) < 1203 device_mem_size) { 1204 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1205 machine->maxram_size); 1206 exit(EXIT_FAILURE); 1207 } 1208 1209 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1210 "device-memory", device_mem_size); 1211 memory_region_add_subregion(system_memory, machine->device_memory->base, 1212 &machine->device_memory->mr); 1213 } 1214 1215 /* Initialize PC system firmware */ 1216 pc_system_firmware_init(pcms, rom_memory); 1217 1218 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1219 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1220 &error_fatal); 1221 if (pcmc->pci_enabled) { 1222 memory_region_set_readonly(option_rom_mr, true); 1223 } 1224 memory_region_add_subregion_overlap(rom_memory, 1225 PC_ROM_MIN_VGA, 1226 option_rom_mr, 1227 1); 1228 1229 fw_cfg = fw_cfg_arch_create(machine, 1230 x86ms->boot_cpus, x86ms->apic_id_limit); 1231 1232 rom_set_fw(fw_cfg); 1233 1234 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1235 uint64_t *val = g_malloc(sizeof(*val)); 1236 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1237 uint64_t res_mem_end = machine->device_memory->base; 1238 1239 if (!pcmc->broken_reserved_end) { 1240 res_mem_end += memory_region_size(&machine->device_memory->mr); 1241 } 1242 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1243 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1244 } 1245 1246 if (linux_boot) { 1247 x86_load_linux(pcms, fw_cfg); 1248 } 1249 1250 for (i = 0; i < nb_option_roms; i++) { 1251 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1252 } 1253 x86ms->fw_cfg = fw_cfg; 1254 1255 /* Init default IOAPIC address space */ 1256 x86ms->ioapic_as = &address_space_memory; 1257 1258 /* Init ACPI memory hotplug IO base address */ 1259 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1260 } 1261 1262 /* 1263 * The 64bit pci hole starts after "above 4G RAM" and 1264 * potentially the space reserved for memory hotplug. 1265 */ 1266 uint64_t pc_pci_hole64_start(void) 1267 { 1268 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1269 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1270 MachineState *ms = MACHINE(pcms); 1271 X86MachineState *x86ms = X86_MACHINE(pcms); 1272 uint64_t hole64_start = 0; 1273 1274 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1275 hole64_start = ms->device_memory->base; 1276 if (!pcmc->broken_reserved_end) { 1277 hole64_start += memory_region_size(&ms->device_memory->mr); 1278 } 1279 } else { 1280 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1281 } 1282 1283 return ROUND_UP(hole64_start, 1 * GiB); 1284 } 1285 1286 qemu_irq pc_allocate_cpu_irq(void) 1287 { 1288 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1289 } 1290 1291 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1292 { 1293 DeviceState *dev = NULL; 1294 1295 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1296 if (pci_bus) { 1297 PCIDevice *pcidev = pci_vga_init(pci_bus); 1298 dev = pcidev ? &pcidev->qdev : NULL; 1299 } else if (isa_bus) { 1300 ISADevice *isadev = isa_vga_init(isa_bus); 1301 dev = isadev ? DEVICE(isadev) : NULL; 1302 } 1303 rom_reset_order_override(); 1304 return dev; 1305 } 1306 1307 static const MemoryRegionOps ioport80_io_ops = { 1308 .write = ioport80_write, 1309 .read = ioport80_read, 1310 .endianness = DEVICE_NATIVE_ENDIAN, 1311 .impl = { 1312 .min_access_size = 1, 1313 .max_access_size = 1, 1314 }, 1315 }; 1316 1317 static const MemoryRegionOps ioportF0_io_ops = { 1318 .write = ioportF0_write, 1319 .read = ioportF0_read, 1320 .endianness = DEVICE_NATIVE_ENDIAN, 1321 .impl = { 1322 .min_access_size = 1, 1323 .max_access_size = 1, 1324 }, 1325 }; 1326 1327 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1328 { 1329 int i; 1330 DriveInfo *fd[MAX_FD]; 1331 qemu_irq *a20_line; 1332 ISADevice *i8042, *port92, *vmmouse; 1333 1334 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1335 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1336 1337 for (i = 0; i < MAX_FD; i++) { 1338 fd[i] = drive_get(IF_FLOPPY, 0, i); 1339 create_fdctrl |= !!fd[i]; 1340 } 1341 if (create_fdctrl) { 1342 fdctrl_init_isa(isa_bus, fd); 1343 } 1344 1345 i8042 = isa_create_simple(isa_bus, "i8042"); 1346 if (!no_vmport) { 1347 vmport_init(isa_bus); 1348 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1349 } else { 1350 vmmouse = NULL; 1351 } 1352 if (vmmouse) { 1353 DeviceState *dev = DEVICE(vmmouse); 1354 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1355 qdev_init_nofail(dev); 1356 } 1357 port92 = isa_create_simple(isa_bus, "port92"); 1358 1359 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1360 i8042_setup_a20_line(i8042, a20_line[0]); 1361 port92_init(port92, a20_line[1]); 1362 g_free(a20_line); 1363 } 1364 1365 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1366 ISADevice **rtc_state, 1367 bool create_fdctrl, 1368 bool no_vmport, 1369 bool has_pit, 1370 uint32_t hpet_irqs) 1371 { 1372 int i; 1373 DeviceState *hpet = NULL; 1374 int pit_isa_irq = 0; 1375 qemu_irq pit_alt_irq = NULL; 1376 qemu_irq rtc_irq = NULL; 1377 ISADevice *pit = NULL; 1378 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1379 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1380 1381 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1382 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1383 1384 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1385 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1386 1387 /* 1388 * Check if an HPET shall be created. 1389 * 1390 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1391 * when the HPET wants to take over. Thus we have to disable the latter. 1392 */ 1393 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1394 /* In order to set property, here not using sysbus_try_create_simple */ 1395 hpet = qdev_try_create(NULL, TYPE_HPET); 1396 if (hpet) { 1397 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1398 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1399 * IRQ8 and IRQ2. 1400 */ 1401 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1402 HPET_INTCAP, NULL); 1403 if (!compat) { 1404 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1405 } 1406 qdev_init_nofail(hpet); 1407 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1408 1409 for (i = 0; i < GSI_NUM_PINS; i++) { 1410 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1411 } 1412 pit_isa_irq = -1; 1413 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1414 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1415 } 1416 } 1417 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1418 1419 qemu_register_boot_set(pc_boot_set, *rtc_state); 1420 1421 if (!xen_enabled() && has_pit) { 1422 if (kvm_pit_in_kernel()) { 1423 pit = kvm_pit_init(isa_bus, 0x40); 1424 } else { 1425 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1426 } 1427 if (hpet) { 1428 /* connect PIT to output control line of the HPET */ 1429 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1430 } 1431 pcspk_init(isa_bus, pit); 1432 } 1433 1434 i8257_dma_init(isa_bus, 0); 1435 1436 /* Super I/O */ 1437 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 1438 } 1439 1440 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1441 { 1442 int i; 1443 1444 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1445 for (i = 0; i < nb_nics; i++) { 1446 NICInfo *nd = &nd_table[i]; 1447 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1448 1449 if (g_str_equal(model, "ne2k_isa")) { 1450 pc_init_ne2k_isa(isa_bus, nd); 1451 } else { 1452 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1453 } 1454 } 1455 rom_reset_order_override(); 1456 } 1457 1458 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1459 { 1460 DeviceState *dev; 1461 SysBusDevice *d; 1462 unsigned int i; 1463 1464 if (kvm_ioapic_in_kernel()) { 1465 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 1466 } else { 1467 dev = qdev_create(NULL, TYPE_IOAPIC); 1468 } 1469 if (parent_name) { 1470 object_property_add_child(object_resolve_path(parent_name, NULL), 1471 "ioapic", OBJECT(dev), NULL); 1472 } 1473 qdev_init_nofail(dev); 1474 d = SYS_BUS_DEVICE(dev); 1475 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1476 1477 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1478 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1479 } 1480 } 1481 1482 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1483 Error **errp) 1484 { 1485 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1486 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1487 const MachineState *ms = MACHINE(hotplug_dev); 1488 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1489 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1490 Error *local_err = NULL; 1491 1492 /* 1493 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1494 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1495 * addition to cover this case. 1496 */ 1497 if (!pcms->acpi_dev || !acpi_enabled) { 1498 error_setg(errp, 1499 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1500 return; 1501 } 1502 1503 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1504 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1505 return; 1506 } 1507 1508 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 1509 if (local_err) { 1510 error_propagate(errp, local_err); 1511 return; 1512 } 1513 1514 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1515 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1516 } 1517 1518 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1519 DeviceState *dev, Error **errp) 1520 { 1521 Error *local_err = NULL; 1522 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1523 MachineState *ms = MACHINE(hotplug_dev); 1524 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1525 1526 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 1527 if (local_err) { 1528 goto out; 1529 } 1530 1531 if (is_nvdimm) { 1532 nvdimm_plug(ms->nvdimms_state); 1533 } 1534 1535 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1536 out: 1537 error_propagate(errp, local_err); 1538 } 1539 1540 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1541 DeviceState *dev, Error **errp) 1542 { 1543 Error *local_err = NULL; 1544 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1545 1546 /* 1547 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1548 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1549 * addition to cover this case. 1550 */ 1551 if (!pcms->acpi_dev || !acpi_enabled) { 1552 error_setg(&local_err, 1553 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1554 goto out; 1555 } 1556 1557 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1558 error_setg(&local_err, 1559 "nvdimm device hot unplug is not supported yet."); 1560 goto out; 1561 } 1562 1563 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 1564 &local_err); 1565 out: 1566 error_propagate(errp, local_err); 1567 } 1568 1569 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1570 DeviceState *dev, Error **errp) 1571 { 1572 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1573 Error *local_err = NULL; 1574 1575 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1576 if (local_err) { 1577 goto out; 1578 } 1579 1580 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1581 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 1582 out: 1583 error_propagate(errp, local_err); 1584 } 1585 1586 static int pc_apic_cmp(const void *a, const void *b) 1587 { 1588 CPUArchId *apic_a = (CPUArchId *)a; 1589 CPUArchId *apic_b = (CPUArchId *)b; 1590 1591 return apic_a->arch_id - apic_b->arch_id; 1592 } 1593 1594 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1595 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 1596 * entry corresponding to CPU's apic_id returns NULL. 1597 */ 1598 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1599 { 1600 CPUArchId apic_id, *found_cpu; 1601 1602 apic_id.arch_id = id; 1603 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 1604 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 1605 pc_apic_cmp); 1606 if (found_cpu && idx) { 1607 *idx = found_cpu - ms->possible_cpus->cpus; 1608 } 1609 return found_cpu; 1610 } 1611 1612 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1613 DeviceState *dev, Error **errp) 1614 { 1615 CPUArchId *found_cpu; 1616 Error *local_err = NULL; 1617 X86CPU *cpu = X86_CPU(dev); 1618 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1619 X86MachineState *x86ms = X86_MACHINE(pcms); 1620 1621 if (pcms->acpi_dev) { 1622 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1623 if (local_err) { 1624 goto out; 1625 } 1626 } 1627 1628 /* increment the number of CPUs */ 1629 x86ms->boot_cpus++; 1630 if (x86ms->rtc) { 1631 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1632 } 1633 if (x86ms->fw_cfg) { 1634 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1635 } 1636 1637 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1638 found_cpu->cpu = OBJECT(dev); 1639 out: 1640 error_propagate(errp, local_err); 1641 } 1642 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1643 DeviceState *dev, Error **errp) 1644 { 1645 int idx = -1; 1646 Error *local_err = NULL; 1647 X86CPU *cpu = X86_CPU(dev); 1648 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1649 1650 if (!pcms->acpi_dev) { 1651 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 1652 goto out; 1653 } 1654 1655 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1656 assert(idx != -1); 1657 if (idx == 0) { 1658 error_setg(&local_err, "Boot CPU is unpluggable"); 1659 goto out; 1660 } 1661 1662 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 1663 &local_err); 1664 if (local_err) { 1665 goto out; 1666 } 1667 1668 out: 1669 error_propagate(errp, local_err); 1670 1671 } 1672 1673 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1674 DeviceState *dev, Error **errp) 1675 { 1676 CPUArchId *found_cpu; 1677 Error *local_err = NULL; 1678 X86CPU *cpu = X86_CPU(dev); 1679 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1680 X86MachineState *x86ms = X86_MACHINE(pcms); 1681 1682 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1683 if (local_err) { 1684 goto out; 1685 } 1686 1687 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1688 found_cpu->cpu = NULL; 1689 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 1690 1691 /* decrement the number of CPUs */ 1692 x86ms->boot_cpus--; 1693 /* Update the number of CPUs in CMOS */ 1694 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1695 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1696 out: 1697 error_propagate(errp, local_err); 1698 } 1699 1700 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1701 DeviceState *dev, Error **errp) 1702 { 1703 int idx; 1704 CPUState *cs; 1705 CPUArchId *cpu_slot; 1706 X86CPUTopoInfo topo; 1707 X86CPU *cpu = X86_CPU(dev); 1708 CPUX86State *env = &cpu->env; 1709 MachineState *ms = MACHINE(hotplug_dev); 1710 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1711 X86MachineState *x86ms = X86_MACHINE(pcms); 1712 unsigned int smp_cores = ms->smp.cores; 1713 unsigned int smp_threads = ms->smp.threads; 1714 1715 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 1716 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 1717 ms->cpu_type); 1718 return; 1719 } 1720 1721 env->nr_dies = x86ms->smp_dies; 1722 1723 /* 1724 * If APIC ID is not set, 1725 * set it based on socket/die/core/thread properties. 1726 */ 1727 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1728 int max_socket = (ms->smp.max_cpus - 1) / 1729 smp_threads / smp_cores / x86ms->smp_dies; 1730 1731 /* 1732 * die-id was optional in QEMU 4.0 and older, so keep it optional 1733 * if there's only one die per socket. 1734 */ 1735 if (cpu->die_id < 0 && x86ms->smp_dies == 1) { 1736 cpu->die_id = 0; 1737 } 1738 1739 if (cpu->socket_id < 0) { 1740 error_setg(errp, "CPU socket-id is not set"); 1741 return; 1742 } else if (cpu->socket_id > max_socket) { 1743 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1744 cpu->socket_id, max_socket); 1745 return; 1746 } 1747 if (cpu->die_id < 0) { 1748 error_setg(errp, "CPU die-id is not set"); 1749 return; 1750 } else if (cpu->die_id > x86ms->smp_dies - 1) { 1751 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 1752 cpu->die_id, x86ms->smp_dies - 1); 1753 return; 1754 } 1755 if (cpu->core_id < 0) { 1756 error_setg(errp, "CPU core-id is not set"); 1757 return; 1758 } else if (cpu->core_id > (smp_cores - 1)) { 1759 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1760 cpu->core_id, smp_cores - 1); 1761 return; 1762 } 1763 if (cpu->thread_id < 0) { 1764 error_setg(errp, "CPU thread-id is not set"); 1765 return; 1766 } else if (cpu->thread_id > (smp_threads - 1)) { 1767 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1768 cpu->thread_id, smp_threads - 1); 1769 return; 1770 } 1771 1772 topo.pkg_id = cpu->socket_id; 1773 topo.die_id = cpu->die_id; 1774 topo.core_id = cpu->core_id; 1775 topo.smt_id = cpu->thread_id; 1776 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, 1777 smp_threads, &topo); 1778 } 1779 1780 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1781 if (!cpu_slot) { 1782 MachineState *ms = MACHINE(pcms); 1783 1784 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, 1785 smp_cores, smp_threads, &topo); 1786 error_setg(errp, 1787 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 1788 " APIC ID %" PRIu32 ", valid index range 0:%d", 1789 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 1790 cpu->apic_id, ms->possible_cpus->len - 1); 1791 return; 1792 } 1793 1794 if (cpu_slot->cpu) { 1795 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1796 idx, cpu->apic_id); 1797 return; 1798 } 1799 1800 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1801 * so that machine_query_hotpluggable_cpus would show correct values 1802 */ 1803 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1804 * once -smp refactoring is complete and there will be CPU private 1805 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1806 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, 1807 smp_cores, smp_threads, &topo); 1808 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1809 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1810 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1811 return; 1812 } 1813 cpu->socket_id = topo.pkg_id; 1814 1815 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 1816 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 1817 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 1818 return; 1819 } 1820 cpu->die_id = topo.die_id; 1821 1822 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1823 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1824 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1825 return; 1826 } 1827 cpu->core_id = topo.core_id; 1828 1829 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1830 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1831 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1832 return; 1833 } 1834 cpu->thread_id = topo.smt_id; 1835 1836 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 1837 !kvm_hv_vpindex_settable()) { 1838 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 1839 return; 1840 } 1841 1842 cs = CPU(cpu); 1843 cs->cpu_index = idx; 1844 1845 numa_cpu_pre_plug(cpu_slot, dev, errp); 1846 } 1847 1848 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 1849 DeviceState *dev, Error **errp) 1850 { 1851 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1852 Error *local_err = NULL; 1853 1854 if (!hotplug_dev2) { 1855 /* 1856 * Without a bus hotplug handler, we cannot control the plug/unplug 1857 * order. This should never be the case on x86, however better add 1858 * a safety net. 1859 */ 1860 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 1861 return; 1862 } 1863 /* 1864 * First, see if we can plug this memory device at all. If that 1865 * succeeds, branch of to the actual hotplug handler. 1866 */ 1867 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1868 &local_err); 1869 if (!local_err) { 1870 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1871 } 1872 error_propagate(errp, local_err); 1873 } 1874 1875 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 1876 DeviceState *dev, Error **errp) 1877 { 1878 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1879 Error *local_err = NULL; 1880 1881 /* 1882 * Plug the memory device first and then branch off to the actual 1883 * hotplug handler. If that one fails, we can easily undo the memory 1884 * device bits. 1885 */ 1886 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1887 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1888 if (local_err) { 1889 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1890 } 1891 error_propagate(errp, local_err); 1892 } 1893 1894 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 1895 DeviceState *dev, Error **errp) 1896 { 1897 /* We don't support virtio pmem hot unplug */ 1898 error_setg(errp, "virtio pmem device unplug not supported."); 1899 } 1900 1901 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 1902 DeviceState *dev, Error **errp) 1903 { 1904 /* We don't support virtio pmem hot unplug */ 1905 } 1906 1907 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1908 DeviceState *dev, Error **errp) 1909 { 1910 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1911 pc_memory_pre_plug(hotplug_dev, dev, errp); 1912 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1913 pc_cpu_pre_plug(hotplug_dev, dev, errp); 1914 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1915 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 1916 } 1917 } 1918 1919 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1920 DeviceState *dev, Error **errp) 1921 { 1922 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1923 pc_memory_plug(hotplug_dev, dev, errp); 1924 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1925 pc_cpu_plug(hotplug_dev, dev, errp); 1926 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1927 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 1928 } 1929 } 1930 1931 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1932 DeviceState *dev, Error **errp) 1933 { 1934 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1935 pc_memory_unplug_request(hotplug_dev, dev, errp); 1936 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1937 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1938 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1939 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 1940 } else { 1941 error_setg(errp, "acpi: device unplug request for not supported device" 1942 " type: %s", object_get_typename(OBJECT(dev))); 1943 } 1944 } 1945 1946 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1947 DeviceState *dev, Error **errp) 1948 { 1949 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1950 pc_memory_unplug(hotplug_dev, dev, errp); 1951 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1952 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 1953 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1954 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 1955 } else { 1956 error_setg(errp, "acpi: device unplug for not supported device" 1957 " type: %s", object_get_typename(OBJECT(dev))); 1958 } 1959 } 1960 1961 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1962 DeviceState *dev) 1963 { 1964 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1965 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1966 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1967 return HOTPLUG_HANDLER(machine); 1968 } 1969 1970 return NULL; 1971 } 1972 1973 static void 1974 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1975 const char *name, void *opaque, 1976 Error **errp) 1977 { 1978 MachineState *ms = MACHINE(obj); 1979 int64_t value = 0; 1980 1981 if (ms->device_memory) { 1982 value = memory_region_size(&ms->device_memory->mr); 1983 } 1984 1985 visit_type_int(v, name, &value, errp); 1986 } 1987 1988 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1989 void *opaque, Error **errp) 1990 { 1991 PCMachineState *pcms = PC_MACHINE(obj); 1992 OnOffAuto vmport = pcms->vmport; 1993 1994 visit_type_OnOffAuto(v, name, &vmport, errp); 1995 } 1996 1997 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1998 void *opaque, Error **errp) 1999 { 2000 PCMachineState *pcms = PC_MACHINE(obj); 2001 2002 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2003 } 2004 2005 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2006 { 2007 bool smm_available = false; 2008 2009 if (pcms->smm == ON_OFF_AUTO_OFF) { 2010 return false; 2011 } 2012 2013 if (tcg_enabled() || qtest_enabled()) { 2014 smm_available = true; 2015 } else if (kvm_enabled()) { 2016 smm_available = kvm_has_smm(); 2017 } 2018 2019 if (smm_available) { 2020 return true; 2021 } 2022 2023 if (pcms->smm == ON_OFF_AUTO_ON) { 2024 error_report("System Management Mode not supported by this hypervisor."); 2025 exit(1); 2026 } 2027 return false; 2028 } 2029 2030 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2031 void *opaque, Error **errp) 2032 { 2033 PCMachineState *pcms = PC_MACHINE(obj); 2034 OnOffAuto smm = pcms->smm; 2035 2036 visit_type_OnOffAuto(v, name, &smm, errp); 2037 } 2038 2039 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2040 void *opaque, Error **errp) 2041 { 2042 PCMachineState *pcms = PC_MACHINE(obj); 2043 2044 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2045 } 2046 2047 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2048 { 2049 PCMachineState *pcms = PC_MACHINE(obj); 2050 2051 return pcms->smbus_enabled; 2052 } 2053 2054 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2055 { 2056 PCMachineState *pcms = PC_MACHINE(obj); 2057 2058 pcms->smbus_enabled = value; 2059 } 2060 2061 static bool pc_machine_get_sata(Object *obj, Error **errp) 2062 { 2063 PCMachineState *pcms = PC_MACHINE(obj); 2064 2065 return pcms->sata_enabled; 2066 } 2067 2068 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2069 { 2070 PCMachineState *pcms = PC_MACHINE(obj); 2071 2072 pcms->sata_enabled = value; 2073 } 2074 2075 static bool pc_machine_get_pit(Object *obj, Error **errp) 2076 { 2077 PCMachineState *pcms = PC_MACHINE(obj); 2078 2079 return pcms->pit_enabled; 2080 } 2081 2082 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2083 { 2084 PCMachineState *pcms = PC_MACHINE(obj); 2085 2086 pcms->pit_enabled = value; 2087 } 2088 2089 static void pc_machine_initfn(Object *obj) 2090 { 2091 PCMachineState *pcms = PC_MACHINE(obj); 2092 2093 pcms->smm = ON_OFF_AUTO_AUTO; 2094 #ifdef CONFIG_VMPORT 2095 pcms->vmport = ON_OFF_AUTO_AUTO; 2096 #else 2097 pcms->vmport = ON_OFF_AUTO_OFF; 2098 #endif /* CONFIG_VMPORT */ 2099 /* acpi build is enabled by default if machine supports it */ 2100 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2101 pcms->smbus_enabled = true; 2102 pcms->sata_enabled = true; 2103 pcms->pit_enabled = true; 2104 2105 pc_system_flash_create(pcms); 2106 } 2107 2108 static void pc_machine_reset(MachineState *machine) 2109 { 2110 CPUState *cs; 2111 X86CPU *cpu; 2112 2113 qemu_devices_reset(); 2114 2115 /* Reset APIC after devices have been reset to cancel 2116 * any changes that qemu_devices_reset() might have done. 2117 */ 2118 CPU_FOREACH(cs) { 2119 cpu = X86_CPU(cs); 2120 2121 if (cpu->apic_state) { 2122 device_reset(cpu->apic_state); 2123 } 2124 } 2125 } 2126 2127 static void pc_machine_wakeup(MachineState *machine) 2128 { 2129 cpu_synchronize_all_states(); 2130 pc_machine_reset(machine); 2131 cpu_synchronize_all_post_reset(); 2132 } 2133 2134 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 2135 { 2136 X86IOMMUState *iommu = x86_iommu_get_default(); 2137 IntelIOMMUState *intel_iommu; 2138 2139 if (iommu && 2140 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 2141 object_dynamic_cast((Object *)dev, "vfio-pci")) { 2142 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2143 if (!intel_iommu->caching_mode) { 2144 error_setg(errp, "Device assignment is not allowed without " 2145 "enabling caching-mode=on for Intel IOMMU."); 2146 return false; 2147 } 2148 } 2149 2150 return true; 2151 } 2152 2153 static void pc_machine_class_init(ObjectClass *oc, void *data) 2154 { 2155 MachineClass *mc = MACHINE_CLASS(oc); 2156 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2157 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2158 2159 pcmc->pci_enabled = true; 2160 pcmc->has_acpi_build = true; 2161 pcmc->rsdp_in_ram = true; 2162 pcmc->smbios_defaults = true; 2163 pcmc->smbios_uuid_encoded = true; 2164 pcmc->gigabyte_align = true; 2165 pcmc->has_reserved_memory = true; 2166 pcmc->kvmclock_enabled = true; 2167 pcmc->enforce_aligned_dimm = true; 2168 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2169 * to be used at the moment, 32K should be enough for a while. */ 2170 pcmc->acpi_data_size = 0x20000 + 0x8000; 2171 pcmc->save_tsc_khz = true; 2172 pcmc->linuxboot_dma_enabled = true; 2173 pcmc->pvh_enabled = true; 2174 assert(!mc->get_hotplug_handler); 2175 mc->get_hotplug_handler = pc_get_hotplug_handler; 2176 mc->hotplug_allowed = pc_hotplug_allowed; 2177 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 2178 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 2179 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 2180 mc->auto_enable_numa_with_memhp = true; 2181 mc->has_hotpluggable_cpus = true; 2182 mc->default_boot_order = "cad"; 2183 mc->hot_add_cpu = pc_hot_add_cpu; 2184 mc->smp_parse = pc_smp_parse; 2185 mc->block_default_type = IF_IDE; 2186 mc->max_cpus = 255; 2187 mc->reset = pc_machine_reset; 2188 mc->wakeup = pc_machine_wakeup; 2189 hc->pre_plug = pc_machine_device_pre_plug_cb; 2190 hc->plug = pc_machine_device_plug_cb; 2191 hc->unplug_request = pc_machine_device_unplug_request_cb; 2192 hc->unplug = pc_machine_device_unplug_cb; 2193 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2194 mc->nvdimm_supported = true; 2195 mc->numa_mem_supported = true; 2196 2197 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2198 pc_machine_get_device_memory_region_size, NULL, 2199 NULL, NULL, &error_abort); 2200 2201 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2202 pc_machine_get_smm, pc_machine_set_smm, 2203 NULL, NULL, &error_abort); 2204 object_class_property_set_description(oc, PC_MACHINE_SMM, 2205 "Enable SMM (pc & q35)", &error_abort); 2206 2207 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2208 pc_machine_get_vmport, pc_machine_set_vmport, 2209 NULL, NULL, &error_abort); 2210 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2211 "Enable vmport (pc & q35)", &error_abort); 2212 2213 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2214 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2215 2216 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2217 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2218 2219 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2220 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2221 } 2222 2223 static const TypeInfo pc_machine_info = { 2224 .name = TYPE_PC_MACHINE, 2225 .parent = TYPE_X86_MACHINE, 2226 .abstract = true, 2227 .instance_size = sizeof(PCMachineState), 2228 .instance_init = pc_machine_initfn, 2229 .class_size = sizeof(PCMachineClass), 2230 .class_init = pc_machine_class_init, 2231 .interfaces = (InterfaceInfo[]) { 2232 { TYPE_HOTPLUG_HANDLER }, 2233 { } 2234 }, 2235 }; 2236 2237 static void pc_machine_register_types(void) 2238 { 2239 type_register_static(&pc_machine_info); 2240 } 2241 2242 type_init(pc_machine_register_types) 2243