1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial-isa.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_9_1[] = { 83 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 84 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 85 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 86 }; 87 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 88 89 GlobalProperty pc_compat_9_0[] = { 90 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 91 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 92 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 93 { "sev-guest", "legacy-vm-type", "on" }, 94 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 95 }; 96 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 97 98 GlobalProperty pc_compat_8_2[] = {}; 99 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 100 101 GlobalProperty pc_compat_8_1[] = {}; 102 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 103 104 GlobalProperty pc_compat_8_0[] = { 105 { "virtio-mem", "unplugged-inaccessible", "auto" }, 106 }; 107 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 108 109 GlobalProperty pc_compat_7_2[] = { 110 { "ICH9-LPC", "noreboot", "true" }, 111 }; 112 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 113 114 GlobalProperty pc_compat_7_1[] = {}; 115 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 116 117 GlobalProperty pc_compat_7_0[] = {}; 118 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 119 120 GlobalProperty pc_compat_6_2[] = { 121 { "virtio-mem", "unplugged-inaccessible", "off" }, 122 }; 123 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 124 125 GlobalProperty pc_compat_6_1[] = { 126 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 127 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 128 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 129 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 130 }; 131 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 132 133 GlobalProperty pc_compat_6_0[] = { 134 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 135 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 136 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 137 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 138 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 139 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 140 }; 141 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 142 143 GlobalProperty pc_compat_5_2[] = { 144 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 145 }; 146 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 147 148 GlobalProperty pc_compat_5_1[] = { 149 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 150 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 151 }; 152 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 153 154 GlobalProperty pc_compat_5_0[] = { 155 }; 156 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 157 158 GlobalProperty pc_compat_4_2[] = { 159 { "mch", "smbase-smram", "off" }, 160 }; 161 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 162 163 GlobalProperty pc_compat_4_1[] = {}; 164 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 165 166 GlobalProperty pc_compat_4_0[] = {}; 167 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 168 169 GlobalProperty pc_compat_3_1[] = { 170 { "intel-iommu", "dma-drain", "off" }, 171 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 172 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 173 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 174 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 175 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 176 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 177 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 178 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 179 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 180 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 181 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 182 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 183 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 184 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 185 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 186 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 187 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 190 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 191 }; 192 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 193 194 GlobalProperty pc_compat_3_0[] = { 195 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 196 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 197 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 198 }; 199 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 200 201 GlobalProperty pc_compat_2_12[] = { 202 { TYPE_X86_CPU, "legacy-cache", "on" }, 203 { TYPE_X86_CPU, "topoext", "off" }, 204 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 205 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 206 }; 207 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 208 209 GlobalProperty pc_compat_2_11[] = { 210 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 211 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 212 }; 213 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 214 215 GlobalProperty pc_compat_2_10[] = { 216 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 217 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 218 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 219 }; 220 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 221 222 GlobalProperty pc_compat_2_9[] = { 223 { "mch", "extended-tseg-mbytes", "0" }, 224 }; 225 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 226 227 GlobalProperty pc_compat_2_8[] = { 228 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 229 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 230 { "ICH9-LPC", "x-smi-broadcast", "off" }, 231 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 232 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 233 }; 234 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 235 236 GlobalProperty pc_compat_2_7[] = { 237 { TYPE_X86_CPU, "l3-cache", "off" }, 238 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 239 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 240 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 241 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 242 { "isa-pcspk", "migrate", "off" }, 243 }; 244 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 245 246 GlobalProperty pc_compat_2_6[] = { 247 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 248 { "vmxnet3", "romfile", "" }, 249 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 250 { "apic-common", "legacy-instance-id", "on", } 251 }; 252 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 253 254 GlobalProperty pc_compat_2_5[] = {}; 255 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 256 257 GlobalProperty pc_compat_2_4[] = { 258 PC_CPU_MODEL_IDS("2.4.0") 259 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 260 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 261 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 262 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 263 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 264 { TYPE_X86_CPU, "check", "off" }, 265 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 266 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 267 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 268 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 269 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 270 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 271 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 272 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 273 }; 274 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 275 276 /* 277 * @PC_FW_DATA: 278 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 279 * and other BIOS datastructures. 280 * 281 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 282 * reported to be used at the moment, 32K should be enough for a while. 283 */ 284 #define PC_FW_DATA (0x20000 + 0x8000) 285 286 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 287 { 288 GSIState *s; 289 290 s = g_new0(GSIState, 1); 291 if (kvm_ioapic_in_kernel()) { 292 kvm_pc_setup_irq_routing(pci_enabled); 293 } 294 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 295 296 return s; 297 } 298 299 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 300 unsigned size) 301 { 302 } 303 304 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 305 { 306 return 0xffffffffffffffffULL; 307 } 308 309 /* MS-DOS compatibility mode FPU exception support */ 310 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 311 unsigned size) 312 { 313 if (tcg_enabled()) { 314 cpu_set_ignne(); 315 } 316 } 317 318 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 319 { 320 return 0xffffffffffffffffULL; 321 } 322 323 /* PC cmos mappings */ 324 325 #define REG_EQUIPMENT_BYTE 0x14 326 327 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 328 int16_t cylinders, int8_t heads, int8_t sectors) 329 { 330 mc146818rtc_set_cmos_data(s, type_ofs, 47); 331 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 332 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 333 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 334 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 335 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 336 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 337 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 338 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 339 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 340 } 341 342 /* convert boot_device letter to something recognizable by the bios */ 343 static int boot_device2nibble(char boot_device) 344 { 345 switch(boot_device) { 346 case 'a': 347 case 'b': 348 return 0x01; /* floppy boot */ 349 case 'c': 350 return 0x02; /* hard drive boot */ 351 case 'd': 352 return 0x03; /* CD-ROM boot */ 353 case 'n': 354 return 0x04; /* Network boot */ 355 } 356 return 0; 357 } 358 359 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 360 const char *boot_device, Error **errp) 361 { 362 #define PC_MAX_BOOT_DEVICES 3 363 int nbds, bds[3] = { 0, }; 364 int i; 365 366 nbds = strlen(boot_device); 367 if (nbds > PC_MAX_BOOT_DEVICES) { 368 error_setg(errp, "Too many boot devices for PC"); 369 return; 370 } 371 for (i = 0; i < nbds; i++) { 372 bds[i] = boot_device2nibble(boot_device[i]); 373 if (bds[i] == 0) { 374 error_setg(errp, "Invalid boot device for PC: '%c'", 375 boot_device[i]); 376 return; 377 } 378 } 379 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 380 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 381 } 382 383 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 384 { 385 PCMachineState *pcms = opaque; 386 X86MachineState *x86ms = X86_MACHINE(pcms); 387 388 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 389 } 390 391 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 392 { 393 int val, nb; 394 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 395 FLOPPY_DRIVE_TYPE_NONE }; 396 397 #ifdef CONFIG_FDC_ISA 398 /* floppy type */ 399 if (floppy) { 400 for (int i = 0; i < 2; i++) { 401 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 402 } 403 } 404 #endif 405 406 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 407 cmos_get_fd_drive_type(fd_type[1]); 408 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 409 410 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 411 nb = 0; 412 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 413 nb++; 414 } 415 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 416 nb++; 417 } 418 switch (nb) { 419 case 0: 420 break; 421 case 1: 422 val |= 0x01; /* 1 drive, ready for boot */ 423 break; 424 case 2: 425 val |= 0x41; /* 2 drives, ready for boot */ 426 break; 427 } 428 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 429 } 430 431 typedef struct check_fdc_state { 432 ISADevice *floppy; 433 bool multiple; 434 } CheckFdcState; 435 436 static int check_fdc(Object *obj, void *opaque) 437 { 438 CheckFdcState *state = opaque; 439 Object *fdc; 440 uint32_t iobase; 441 Error *local_err = NULL; 442 443 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 444 if (!fdc) { 445 return 0; 446 } 447 448 iobase = object_property_get_uint(obj, "iobase", &local_err); 449 if (local_err || iobase != 0x3f0) { 450 error_free(local_err); 451 return 0; 452 } 453 454 if (state->floppy) { 455 state->multiple = true; 456 } else { 457 state->floppy = ISA_DEVICE(obj); 458 } 459 return 0; 460 } 461 462 static const char * const fdc_container_path[] = { 463 "/unattached", "/peripheral", "/peripheral-anon" 464 }; 465 466 /* 467 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 468 * and ACPI objects. 469 */ 470 static ISADevice *pc_find_fdc0(void) 471 { 472 int i; 473 Object *container; 474 CheckFdcState state = { 0 }; 475 476 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 477 container = container_get(qdev_get_machine(), fdc_container_path[i]); 478 object_child_foreach(container, check_fdc, &state); 479 } 480 481 if (state.multiple) { 482 warn_report("multiple floppy disk controllers with " 483 "iobase=0x3f0 have been found"); 484 error_printf("the one being picked for CMOS setup might not reflect " 485 "your intent"); 486 } 487 488 return state.floppy; 489 } 490 491 static void pc_cmos_init_late(PCMachineState *pcms) 492 { 493 X86MachineState *x86ms = X86_MACHINE(pcms); 494 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 495 int16_t cylinders; 496 int8_t heads, sectors; 497 int val; 498 int i, trans; 499 500 val = 0; 501 if (pcms->idebus[0] && 502 ide_get_geometry(pcms->idebus[0], 0, 503 &cylinders, &heads, §ors) >= 0) { 504 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 505 val |= 0xf0; 506 } 507 if (pcms->idebus[0] && 508 ide_get_geometry(pcms->idebus[0], 1, 509 &cylinders, &heads, §ors) >= 0) { 510 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 511 val |= 0x0f; 512 } 513 mc146818rtc_set_cmos_data(s, 0x12, val); 514 515 val = 0; 516 for (i = 0; i < 4; i++) { 517 /* NOTE: ide_get_geometry() returns the physical 518 geometry. It is always such that: 1 <= sects <= 63, 1 519 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 520 geometry can be different if a translation is done. */ 521 BusState *idebus = pcms->idebus[i / 2]; 522 if (idebus && 523 ide_get_geometry(idebus, i % 2, 524 &cylinders, &heads, §ors) >= 0) { 525 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 526 assert((trans & ~3) == 0); 527 val |= trans << (i * 2); 528 } 529 } 530 mc146818rtc_set_cmos_data(s, 0x39, val); 531 532 pc_cmos_init_floppy(s, pc_find_fdc0()); 533 534 /* various important CMOS locations needed by PC/Bochs bios */ 535 536 /* memory size */ 537 /* base memory (first MiB) */ 538 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 539 mc146818rtc_set_cmos_data(s, 0x15, val); 540 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 541 /* extended memory (next 64MiB) */ 542 if (x86ms->below_4g_mem_size > 1 * MiB) { 543 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 544 } else { 545 val = 0; 546 } 547 if (val > 65535) 548 val = 65535; 549 mc146818rtc_set_cmos_data(s, 0x17, val); 550 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 551 mc146818rtc_set_cmos_data(s, 0x30, val); 552 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 553 /* memory between 16MiB and 4GiB */ 554 if (x86ms->below_4g_mem_size > 16 * MiB) { 555 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 556 } else { 557 val = 0; 558 } 559 if (val > 65535) 560 val = 65535; 561 mc146818rtc_set_cmos_data(s, 0x34, val); 562 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 563 /* memory above 4GiB */ 564 val = x86ms->above_4g_mem_size / 65536; 565 mc146818rtc_set_cmos_data(s, 0x5b, val); 566 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 567 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 568 569 val = 0; 570 val |= 0x02; /* FPU is there */ 571 val |= 0x04; /* PS/2 mouse installed */ 572 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 573 } 574 575 static void handle_a20_line_change(void *opaque, int irq, int level) 576 { 577 X86CPU *cpu = opaque; 578 579 /* XXX: send to all CPUs ? */ 580 /* XXX: add logic to handle multiple A20 line sources */ 581 x86_cpu_set_a20(cpu, level); 582 } 583 584 #define NE2000_NB_MAX 6 585 586 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 587 0x280, 0x380 }; 588 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 589 590 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 591 { 592 static int nb_ne2k = 0; 593 594 if (nb_ne2k == NE2000_NB_MAX) { 595 error_setg(errp, 596 "maximum number of ISA NE2000 devices exceeded"); 597 return false; 598 } 599 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 600 ne2000_irq[nb_ne2k], nd); 601 nb_ne2k++; 602 return true; 603 } 604 605 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 606 { 607 X86CPU *cpu = opaque; 608 609 if (level) { 610 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 611 } 612 } 613 614 static 615 void pc_machine_done(Notifier *notifier, void *data) 616 { 617 PCMachineState *pcms = container_of(notifier, 618 PCMachineState, machine_done); 619 X86MachineState *x86ms = X86_MACHINE(pcms); 620 621 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 622 &error_fatal); 623 624 if (pcms->cxl_devices_state.is_enabled) { 625 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 626 } 627 628 /* set the number of CPUs */ 629 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 630 631 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 632 633 acpi_setup(); 634 if (x86ms->fw_cfg) { 635 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 636 fw_cfg_add_e820(x86ms->fw_cfg); 637 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 638 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 639 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 640 } 641 642 pc_cmos_init_late(pcms); 643 } 644 645 /* setup pci memory address space mapping into system address space */ 646 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 647 MemoryRegion *pci_address_space) 648 { 649 /* Set to lower priority than RAM */ 650 memory_region_add_subregion_overlap(system_memory, 0x0, 651 pci_address_space, -1); 652 } 653 654 void xen_load_linux(PCMachineState *pcms) 655 { 656 int i; 657 FWCfgState *fw_cfg; 658 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 659 X86MachineState *x86ms = X86_MACHINE(pcms); 660 661 assert(MACHINE(pcms)->kernel_filename != NULL); 662 663 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 664 &address_space_memory); 665 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 666 rom_set_fw(fw_cfg); 667 668 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 669 for (i = 0; i < nb_option_roms; i++) { 670 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 671 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 672 !strcmp(option_rom[i].name, "pvh.bin") || 673 !strcmp(option_rom[i].name, "multiboot.bin") || 674 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 675 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 676 } 677 x86ms->fw_cfg = fw_cfg; 678 } 679 680 #define PC_ROM_MIN_VGA 0xc0000 681 #define PC_ROM_MIN_OPTION 0xc8000 682 #define PC_ROM_MAX 0xe0000 683 #define PC_ROM_ALIGN 0x800 684 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 685 686 static hwaddr pc_above_4g_end(PCMachineState *pcms) 687 { 688 X86MachineState *x86ms = X86_MACHINE(pcms); 689 690 if (pcms->sgx_epc.size != 0) { 691 return sgx_epc_above_4g_end(&pcms->sgx_epc); 692 } 693 694 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 695 } 696 697 static void pc_get_device_memory_range(PCMachineState *pcms, 698 hwaddr *base, 699 ram_addr_t *device_mem_size) 700 { 701 MachineState *machine = MACHINE(pcms); 702 ram_addr_t size; 703 hwaddr addr; 704 705 size = machine->maxram_size - machine->ram_size; 706 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 707 708 /* size device region assuming 1G page max alignment per slot */ 709 size += (1 * GiB) * machine->ram_slots; 710 711 *base = addr; 712 *device_mem_size = size; 713 } 714 715 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 716 { 717 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 718 MachineState *ms = MACHINE(pcms); 719 hwaddr cxl_base; 720 ram_addr_t size; 721 722 if (pcmc->has_reserved_memory && 723 (ms->ram_size < ms->maxram_size)) { 724 pc_get_device_memory_range(pcms, &cxl_base, &size); 725 cxl_base += size; 726 } else { 727 cxl_base = pc_above_4g_end(pcms); 728 } 729 730 return cxl_base; 731 } 732 733 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 734 { 735 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 736 737 if (pcms->cxl_devices_state.fixed_windows) { 738 GList *it; 739 740 start = ROUND_UP(start, 256 * MiB); 741 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 742 CXLFixedWindow *fw = it->data; 743 start += fw->size; 744 } 745 } 746 747 return start; 748 } 749 750 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 751 { 752 X86CPU *cpu = X86_CPU(first_cpu); 753 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 754 MachineState *ms = MACHINE(pcms); 755 756 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 757 /* 64-bit systems */ 758 return pc_pci_hole64_start() + pci_hole64_size - 1; 759 } 760 761 /* 32-bit systems */ 762 if (pcmc->broken_32bit_mem_addr_check) { 763 /* old value for compatibility reasons */ 764 return ((hwaddr)1 << cpu->phys_bits) - 1; 765 } 766 767 /* 768 * 32-bit systems don't have hole64 but they might have a region for 769 * memory devices. Even if additional hotplugged memory devices might 770 * not be usable by most guest OSes, we need to still consider them for 771 * calculating the highest possible GPA so that we can properly report 772 * if someone configures them on a CPU that cannot possibly address them. 773 */ 774 if (pcmc->has_reserved_memory && 775 (ms->ram_size < ms->maxram_size)) { 776 hwaddr devmem_start; 777 ram_addr_t devmem_size; 778 779 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 780 devmem_start += devmem_size; 781 return devmem_start - 1; 782 } 783 784 /* configuration without any memory hotplug */ 785 return pc_above_4g_end(pcms) - 1; 786 } 787 788 /* 789 * AMD systems with an IOMMU have an additional hole close to the 790 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 791 * on kernel version, VFIO may or may not let you DMA map those ranges. 792 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 793 * with certain memory sizes. It's also wrong to use those IOVA ranges 794 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 795 * The ranges reserved for Hyper-Transport are: 796 * 797 * FD_0000_0000h - FF_FFFF_FFFFh 798 * 799 * The ranges represent the following: 800 * 801 * Base Address Top Address Use 802 * 803 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 804 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 805 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 806 * FD_F910_0000h FD_F91F_FFFFh System Management 807 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 808 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 809 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 810 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 811 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 812 * FE_2000_0000h FF_FFFF_FFFFh Reserved 813 * 814 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 815 * Table 3: Special Address Controls (GPA) for more information. 816 */ 817 #define AMD_HT_START 0xfd00000000UL 818 #define AMD_HT_END 0xffffffffffUL 819 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 820 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 821 822 void pc_memory_init(PCMachineState *pcms, 823 MemoryRegion *system_memory, 824 MemoryRegion *rom_memory, 825 uint64_t pci_hole64_size) 826 { 827 int linux_boot, i; 828 MemoryRegion *option_rom_mr; 829 MemoryRegion *ram_below_4g, *ram_above_4g; 830 FWCfgState *fw_cfg; 831 MachineState *machine = MACHINE(pcms); 832 MachineClass *mc = MACHINE_GET_CLASS(machine); 833 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 834 X86MachineState *x86ms = X86_MACHINE(pcms); 835 hwaddr maxphysaddr, maxusedaddr; 836 hwaddr cxl_base, cxl_resv_end = 0; 837 X86CPU *cpu = X86_CPU(first_cpu); 838 839 assert(machine->ram_size == x86ms->below_4g_mem_size + 840 x86ms->above_4g_mem_size); 841 842 linux_boot = (machine->kernel_filename != NULL); 843 844 /* 845 * The HyperTransport range close to the 1T boundary is unique to AMD 846 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 847 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 848 * older machine types (<= 7.0) for compatibility purposes. 849 */ 850 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 851 /* Bail out if max possible address does not cross HT range */ 852 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 853 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 854 } 855 856 /* 857 * Advertise the HT region if address space covers the reserved 858 * region or if we relocate. 859 */ 860 if (cpu->phys_bits >= 40) { 861 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 862 } 863 } 864 865 /* 866 * phys-bits is required to be appropriately configured 867 * to make sure max used GPA is reachable. 868 */ 869 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 870 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 871 if (maxphysaddr < maxusedaddr) { 872 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 873 " phys-bits too low (%u)", 874 maxphysaddr, maxusedaddr, cpu->phys_bits); 875 exit(EXIT_FAILURE); 876 } 877 878 /* 879 * Split single memory region and use aliases to address portions of it, 880 * done for backwards compatibility with older qemus. 881 */ 882 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 883 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 884 0, x86ms->below_4g_mem_size); 885 memory_region_add_subregion(system_memory, 0, ram_below_4g); 886 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 887 if (x86ms->above_4g_mem_size > 0) { 888 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 889 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 890 machine->ram, 891 x86ms->below_4g_mem_size, 892 x86ms->above_4g_mem_size); 893 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 894 ram_above_4g); 895 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 896 E820_RAM); 897 } 898 899 if (pcms->sgx_epc.size != 0) { 900 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 901 } 902 903 if (!pcmc->has_reserved_memory && 904 (machine->ram_slots || 905 (machine->maxram_size > machine->ram_size))) { 906 907 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 908 mc->name); 909 exit(EXIT_FAILURE); 910 } 911 912 /* initialize device memory address space */ 913 if (pcmc->has_reserved_memory && 914 (machine->ram_size < machine->maxram_size)) { 915 ram_addr_t device_mem_size; 916 hwaddr device_mem_base; 917 918 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 919 error_report("unsupported amount of memory slots: %"PRIu64, 920 machine->ram_slots); 921 exit(EXIT_FAILURE); 922 } 923 924 if (QEMU_ALIGN_UP(machine->maxram_size, 925 TARGET_PAGE_SIZE) != machine->maxram_size) { 926 error_report("maximum memory size must by aligned to multiple of " 927 "%d bytes", TARGET_PAGE_SIZE); 928 exit(EXIT_FAILURE); 929 } 930 931 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 932 933 if (device_mem_base + device_mem_size < device_mem_size) { 934 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 935 machine->maxram_size); 936 exit(EXIT_FAILURE); 937 } 938 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 939 } 940 941 if (pcms->cxl_devices_state.is_enabled) { 942 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 943 hwaddr cxl_size = MiB; 944 945 cxl_base = pc_get_cxl_range_start(pcms); 946 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 947 memory_region_add_subregion(system_memory, cxl_base, mr); 948 cxl_resv_end = cxl_base + cxl_size; 949 if (pcms->cxl_devices_state.fixed_windows) { 950 hwaddr cxl_fmw_base; 951 GList *it; 952 953 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 954 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 955 CXLFixedWindow *fw = it->data; 956 957 fw->base = cxl_fmw_base; 958 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 959 "cxl-fixed-memory-region", fw->size); 960 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 961 cxl_fmw_base += fw->size; 962 cxl_resv_end = cxl_fmw_base; 963 } 964 } 965 } 966 967 /* Initialize PC system firmware */ 968 pc_system_firmware_init(pcms, rom_memory); 969 970 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 971 if (machine_require_guest_memfd(machine)) { 972 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 973 PC_ROM_SIZE, &error_fatal); 974 } else { 975 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 976 &error_fatal); 977 if (pcmc->pci_enabled) { 978 memory_region_set_readonly(option_rom_mr, true); 979 } 980 } 981 memory_region_add_subregion_overlap(rom_memory, 982 PC_ROM_MIN_VGA, 983 option_rom_mr, 984 1); 985 986 fw_cfg = fw_cfg_arch_create(machine, 987 x86ms->boot_cpus, x86ms->apic_id_limit); 988 989 rom_set_fw(fw_cfg); 990 991 if (machine->device_memory) { 992 uint64_t *val = g_malloc(sizeof(*val)); 993 uint64_t res_mem_end = machine->device_memory->base; 994 995 if (!pcmc->broken_reserved_end) { 996 res_mem_end += memory_region_size(&machine->device_memory->mr); 997 } 998 999 if (pcms->cxl_devices_state.is_enabled) { 1000 res_mem_end = cxl_resv_end; 1001 } 1002 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1003 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1004 } 1005 1006 if (linux_boot) { 1007 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1008 } 1009 1010 for (i = 0; i < nb_option_roms; i++) { 1011 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1012 } 1013 x86ms->fw_cfg = fw_cfg; 1014 1015 /* Init default IOAPIC address space */ 1016 x86ms->ioapic_as = &address_space_memory; 1017 1018 /* Init ACPI memory hotplug IO base address */ 1019 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1020 } 1021 1022 /* 1023 * The 64bit pci hole starts after "above 4G RAM" and 1024 * potentially the space reserved for memory hotplug. 1025 */ 1026 uint64_t pc_pci_hole64_start(void) 1027 { 1028 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1029 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1030 MachineState *ms = MACHINE(pcms); 1031 uint64_t hole64_start = 0; 1032 ram_addr_t size = 0; 1033 1034 if (pcms->cxl_devices_state.is_enabled) { 1035 hole64_start = pc_get_cxl_range_end(pcms); 1036 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1037 pc_get_device_memory_range(pcms, &hole64_start, &size); 1038 if (!pcmc->broken_reserved_end) { 1039 hole64_start += size; 1040 } 1041 } else { 1042 hole64_start = pc_above_4g_end(pcms); 1043 } 1044 1045 return ROUND_UP(hole64_start, 1 * GiB); 1046 } 1047 1048 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1049 { 1050 DeviceState *dev = NULL; 1051 1052 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1053 if (pci_bus) { 1054 PCIDevice *pcidev = pci_vga_init(pci_bus); 1055 dev = pcidev ? &pcidev->qdev : NULL; 1056 } else if (isa_bus) { 1057 ISADevice *isadev = isa_vga_init(isa_bus); 1058 dev = isadev ? DEVICE(isadev) : NULL; 1059 } 1060 rom_reset_order_override(); 1061 return dev; 1062 } 1063 1064 static const MemoryRegionOps ioport80_io_ops = { 1065 .write = ioport80_write, 1066 .read = ioport80_read, 1067 .endianness = DEVICE_NATIVE_ENDIAN, 1068 .impl = { 1069 .min_access_size = 1, 1070 .max_access_size = 1, 1071 }, 1072 }; 1073 1074 static const MemoryRegionOps ioportF0_io_ops = { 1075 .write = ioportF0_write, 1076 .read = ioportF0_read, 1077 .endianness = DEVICE_NATIVE_ENDIAN, 1078 .impl = { 1079 .min_access_size = 1, 1080 .max_access_size = 1, 1081 }, 1082 }; 1083 1084 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1085 bool create_i8042, bool no_vmport, Error **errp) 1086 { 1087 int i; 1088 DriveInfo *fd[MAX_FD]; 1089 qemu_irq *a20_line; 1090 ISADevice *i8042, *port92, *vmmouse; 1091 1092 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1093 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1094 1095 for (i = 0; i < MAX_FD; i++) { 1096 fd[i] = drive_get(IF_FLOPPY, 0, i); 1097 create_fdctrl |= !!fd[i]; 1098 } 1099 if (create_fdctrl) { 1100 #ifdef CONFIG_FDC_ISA 1101 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1102 if (fdc) { 1103 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1104 isa_fdc_init_drives(fdc, fd); 1105 } 1106 #endif 1107 } 1108 1109 if (!create_i8042) { 1110 if (!no_vmport) { 1111 error_setg(errp, 1112 "vmport requires the i8042 controller to be enabled"); 1113 } 1114 return; 1115 } 1116 1117 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1118 if (!no_vmport) { 1119 isa_create_simple(isa_bus, TYPE_VMPORT); 1120 vmmouse = isa_try_new("vmmouse"); 1121 } else { 1122 vmmouse = NULL; 1123 } 1124 if (vmmouse) { 1125 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1126 &error_abort); 1127 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1128 } 1129 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1130 1131 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1132 qdev_connect_gpio_out_named(DEVICE(i8042), 1133 I8042_A20_LINE, 0, a20_line[0]); 1134 qdev_connect_gpio_out_named(DEVICE(port92), 1135 PORT92_A20_LINE, 0, a20_line[1]); 1136 g_free(a20_line); 1137 } 1138 1139 void pc_basic_device_init(struct PCMachineState *pcms, 1140 ISABus *isa_bus, qemu_irq *gsi, 1141 ISADevice *rtc_state, 1142 bool create_fdctrl, 1143 uint32_t hpet_irqs) 1144 { 1145 int i; 1146 DeviceState *hpet = NULL; 1147 int pit_isa_irq = 0; 1148 qemu_irq pit_alt_irq = NULL; 1149 ISADevice *pit = NULL; 1150 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1151 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1152 X86MachineState *x86ms = X86_MACHINE(pcms); 1153 1154 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1155 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1156 1157 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1158 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1159 1160 /* 1161 * Check if an HPET shall be created. 1162 */ 1163 if (pcms->hpet_enabled) { 1164 qemu_irq rtc_irq; 1165 1166 hpet = qdev_try_new(TYPE_HPET); 1167 if (!hpet) { 1168 error_report("couldn't create HPET device"); 1169 exit(1); 1170 } 1171 /* 1172 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1173 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1174 * the property, use whatever mask they specified. 1175 */ 1176 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1177 HPET_INTCAP, NULL); 1178 if (!compat) { 1179 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1180 } 1181 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1182 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1183 1184 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1185 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1186 } 1187 pit_isa_irq = -1; 1188 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1189 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1190 1191 /* overwrite connection created by south bridge */ 1192 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1193 } 1194 1195 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1196 "date"); 1197 1198 #ifdef CONFIG_XEN_EMU 1199 if (xen_mode == XEN_EMULATE) { 1200 xen_overlay_create(); 1201 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1202 xen_gnttab_create(); 1203 xen_xenstore_create(); 1204 if (pcms->pcibus) { 1205 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1206 } 1207 xen_bus_init(); 1208 } 1209 #endif 1210 1211 qemu_register_boot_set(pc_boot_set, pcms); 1212 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1213 MACHINE(pcms)->boot_config.order, &error_fatal); 1214 1215 if (!xen_enabled() && 1216 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1217 if (kvm_pit_in_kernel()) { 1218 pit = kvm_pit_init(isa_bus, 0x40); 1219 } else { 1220 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1221 } 1222 if (hpet) { 1223 /* connect PIT to output control line of the HPET */ 1224 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1225 } 1226 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1227 OBJECT(pit), &error_fatal); 1228 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1229 } 1230 1231 assert(pcms->vmport >= 0 && pcms->vmport < ON_OFF_AUTO__MAX); 1232 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1233 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1234 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1235 } 1236 1237 /* Super I/O */ 1238 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1239 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1240 } 1241 1242 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1243 { 1244 MachineClass *mc = MACHINE_CLASS(pcmc); 1245 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1246 NICInfo *nd; 1247 1248 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1249 1250 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1251 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1252 } 1253 1254 /* Anything remaining should be a PCI NIC */ 1255 if (pci_bus) { 1256 pci_init_nic_devices(pci_bus, mc->default_nic); 1257 } 1258 1259 rom_reset_order_override(); 1260 } 1261 1262 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1263 { 1264 qemu_irq *i8259; 1265 1266 if (kvm_pic_in_kernel()) { 1267 i8259 = kvm_i8259_init(isa_bus); 1268 } else if (xen_enabled()) { 1269 i8259 = xen_interrupt_controller_init(); 1270 } else { 1271 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1272 } 1273 1274 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1275 i8259_irqs[i] = i8259[i]; 1276 } 1277 1278 g_free(i8259); 1279 } 1280 1281 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1282 Error **errp) 1283 { 1284 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1285 const MachineState *ms = MACHINE(hotplug_dev); 1286 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1287 Error *local_err = NULL; 1288 1289 /* 1290 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1291 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1292 * addition to cover this case. 1293 */ 1294 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1295 error_setg(errp, 1296 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1297 return; 1298 } 1299 1300 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1301 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1302 return; 1303 } 1304 1305 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1306 if (local_err) { 1307 error_propagate(errp, local_err); 1308 return; 1309 } 1310 1311 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1312 } 1313 1314 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1315 DeviceState *dev, Error **errp) 1316 { 1317 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1318 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1319 MachineState *ms = MACHINE(hotplug_dev); 1320 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1321 1322 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1323 1324 if (is_nvdimm) { 1325 nvdimm_plug(ms->nvdimms_state); 1326 } 1327 1328 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1329 } 1330 1331 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1332 DeviceState *dev, Error **errp) 1333 { 1334 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1335 1336 /* 1337 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1338 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1339 * addition to cover this case. 1340 */ 1341 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1342 error_setg(errp, 1343 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1344 return; 1345 } 1346 1347 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1348 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1349 return; 1350 } 1351 1352 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1353 errp); 1354 } 1355 1356 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1357 DeviceState *dev, Error **errp) 1358 { 1359 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1360 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1361 Error *local_err = NULL; 1362 1363 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1364 if (local_err) { 1365 goto out; 1366 } 1367 1368 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1369 qdev_unrealize(dev); 1370 out: 1371 error_propagate(errp, local_err); 1372 } 1373 1374 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1375 DeviceState *dev, Error **errp) 1376 { 1377 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1378 g_assert(!dev->hotplugged); 1379 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1380 } 1381 1382 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1383 DeviceState *dev, Error **errp) 1384 { 1385 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1386 } 1387 1388 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1389 DeviceState *dev, Error **errp) 1390 { 1391 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1392 pc_memory_pre_plug(hotplug_dev, dev, errp); 1393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1394 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1396 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1397 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1398 /* Declare the APIC range as the reserved MSI region */ 1399 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1400 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1401 QList *reserved_regions = qlist_new(); 1402 1403 qlist_append_str(reserved_regions, resv_prop_str); 1404 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1405 1406 g_free(resv_prop_str); 1407 } 1408 1409 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1410 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1411 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1412 1413 if (pcms->iommu) { 1414 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1415 "for x86 yet."); 1416 return; 1417 } 1418 pcms->iommu = dev; 1419 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1420 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1421 } 1422 } 1423 1424 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1425 DeviceState *dev, Error **errp) 1426 { 1427 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1428 pc_memory_plug(hotplug_dev, dev, errp); 1429 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1430 x86_cpu_plug(hotplug_dev, dev, errp); 1431 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1432 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1433 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1434 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1435 } 1436 } 1437 1438 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1439 DeviceState *dev, Error **errp) 1440 { 1441 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1442 pc_memory_unplug_request(hotplug_dev, dev, errp); 1443 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1444 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1445 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1446 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1447 errp); 1448 } else { 1449 error_setg(errp, "acpi: device unplug request for not supported device" 1450 " type: %s", object_get_typename(OBJECT(dev))); 1451 } 1452 } 1453 1454 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1455 DeviceState *dev, Error **errp) 1456 { 1457 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1458 pc_memory_unplug(hotplug_dev, dev, errp); 1459 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1460 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1461 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1462 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1463 } else { 1464 error_setg(errp, "acpi: device unplug for not supported device" 1465 " type: %s", object_get_typename(OBJECT(dev))); 1466 } 1467 } 1468 1469 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1470 DeviceState *dev) 1471 { 1472 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1473 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1474 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1475 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1476 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1477 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1478 return HOTPLUG_HANDLER(machine); 1479 } 1480 1481 return NULL; 1482 } 1483 1484 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1485 void *opaque, Error **errp) 1486 { 1487 PCMachineState *pcms = PC_MACHINE(obj); 1488 OnOffAuto vmport = pcms->vmport; 1489 1490 visit_type_OnOffAuto(v, name, &vmport, errp); 1491 } 1492 1493 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1494 void *opaque, Error **errp) 1495 { 1496 PCMachineState *pcms = PC_MACHINE(obj); 1497 1498 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1499 } 1500 1501 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1502 { 1503 PCMachineState *pcms = PC_MACHINE(obj); 1504 1505 return pcms->fd_bootchk; 1506 } 1507 1508 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1509 { 1510 PCMachineState *pcms = PC_MACHINE(obj); 1511 1512 pcms->fd_bootchk = value; 1513 } 1514 1515 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 return pcms->smbus_enabled; 1520 } 1521 1522 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 1526 pcms->smbus_enabled = value; 1527 } 1528 1529 static bool pc_machine_get_sata(Object *obj, Error **errp) 1530 { 1531 PCMachineState *pcms = PC_MACHINE(obj); 1532 1533 return pcms->sata_enabled; 1534 } 1535 1536 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 1540 pcms->sata_enabled = value; 1541 } 1542 1543 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1544 { 1545 PCMachineState *pcms = PC_MACHINE(obj); 1546 1547 return pcms->hpet_enabled; 1548 } 1549 1550 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1551 { 1552 PCMachineState *pcms = PC_MACHINE(obj); 1553 1554 pcms->hpet_enabled = value; 1555 } 1556 1557 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1558 { 1559 PCMachineState *pcms = PC_MACHINE(obj); 1560 1561 return pcms->i8042_enabled; 1562 } 1563 1564 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1565 { 1566 PCMachineState *pcms = PC_MACHINE(obj); 1567 1568 pcms->i8042_enabled = value; 1569 } 1570 1571 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1572 { 1573 PCMachineState *pcms = PC_MACHINE(obj); 1574 1575 return pcms->default_bus_bypass_iommu; 1576 } 1577 1578 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1579 Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 1583 pcms->default_bus_bypass_iommu = value; 1584 } 1585 1586 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1587 void *opaque, Error **errp) 1588 { 1589 PCMachineState *pcms = PC_MACHINE(obj); 1590 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1591 1592 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1593 } 1594 1595 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1596 void *opaque, Error **errp) 1597 { 1598 PCMachineState *pcms = PC_MACHINE(obj); 1599 1600 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1601 } 1602 1603 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1604 const char *name, void *opaque, 1605 Error **errp) 1606 { 1607 PCMachineState *pcms = PC_MACHINE(obj); 1608 uint64_t value = pcms->max_ram_below_4g; 1609 1610 visit_type_size(v, name, &value, errp); 1611 } 1612 1613 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1614 const char *name, void *opaque, 1615 Error **errp) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 uint64_t value; 1619 1620 if (!visit_type_size(v, name, &value, errp)) { 1621 return; 1622 } 1623 if (value > 4 * GiB) { 1624 error_setg(errp, 1625 "Machine option 'max-ram-below-4g=%"PRIu64 1626 "' expects size less than or equal to 4G", value); 1627 return; 1628 } 1629 1630 if (value < 1 * MiB) { 1631 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1632 "BIOS may not work with less than 1MiB", value); 1633 } 1634 1635 pcms->max_ram_below_4g = value; 1636 } 1637 1638 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1639 const char *name, void *opaque, 1640 Error **errp) 1641 { 1642 PCMachineState *pcms = PC_MACHINE(obj); 1643 uint64_t value = pcms->max_fw_size; 1644 1645 visit_type_size(v, name, &value, errp); 1646 } 1647 1648 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1649 const char *name, void *opaque, 1650 Error **errp) 1651 { 1652 PCMachineState *pcms = PC_MACHINE(obj); 1653 uint64_t value; 1654 1655 if (!visit_type_size(v, name, &value, errp)) { 1656 return; 1657 } 1658 1659 /* 1660 * We don't have a theoretically justifiable exact lower bound on the base 1661 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1662 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1663 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1664 * 16MiB in size. 1665 */ 1666 if (value > 16 * MiB) { 1667 error_setg(errp, 1668 "User specified max allowed firmware size %" PRIu64 " is " 1669 "greater than 16MiB. If combined firmware size exceeds " 1670 "16MiB the system may not boot, or experience intermittent" 1671 "stability issues.", 1672 value); 1673 return; 1674 } 1675 1676 pcms->max_fw_size = value; 1677 } 1678 1679 1680 static void pc_machine_initfn(Object *obj) 1681 { 1682 PCMachineState *pcms = PC_MACHINE(obj); 1683 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1684 1685 #ifdef CONFIG_VMPORT 1686 pcms->vmport = ON_OFF_AUTO_AUTO; 1687 #else 1688 pcms->vmport = ON_OFF_AUTO_OFF; 1689 #endif /* CONFIG_VMPORT */ 1690 pcms->max_ram_below_4g = 0; /* use default */ 1691 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1692 pcms->south_bridge = pcmc->default_south_bridge; 1693 1694 /* acpi build is enabled by default if machine supports it */ 1695 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1696 pcms->smbus_enabled = true; 1697 pcms->sata_enabled = true; 1698 pcms->i8042_enabled = true; 1699 pcms->max_fw_size = 8 * MiB; 1700 #ifdef CONFIG_HPET 1701 pcms->hpet_enabled = true; 1702 #endif 1703 pcms->fd_bootchk = true; 1704 pcms->default_bus_bypass_iommu = false; 1705 1706 pc_system_flash_create(pcms); 1707 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1708 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1709 OBJECT(pcms->pcspk), "audiodev"); 1710 if (pcmc->pci_enabled) { 1711 cxl_machine_init(obj, &pcms->cxl_devices_state); 1712 } 1713 1714 pcms->machine_done.notify = pc_machine_done; 1715 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1716 } 1717 1718 static void pc_machine_reset(MachineState *machine, ResetType type) 1719 { 1720 CPUState *cs; 1721 X86CPU *cpu; 1722 1723 qemu_devices_reset(type); 1724 1725 /* Reset APIC after devices have been reset to cancel 1726 * any changes that qemu_devices_reset() might have done. 1727 */ 1728 CPU_FOREACH(cs) { 1729 cpu = X86_CPU(cs); 1730 1731 x86_cpu_after_reset(cpu); 1732 } 1733 } 1734 1735 static void pc_machine_wakeup(MachineState *machine) 1736 { 1737 cpu_synchronize_all_states(); 1738 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1739 cpu_synchronize_all_post_reset(); 1740 } 1741 1742 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1743 { 1744 X86IOMMUState *iommu = x86_iommu_get_default(); 1745 IntelIOMMUState *intel_iommu; 1746 1747 if (iommu && 1748 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1749 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1750 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1751 if (!intel_iommu->caching_mode) { 1752 error_setg(errp, "Device assignment is not allowed without " 1753 "enabling caching-mode=on for Intel IOMMU."); 1754 return false; 1755 } 1756 } 1757 1758 return true; 1759 } 1760 1761 static void pc_machine_class_init(ObjectClass *oc, void *data) 1762 { 1763 MachineClass *mc = MACHINE_CLASS(oc); 1764 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1765 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1766 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1767 1768 pcmc->pci_enabled = true; 1769 pcmc->has_acpi_build = true; 1770 pcmc->smbios_defaults = true; 1771 pcmc->gigabyte_align = true; 1772 pcmc->has_reserved_memory = true; 1773 pcmc->enforce_amd_1tb_hole = true; 1774 pcmc->isa_bios_alias = true; 1775 pcmc->pvh_enabled = true; 1776 pcmc->kvmclock_create_always = true; 1777 x86mc->apic_xrupt_override = true; 1778 assert(!mc->get_hotplug_handler); 1779 mc->get_hotplug_handler = pc_get_hotplug_handler; 1780 mc->hotplug_allowed = pc_hotplug_allowed; 1781 mc->auto_enable_numa_with_memhp = true; 1782 mc->auto_enable_numa_with_memdev = true; 1783 mc->has_hotpluggable_cpus = true; 1784 mc->default_boot_order = "cad"; 1785 mc->block_default_type = IF_IDE; 1786 mc->max_cpus = 255; 1787 mc->reset = pc_machine_reset; 1788 mc->wakeup = pc_machine_wakeup; 1789 hc->pre_plug = pc_machine_device_pre_plug_cb; 1790 hc->plug = pc_machine_device_plug_cb; 1791 hc->unplug_request = pc_machine_device_unplug_request_cb; 1792 hc->unplug = pc_machine_device_unplug_cb; 1793 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1794 mc->nvdimm_supported = true; 1795 mc->smp_props.dies_supported = true; 1796 mc->smp_props.modules_supported = true; 1797 mc->default_ram_id = "pc.ram"; 1798 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1799 1800 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1801 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1802 NULL, NULL); 1803 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1804 "Maximum ram below the 4G boundary (32bit boundary)"); 1805 1806 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1807 pc_machine_get_vmport, pc_machine_set_vmport, 1808 NULL, NULL); 1809 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1810 "Enable vmport (pc & q35)"); 1811 1812 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1813 pc_machine_get_smbus, pc_machine_set_smbus); 1814 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1815 "Enable/disable system management bus"); 1816 1817 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1818 pc_machine_get_sata, pc_machine_set_sata); 1819 object_class_property_set_description(oc, PC_MACHINE_SATA, 1820 "Enable/disable Serial ATA bus"); 1821 1822 object_class_property_add_bool(oc, "hpet", 1823 pc_machine_get_hpet, pc_machine_set_hpet); 1824 object_class_property_set_description(oc, "hpet", 1825 "Enable/disable high precision event timer emulation"); 1826 1827 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1828 pc_machine_get_i8042, pc_machine_set_i8042); 1829 object_class_property_set_description(oc, PC_MACHINE_I8042, 1830 "Enable/disable Intel 8042 PS/2 controller emulation"); 1831 1832 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1833 pc_machine_get_default_bus_bypass_iommu, 1834 pc_machine_set_default_bus_bypass_iommu); 1835 1836 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1837 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1838 NULL, NULL); 1839 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1840 "Maximum combined firmware size"); 1841 1842 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1843 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1844 NULL, NULL); 1845 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1846 "SMBIOS Entry Point type [32, 64]"); 1847 1848 object_class_property_add_bool(oc, "fd-bootchk", 1849 pc_machine_get_fd_bootchk, 1850 pc_machine_set_fd_bootchk); 1851 } 1852 1853 static const TypeInfo pc_machine_info = { 1854 .name = TYPE_PC_MACHINE, 1855 .parent = TYPE_X86_MACHINE, 1856 .abstract = true, 1857 .instance_size = sizeof(PCMachineState), 1858 .instance_init = pc_machine_initfn, 1859 .class_size = sizeof(PCMachineClass), 1860 .class_init = pc_machine_class_init, 1861 .interfaces = (InterfaceInfo[]) { 1862 { TYPE_HOTPLUG_HANDLER }, 1863 { } 1864 }, 1865 }; 1866 1867 static void pc_machine_register_types(void) 1868 { 1869 type_register_static(&pc_machine_info); 1870 } 1871 1872 type_init(pc_machine_register_types) 1873