xref: /openbmc/qemu/hw/i386/pc.c (revision ee48fef0)
1 /*
2  * QEMU PC System Emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/char/parallel.h"
30 #include "hw/hyperv/hv-balloon.h"
31 #include "hw/i386/fw_cfg.h"
32 #include "hw/i386/vmport.h"
33 #include "sysemu/cpus.h"
34 #include "hw/ide/ide-bus.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/loader.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/input/i8042.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/xen.h"
44 #include "sysemu/reset.h"
45 #include "kvm/kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "qapi/qmp/qlist.h"
48 #include "qemu/error-report.h"
49 #include "hw/acpi/cpu_hotplug.h"
50 #include "acpi-build.h"
51 #include "hw/mem/nvdimm.h"
52 #include "hw/cxl/cxl_host.h"
53 #include "hw/usb.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/net/ne2000-isa.h"
56 #include "hw/virtio/virtio-iommu.h"
57 #include "hw/virtio/virtio-md-pci.h"
58 #include "hw/i386/kvm/xen_overlay.h"
59 #include "hw/i386/kvm/xen_evtchn.h"
60 #include "hw/i386/kvm/xen_gnttab.h"
61 #include "hw/i386/kvm/xen_xenstore.h"
62 #include "hw/mem/memory-device.h"
63 #include "e820_memory_layout.h"
64 #include "trace.h"
65 #include "sev.h"
66 #include CONFIG_DEVICES
67 
68 #ifdef CONFIG_XEN_EMU
69 #include "hw/xen/xen-legacy-backend.h"
70 #include "hw/xen/xen-bus.h"
71 #endif
72 
73 /*
74  * Helper for setting model-id for CPU models that changed model-id
75  * depending on QEMU versions up to QEMU 2.4.
76  */
77 #define PC_CPU_MODEL_IDS(v) \
78     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
79     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
80     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
81 
82 GlobalProperty pc_compat_9_0[] = {
83     { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" },
84     { TYPE_X86_CPU, "guest-phys-bits", "0" },
85     { "sev-guest", "legacy-vm-type", "true" },
86     { TYPE_X86_CPU, "legacy-multi-node", "on" },
87 };
88 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
89 
90 GlobalProperty pc_compat_8_2[] = {};
91 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2);
92 
93 GlobalProperty pc_compat_8_1[] = {};
94 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
95 
96 GlobalProperty pc_compat_8_0[] = {
97     { "virtio-mem", "unplugged-inaccessible", "auto" },
98 };
99 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
100 
101 GlobalProperty pc_compat_7_2[] = {
102     { "ICH9-LPC", "noreboot", "true" },
103 };
104 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
105 
106 GlobalProperty pc_compat_7_1[] = {};
107 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
108 
109 GlobalProperty pc_compat_7_0[] = {};
110 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
111 
112 GlobalProperty pc_compat_6_2[] = {
113     { "virtio-mem", "unplugged-inaccessible", "off" },
114 };
115 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
116 
117 GlobalProperty pc_compat_6_1[] = {
118     { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
119     { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
120     { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
121     { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
122 };
123 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
124 
125 GlobalProperty pc_compat_6_0[] = {
126     { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
127     { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
128     { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
129     { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
130     { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
131     { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
132 };
133 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
134 
135 GlobalProperty pc_compat_5_2[] = {
136     { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
137 };
138 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
139 
140 GlobalProperty pc_compat_5_1[] = {
141     { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
142     { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
143 };
144 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
145 
146 GlobalProperty pc_compat_5_0[] = {
147 };
148 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
149 
150 GlobalProperty pc_compat_4_2[] = {
151     { "mch", "smbase-smram", "off" },
152 };
153 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
154 
155 GlobalProperty pc_compat_4_1[] = {};
156 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
157 
158 GlobalProperty pc_compat_4_0[] = {};
159 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
160 
161 GlobalProperty pc_compat_3_1[] = {
162     { "intel-iommu", "dma-drain", "off" },
163     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
164     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
165     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
166     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
167     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
168     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
169     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
170     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
171     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
172     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
173     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
174     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
175     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
176     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
177     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
178     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
179     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
180     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
181     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
182     { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
183 };
184 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
185 
186 GlobalProperty pc_compat_3_0[] = {
187     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
188     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
189     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
190 };
191 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
192 
193 GlobalProperty pc_compat_2_12[] = {
194     { TYPE_X86_CPU, "legacy-cache", "on" },
195     { TYPE_X86_CPU, "topoext", "off" },
196     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
197     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
198 };
199 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
200 
201 GlobalProperty pc_compat_2_11[] = {
202     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
203     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
204 };
205 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
206 
207 GlobalProperty pc_compat_2_10[] = {
208     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
209     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
210     { "q35-pcihost", "x-pci-hole64-fix", "off" },
211 };
212 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
213 
214 GlobalProperty pc_compat_2_9[] = {
215     { "mch", "extended-tseg-mbytes", "0" },
216 };
217 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
218 
219 GlobalProperty pc_compat_2_8[] = {
220     { TYPE_X86_CPU, "tcg-cpuid", "off" },
221     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
222     { "ICH9-LPC", "x-smi-broadcast", "off" },
223     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
224     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
225 };
226 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
227 
228 GlobalProperty pc_compat_2_7[] = {
229     { TYPE_X86_CPU, "l3-cache", "off" },
230     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
231     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
232     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
233     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
234     { "isa-pcspk", "migrate", "off" },
235 };
236 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
237 
238 GlobalProperty pc_compat_2_6[] = {
239     { TYPE_X86_CPU, "cpuid-0xb", "off" },
240     { "vmxnet3", "romfile", "" },
241     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
242     { "apic-common", "legacy-instance-id", "on", }
243 };
244 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
245 
246 GlobalProperty pc_compat_2_5[] = {};
247 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
248 
249 GlobalProperty pc_compat_2_4[] = {
250     PC_CPU_MODEL_IDS("2.4.0")
251     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
252     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
253     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
254     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
255     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
256     { TYPE_X86_CPU, "check", "off" },
257     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
258     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
259     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
260     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
261     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
262     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
263     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
264     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
265 };
266 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
267 
268 GlobalProperty pc_compat_2_3[] = {
269     PC_CPU_MODEL_IDS("2.3.0")
270     { TYPE_X86_CPU, "arat", "off" },
271     { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
272     { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
273     { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
274     { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
275     { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
276     { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
277     { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
278     { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
279     { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
280     { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
281     { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
282     { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
283     { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
284     { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
285     { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
286     { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
287     { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288     { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289     { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
290 };
291 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
292 
293 GlobalProperty pc_compat_2_2[] = {
294     PC_CPU_MODEL_IDS("2.2.0")
295     { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
296     { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
297     { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
298     { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
299     { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
300     { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
301     { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
302     { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
303     { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
304     { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
305     { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
306     { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
307     { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
308     { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
309     { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
310     { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
311     { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
312     { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
313 };
314 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
315 
316 GlobalProperty pc_compat_2_1[] = {
317     PC_CPU_MODEL_IDS("2.1.0")
318     { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
319     { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
320 };
321 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
322 
323 GlobalProperty pc_compat_2_0[] = {
324     PC_CPU_MODEL_IDS("2.0.0")
325     { "virtio-scsi-pci", "any_layout", "off" },
326     { "PIIX4_PM", "memory-hotplug-support", "off" },
327     { "apic", "version", "0x11" },
328     { "nec-usb-xhci", "superspeed-ports-first", "off" },
329     { "nec-usb-xhci", "force-pcie-endcap", "on" },
330     { "pci-serial", "prog_if", "0" },
331     { "pci-serial-2x", "prog_if", "0" },
332     { "pci-serial-4x", "prog_if", "0" },
333     { "virtio-net-pci", "guest_announce", "off" },
334     { "ICH9-LPC", "memory-hotplug-support", "off" },
335 };
336 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
337 
338 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
339 {
340     GSIState *s;
341 
342     s = g_new0(GSIState, 1);
343     if (kvm_ioapic_in_kernel()) {
344         kvm_pc_setup_irq_routing(pci_enabled);
345     }
346     *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
347 
348     return s;
349 }
350 
351 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
352                            unsigned size)
353 {
354 }
355 
356 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
357 {
358     return 0xffffffffffffffffULL;
359 }
360 
361 /* MS-DOS compatibility mode FPU exception support */
362 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
363                            unsigned size)
364 {
365     if (tcg_enabled()) {
366         cpu_set_ignne();
367     }
368 }
369 
370 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
371 {
372     return 0xffffffffffffffffULL;
373 }
374 
375 /* PC cmos mappings */
376 
377 #define REG_EQUIPMENT_BYTE          0x14
378 
379 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
380                          int16_t cylinders, int8_t heads, int8_t sectors)
381 {
382     mc146818rtc_set_cmos_data(s, type_ofs, 47);
383     mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
384     mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
385     mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
386     mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
387     mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
388     mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
389     mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
390     mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
391     mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
392 }
393 
394 /* convert boot_device letter to something recognizable by the bios */
395 static int boot_device2nibble(char boot_device)
396 {
397     switch(boot_device) {
398     case 'a':
399     case 'b':
400         return 0x01; /* floppy boot */
401     case 'c':
402         return 0x02; /* hard drive boot */
403     case 'd':
404         return 0x03; /* CD-ROM boot */
405     case 'n':
406         return 0x04; /* Network boot */
407     }
408     return 0;
409 }
410 
411 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s,
412                          const char *boot_device, Error **errp)
413 {
414 #define PC_MAX_BOOT_DEVICES 3
415     int nbds, bds[3] = { 0, };
416     int i;
417 
418     nbds = strlen(boot_device);
419     if (nbds > PC_MAX_BOOT_DEVICES) {
420         error_setg(errp, "Too many boot devices for PC");
421         return;
422     }
423     for (i = 0; i < nbds; i++) {
424         bds[i] = boot_device2nibble(boot_device[i]);
425         if (bds[i] == 0) {
426             error_setg(errp, "Invalid boot device for PC: '%c'",
427                        boot_device[i]);
428             return;
429         }
430     }
431     mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
432     mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk);
433 }
434 
435 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
436 {
437     PCMachineState *pcms = opaque;
438     X86MachineState *x86ms = X86_MACHINE(pcms);
439 
440     set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp);
441 }
442 
443 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
444 {
445     int val, nb;
446     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
447                                    FLOPPY_DRIVE_TYPE_NONE };
448 
449 #ifdef CONFIG_FDC_ISA
450     /* floppy type */
451     if (floppy) {
452         for (int i = 0; i < 2; i++) {
453             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
454         }
455     }
456 #endif
457 
458     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
459         cmos_get_fd_drive_type(fd_type[1]);
460     mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
461 
462     val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
463     nb = 0;
464     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
465         nb++;
466     }
467     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
468         nb++;
469     }
470     switch (nb) {
471     case 0:
472         break;
473     case 1:
474         val |= 0x01; /* 1 drive, ready for boot */
475         break;
476     case 2:
477         val |= 0x41; /* 2 drives, ready for boot */
478         break;
479     }
480     mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
481 }
482 
483 typedef struct check_fdc_state {
484     ISADevice *floppy;
485     bool multiple;
486 } CheckFdcState;
487 
488 static int check_fdc(Object *obj, void *opaque)
489 {
490     CheckFdcState *state = opaque;
491     Object *fdc;
492     uint32_t iobase;
493     Error *local_err = NULL;
494 
495     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
496     if (!fdc) {
497         return 0;
498     }
499 
500     iobase = object_property_get_uint(obj, "iobase", &local_err);
501     if (local_err || iobase != 0x3f0) {
502         error_free(local_err);
503         return 0;
504     }
505 
506     if (state->floppy) {
507         state->multiple = true;
508     } else {
509         state->floppy = ISA_DEVICE(obj);
510     }
511     return 0;
512 }
513 
514 static const char * const fdc_container_path[] = {
515     "/unattached", "/peripheral", "/peripheral-anon"
516 };
517 
518 /*
519  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
520  * and ACPI objects.
521  */
522 static ISADevice *pc_find_fdc0(void)
523 {
524     int i;
525     Object *container;
526     CheckFdcState state = { 0 };
527 
528     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
529         container = container_get(qdev_get_machine(), fdc_container_path[i]);
530         object_child_foreach(container, check_fdc, &state);
531     }
532 
533     if (state.multiple) {
534         warn_report("multiple floppy disk controllers with "
535                     "iobase=0x3f0 have been found");
536         error_printf("the one being picked for CMOS setup might not reflect "
537                      "your intent");
538     }
539 
540     return state.floppy;
541 }
542 
543 static void pc_cmos_init_late(PCMachineState *pcms)
544 {
545     X86MachineState *x86ms = X86_MACHINE(pcms);
546     MC146818RtcState *s = MC146818_RTC(x86ms->rtc);
547     int16_t cylinders;
548     int8_t heads, sectors;
549     int val;
550     int i, trans;
551 
552     val = 0;
553     if (pcms->idebus[0] &&
554         ide_get_geometry(pcms->idebus[0], 0,
555                          &cylinders, &heads, &sectors) >= 0) {
556         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
557         val |= 0xf0;
558     }
559     if (pcms->idebus[0] &&
560         ide_get_geometry(pcms->idebus[0], 1,
561                          &cylinders, &heads, &sectors) >= 0) {
562         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
563         val |= 0x0f;
564     }
565     mc146818rtc_set_cmos_data(s, 0x12, val);
566 
567     val = 0;
568     for (i = 0; i < 4; i++) {
569         /* NOTE: ide_get_geometry() returns the physical
570            geometry.  It is always such that: 1 <= sects <= 63, 1
571            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
572            geometry can be different if a translation is done. */
573         BusState *idebus = pcms->idebus[i / 2];
574         if (idebus &&
575             ide_get_geometry(idebus, i % 2,
576                              &cylinders, &heads, &sectors) >= 0) {
577             trans = ide_get_bios_chs_trans(idebus, i % 2) - 1;
578             assert((trans & ~3) == 0);
579             val |= trans << (i * 2);
580         }
581     }
582     mc146818rtc_set_cmos_data(s, 0x39, val);
583 
584     pc_cmos_init_floppy(s, pc_find_fdc0());
585 
586     /* various important CMOS locations needed by PC/Bochs bios */
587 
588     /* memory size */
589     /* base memory (first MiB) */
590     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
591     mc146818rtc_set_cmos_data(s, 0x15, val);
592     mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
593     /* extended memory (next 64MiB) */
594     if (x86ms->below_4g_mem_size > 1 * MiB) {
595         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
596     } else {
597         val = 0;
598     }
599     if (val > 65535)
600         val = 65535;
601     mc146818rtc_set_cmos_data(s, 0x17, val);
602     mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
603     mc146818rtc_set_cmos_data(s, 0x30, val);
604     mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
605     /* memory between 16MiB and 4GiB */
606     if (x86ms->below_4g_mem_size > 16 * MiB) {
607         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
608     } else {
609         val = 0;
610     }
611     if (val > 65535)
612         val = 65535;
613     mc146818rtc_set_cmos_data(s, 0x34, val);
614     mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
615     /* memory above 4GiB */
616     val = x86ms->above_4g_mem_size / 65536;
617     mc146818rtc_set_cmos_data(s, 0x5b, val);
618     mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
619     mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
620 
621     val = 0;
622     val |= 0x02; /* FPU is there */
623     val |= 0x04; /* PS/2 mouse installed */
624     mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
625 }
626 
627 static void handle_a20_line_change(void *opaque, int irq, int level)
628 {
629     X86CPU *cpu = opaque;
630 
631     /* XXX: send to all CPUs ? */
632     /* XXX: add logic to handle multiple A20 line sources */
633     x86_cpu_set_a20(cpu, level);
634 }
635 
636 #define NE2000_NB_MAX 6
637 
638 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
639                                               0x280, 0x380 };
640 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
641 
642 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
643 {
644     static int nb_ne2k = 0;
645 
646     if (nb_ne2k == NE2000_NB_MAX) {
647         error_setg(errp,
648                    "maximum number of ISA NE2000 devices exceeded");
649         return false;
650     }
651     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
652                     ne2000_irq[nb_ne2k], nd);
653     nb_ne2k++;
654     return true;
655 }
656 
657 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
658 {
659     X86CPU *cpu = opaque;
660 
661     if (level) {
662         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
663     }
664 }
665 
666 static
667 void pc_machine_done(Notifier *notifier, void *data)
668 {
669     PCMachineState *pcms = container_of(notifier,
670                                         PCMachineState, machine_done);
671     X86MachineState *x86ms = X86_MACHINE(pcms);
672 
673     cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
674                               &error_fatal);
675 
676     if (pcms->cxl_devices_state.is_enabled) {
677         cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
678     }
679 
680     /* set the number of CPUs */
681     x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
682 
683     fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg);
684 
685     acpi_setup();
686     if (x86ms->fw_cfg) {
687         fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type);
688         fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
689         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
690         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
691     }
692 
693     pc_cmos_init_late(pcms);
694 }
695 
696 /* setup pci memory address space mapping into system address space */
697 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
698                             MemoryRegion *pci_address_space)
699 {
700     /* Set to lower priority than RAM */
701     memory_region_add_subregion_overlap(system_memory, 0x0,
702                                         pci_address_space, -1);
703 }
704 
705 void xen_load_linux(PCMachineState *pcms)
706 {
707     int i;
708     FWCfgState *fw_cfg;
709     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
710     X86MachineState *x86ms = X86_MACHINE(pcms);
711 
712     assert(MACHINE(pcms)->kernel_filename != NULL);
713 
714     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
715                                 &address_space_memory);
716     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
717     rom_set_fw(fw_cfg);
718 
719     x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
720                    pcmc->pvh_enabled);
721     for (i = 0; i < nb_option_roms; i++) {
722         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
723                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
724                !strcmp(option_rom[i].name, "pvh.bin") ||
725                !strcmp(option_rom[i].name, "multiboot.bin") ||
726                !strcmp(option_rom[i].name, "multiboot_dma.bin"));
727         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
728     }
729     x86ms->fw_cfg = fw_cfg;
730 }
731 
732 #define PC_ROM_MIN_VGA     0xc0000
733 #define PC_ROM_MIN_OPTION  0xc8000
734 #define PC_ROM_MAX         0xe0000
735 #define PC_ROM_ALIGN       0x800
736 #define PC_ROM_SIZE        (PC_ROM_MAX - PC_ROM_MIN_VGA)
737 
738 static hwaddr pc_above_4g_end(PCMachineState *pcms)
739 {
740     X86MachineState *x86ms = X86_MACHINE(pcms);
741 
742     if (pcms->sgx_epc.size != 0) {
743         return sgx_epc_above_4g_end(&pcms->sgx_epc);
744     }
745 
746     return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
747 }
748 
749 static void pc_get_device_memory_range(PCMachineState *pcms,
750                                        hwaddr *base,
751                                        ram_addr_t *device_mem_size)
752 {
753     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
754     MachineState *machine = MACHINE(pcms);
755     ram_addr_t size;
756     hwaddr addr;
757 
758     size = machine->maxram_size - machine->ram_size;
759     addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
760 
761     if (pcmc->enforce_aligned_dimm) {
762         /* size device region assuming 1G page max alignment per slot */
763         size += (1 * GiB) * machine->ram_slots;
764     }
765 
766     *base = addr;
767     *device_mem_size = size;
768 }
769 
770 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
771 {
772     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
773     MachineState *ms = MACHINE(pcms);
774     hwaddr cxl_base;
775     ram_addr_t size;
776 
777     if (pcmc->has_reserved_memory &&
778         (ms->ram_size < ms->maxram_size)) {
779         pc_get_device_memory_range(pcms, &cxl_base, &size);
780         cxl_base += size;
781     } else {
782         cxl_base = pc_above_4g_end(pcms);
783     }
784 
785     return cxl_base;
786 }
787 
788 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
789 {
790     uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
791 
792     if (pcms->cxl_devices_state.fixed_windows) {
793         GList *it;
794 
795         start = ROUND_UP(start, 256 * MiB);
796         for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
797             CXLFixedWindow *fw = it->data;
798             start += fw->size;
799         }
800     }
801 
802     return start;
803 }
804 
805 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
806 {
807     X86CPU *cpu = X86_CPU(first_cpu);
808     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
809     MachineState *ms = MACHINE(pcms);
810 
811     if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
812         /* 64-bit systems */
813         return pc_pci_hole64_start() + pci_hole64_size - 1;
814     }
815 
816     /* 32-bit systems */
817     if (pcmc->broken_32bit_mem_addr_check) {
818         /* old value for compatibility reasons */
819         return ((hwaddr)1 << cpu->phys_bits) - 1;
820     }
821 
822     /*
823      * 32-bit systems don't have hole64 but they might have a region for
824      * memory devices. Even if additional hotplugged memory devices might
825      * not be usable by most guest OSes, we need to still consider them for
826      * calculating the highest possible GPA so that we can properly report
827      * if someone configures them on a CPU that cannot possibly address them.
828      */
829     if (pcmc->has_reserved_memory &&
830         (ms->ram_size < ms->maxram_size)) {
831         hwaddr devmem_start;
832         ram_addr_t devmem_size;
833 
834         pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
835         devmem_start += devmem_size;
836         return devmem_start - 1;
837     }
838 
839     /* configuration without any memory hotplug */
840     return pc_above_4g_end(pcms) - 1;
841 }
842 
843 /*
844  * AMD systems with an IOMMU have an additional hole close to the
845  * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
846  * on kernel version, VFIO may or may not let you DMA map those ranges.
847  * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
848  * with certain memory sizes. It's also wrong to use those IOVA ranges
849  * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
850  * The ranges reserved for Hyper-Transport are:
851  *
852  * FD_0000_0000h - FF_FFFF_FFFFh
853  *
854  * The ranges represent the following:
855  *
856  * Base Address   Top Address  Use
857  *
858  * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
859  * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
860  * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
861  * FD_F910_0000h FD_F91F_FFFFh System Management
862  * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
863  * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
864  * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
865  * FD_FE00_0000h FD_FFFF_FFFFh Configuration
866  * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
867  * FE_2000_0000h FF_FFFF_FFFFh Reserved
868  *
869  * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
870  * Table 3: Special Address Controls (GPA) for more information.
871  */
872 #define AMD_HT_START         0xfd00000000UL
873 #define AMD_HT_END           0xffffffffffUL
874 #define AMD_ABOVE_1TB_START  (AMD_HT_END + 1)
875 #define AMD_HT_SIZE          (AMD_ABOVE_1TB_START - AMD_HT_START)
876 
877 void pc_memory_init(PCMachineState *pcms,
878                     MemoryRegion *system_memory,
879                     MemoryRegion *rom_memory,
880                     uint64_t pci_hole64_size)
881 {
882     int linux_boot, i;
883     MemoryRegion *option_rom_mr;
884     MemoryRegion *ram_below_4g, *ram_above_4g;
885     FWCfgState *fw_cfg;
886     MachineState *machine = MACHINE(pcms);
887     MachineClass *mc = MACHINE_GET_CLASS(machine);
888     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
889     X86MachineState *x86ms = X86_MACHINE(pcms);
890     hwaddr maxphysaddr, maxusedaddr;
891     hwaddr cxl_base, cxl_resv_end = 0;
892     X86CPU *cpu = X86_CPU(first_cpu);
893 
894     assert(machine->ram_size == x86ms->below_4g_mem_size +
895                                 x86ms->above_4g_mem_size);
896 
897     linux_boot = (machine->kernel_filename != NULL);
898 
899     /*
900      * The HyperTransport range close to the 1T boundary is unique to AMD
901      * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
902      * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
903      * older machine types (<= 7.0) for compatibility purposes.
904      */
905     if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
906         /* Bail out if max possible address does not cross HT range */
907         if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
908             x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
909         }
910 
911         /*
912          * Advertise the HT region if address space covers the reserved
913          * region or if we relocate.
914          */
915         if (cpu->phys_bits >= 40) {
916             e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
917         }
918     }
919 
920     /*
921      * phys-bits is required to be appropriately configured
922      * to make sure max used GPA is reachable.
923      */
924     maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
925     maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
926     if (maxphysaddr < maxusedaddr) {
927         error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
928                      " phys-bits too low (%u)",
929                      maxphysaddr, maxusedaddr, cpu->phys_bits);
930         exit(EXIT_FAILURE);
931     }
932 
933     /*
934      * Split single memory region and use aliases to address portions of it,
935      * done for backwards compatibility with older qemus.
936      */
937     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
938     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
939                              0, x86ms->below_4g_mem_size);
940     memory_region_add_subregion(system_memory, 0, ram_below_4g);
941     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
942     if (x86ms->above_4g_mem_size > 0) {
943         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
944         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
945                                  machine->ram,
946                                  x86ms->below_4g_mem_size,
947                                  x86ms->above_4g_mem_size);
948         memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
949                                     ram_above_4g);
950         e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
951                        E820_RAM);
952     }
953 
954     if (pcms->sgx_epc.size != 0) {
955         e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
956     }
957 
958     if (!pcmc->has_reserved_memory &&
959         (machine->ram_slots ||
960          (machine->maxram_size > machine->ram_size))) {
961 
962         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
963                      mc->name);
964         exit(EXIT_FAILURE);
965     }
966 
967     /* initialize device memory address space */
968     if (pcmc->has_reserved_memory &&
969         (machine->ram_size < machine->maxram_size)) {
970         ram_addr_t device_mem_size;
971         hwaddr device_mem_base;
972 
973         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
974             error_report("unsupported amount of memory slots: %"PRIu64,
975                          machine->ram_slots);
976             exit(EXIT_FAILURE);
977         }
978 
979         if (QEMU_ALIGN_UP(machine->maxram_size,
980                           TARGET_PAGE_SIZE) != machine->maxram_size) {
981             error_report("maximum memory size must by aligned to multiple of "
982                          "%d bytes", TARGET_PAGE_SIZE);
983             exit(EXIT_FAILURE);
984         }
985 
986         pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
987 
988         if (device_mem_base + device_mem_size < device_mem_size) {
989             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
990                          machine->maxram_size);
991             exit(EXIT_FAILURE);
992         }
993         machine_memory_devices_init(machine, device_mem_base, device_mem_size);
994     }
995 
996     if (pcms->cxl_devices_state.is_enabled) {
997         MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
998         hwaddr cxl_size = MiB;
999 
1000         cxl_base = pc_get_cxl_range_start(pcms);
1001         memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1002         memory_region_add_subregion(system_memory, cxl_base, mr);
1003         cxl_resv_end = cxl_base + cxl_size;
1004         if (pcms->cxl_devices_state.fixed_windows) {
1005             hwaddr cxl_fmw_base;
1006             GList *it;
1007 
1008             cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1009             for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1010                 CXLFixedWindow *fw = it->data;
1011 
1012                 fw->base = cxl_fmw_base;
1013                 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1014                                       "cxl-fixed-memory-region", fw->size);
1015                 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1016                 cxl_fmw_base += fw->size;
1017                 cxl_resv_end = cxl_fmw_base;
1018             }
1019         }
1020     }
1021 
1022     /* Initialize PC system firmware */
1023     pc_system_firmware_init(pcms, rom_memory);
1024 
1025     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1026     if (machine_require_guest_memfd(machine)) {
1027         memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom",
1028                                            PC_ROM_SIZE, &error_fatal);
1029     } else {
1030         memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1031                                &error_fatal);
1032         if (pcmc->pci_enabled) {
1033             memory_region_set_readonly(option_rom_mr, true);
1034         }
1035     }
1036     memory_region_add_subregion_overlap(rom_memory,
1037                                         PC_ROM_MIN_VGA,
1038                                         option_rom_mr,
1039                                         1);
1040 
1041     fw_cfg = fw_cfg_arch_create(machine,
1042                                 x86ms->boot_cpus, x86ms->apic_id_limit);
1043 
1044     rom_set_fw(fw_cfg);
1045 
1046     if (machine->device_memory) {
1047         uint64_t *val = g_malloc(sizeof(*val));
1048         uint64_t res_mem_end = machine->device_memory->base;
1049 
1050         if (!pcmc->broken_reserved_end) {
1051             res_mem_end += memory_region_size(&machine->device_memory->mr);
1052         }
1053 
1054         if (pcms->cxl_devices_state.is_enabled) {
1055             res_mem_end = cxl_resv_end;
1056         }
1057         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1058         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1059     }
1060 
1061     if (linux_boot) {
1062         x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1063                        pcmc->pvh_enabled);
1064     }
1065 
1066     for (i = 0; i < nb_option_roms; i++) {
1067         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1068     }
1069     x86ms->fw_cfg = fw_cfg;
1070 
1071     /* Init default IOAPIC address space */
1072     x86ms->ioapic_as = &address_space_memory;
1073 
1074     /* Init ACPI memory hotplug IO base address */
1075     pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1076 }
1077 
1078 /*
1079  * The 64bit pci hole starts after "above 4G RAM" and
1080  * potentially the space reserved for memory hotplug.
1081  */
1082 uint64_t pc_pci_hole64_start(void)
1083 {
1084     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1085     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1086     MachineState *ms = MACHINE(pcms);
1087     uint64_t hole64_start = 0;
1088     ram_addr_t size = 0;
1089 
1090     if (pcms->cxl_devices_state.is_enabled) {
1091         hole64_start = pc_get_cxl_range_end(pcms);
1092     } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1093         pc_get_device_memory_range(pcms, &hole64_start, &size);
1094         if (!pcmc->broken_reserved_end) {
1095             hole64_start += size;
1096         }
1097     } else {
1098         hole64_start = pc_above_4g_end(pcms);
1099     }
1100 
1101     return ROUND_UP(hole64_start, 1 * GiB);
1102 }
1103 
1104 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1105 {
1106     DeviceState *dev = NULL;
1107 
1108     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1109     if (pci_bus) {
1110         PCIDevice *pcidev = pci_vga_init(pci_bus);
1111         dev = pcidev ? &pcidev->qdev : NULL;
1112     } else if (isa_bus) {
1113         ISADevice *isadev = isa_vga_init(isa_bus);
1114         dev = isadev ? DEVICE(isadev) : NULL;
1115     }
1116     rom_reset_order_override();
1117     return dev;
1118 }
1119 
1120 static const MemoryRegionOps ioport80_io_ops = {
1121     .write = ioport80_write,
1122     .read = ioport80_read,
1123     .endianness = DEVICE_NATIVE_ENDIAN,
1124     .impl = {
1125         .min_access_size = 1,
1126         .max_access_size = 1,
1127     },
1128 };
1129 
1130 static const MemoryRegionOps ioportF0_io_ops = {
1131     .write = ioportF0_write,
1132     .read = ioportF0_read,
1133     .endianness = DEVICE_NATIVE_ENDIAN,
1134     .impl = {
1135         .min_access_size = 1,
1136         .max_access_size = 1,
1137     },
1138 };
1139 
1140 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1141                             bool create_i8042, bool no_vmport)
1142 {
1143     int i;
1144     DriveInfo *fd[MAX_FD];
1145     qemu_irq *a20_line;
1146     ISADevice *i8042, *port92, *vmmouse;
1147 
1148     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1149     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1150 
1151     for (i = 0; i < MAX_FD; i++) {
1152         fd[i] = drive_get(IF_FLOPPY, 0, i);
1153         create_fdctrl |= !!fd[i];
1154     }
1155     if (create_fdctrl) {
1156 #ifdef CONFIG_FDC_ISA
1157         ISADevice *fdc = isa_new(TYPE_ISA_FDC);
1158         if (fdc) {
1159             isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1160             isa_fdc_init_drives(fdc, fd);
1161         }
1162 #endif
1163     }
1164 
1165     if (!create_i8042) {
1166         return;
1167     }
1168 
1169     i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1170     if (!no_vmport) {
1171         isa_create_simple(isa_bus, TYPE_VMPORT);
1172         vmmouse = isa_try_new("vmmouse");
1173     } else {
1174         vmmouse = NULL;
1175     }
1176     if (vmmouse) {
1177         object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1178                                  &error_abort);
1179         isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1180     }
1181     port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1182 
1183     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1184     qdev_connect_gpio_out_named(DEVICE(i8042),
1185                                 I8042_A20_LINE, 0, a20_line[0]);
1186     qdev_connect_gpio_out_named(DEVICE(port92),
1187                                 PORT92_A20_LINE, 0, a20_line[1]);
1188     g_free(a20_line);
1189 }
1190 
1191 void pc_basic_device_init(struct PCMachineState *pcms,
1192                           ISABus *isa_bus, qemu_irq *gsi,
1193                           ISADevice *rtc_state,
1194                           bool create_fdctrl,
1195                           uint32_t hpet_irqs)
1196 {
1197     int i;
1198     DeviceState *hpet = NULL;
1199     int pit_isa_irq = 0;
1200     qemu_irq pit_alt_irq = NULL;
1201     ISADevice *pit = NULL;
1202     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1203     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1204     X86MachineState *x86ms = X86_MACHINE(pcms);
1205 
1206     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1207     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1208 
1209     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1210     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1211 
1212     /*
1213      * Check if an HPET shall be created.
1214      */
1215     if (pcms->hpet_enabled) {
1216         qemu_irq rtc_irq;
1217 
1218         hpet = qdev_try_new(TYPE_HPET);
1219         if (!hpet) {
1220             error_report("couldn't create HPET device");
1221             exit(1);
1222         }
1223         /*
1224          * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1225          * use IRQ16~23, IRQ8 and IRQ2.  If the user has already set
1226          * the property, use whatever mask they specified.
1227          */
1228         uint8_t compat = object_property_get_uint(OBJECT(hpet),
1229                 HPET_INTCAP, NULL);
1230         if (!compat) {
1231             qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1232         }
1233         sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1234         sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1235 
1236         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1237             sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1238         }
1239         pit_isa_irq = -1;
1240         pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1241         rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1242 
1243         /* overwrite connection created by south bridge */
1244         qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1245     }
1246 
1247     object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1248                               "date");
1249 
1250 #ifdef CONFIG_XEN_EMU
1251     if (xen_mode == XEN_EMULATE) {
1252         xen_overlay_create();
1253         xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1254         xen_gnttab_create();
1255         xen_xenstore_create();
1256         if (pcms->pcibus) {
1257             pci_create_simple(pcms->pcibus, -1, "xen-platform");
1258         }
1259         xen_bus_init();
1260     }
1261 #endif
1262 
1263     qemu_register_boot_set(pc_boot_set, pcms);
1264     set_boot_dev(pcms, MC146818_RTC(rtc_state),
1265                  MACHINE(pcms)->boot_config.order, &error_fatal);
1266 
1267     if (!xen_enabled() &&
1268         (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1269         if (kvm_pit_in_kernel()) {
1270             pit = kvm_pit_init(isa_bus, 0x40);
1271         } else {
1272             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1273         }
1274         if (hpet) {
1275             /* connect PIT to output control line of the HPET */
1276             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1277         }
1278         object_property_set_link(OBJECT(pcms->pcspk), "pit",
1279                                  OBJECT(pit), &error_fatal);
1280         isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1281     }
1282 
1283     /* Super I/O */
1284     pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1285                     pcms->vmport != ON_OFF_AUTO_ON);
1286 }
1287 
1288 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1289 {
1290     MachineClass *mc = MACHINE_CLASS(pcmc);
1291     bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
1292     NICInfo *nd;
1293 
1294     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1295 
1296     while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
1297         pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
1298     }
1299 
1300     /* Anything remaining should be a PCI NIC */
1301     pci_init_nic_devices(pci_bus, mc->default_nic);
1302 
1303     rom_reset_order_override();
1304 }
1305 
1306 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1307 {
1308     qemu_irq *i8259;
1309 
1310     if (kvm_pic_in_kernel()) {
1311         i8259 = kvm_i8259_init(isa_bus);
1312     } else if (xen_enabled()) {
1313         i8259 = xen_interrupt_controller_init();
1314     } else {
1315         i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1316     }
1317 
1318     for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1319         i8259_irqs[i] = i8259[i];
1320     }
1321 
1322     g_free(i8259);
1323 }
1324 
1325 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1326                                Error **errp)
1327 {
1328     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1329     const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1330     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1331     const MachineState *ms = MACHINE(hotplug_dev);
1332     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1333     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1334     Error *local_err = NULL;
1335 
1336     /*
1337      * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1338      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1339      * addition to cover this case.
1340      */
1341     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1342         error_setg(errp,
1343                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1344         return;
1345     }
1346 
1347     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1348         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1349         return;
1350     }
1351 
1352     hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1353     if (local_err) {
1354         error_propagate(errp, local_err);
1355         return;
1356     }
1357 
1358     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1359                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1360 }
1361 
1362 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1363                            DeviceState *dev, Error **errp)
1364 {
1365     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1366     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1367     MachineState *ms = MACHINE(hotplug_dev);
1368     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1369 
1370     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1371 
1372     if (is_nvdimm) {
1373         nvdimm_plug(ms->nvdimms_state);
1374     }
1375 
1376     hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1377 }
1378 
1379 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1380                                      DeviceState *dev, Error **errp)
1381 {
1382     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1383 
1384     /*
1385      * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1386      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1387      * addition to cover this case.
1388      */
1389     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1390         error_setg(errp,
1391                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1392         return;
1393     }
1394 
1395     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1396         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1397         return;
1398     }
1399 
1400     hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1401                                    errp);
1402 }
1403 
1404 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1405                              DeviceState *dev, Error **errp)
1406 {
1407     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1408     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1409     Error *local_err = NULL;
1410 
1411     hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1412     if (local_err) {
1413         goto out;
1414     }
1415 
1416     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1417     qdev_unrealize(dev);
1418  out:
1419     error_propagate(errp, local_err);
1420 }
1421 
1422 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1423                                    DeviceState *dev, Error **errp)
1424 {
1425     /* The vmbus handler has no hotplug handler; we should never end up here. */
1426     g_assert(!dev->hotplugged);
1427     memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1428                            errp);
1429 }
1430 
1431 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1432                                DeviceState *dev, Error **errp)
1433 {
1434     memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1435 }
1436 
1437 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1438                                           DeviceState *dev, Error **errp)
1439 {
1440     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1441         pc_memory_pre_plug(hotplug_dev, dev, errp);
1442     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1443         x86_cpu_pre_plug(hotplug_dev, dev, errp);
1444     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1445         virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1446     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1447         /* Declare the APIC range as the reserved MSI region */
1448         char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1449                                               VIRTIO_IOMMU_RESV_MEM_T_MSI);
1450         QList *reserved_regions = qlist_new();
1451 
1452         qlist_append_str(reserved_regions, resv_prop_str);
1453         qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1454 
1455         g_free(resv_prop_str);
1456     }
1457 
1458     if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1459         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1460         PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1461 
1462         if (pcms->iommu) {
1463             error_setg(errp, "QEMU does not support multiple vIOMMUs "
1464                        "for x86 yet.");
1465             return;
1466         }
1467         pcms->iommu = dev;
1468     } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1469         pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1470     }
1471 }
1472 
1473 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1474                                       DeviceState *dev, Error **errp)
1475 {
1476     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1477         pc_memory_plug(hotplug_dev, dev, errp);
1478     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1479         x86_cpu_plug(hotplug_dev, dev, errp);
1480     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1481         virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1482     } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1483         pc_hv_balloon_plug(hotplug_dev, dev, errp);
1484     }
1485 }
1486 
1487 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1488                                                 DeviceState *dev, Error **errp)
1489 {
1490     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1491         pc_memory_unplug_request(hotplug_dev, dev, errp);
1492     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1493         x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1494     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1495         virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1496                                      errp);
1497     } else {
1498         error_setg(errp, "acpi: device unplug request for not supported device"
1499                    " type: %s", object_get_typename(OBJECT(dev)));
1500     }
1501 }
1502 
1503 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1504                                         DeviceState *dev, Error **errp)
1505 {
1506     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1507         pc_memory_unplug(hotplug_dev, dev, errp);
1508     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1509         x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1510     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1511         virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1512     } else {
1513         error_setg(errp, "acpi: device unplug for not supported device"
1514                    " type: %s", object_get_typename(OBJECT(dev)));
1515     }
1516 }
1517 
1518 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1519                                              DeviceState *dev)
1520 {
1521     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1522         object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1523         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1524         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1525         object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1526         object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1527         return HOTPLUG_HANDLER(machine);
1528     }
1529 
1530     return NULL;
1531 }
1532 
1533 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1534                                   void *opaque, Error **errp)
1535 {
1536     PCMachineState *pcms = PC_MACHINE(obj);
1537     OnOffAuto vmport = pcms->vmport;
1538 
1539     visit_type_OnOffAuto(v, name, &vmport, errp);
1540 }
1541 
1542 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1543                                   void *opaque, Error **errp)
1544 {
1545     PCMachineState *pcms = PC_MACHINE(obj);
1546 
1547     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1548 }
1549 
1550 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp)
1551 {
1552     PCMachineState *pcms = PC_MACHINE(obj);
1553 
1554     return pcms->fd_bootchk;
1555 }
1556 
1557 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp)
1558 {
1559     PCMachineState *pcms = PC_MACHINE(obj);
1560 
1561     pcms->fd_bootchk = value;
1562 }
1563 
1564 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1565 {
1566     PCMachineState *pcms = PC_MACHINE(obj);
1567 
1568     return pcms->smbus_enabled;
1569 }
1570 
1571 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1572 {
1573     PCMachineState *pcms = PC_MACHINE(obj);
1574 
1575     pcms->smbus_enabled = value;
1576 }
1577 
1578 static bool pc_machine_get_sata(Object *obj, Error **errp)
1579 {
1580     PCMachineState *pcms = PC_MACHINE(obj);
1581 
1582     return pcms->sata_enabled;
1583 }
1584 
1585 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1586 {
1587     PCMachineState *pcms = PC_MACHINE(obj);
1588 
1589     pcms->sata_enabled = value;
1590 }
1591 
1592 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1593 {
1594     PCMachineState *pcms = PC_MACHINE(obj);
1595 
1596     return pcms->hpet_enabled;
1597 }
1598 
1599 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1600 {
1601     PCMachineState *pcms = PC_MACHINE(obj);
1602 
1603     pcms->hpet_enabled = value;
1604 }
1605 
1606 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1607 {
1608     PCMachineState *pcms = PC_MACHINE(obj);
1609 
1610     return pcms->i8042_enabled;
1611 }
1612 
1613 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1614 {
1615     PCMachineState *pcms = PC_MACHINE(obj);
1616 
1617     pcms->i8042_enabled = value;
1618 }
1619 
1620 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1621 {
1622     PCMachineState *pcms = PC_MACHINE(obj);
1623 
1624     return pcms->default_bus_bypass_iommu;
1625 }
1626 
1627 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1628                                                     Error **errp)
1629 {
1630     PCMachineState *pcms = PC_MACHINE(obj);
1631 
1632     pcms->default_bus_bypass_iommu = value;
1633 }
1634 
1635 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1636                                      void *opaque, Error **errp)
1637 {
1638     PCMachineState *pcms = PC_MACHINE(obj);
1639     SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1640 
1641     visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1642 }
1643 
1644 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1645                                      void *opaque, Error **errp)
1646 {
1647     PCMachineState *pcms = PC_MACHINE(obj);
1648 
1649     visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1650 }
1651 
1652 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1653                                             const char *name, void *opaque,
1654                                             Error **errp)
1655 {
1656     PCMachineState *pcms = PC_MACHINE(obj);
1657     uint64_t value = pcms->max_ram_below_4g;
1658 
1659     visit_type_size(v, name, &value, errp);
1660 }
1661 
1662 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1663                                             const char *name, void *opaque,
1664                                             Error **errp)
1665 {
1666     PCMachineState *pcms = PC_MACHINE(obj);
1667     uint64_t value;
1668 
1669     if (!visit_type_size(v, name, &value, errp)) {
1670         return;
1671     }
1672     if (value > 4 * GiB) {
1673         error_setg(errp,
1674                    "Machine option 'max-ram-below-4g=%"PRIu64
1675                    "' expects size less than or equal to 4G", value);
1676         return;
1677     }
1678 
1679     if (value < 1 * MiB) {
1680         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1681                     "BIOS may not work with less than 1MiB", value);
1682     }
1683 
1684     pcms->max_ram_below_4g = value;
1685 }
1686 
1687 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1688                                        const char *name, void *opaque,
1689                                        Error **errp)
1690 {
1691     PCMachineState *pcms = PC_MACHINE(obj);
1692     uint64_t value = pcms->max_fw_size;
1693 
1694     visit_type_size(v, name, &value, errp);
1695 }
1696 
1697 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1698                                        const char *name, void *opaque,
1699                                        Error **errp)
1700 {
1701     PCMachineState *pcms = PC_MACHINE(obj);
1702     uint64_t value;
1703 
1704     if (!visit_type_size(v, name, &value, errp)) {
1705         return;
1706     }
1707 
1708     /*
1709      * We don't have a theoretically justifiable exact lower bound on the base
1710      * address of any flash mapping. In practice, the IO-APIC MMIO range is
1711      * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1712      * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1713      * 16MiB in size.
1714      */
1715     if (value > 16 * MiB) {
1716         error_setg(errp,
1717                    "User specified max allowed firmware size %" PRIu64 " is "
1718                    "greater than 16MiB. If combined firmware size exceeds "
1719                    "16MiB the system may not boot, or experience intermittent"
1720                    "stability issues.",
1721                    value);
1722         return;
1723     }
1724 
1725     pcms->max_fw_size = value;
1726 }
1727 
1728 
1729 static void pc_machine_initfn(Object *obj)
1730 {
1731     PCMachineState *pcms = PC_MACHINE(obj);
1732     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1733 
1734 #ifdef CONFIG_VMPORT
1735     pcms->vmport = ON_OFF_AUTO_AUTO;
1736 #else
1737     pcms->vmport = ON_OFF_AUTO_OFF;
1738 #endif /* CONFIG_VMPORT */
1739     pcms->max_ram_below_4g = 0; /* use default */
1740     pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1741     pcms->south_bridge = pcmc->default_south_bridge;
1742 
1743     /* acpi build is enabled by default if machine supports it */
1744     pcms->acpi_build_enabled = pcmc->has_acpi_build;
1745     pcms->smbus_enabled = true;
1746     pcms->sata_enabled = true;
1747     pcms->i8042_enabled = true;
1748     pcms->max_fw_size = 8 * MiB;
1749 #ifdef CONFIG_HPET
1750     pcms->hpet_enabled = true;
1751 #endif
1752     pcms->fd_bootchk = true;
1753     pcms->default_bus_bypass_iommu = false;
1754 
1755     pc_system_flash_create(pcms);
1756     pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1757     object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1758                               OBJECT(pcms->pcspk), "audiodev");
1759     if (pcmc->pci_enabled) {
1760         cxl_machine_init(obj, &pcms->cxl_devices_state);
1761     }
1762 
1763     pcms->machine_done.notify = pc_machine_done;
1764     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1765 }
1766 
1767 static void pc_machine_reset(MachineState *machine, ShutdownCause reason)
1768 {
1769     CPUState *cs;
1770     X86CPU *cpu;
1771 
1772     qemu_devices_reset(reason);
1773 
1774     /* Reset APIC after devices have been reset to cancel
1775      * any changes that qemu_devices_reset() might have done.
1776      */
1777     CPU_FOREACH(cs) {
1778         cpu = X86_CPU(cs);
1779 
1780         x86_cpu_after_reset(cpu);
1781     }
1782 }
1783 
1784 static void pc_machine_wakeup(MachineState *machine)
1785 {
1786     cpu_synchronize_all_states();
1787     pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE);
1788     cpu_synchronize_all_post_reset();
1789 }
1790 
1791 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1792 {
1793     X86IOMMUState *iommu = x86_iommu_get_default();
1794     IntelIOMMUState *intel_iommu;
1795 
1796     if (iommu &&
1797         object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1798         object_dynamic_cast((Object *)dev, "vfio-pci")) {
1799         intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1800         if (!intel_iommu->caching_mode) {
1801             error_setg(errp, "Device assignment is not allowed without "
1802                        "enabling caching-mode=on for Intel IOMMU.");
1803             return false;
1804         }
1805     }
1806 
1807     return true;
1808 }
1809 
1810 static void pc_machine_class_init(ObjectClass *oc, void *data)
1811 {
1812     MachineClass *mc = MACHINE_CLASS(oc);
1813     X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1814     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1815     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1816 
1817     pcmc->pci_enabled = true;
1818     pcmc->has_acpi_build = true;
1819     pcmc->rsdp_in_ram = true;
1820     pcmc->smbios_defaults = true;
1821     pcmc->smbios_uuid_encoded = true;
1822     pcmc->gigabyte_align = true;
1823     pcmc->has_reserved_memory = true;
1824     pcmc->enforce_aligned_dimm = true;
1825     pcmc->enforce_amd_1tb_hole = true;
1826     pcmc->isa_bios_alias = true;
1827     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1828      * to be used at the moment, 32K should be enough for a while.  */
1829     pcmc->acpi_data_size = 0x20000 + 0x8000;
1830     pcmc->pvh_enabled = true;
1831     pcmc->kvmclock_create_always = true;
1832     pcmc->resizable_acpi_blob = true;
1833     x86mc->apic_xrupt_override = true;
1834     assert(!mc->get_hotplug_handler);
1835     mc->get_hotplug_handler = pc_get_hotplug_handler;
1836     mc->hotplug_allowed = pc_hotplug_allowed;
1837     mc->auto_enable_numa_with_memhp = true;
1838     mc->auto_enable_numa_with_memdev = true;
1839     mc->has_hotpluggable_cpus = true;
1840     mc->default_boot_order = "cad";
1841     mc->block_default_type = IF_IDE;
1842     mc->max_cpus = 255;
1843     mc->reset = pc_machine_reset;
1844     mc->wakeup = pc_machine_wakeup;
1845     hc->pre_plug = pc_machine_device_pre_plug_cb;
1846     hc->plug = pc_machine_device_plug_cb;
1847     hc->unplug_request = pc_machine_device_unplug_request_cb;
1848     hc->unplug = pc_machine_device_unplug_cb;
1849     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1850     mc->nvdimm_supported = true;
1851     mc->smp_props.dies_supported = true;
1852     mc->smp_props.modules_supported = true;
1853     mc->default_ram_id = "pc.ram";
1854     pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;
1855 
1856     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1857         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1858         NULL, NULL);
1859     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1860         "Maximum ram below the 4G boundary (32bit boundary)");
1861 
1862     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1863         pc_machine_get_vmport, pc_machine_set_vmport,
1864         NULL, NULL);
1865     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1866         "Enable vmport (pc & q35)");
1867 
1868     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1869         pc_machine_get_smbus, pc_machine_set_smbus);
1870     object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1871         "Enable/disable system management bus");
1872 
1873     object_class_property_add_bool(oc, PC_MACHINE_SATA,
1874         pc_machine_get_sata, pc_machine_set_sata);
1875     object_class_property_set_description(oc, PC_MACHINE_SATA,
1876         "Enable/disable Serial ATA bus");
1877 
1878     object_class_property_add_bool(oc, "hpet",
1879         pc_machine_get_hpet, pc_machine_set_hpet);
1880     object_class_property_set_description(oc, "hpet",
1881         "Enable/disable high precision event timer emulation");
1882 
1883     object_class_property_add_bool(oc, PC_MACHINE_I8042,
1884         pc_machine_get_i8042, pc_machine_set_i8042);
1885 
1886     object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1887         pc_machine_get_default_bus_bypass_iommu,
1888         pc_machine_set_default_bus_bypass_iommu);
1889 
1890     object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1891         pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1892         NULL, NULL);
1893     object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1894         "Maximum combined firmware size");
1895 
1896     object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1897         pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1898         NULL, NULL);
1899     object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1900         "SMBIOS Entry Point type [32, 64]");
1901 
1902     object_class_property_add_bool(oc, "fd-bootchk",
1903         pc_machine_get_fd_bootchk,
1904         pc_machine_set_fd_bootchk);
1905 }
1906 
1907 static const TypeInfo pc_machine_info = {
1908     .name = TYPE_PC_MACHINE,
1909     .parent = TYPE_X86_MACHINE,
1910     .abstract = true,
1911     .instance_size = sizeof(PCMachineState),
1912     .instance_init = pc_machine_initfn,
1913     .class_size = sizeof(PCMachineClass),
1914     .class_init = pc_machine_class_init,
1915     .interfaces = (InterfaceInfo[]) {
1916          { TYPE_HOTPLUG_HANDLER },
1917          { }
1918     },
1919 };
1920 
1921 static void pc_machine_register_types(void)
1922 {
1923     type_register_static(&pc_machine_info);
1924 }
1925 
1926 type_init(pc_machine_register_types)
1927