1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/internal.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_8_2[] = {}; 82 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 83 84 GlobalProperty pc_compat_8_1[] = {}; 85 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 86 87 GlobalProperty pc_compat_8_0[] = { 88 { "virtio-mem", "unplugged-inaccessible", "auto" }, 89 }; 90 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 91 92 GlobalProperty pc_compat_7_2[] = { 93 { "ICH9-LPC", "noreboot", "true" }, 94 }; 95 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 96 97 GlobalProperty pc_compat_7_1[] = {}; 98 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 99 100 GlobalProperty pc_compat_7_0[] = {}; 101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 102 103 GlobalProperty pc_compat_6_2[] = { 104 { "virtio-mem", "unplugged-inaccessible", "off" }, 105 }; 106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 107 108 GlobalProperty pc_compat_6_1[] = { 109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 113 }; 114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 115 116 GlobalProperty pc_compat_6_0[] = { 117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 123 }; 124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 125 126 GlobalProperty pc_compat_5_2[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 128 }; 129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 130 131 GlobalProperty pc_compat_5_1[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 134 }; 135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 136 137 GlobalProperty pc_compat_5_0[] = { 138 }; 139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 140 141 GlobalProperty pc_compat_4_2[] = { 142 { "mch", "smbase-smram", "off" }, 143 }; 144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 145 146 GlobalProperty pc_compat_4_1[] = {}; 147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 148 149 GlobalProperty pc_compat_4_0[] = {}; 150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 151 152 GlobalProperty pc_compat_3_1[] = { 153 { "intel-iommu", "dma-drain", "off" }, 154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 174 }; 175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 176 177 GlobalProperty pc_compat_3_0[] = { 178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 181 }; 182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 183 184 GlobalProperty pc_compat_2_12[] = { 185 { TYPE_X86_CPU, "legacy-cache", "on" }, 186 { TYPE_X86_CPU, "topoext", "off" }, 187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 }; 190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 191 192 GlobalProperty pc_compat_2_11[] = { 193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 195 }; 196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 197 198 GlobalProperty pc_compat_2_10[] = { 199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 201 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 202 }; 203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 204 205 GlobalProperty pc_compat_2_9[] = { 206 { "mch", "extended-tseg-mbytes", "0" }, 207 }; 208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 209 210 GlobalProperty pc_compat_2_8[] = { 211 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 213 { "ICH9-LPC", "x-smi-broadcast", "off" }, 214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 216 }; 217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 218 219 GlobalProperty pc_compat_2_7[] = { 220 { TYPE_X86_CPU, "l3-cache", "off" }, 221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 225 { "isa-pcspk", "migrate", "off" }, 226 }; 227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 228 229 GlobalProperty pc_compat_2_6[] = { 230 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 231 { "vmxnet3", "romfile", "" }, 232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 233 { "apic-common", "legacy-instance-id", "on", } 234 }; 235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 236 237 GlobalProperty pc_compat_2_5[] = {}; 238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 239 240 GlobalProperty pc_compat_2_4[] = { 241 PC_CPU_MODEL_IDS("2.4.0") 242 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 247 { TYPE_X86_CPU, "check", "off" }, 248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 256 }; 257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 258 259 GlobalProperty pc_compat_2_3[] = { 260 PC_CPU_MODEL_IDS("2.3.0") 261 { TYPE_X86_CPU, "arat", "off" }, 262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 281 }; 282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 283 284 GlobalProperty pc_compat_2_2[] = { 285 PC_CPU_MODEL_IDS("2.2.0") 286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 304 }; 305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 306 307 GlobalProperty pc_compat_2_1[] = { 308 PC_CPU_MODEL_IDS("2.1.0") 309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 }; 312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 313 314 GlobalProperty pc_compat_2_0[] = { 315 PC_CPU_MODEL_IDS("2.0.0") 316 { "virtio-scsi-pci", "any_layout", "off" }, 317 { "PIIX4_PM", "memory-hotplug-support", "off" }, 318 { "apic", "version", "0x11" }, 319 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 320 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 321 { "pci-serial", "prog_if", "0" }, 322 { "pci-serial-2x", "prog_if", "0" }, 323 { "pci-serial-4x", "prog_if", "0" }, 324 { "virtio-net-pci", "guest_announce", "off" }, 325 { "ICH9-LPC", "memory-hotplug-support", "off" }, 326 }; 327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 328 329 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 330 { 331 GSIState *s; 332 333 s = g_new0(GSIState, 1); 334 if (kvm_ioapic_in_kernel()) { 335 kvm_pc_setup_irq_routing(pci_enabled); 336 } 337 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 338 339 return s; 340 } 341 342 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 343 unsigned size) 344 { 345 } 346 347 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 348 { 349 return 0xffffffffffffffffULL; 350 } 351 352 /* MS-DOS compatibility mode FPU exception support */ 353 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 354 unsigned size) 355 { 356 if (tcg_enabled()) { 357 cpu_set_ignne(); 358 } 359 } 360 361 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 362 { 363 return 0xffffffffffffffffULL; 364 } 365 366 /* PC cmos mappings */ 367 368 #define REG_EQUIPMENT_BYTE 0x14 369 370 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 371 int16_t cylinders, int8_t heads, int8_t sectors) 372 { 373 mc146818rtc_set_cmos_data(s, type_ofs, 47); 374 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 375 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 376 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 377 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 378 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 379 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 380 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 381 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 382 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 383 } 384 385 /* convert boot_device letter to something recognizable by the bios */ 386 static int boot_device2nibble(char boot_device) 387 { 388 switch(boot_device) { 389 case 'a': 390 case 'b': 391 return 0x01; /* floppy boot */ 392 case 'c': 393 return 0x02; /* hard drive boot */ 394 case 'd': 395 return 0x03; /* CD-ROM boot */ 396 case 'n': 397 return 0x04; /* Network boot */ 398 } 399 return 0; 400 } 401 402 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 403 Error **errp) 404 { 405 #define PC_MAX_BOOT_DEVICES 3 406 int nbds, bds[3] = { 0, }; 407 int i; 408 409 nbds = strlen(boot_device); 410 if (nbds > PC_MAX_BOOT_DEVICES) { 411 error_setg(errp, "Too many boot devices for PC"); 412 return; 413 } 414 for (i = 0; i < nbds; i++) { 415 bds[i] = boot_device2nibble(boot_device[i]); 416 if (bds[i] == 0) { 417 error_setg(errp, "Invalid boot device for PC: '%c'", 418 boot_device[i]); 419 return; 420 } 421 } 422 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 423 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 424 } 425 426 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 427 { 428 set_boot_dev(opaque, boot_device, errp); 429 } 430 431 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 432 { 433 int val, nb, i; 434 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 435 FLOPPY_DRIVE_TYPE_NONE }; 436 437 /* floppy type */ 438 if (floppy) { 439 for (i = 0; i < 2; i++) { 440 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 441 } 442 } 443 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 444 cmos_get_fd_drive_type(fd_type[1]); 445 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 446 447 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 448 nb = 0; 449 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 450 nb++; 451 } 452 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 453 nb++; 454 } 455 switch (nb) { 456 case 0: 457 break; 458 case 1: 459 val |= 0x01; /* 1 drive, ready for boot */ 460 break; 461 case 2: 462 val |= 0x41; /* 2 drives, ready for boot */ 463 break; 464 } 465 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 466 } 467 468 typedef struct pc_cmos_init_late_arg { 469 MC146818RtcState *rtc_state; 470 BusState *idebus[2]; 471 } pc_cmos_init_late_arg; 472 473 typedef struct check_fdc_state { 474 ISADevice *floppy; 475 bool multiple; 476 } CheckFdcState; 477 478 static int check_fdc(Object *obj, void *opaque) 479 { 480 CheckFdcState *state = opaque; 481 Object *fdc; 482 uint32_t iobase; 483 Error *local_err = NULL; 484 485 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 486 if (!fdc) { 487 return 0; 488 } 489 490 iobase = object_property_get_uint(obj, "iobase", &local_err); 491 if (local_err || iobase != 0x3f0) { 492 error_free(local_err); 493 return 0; 494 } 495 496 if (state->floppy) { 497 state->multiple = true; 498 } else { 499 state->floppy = ISA_DEVICE(obj); 500 } 501 return 0; 502 } 503 504 static const char * const fdc_container_path[] = { 505 "/unattached", "/peripheral", "/peripheral-anon" 506 }; 507 508 /* 509 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 510 * and ACPI objects. 511 */ 512 static ISADevice *pc_find_fdc0(void) 513 { 514 int i; 515 Object *container; 516 CheckFdcState state = { 0 }; 517 518 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 519 container = container_get(qdev_get_machine(), fdc_container_path[i]); 520 object_child_foreach(container, check_fdc, &state); 521 } 522 523 if (state.multiple) { 524 warn_report("multiple floppy disk controllers with " 525 "iobase=0x3f0 have been found"); 526 error_printf("the one being picked for CMOS setup might not reflect " 527 "your intent"); 528 } 529 530 return state.floppy; 531 } 532 533 static void pc_cmos_init_late(void *opaque) 534 { 535 pc_cmos_init_late_arg *arg = opaque; 536 MC146818RtcState *s = arg->rtc_state; 537 int16_t cylinders; 538 int8_t heads, sectors; 539 int val; 540 int i, trans; 541 542 val = 0; 543 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 544 &cylinders, &heads, §ors) >= 0) { 545 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 546 val |= 0xf0; 547 } 548 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 549 &cylinders, &heads, §ors) >= 0) { 550 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 551 val |= 0x0f; 552 } 553 mc146818rtc_set_cmos_data(s, 0x12, val); 554 555 val = 0; 556 for (i = 0; i < 4; i++) { 557 /* NOTE: ide_get_geometry() returns the physical 558 geometry. It is always such that: 1 <= sects <= 63, 1 559 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 560 geometry can be different if a translation is done. */ 561 if (arg->idebus[i / 2] && 562 ide_get_geometry(arg->idebus[i / 2], i % 2, 563 &cylinders, &heads, §ors) >= 0) { 564 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 565 assert((trans & ~3) == 0); 566 val |= trans << (i * 2); 567 } 568 } 569 mc146818rtc_set_cmos_data(s, 0x39, val); 570 571 pc_cmos_init_floppy(s, pc_find_fdc0()); 572 573 qemu_unregister_reset(pc_cmos_init_late, opaque); 574 } 575 576 void pc_cmos_init(PCMachineState *pcms, 577 BusState *idebus0, BusState *idebus1, 578 ISADevice *rtc) 579 { 580 int val; 581 static pc_cmos_init_late_arg arg; 582 X86MachineState *x86ms = X86_MACHINE(pcms); 583 MC146818RtcState *s = MC146818_RTC(rtc); 584 585 /* various important CMOS locations needed by PC/Bochs bios */ 586 587 /* memory size */ 588 /* base memory (first MiB) */ 589 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 590 mc146818rtc_set_cmos_data(s, 0x15, val); 591 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 592 /* extended memory (next 64MiB) */ 593 if (x86ms->below_4g_mem_size > 1 * MiB) { 594 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 595 } else { 596 val = 0; 597 } 598 if (val > 65535) 599 val = 65535; 600 mc146818rtc_set_cmos_data(s, 0x17, val); 601 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 602 mc146818rtc_set_cmos_data(s, 0x30, val); 603 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 604 /* memory between 16MiB and 4GiB */ 605 if (x86ms->below_4g_mem_size > 16 * MiB) { 606 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 607 } else { 608 val = 0; 609 } 610 if (val > 65535) 611 val = 65535; 612 mc146818rtc_set_cmos_data(s, 0x34, val); 613 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 614 /* memory above 4GiB */ 615 val = x86ms->above_4g_mem_size / 65536; 616 mc146818rtc_set_cmos_data(s, 0x5b, val); 617 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 618 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 619 620 object_property_add_link(OBJECT(pcms), "rtc_state", 621 TYPE_ISA_DEVICE, 622 (Object **)&x86ms->rtc, 623 object_property_allow_set_link, 624 OBJ_PROP_LINK_STRONG); 625 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 626 &error_abort); 627 628 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 629 630 val = 0; 631 val |= 0x02; /* FPU is there */ 632 val |= 0x04; /* PS/2 mouse installed */ 633 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 634 635 /* hard drives and FDC */ 636 arg.rtc_state = s; 637 arg.idebus[0] = idebus0; 638 arg.idebus[1] = idebus1; 639 qemu_register_reset(pc_cmos_init_late, &arg); 640 } 641 642 static void handle_a20_line_change(void *opaque, int irq, int level) 643 { 644 X86CPU *cpu = opaque; 645 646 /* XXX: send to all CPUs ? */ 647 /* XXX: add logic to handle multiple A20 line sources */ 648 x86_cpu_set_a20(cpu, level); 649 } 650 651 #define NE2000_NB_MAX 6 652 653 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 654 0x280, 0x380 }; 655 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 656 657 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 658 { 659 static int nb_ne2k = 0; 660 661 if (nb_ne2k == NE2000_NB_MAX) { 662 error_setg(errp, 663 "maximum number of ISA NE2000 devices exceeded"); 664 return false; 665 } 666 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 667 ne2000_irq[nb_ne2k], nd); 668 nb_ne2k++; 669 return true; 670 } 671 672 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 673 { 674 X86CPU *cpu = opaque; 675 676 if (level) { 677 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 678 } 679 } 680 681 static 682 void pc_machine_done(Notifier *notifier, void *data) 683 { 684 PCMachineState *pcms = container_of(notifier, 685 PCMachineState, machine_done); 686 X86MachineState *x86ms = X86_MACHINE(pcms); 687 688 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 689 &error_fatal); 690 691 if (pcms->cxl_devices_state.is_enabled) { 692 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 693 } 694 695 /* set the number of CPUs */ 696 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 697 698 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 699 700 acpi_setup(); 701 if (x86ms->fw_cfg) { 702 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 703 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 704 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 705 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 706 } 707 } 708 709 void pc_guest_info_init(PCMachineState *pcms) 710 { 711 X86MachineState *x86ms = X86_MACHINE(pcms); 712 713 x86ms->apic_xrupt_override = true; 714 pcms->machine_done.notify = pc_machine_done; 715 qemu_add_machine_init_done_notifier(&pcms->machine_done); 716 } 717 718 /* setup pci memory address space mapping into system address space */ 719 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 720 MemoryRegion *pci_address_space) 721 { 722 /* Set to lower priority than RAM */ 723 memory_region_add_subregion_overlap(system_memory, 0x0, 724 pci_address_space, -1); 725 } 726 727 void xen_load_linux(PCMachineState *pcms) 728 { 729 int i; 730 FWCfgState *fw_cfg; 731 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 732 X86MachineState *x86ms = X86_MACHINE(pcms); 733 734 assert(MACHINE(pcms)->kernel_filename != NULL); 735 736 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 737 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 738 rom_set_fw(fw_cfg); 739 740 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 741 pcmc->pvh_enabled); 742 for (i = 0; i < nb_option_roms; i++) { 743 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 744 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 745 !strcmp(option_rom[i].name, "pvh.bin") || 746 !strcmp(option_rom[i].name, "multiboot.bin") || 747 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 748 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 749 } 750 x86ms->fw_cfg = fw_cfg; 751 } 752 753 #define PC_ROM_MIN_VGA 0xc0000 754 #define PC_ROM_MIN_OPTION 0xc8000 755 #define PC_ROM_MAX 0xe0000 756 #define PC_ROM_ALIGN 0x800 757 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 758 759 static hwaddr pc_above_4g_end(PCMachineState *pcms) 760 { 761 X86MachineState *x86ms = X86_MACHINE(pcms); 762 763 if (pcms->sgx_epc.size != 0) { 764 return sgx_epc_above_4g_end(&pcms->sgx_epc); 765 } 766 767 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 768 } 769 770 static void pc_get_device_memory_range(PCMachineState *pcms, 771 hwaddr *base, 772 ram_addr_t *device_mem_size) 773 { 774 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 775 MachineState *machine = MACHINE(pcms); 776 ram_addr_t size; 777 hwaddr addr; 778 779 size = machine->maxram_size - machine->ram_size; 780 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 781 782 if (pcmc->enforce_aligned_dimm) { 783 /* size device region assuming 1G page max alignment per slot */ 784 size += (1 * GiB) * machine->ram_slots; 785 } 786 787 *base = addr; 788 *device_mem_size = size; 789 } 790 791 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 792 { 793 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 794 MachineState *ms = MACHINE(pcms); 795 hwaddr cxl_base; 796 ram_addr_t size; 797 798 if (pcmc->has_reserved_memory && 799 (ms->ram_size < ms->maxram_size)) { 800 pc_get_device_memory_range(pcms, &cxl_base, &size); 801 cxl_base += size; 802 } else { 803 cxl_base = pc_above_4g_end(pcms); 804 } 805 806 return cxl_base; 807 } 808 809 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 810 { 811 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 812 813 if (pcms->cxl_devices_state.fixed_windows) { 814 GList *it; 815 816 start = ROUND_UP(start, 256 * MiB); 817 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 818 CXLFixedWindow *fw = it->data; 819 start += fw->size; 820 } 821 } 822 823 return start; 824 } 825 826 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 827 { 828 X86CPU *cpu = X86_CPU(first_cpu); 829 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 830 MachineState *ms = MACHINE(pcms); 831 832 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 833 /* 64-bit systems */ 834 return pc_pci_hole64_start() + pci_hole64_size - 1; 835 } 836 837 /* 32-bit systems */ 838 if (pcmc->broken_32bit_mem_addr_check) { 839 /* old value for compatibility reasons */ 840 return ((hwaddr)1 << cpu->phys_bits) - 1; 841 } 842 843 /* 844 * 32-bit systems don't have hole64 but they might have a region for 845 * memory devices. Even if additional hotplugged memory devices might 846 * not be usable by most guest OSes, we need to still consider them for 847 * calculating the highest possible GPA so that we can properly report 848 * if someone configures them on a CPU that cannot possibly address them. 849 */ 850 if (pcmc->has_reserved_memory && 851 (ms->ram_size < ms->maxram_size)) { 852 hwaddr devmem_start; 853 ram_addr_t devmem_size; 854 855 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 856 devmem_start += devmem_size; 857 return devmem_start - 1; 858 } 859 860 /* configuration without any memory hotplug */ 861 return pc_above_4g_end(pcms) - 1; 862 } 863 864 /* 865 * AMD systems with an IOMMU have an additional hole close to the 866 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 867 * on kernel version, VFIO may or may not let you DMA map those ranges. 868 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 869 * with certain memory sizes. It's also wrong to use those IOVA ranges 870 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 871 * The ranges reserved for Hyper-Transport are: 872 * 873 * FD_0000_0000h - FF_FFFF_FFFFh 874 * 875 * The ranges represent the following: 876 * 877 * Base Address Top Address Use 878 * 879 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 880 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 881 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 882 * FD_F910_0000h FD_F91F_FFFFh System Management 883 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 884 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 885 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 886 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 887 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 888 * FE_2000_0000h FF_FFFF_FFFFh Reserved 889 * 890 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 891 * Table 3: Special Address Controls (GPA) for more information. 892 */ 893 #define AMD_HT_START 0xfd00000000UL 894 #define AMD_HT_END 0xffffffffffUL 895 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 896 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 897 898 void pc_memory_init(PCMachineState *pcms, 899 MemoryRegion *system_memory, 900 MemoryRegion *rom_memory, 901 uint64_t pci_hole64_size) 902 { 903 int linux_boot, i; 904 MemoryRegion *option_rom_mr; 905 MemoryRegion *ram_below_4g, *ram_above_4g; 906 FWCfgState *fw_cfg; 907 MachineState *machine = MACHINE(pcms); 908 MachineClass *mc = MACHINE_GET_CLASS(machine); 909 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 910 X86MachineState *x86ms = X86_MACHINE(pcms); 911 hwaddr maxphysaddr, maxusedaddr; 912 hwaddr cxl_base, cxl_resv_end = 0; 913 X86CPU *cpu = X86_CPU(first_cpu); 914 915 assert(machine->ram_size == x86ms->below_4g_mem_size + 916 x86ms->above_4g_mem_size); 917 918 linux_boot = (machine->kernel_filename != NULL); 919 920 /* 921 * The HyperTransport range close to the 1T boundary is unique to AMD 922 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 923 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 924 * older machine types (<= 7.0) for compatibility purposes. 925 */ 926 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 927 /* Bail out if max possible address does not cross HT range */ 928 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 929 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 930 } 931 932 /* 933 * Advertise the HT region if address space covers the reserved 934 * region or if we relocate. 935 */ 936 if (cpu->phys_bits >= 40) { 937 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 938 } 939 } 940 941 /* 942 * phys-bits is required to be appropriately configured 943 * to make sure max used GPA is reachable. 944 */ 945 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 946 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 947 if (maxphysaddr < maxusedaddr) { 948 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 949 " phys-bits too low (%u)", 950 maxphysaddr, maxusedaddr, cpu->phys_bits); 951 exit(EXIT_FAILURE); 952 } 953 954 /* 955 * Split single memory region and use aliases to address portions of it, 956 * done for backwards compatibility with older qemus. 957 */ 958 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 959 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 960 0, x86ms->below_4g_mem_size); 961 memory_region_add_subregion(system_memory, 0, ram_below_4g); 962 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 963 if (x86ms->above_4g_mem_size > 0) { 964 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 965 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 966 machine->ram, 967 x86ms->below_4g_mem_size, 968 x86ms->above_4g_mem_size); 969 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 970 ram_above_4g); 971 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 972 E820_RAM); 973 } 974 975 if (pcms->sgx_epc.size != 0) { 976 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 977 } 978 979 if (!pcmc->has_reserved_memory && 980 (machine->ram_slots || 981 (machine->maxram_size > machine->ram_size))) { 982 983 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 984 mc->name); 985 exit(EXIT_FAILURE); 986 } 987 988 /* initialize device memory address space */ 989 if (pcmc->has_reserved_memory && 990 (machine->ram_size < machine->maxram_size)) { 991 ram_addr_t device_mem_size; 992 hwaddr device_mem_base; 993 994 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 995 error_report("unsupported amount of memory slots: %"PRIu64, 996 machine->ram_slots); 997 exit(EXIT_FAILURE); 998 } 999 1000 if (QEMU_ALIGN_UP(machine->maxram_size, 1001 TARGET_PAGE_SIZE) != machine->maxram_size) { 1002 error_report("maximum memory size must by aligned to multiple of " 1003 "%d bytes", TARGET_PAGE_SIZE); 1004 exit(EXIT_FAILURE); 1005 } 1006 1007 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 1008 1009 if (device_mem_base + device_mem_size < device_mem_size) { 1010 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1011 machine->maxram_size); 1012 exit(EXIT_FAILURE); 1013 } 1014 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 1015 } 1016 1017 if (pcms->cxl_devices_state.is_enabled) { 1018 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1019 hwaddr cxl_size = MiB; 1020 1021 cxl_base = pc_get_cxl_range_start(pcms); 1022 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1023 memory_region_add_subregion(system_memory, cxl_base, mr); 1024 cxl_resv_end = cxl_base + cxl_size; 1025 if (pcms->cxl_devices_state.fixed_windows) { 1026 hwaddr cxl_fmw_base; 1027 GList *it; 1028 1029 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1030 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1031 CXLFixedWindow *fw = it->data; 1032 1033 fw->base = cxl_fmw_base; 1034 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1035 "cxl-fixed-memory-region", fw->size); 1036 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1037 cxl_fmw_base += fw->size; 1038 cxl_resv_end = cxl_fmw_base; 1039 } 1040 } 1041 } 1042 1043 /* Initialize PC system firmware */ 1044 pc_system_firmware_init(pcms, rom_memory); 1045 1046 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1047 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1048 &error_fatal); 1049 if (pcmc->pci_enabled) { 1050 memory_region_set_readonly(option_rom_mr, true); 1051 } 1052 memory_region_add_subregion_overlap(rom_memory, 1053 PC_ROM_MIN_VGA, 1054 option_rom_mr, 1055 1); 1056 1057 fw_cfg = fw_cfg_arch_create(machine, 1058 x86ms->boot_cpus, x86ms->apic_id_limit); 1059 1060 rom_set_fw(fw_cfg); 1061 1062 if (machine->device_memory) { 1063 uint64_t *val = g_malloc(sizeof(*val)); 1064 uint64_t res_mem_end = machine->device_memory->base; 1065 1066 if (!pcmc->broken_reserved_end) { 1067 res_mem_end += memory_region_size(&machine->device_memory->mr); 1068 } 1069 1070 if (pcms->cxl_devices_state.is_enabled) { 1071 res_mem_end = cxl_resv_end; 1072 } 1073 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1074 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1075 } 1076 1077 if (linux_boot) { 1078 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1079 pcmc->pvh_enabled); 1080 } 1081 1082 for (i = 0; i < nb_option_roms; i++) { 1083 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1084 } 1085 x86ms->fw_cfg = fw_cfg; 1086 1087 /* Init default IOAPIC address space */ 1088 x86ms->ioapic_as = &address_space_memory; 1089 1090 /* Init ACPI memory hotplug IO base address */ 1091 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1092 } 1093 1094 /* 1095 * The 64bit pci hole starts after "above 4G RAM" and 1096 * potentially the space reserved for memory hotplug. 1097 */ 1098 uint64_t pc_pci_hole64_start(void) 1099 { 1100 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1101 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1102 MachineState *ms = MACHINE(pcms); 1103 uint64_t hole64_start = 0; 1104 ram_addr_t size = 0; 1105 1106 if (pcms->cxl_devices_state.is_enabled) { 1107 hole64_start = pc_get_cxl_range_end(pcms); 1108 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1109 pc_get_device_memory_range(pcms, &hole64_start, &size); 1110 if (!pcmc->broken_reserved_end) { 1111 hole64_start += size; 1112 } 1113 } else { 1114 hole64_start = pc_above_4g_end(pcms); 1115 } 1116 1117 return ROUND_UP(hole64_start, 1 * GiB); 1118 } 1119 1120 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1121 { 1122 DeviceState *dev = NULL; 1123 1124 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1125 if (pci_bus) { 1126 PCIDevice *pcidev = pci_vga_init(pci_bus); 1127 dev = pcidev ? &pcidev->qdev : NULL; 1128 } else if (isa_bus) { 1129 ISADevice *isadev = isa_vga_init(isa_bus); 1130 dev = isadev ? DEVICE(isadev) : NULL; 1131 } 1132 rom_reset_order_override(); 1133 return dev; 1134 } 1135 1136 static const MemoryRegionOps ioport80_io_ops = { 1137 .write = ioport80_write, 1138 .read = ioport80_read, 1139 .endianness = DEVICE_NATIVE_ENDIAN, 1140 .impl = { 1141 .min_access_size = 1, 1142 .max_access_size = 1, 1143 }, 1144 }; 1145 1146 static const MemoryRegionOps ioportF0_io_ops = { 1147 .write = ioportF0_write, 1148 .read = ioportF0_read, 1149 .endianness = DEVICE_NATIVE_ENDIAN, 1150 .impl = { 1151 .min_access_size = 1, 1152 .max_access_size = 1, 1153 }, 1154 }; 1155 1156 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1157 bool create_i8042, bool no_vmport) 1158 { 1159 int i; 1160 DriveInfo *fd[MAX_FD]; 1161 qemu_irq *a20_line; 1162 ISADevice *fdc, *i8042, *port92, *vmmouse; 1163 1164 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1165 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1166 1167 for (i = 0; i < MAX_FD; i++) { 1168 fd[i] = drive_get(IF_FLOPPY, 0, i); 1169 create_fdctrl |= !!fd[i]; 1170 } 1171 if (create_fdctrl) { 1172 fdc = isa_new(TYPE_ISA_FDC); 1173 if (fdc) { 1174 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1175 isa_fdc_init_drives(fdc, fd); 1176 } 1177 } 1178 1179 if (!create_i8042) { 1180 return; 1181 } 1182 1183 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1184 if (!no_vmport) { 1185 isa_create_simple(isa_bus, TYPE_VMPORT); 1186 vmmouse = isa_try_new("vmmouse"); 1187 } else { 1188 vmmouse = NULL; 1189 } 1190 if (vmmouse) { 1191 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1192 &error_abort); 1193 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1194 } 1195 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1196 1197 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1198 i8042_setup_a20_line(i8042, a20_line[0]); 1199 qdev_connect_gpio_out_named(DEVICE(port92), 1200 PORT92_A20_LINE, 0, a20_line[1]); 1201 g_free(a20_line); 1202 } 1203 1204 void pc_basic_device_init(struct PCMachineState *pcms, 1205 ISABus *isa_bus, qemu_irq *gsi, 1206 ISADevice *rtc_state, 1207 bool create_fdctrl, 1208 uint32_t hpet_irqs) 1209 { 1210 int i; 1211 DeviceState *hpet = NULL; 1212 int pit_isa_irq = 0; 1213 qemu_irq pit_alt_irq = NULL; 1214 ISADevice *pit = NULL; 1215 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1216 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1217 X86MachineState *x86ms = X86_MACHINE(pcms); 1218 1219 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1220 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1221 1222 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1223 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1224 1225 /* 1226 * Check if an HPET shall be created. 1227 */ 1228 if (pcms->hpet_enabled) { 1229 qemu_irq rtc_irq; 1230 1231 hpet = qdev_try_new(TYPE_HPET); 1232 if (!hpet) { 1233 error_report("couldn't create HPET device"); 1234 exit(1); 1235 } 1236 /* 1237 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1238 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1239 * the property, use whatever mask they specified. 1240 */ 1241 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1242 HPET_INTCAP, NULL); 1243 if (!compat) { 1244 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1245 } 1246 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1247 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1248 1249 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1250 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1251 } 1252 pit_isa_irq = -1; 1253 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1254 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1255 1256 /* overwrite connection created by south bridge */ 1257 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1258 } 1259 1260 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1261 "date"); 1262 1263 #ifdef CONFIG_XEN_EMU 1264 if (xen_mode == XEN_EMULATE) { 1265 xen_overlay_create(); 1266 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1267 xen_gnttab_create(); 1268 xen_xenstore_create(); 1269 if (pcms->bus) { 1270 pci_create_simple(pcms->bus, -1, "xen-platform"); 1271 } 1272 xen_bus_init(); 1273 xen_be_init(); 1274 } 1275 #endif 1276 1277 qemu_register_boot_set(pc_boot_set, rtc_state); 1278 1279 if (!xen_enabled() && 1280 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1281 if (kvm_pit_in_kernel()) { 1282 pit = kvm_pit_init(isa_bus, 0x40); 1283 } else { 1284 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1285 } 1286 if (hpet) { 1287 /* connect PIT to output control line of the HPET */ 1288 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1289 } 1290 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1291 OBJECT(pit), &error_fatal); 1292 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1293 } 1294 1295 /* Super I/O */ 1296 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1297 pcms->vmport != ON_OFF_AUTO_ON); 1298 } 1299 1300 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1301 { 1302 MachineClass *mc = MACHINE_CLASS(pcmc); 1303 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1304 NICInfo *nd; 1305 1306 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1307 1308 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1309 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1310 } 1311 1312 /* Anything remaining should be a PCI NIC */ 1313 pci_init_nic_devices(pci_bus, mc->default_nic); 1314 1315 rom_reset_order_override(); 1316 } 1317 1318 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1319 { 1320 qemu_irq *i8259; 1321 1322 if (kvm_pic_in_kernel()) { 1323 i8259 = kvm_i8259_init(isa_bus); 1324 } else if (xen_enabled()) { 1325 i8259 = xen_interrupt_controller_init(); 1326 } else { 1327 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1328 } 1329 1330 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1331 i8259_irqs[i] = i8259[i]; 1332 } 1333 1334 g_free(i8259); 1335 } 1336 1337 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1338 Error **errp) 1339 { 1340 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1341 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1342 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1343 const MachineState *ms = MACHINE(hotplug_dev); 1344 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1345 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1346 Error *local_err = NULL; 1347 1348 /* 1349 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1350 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1351 * addition to cover this case. 1352 */ 1353 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1354 error_setg(errp, 1355 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1356 return; 1357 } 1358 1359 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1360 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1361 return; 1362 } 1363 1364 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1365 if (local_err) { 1366 error_propagate(errp, local_err); 1367 return; 1368 } 1369 1370 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1371 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1372 } 1373 1374 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1375 DeviceState *dev, Error **errp) 1376 { 1377 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1378 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1379 MachineState *ms = MACHINE(hotplug_dev); 1380 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1381 1382 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1383 1384 if (is_nvdimm) { 1385 nvdimm_plug(ms->nvdimms_state); 1386 } 1387 1388 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1389 } 1390 1391 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1392 DeviceState *dev, Error **errp) 1393 { 1394 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1395 1396 /* 1397 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1398 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1399 * addition to cover this case. 1400 */ 1401 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1402 error_setg(errp, 1403 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1404 return; 1405 } 1406 1407 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1408 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1409 return; 1410 } 1411 1412 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1413 errp); 1414 } 1415 1416 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1417 DeviceState *dev, Error **errp) 1418 { 1419 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1420 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1421 Error *local_err = NULL; 1422 1423 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1424 if (local_err) { 1425 goto out; 1426 } 1427 1428 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1429 qdev_unrealize(dev); 1430 out: 1431 error_propagate(errp, local_err); 1432 } 1433 1434 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1435 DeviceState *dev, Error **errp) 1436 { 1437 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1438 g_assert(!dev->hotplugged); 1439 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1440 errp); 1441 } 1442 1443 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1444 DeviceState *dev, Error **errp) 1445 { 1446 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1447 } 1448 1449 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1450 DeviceState *dev, Error **errp) 1451 { 1452 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1453 pc_memory_pre_plug(hotplug_dev, dev, errp); 1454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1455 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1457 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1458 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1459 /* Declare the APIC range as the reserved MSI region */ 1460 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1461 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1462 QList *reserved_regions = qlist_new(); 1463 1464 qlist_append_str(reserved_regions, resv_prop_str); 1465 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1466 1467 g_free(resv_prop_str); 1468 } 1469 1470 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1471 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1472 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1473 1474 if (pcms->iommu) { 1475 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1476 "for x86 yet."); 1477 return; 1478 } 1479 pcms->iommu = dev; 1480 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1481 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1482 } 1483 } 1484 1485 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1486 DeviceState *dev, Error **errp) 1487 { 1488 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1489 pc_memory_plug(hotplug_dev, dev, errp); 1490 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1491 x86_cpu_plug(hotplug_dev, dev, errp); 1492 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1493 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1494 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1495 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1496 } 1497 } 1498 1499 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1500 DeviceState *dev, Error **errp) 1501 { 1502 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1503 pc_memory_unplug_request(hotplug_dev, dev, errp); 1504 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1505 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1507 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1508 errp); 1509 } else { 1510 error_setg(errp, "acpi: device unplug request for not supported device" 1511 " type: %s", object_get_typename(OBJECT(dev))); 1512 } 1513 } 1514 1515 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1516 DeviceState *dev, Error **errp) 1517 { 1518 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1519 pc_memory_unplug(hotplug_dev, dev, errp); 1520 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1521 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1522 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1523 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1524 } else { 1525 error_setg(errp, "acpi: device unplug for not supported device" 1526 " type: %s", object_get_typename(OBJECT(dev))); 1527 } 1528 } 1529 1530 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1531 DeviceState *dev) 1532 { 1533 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1534 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1535 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1536 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1537 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1538 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1539 return HOTPLUG_HANDLER(machine); 1540 } 1541 1542 return NULL; 1543 } 1544 1545 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1546 void *opaque, Error **errp) 1547 { 1548 PCMachineState *pcms = PC_MACHINE(obj); 1549 OnOffAuto vmport = pcms->vmport; 1550 1551 visit_type_OnOffAuto(v, name, &vmport, errp); 1552 } 1553 1554 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1555 void *opaque, Error **errp) 1556 { 1557 PCMachineState *pcms = PC_MACHINE(obj); 1558 1559 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1560 } 1561 1562 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1563 { 1564 PCMachineState *pcms = PC_MACHINE(obj); 1565 1566 return pcms->smbus_enabled; 1567 } 1568 1569 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1570 { 1571 PCMachineState *pcms = PC_MACHINE(obj); 1572 1573 pcms->smbus_enabled = value; 1574 } 1575 1576 static bool pc_machine_get_sata(Object *obj, Error **errp) 1577 { 1578 PCMachineState *pcms = PC_MACHINE(obj); 1579 1580 return pcms->sata_enabled; 1581 } 1582 1583 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1584 { 1585 PCMachineState *pcms = PC_MACHINE(obj); 1586 1587 pcms->sata_enabled = value; 1588 } 1589 1590 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 1594 return pcms->hpet_enabled; 1595 } 1596 1597 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1598 { 1599 PCMachineState *pcms = PC_MACHINE(obj); 1600 1601 pcms->hpet_enabled = value; 1602 } 1603 1604 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1605 { 1606 PCMachineState *pcms = PC_MACHINE(obj); 1607 1608 return pcms->i8042_enabled; 1609 } 1610 1611 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1612 { 1613 PCMachineState *pcms = PC_MACHINE(obj); 1614 1615 pcms->i8042_enabled = value; 1616 } 1617 1618 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1619 { 1620 PCMachineState *pcms = PC_MACHINE(obj); 1621 1622 return pcms->default_bus_bypass_iommu; 1623 } 1624 1625 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1626 Error **errp) 1627 { 1628 PCMachineState *pcms = PC_MACHINE(obj); 1629 1630 pcms->default_bus_bypass_iommu = value; 1631 } 1632 1633 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1634 void *opaque, Error **errp) 1635 { 1636 PCMachineState *pcms = PC_MACHINE(obj); 1637 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1638 1639 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1640 } 1641 1642 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1643 void *opaque, Error **errp) 1644 { 1645 PCMachineState *pcms = PC_MACHINE(obj); 1646 1647 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1648 } 1649 1650 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1651 const char *name, void *opaque, 1652 Error **errp) 1653 { 1654 PCMachineState *pcms = PC_MACHINE(obj); 1655 uint64_t value = pcms->max_ram_below_4g; 1656 1657 visit_type_size(v, name, &value, errp); 1658 } 1659 1660 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1661 const char *name, void *opaque, 1662 Error **errp) 1663 { 1664 PCMachineState *pcms = PC_MACHINE(obj); 1665 uint64_t value; 1666 1667 if (!visit_type_size(v, name, &value, errp)) { 1668 return; 1669 } 1670 if (value > 4 * GiB) { 1671 error_setg(errp, 1672 "Machine option 'max-ram-below-4g=%"PRIu64 1673 "' expects size less than or equal to 4G", value); 1674 return; 1675 } 1676 1677 if (value < 1 * MiB) { 1678 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1679 "BIOS may not work with less than 1MiB", value); 1680 } 1681 1682 pcms->max_ram_below_4g = value; 1683 } 1684 1685 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1686 const char *name, void *opaque, 1687 Error **errp) 1688 { 1689 PCMachineState *pcms = PC_MACHINE(obj); 1690 uint64_t value = pcms->max_fw_size; 1691 1692 visit_type_size(v, name, &value, errp); 1693 } 1694 1695 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1696 const char *name, void *opaque, 1697 Error **errp) 1698 { 1699 PCMachineState *pcms = PC_MACHINE(obj); 1700 uint64_t value; 1701 1702 if (!visit_type_size(v, name, &value, errp)) { 1703 return; 1704 } 1705 1706 /* 1707 * We don't have a theoretically justifiable exact lower bound on the base 1708 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1709 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1710 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1711 * 16MiB in size. 1712 */ 1713 if (value > 16 * MiB) { 1714 error_setg(errp, 1715 "User specified max allowed firmware size %" PRIu64 " is " 1716 "greater than 16MiB. If combined firmware size exceeds " 1717 "16MiB the system may not boot, or experience intermittent" 1718 "stability issues.", 1719 value); 1720 return; 1721 } 1722 1723 pcms->max_fw_size = value; 1724 } 1725 1726 1727 static void pc_machine_initfn(Object *obj) 1728 { 1729 PCMachineState *pcms = PC_MACHINE(obj); 1730 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1731 1732 #ifdef CONFIG_VMPORT 1733 pcms->vmport = ON_OFF_AUTO_AUTO; 1734 #else 1735 pcms->vmport = ON_OFF_AUTO_OFF; 1736 #endif /* CONFIG_VMPORT */ 1737 pcms->max_ram_below_4g = 0; /* use default */ 1738 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1739 pcms->south_bridge = pcmc->default_south_bridge; 1740 1741 /* acpi build is enabled by default if machine supports it */ 1742 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1743 pcms->smbus_enabled = true; 1744 pcms->sata_enabled = true; 1745 pcms->i8042_enabled = true; 1746 pcms->max_fw_size = 8 * MiB; 1747 #ifdef CONFIG_HPET 1748 pcms->hpet_enabled = true; 1749 #endif 1750 pcms->default_bus_bypass_iommu = false; 1751 1752 pc_system_flash_create(pcms); 1753 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1754 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1755 OBJECT(pcms->pcspk), "audiodev"); 1756 cxl_machine_init(obj, &pcms->cxl_devices_state); 1757 } 1758 1759 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) 1760 { 1761 return 0; 1762 } 1763 1764 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1765 { 1766 CPUState *cs; 1767 X86CPU *cpu; 1768 1769 qemu_devices_reset(reason); 1770 1771 /* Reset APIC after devices have been reset to cancel 1772 * any changes that qemu_devices_reset() might have done. 1773 */ 1774 CPU_FOREACH(cs) { 1775 cpu = X86_CPU(cs); 1776 1777 x86_cpu_after_reset(cpu); 1778 } 1779 } 1780 1781 static void pc_machine_wakeup(MachineState *machine) 1782 { 1783 cpu_synchronize_all_states(); 1784 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1785 cpu_synchronize_all_post_reset(); 1786 } 1787 1788 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1789 { 1790 X86IOMMUState *iommu = x86_iommu_get_default(); 1791 IntelIOMMUState *intel_iommu; 1792 1793 if (iommu && 1794 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1795 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1796 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1797 if (!intel_iommu->caching_mode) { 1798 error_setg(errp, "Device assignment is not allowed without " 1799 "enabling caching-mode=on for Intel IOMMU."); 1800 return false; 1801 } 1802 } 1803 1804 return true; 1805 } 1806 1807 static void pc_machine_class_init(ObjectClass *oc, void *data) 1808 { 1809 MachineClass *mc = MACHINE_CLASS(oc); 1810 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1811 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1812 1813 pcmc->pci_enabled = true; 1814 pcmc->has_acpi_build = true; 1815 pcmc->rsdp_in_ram = true; 1816 pcmc->smbios_defaults = true; 1817 pcmc->smbios_uuid_encoded = true; 1818 pcmc->gigabyte_align = true; 1819 pcmc->has_reserved_memory = true; 1820 pcmc->kvmclock_enabled = true; 1821 pcmc->enforce_aligned_dimm = true; 1822 pcmc->enforce_amd_1tb_hole = true; 1823 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1824 * to be used at the moment, 32K should be enough for a while. */ 1825 pcmc->acpi_data_size = 0x20000 + 0x8000; 1826 pcmc->pvh_enabled = true; 1827 pcmc->kvmclock_create_always = true; 1828 pcmc->resizable_acpi_blob = true; 1829 assert(!mc->get_hotplug_handler); 1830 mc->get_hotplug_handler = pc_get_hotplug_handler; 1831 mc->hotplug_allowed = pc_hotplug_allowed; 1832 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1833 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1834 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1835 mc->auto_enable_numa_with_memhp = true; 1836 mc->auto_enable_numa_with_memdev = true; 1837 mc->has_hotpluggable_cpus = true; 1838 mc->default_boot_order = "cad"; 1839 mc->block_default_type = IF_IDE; 1840 mc->max_cpus = 255; 1841 mc->reset = pc_machine_reset; 1842 mc->wakeup = pc_machine_wakeup; 1843 hc->pre_plug = pc_machine_device_pre_plug_cb; 1844 hc->plug = pc_machine_device_plug_cb; 1845 hc->unplug_request = pc_machine_device_unplug_request_cb; 1846 hc->unplug = pc_machine_device_unplug_cb; 1847 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1848 mc->nvdimm_supported = true; 1849 mc->smp_props.dies_supported = true; 1850 mc->default_ram_id = "pc.ram"; 1851 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 1852 1853 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1854 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1855 NULL, NULL); 1856 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1857 "Maximum ram below the 4G boundary (32bit boundary)"); 1858 1859 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1860 pc_machine_get_vmport, pc_machine_set_vmport, 1861 NULL, NULL); 1862 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1863 "Enable vmport (pc & q35)"); 1864 1865 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1866 pc_machine_get_smbus, pc_machine_set_smbus); 1867 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1868 "Enable/disable system management bus"); 1869 1870 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1871 pc_machine_get_sata, pc_machine_set_sata); 1872 object_class_property_set_description(oc, PC_MACHINE_SATA, 1873 "Enable/disable Serial ATA bus"); 1874 1875 object_class_property_add_bool(oc, "hpet", 1876 pc_machine_get_hpet, pc_machine_set_hpet); 1877 object_class_property_set_description(oc, "hpet", 1878 "Enable/disable high precision event timer emulation"); 1879 1880 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1881 pc_machine_get_i8042, pc_machine_set_i8042); 1882 1883 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1884 pc_machine_get_default_bus_bypass_iommu, 1885 pc_machine_set_default_bus_bypass_iommu); 1886 1887 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1888 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1889 NULL, NULL); 1890 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1891 "Maximum combined firmware size"); 1892 1893 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1894 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1895 NULL, NULL); 1896 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1897 "SMBIOS Entry Point type [32, 64]"); 1898 } 1899 1900 static const TypeInfo pc_machine_info = { 1901 .name = TYPE_PC_MACHINE, 1902 .parent = TYPE_X86_MACHINE, 1903 .abstract = true, 1904 .instance_size = sizeof(PCMachineState), 1905 .instance_init = pc_machine_initfn, 1906 .class_size = sizeof(PCMachineClass), 1907 .class_init = pc_machine_class_init, 1908 .interfaces = (InterfaceInfo[]) { 1909 { TYPE_HOTPLUG_HANDLER }, 1910 { } 1911 }, 1912 }; 1913 1914 static void pc_machine_register_types(void) 1915 { 1916 type_register_static(&pc_machine_info); 1917 } 1918 1919 type_init(pc_machine_register_types) 1920