1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/i386/pc.h" 27 #include "hw/char/serial.h" 28 #include "hw/i386/apic.h" 29 #include "hw/i386/topology.h" 30 #include "sysemu/cpus.h" 31 #include "hw/block/fdc.h" 32 #include "hw/ide.h" 33 #include "hw/pci/pci.h" 34 #include "hw/pci/pci_bus.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/smbios/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "qemu/error-report.h" 61 #include "hw/acpi/acpi.h" 62 #include "hw/acpi/cpu_hotplug.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 #include "qom/cpu.h" 70 71 /* debug PC/ISA interrupts */ 72 //#define DEBUG_IRQ 73 74 #ifdef DEBUG_IRQ 75 #define DPRINTF(fmt, ...) \ 76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 77 #else 78 #define DPRINTF(fmt, ...) 79 #endif 80 81 #define BIOS_CFG_IOPORT 0x510 82 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 83 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 84 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 85 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 86 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 87 88 #define E820_NR_ENTRIES 16 89 90 struct e820_entry { 91 uint64_t address; 92 uint64_t length; 93 uint32_t type; 94 } QEMU_PACKED __attribute((__aligned__(4))); 95 96 struct e820_table { 97 uint32_t count; 98 struct e820_entry entry[E820_NR_ENTRIES]; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 static struct e820_table e820_reserve; 102 static struct e820_entry *e820_table; 103 static unsigned e820_entries; 104 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 105 106 void gsi_handler(void *opaque, int n, int level) 107 { 108 GSIState *s = opaque; 109 110 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 111 if (n < ISA_NUM_IRQS) { 112 qemu_set_irq(s->i8259_irq[n], level); 113 } 114 qemu_set_irq(s->ioapic_irq[n], level); 115 } 116 117 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 118 unsigned size) 119 { 120 } 121 122 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 123 { 124 return 0xffffffffffffffffULL; 125 } 126 127 /* MSDOS compatibility mode FPU exception support */ 128 static qemu_irq ferr_irq; 129 130 void pc_register_ferr_irq(qemu_irq irq) 131 { 132 ferr_irq = irq; 133 } 134 135 /* XXX: add IGNNE support */ 136 void cpu_set_ferr(CPUX86State *s) 137 { 138 qemu_irq_raise(ferr_irq); 139 } 140 141 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 142 unsigned size) 143 { 144 qemu_irq_lower(ferr_irq); 145 } 146 147 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 148 { 149 return 0xffffffffffffffffULL; 150 } 151 152 /* TSC handling */ 153 uint64_t cpu_get_tsc(CPUX86State *env) 154 { 155 return cpu_get_ticks(); 156 } 157 158 /* IRQ handling */ 159 int cpu_get_pic_interrupt(CPUX86State *env) 160 { 161 X86CPU *cpu = x86_env_get_cpu(env); 162 int intno; 163 164 intno = apic_get_interrupt(cpu->apic_state); 165 if (intno >= 0) { 166 return intno; 167 } 168 /* read the irq from the PIC */ 169 if (!apic_accept_pic_intr(cpu->apic_state)) { 170 return -1; 171 } 172 173 intno = pic_read_irq(isa_pic); 174 return intno; 175 } 176 177 static void pic_irq_request(void *opaque, int irq, int level) 178 { 179 CPUState *cs = first_cpu; 180 X86CPU *cpu = X86_CPU(cs); 181 182 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 183 if (cpu->apic_state) { 184 CPU_FOREACH(cs) { 185 cpu = X86_CPU(cs); 186 if (apic_accept_pic_intr(cpu->apic_state)) { 187 apic_deliver_pic_intr(cpu->apic_state, level); 188 } 189 } 190 } else { 191 if (level) { 192 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 193 } else { 194 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 195 } 196 } 197 } 198 199 /* PC cmos mappings */ 200 201 #define REG_EQUIPMENT_BYTE 0x14 202 203 static int cmos_get_fd_drive_type(FloppyDriveType fd0) 204 { 205 int val; 206 207 switch (fd0) { 208 case FLOPPY_DRIVE_TYPE_144: 209 /* 1.44 Mb 3"5 drive */ 210 val = 4; 211 break; 212 case FLOPPY_DRIVE_TYPE_288: 213 /* 2.88 Mb 3"5 drive */ 214 val = 5; 215 break; 216 case FLOPPY_DRIVE_TYPE_120: 217 /* 1.2 Mb 5"5 drive */ 218 val = 2; 219 break; 220 case FLOPPY_DRIVE_TYPE_NONE: 221 default: 222 val = 0; 223 break; 224 } 225 return val; 226 } 227 228 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 229 int16_t cylinders, int8_t heads, int8_t sectors) 230 { 231 rtc_set_memory(s, type_ofs, 47); 232 rtc_set_memory(s, info_ofs, cylinders); 233 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 234 rtc_set_memory(s, info_ofs + 2, heads); 235 rtc_set_memory(s, info_ofs + 3, 0xff); 236 rtc_set_memory(s, info_ofs + 4, 0xff); 237 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 238 rtc_set_memory(s, info_ofs + 6, cylinders); 239 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 240 rtc_set_memory(s, info_ofs + 8, sectors); 241 } 242 243 /* convert boot_device letter to something recognizable by the bios */ 244 static int boot_device2nibble(char boot_device) 245 { 246 switch(boot_device) { 247 case 'a': 248 case 'b': 249 return 0x01; /* floppy boot */ 250 case 'c': 251 return 0x02; /* hard drive boot */ 252 case 'd': 253 return 0x03; /* CD-ROM boot */ 254 case 'n': 255 return 0x04; /* Network boot */ 256 } 257 return 0; 258 } 259 260 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 261 { 262 #define PC_MAX_BOOT_DEVICES 3 263 int nbds, bds[3] = { 0, }; 264 int i; 265 266 nbds = strlen(boot_device); 267 if (nbds > PC_MAX_BOOT_DEVICES) { 268 error_setg(errp, "Too many boot devices for PC"); 269 return; 270 } 271 for (i = 0; i < nbds; i++) { 272 bds[i] = boot_device2nibble(boot_device[i]); 273 if (bds[i] == 0) { 274 error_setg(errp, "Invalid boot device for PC: '%c'", 275 boot_device[i]); 276 return; 277 } 278 } 279 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 280 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 281 } 282 283 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 284 { 285 set_boot_dev(opaque, boot_device, errp); 286 } 287 288 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 289 { 290 int val, nb, i; 291 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 292 FLOPPY_DRIVE_TYPE_NONE }; 293 294 /* floppy type */ 295 if (floppy) { 296 for (i = 0; i < 2; i++) { 297 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 298 } 299 } 300 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 301 cmos_get_fd_drive_type(fd_type[1]); 302 rtc_set_memory(rtc_state, 0x10, val); 303 304 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 305 nb = 0; 306 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 307 nb++; 308 } 309 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 310 nb++; 311 } 312 switch (nb) { 313 case 0: 314 break; 315 case 1: 316 val |= 0x01; /* 1 drive, ready for boot */ 317 break; 318 case 2: 319 val |= 0x41; /* 2 drives, ready for boot */ 320 break; 321 } 322 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 323 } 324 325 typedef struct pc_cmos_init_late_arg { 326 ISADevice *rtc_state; 327 BusState *idebus[2]; 328 } pc_cmos_init_late_arg; 329 330 typedef struct check_fdc_state { 331 ISADevice *floppy; 332 bool multiple; 333 } CheckFdcState; 334 335 static int check_fdc(Object *obj, void *opaque) 336 { 337 CheckFdcState *state = opaque; 338 Object *fdc; 339 uint32_t iobase; 340 Error *local_err = NULL; 341 342 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 343 if (!fdc) { 344 return 0; 345 } 346 347 iobase = object_property_get_int(obj, "iobase", &local_err); 348 if (local_err || iobase != 0x3f0) { 349 error_free(local_err); 350 return 0; 351 } 352 353 if (state->floppy) { 354 state->multiple = true; 355 } else { 356 state->floppy = ISA_DEVICE(obj); 357 } 358 return 0; 359 } 360 361 static const char * const fdc_container_path[] = { 362 "/unattached", "/peripheral", "/peripheral-anon" 363 }; 364 365 /* 366 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 367 * and ACPI objects. 368 */ 369 ISADevice *pc_find_fdc0(void) 370 { 371 int i; 372 Object *container; 373 CheckFdcState state = { 0 }; 374 375 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 376 container = container_get(qdev_get_machine(), fdc_container_path[i]); 377 object_child_foreach(container, check_fdc, &state); 378 } 379 380 if (state.multiple) { 381 error_report("warning: multiple floppy disk controllers with " 382 "iobase=0x3f0 have been found"); 383 error_printf("the one being picked for CMOS setup might not reflect " 384 "your intent"); 385 } 386 387 return state.floppy; 388 } 389 390 static void pc_cmos_init_late(void *opaque) 391 { 392 pc_cmos_init_late_arg *arg = opaque; 393 ISADevice *s = arg->rtc_state; 394 int16_t cylinders; 395 int8_t heads, sectors; 396 int val; 397 int i, trans; 398 399 val = 0; 400 if (ide_get_geometry(arg->idebus[0], 0, 401 &cylinders, &heads, §ors) >= 0) { 402 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 403 val |= 0xf0; 404 } 405 if (ide_get_geometry(arg->idebus[0], 1, 406 &cylinders, &heads, §ors) >= 0) { 407 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 408 val |= 0x0f; 409 } 410 rtc_set_memory(s, 0x12, val); 411 412 val = 0; 413 for (i = 0; i < 4; i++) { 414 /* NOTE: ide_get_geometry() returns the physical 415 geometry. It is always such that: 1 <= sects <= 63, 1 416 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 417 geometry can be different if a translation is done. */ 418 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 419 &cylinders, &heads, §ors) >= 0) { 420 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 421 assert((trans & ~3) == 0); 422 val |= trans << (i * 2); 423 } 424 } 425 rtc_set_memory(s, 0x39, val); 426 427 pc_cmos_init_floppy(s, pc_find_fdc0()); 428 429 qemu_unregister_reset(pc_cmos_init_late, opaque); 430 } 431 432 void pc_cmos_init(PCMachineState *pcms, 433 BusState *idebus0, BusState *idebus1, 434 ISADevice *s) 435 { 436 int val; 437 static pc_cmos_init_late_arg arg; 438 439 /* various important CMOS locations needed by PC/Bochs bios */ 440 441 /* memory size */ 442 /* base memory (first MiB) */ 443 val = MIN(pcms->below_4g_mem_size / 1024, 640); 444 rtc_set_memory(s, 0x15, val); 445 rtc_set_memory(s, 0x16, val >> 8); 446 /* extended memory (next 64MiB) */ 447 if (pcms->below_4g_mem_size > 1024 * 1024) { 448 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 449 } else { 450 val = 0; 451 } 452 if (val > 65535) 453 val = 65535; 454 rtc_set_memory(s, 0x17, val); 455 rtc_set_memory(s, 0x18, val >> 8); 456 rtc_set_memory(s, 0x30, val); 457 rtc_set_memory(s, 0x31, val >> 8); 458 /* memory between 16MiB and 4GiB */ 459 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 460 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 461 } else { 462 val = 0; 463 } 464 if (val > 65535) 465 val = 65535; 466 rtc_set_memory(s, 0x34, val); 467 rtc_set_memory(s, 0x35, val >> 8); 468 /* memory above 4GiB */ 469 val = pcms->above_4g_mem_size / 65536; 470 rtc_set_memory(s, 0x5b, val); 471 rtc_set_memory(s, 0x5c, val >> 8); 472 rtc_set_memory(s, 0x5d, val >> 16); 473 474 /* set the number of CPU */ 475 rtc_set_memory(s, 0x5f, smp_cpus - 1); 476 477 object_property_add_link(OBJECT(pcms), "rtc_state", 478 TYPE_ISA_DEVICE, 479 (Object **)&pcms->rtc, 480 object_property_allow_set_link, 481 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 482 object_property_set_link(OBJECT(pcms), OBJECT(s), 483 "rtc_state", &error_abort); 484 485 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 486 487 val = 0; 488 val |= 0x02; /* FPU is there */ 489 val |= 0x04; /* PS/2 mouse installed */ 490 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 491 492 /* hard drives and FDC */ 493 arg.rtc_state = s; 494 arg.idebus[0] = idebus0; 495 arg.idebus[1] = idebus1; 496 qemu_register_reset(pc_cmos_init_late, &arg); 497 } 498 499 #define TYPE_PORT92 "port92" 500 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 501 502 /* port 92 stuff: could be split off */ 503 typedef struct Port92State { 504 ISADevice parent_obj; 505 506 MemoryRegion io; 507 uint8_t outport; 508 qemu_irq *a20_out; 509 } Port92State; 510 511 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 512 unsigned size) 513 { 514 Port92State *s = opaque; 515 int oldval = s->outport; 516 517 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 518 s->outport = val; 519 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 520 if ((val & 1) && !(oldval & 1)) { 521 qemu_system_reset_request(); 522 } 523 } 524 525 static uint64_t port92_read(void *opaque, hwaddr addr, 526 unsigned size) 527 { 528 Port92State *s = opaque; 529 uint32_t ret; 530 531 ret = s->outport; 532 DPRINTF("port92: read 0x%02x\n", ret); 533 return ret; 534 } 535 536 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 537 { 538 Port92State *s = PORT92(dev); 539 540 s->a20_out = a20_out; 541 } 542 543 static const VMStateDescription vmstate_port92_isa = { 544 .name = "port92", 545 .version_id = 1, 546 .minimum_version_id = 1, 547 .fields = (VMStateField[]) { 548 VMSTATE_UINT8(outport, Port92State), 549 VMSTATE_END_OF_LIST() 550 } 551 }; 552 553 static void port92_reset(DeviceState *d) 554 { 555 Port92State *s = PORT92(d); 556 557 s->outport &= ~1; 558 } 559 560 static const MemoryRegionOps port92_ops = { 561 .read = port92_read, 562 .write = port92_write, 563 .impl = { 564 .min_access_size = 1, 565 .max_access_size = 1, 566 }, 567 .endianness = DEVICE_LITTLE_ENDIAN, 568 }; 569 570 static void port92_initfn(Object *obj) 571 { 572 Port92State *s = PORT92(obj); 573 574 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 575 576 s->outport = 0; 577 } 578 579 static void port92_realizefn(DeviceState *dev, Error **errp) 580 { 581 ISADevice *isadev = ISA_DEVICE(dev); 582 Port92State *s = PORT92(dev); 583 584 isa_register_ioport(isadev, &s->io, 0x92); 585 } 586 587 static void port92_class_initfn(ObjectClass *klass, void *data) 588 { 589 DeviceClass *dc = DEVICE_CLASS(klass); 590 591 dc->realize = port92_realizefn; 592 dc->reset = port92_reset; 593 dc->vmsd = &vmstate_port92_isa; 594 /* 595 * Reason: unlike ordinary ISA devices, this one needs additional 596 * wiring: its A20 output line needs to be wired up by 597 * port92_init(). 598 */ 599 dc->cannot_instantiate_with_device_add_yet = true; 600 } 601 602 static const TypeInfo port92_info = { 603 .name = TYPE_PORT92, 604 .parent = TYPE_ISA_DEVICE, 605 .instance_size = sizeof(Port92State), 606 .instance_init = port92_initfn, 607 .class_init = port92_class_initfn, 608 }; 609 610 static void port92_register_types(void) 611 { 612 type_register_static(&port92_info); 613 } 614 615 type_init(port92_register_types) 616 617 static void handle_a20_line_change(void *opaque, int irq, int level) 618 { 619 X86CPU *cpu = opaque; 620 621 /* XXX: send to all CPUs ? */ 622 /* XXX: add logic to handle multiple A20 line sources */ 623 x86_cpu_set_a20(cpu, level); 624 } 625 626 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 627 { 628 int index = le32_to_cpu(e820_reserve.count); 629 struct e820_entry *entry; 630 631 if (type != E820_RAM) { 632 /* old FW_CFG_E820_TABLE entry -- reservations only */ 633 if (index >= E820_NR_ENTRIES) { 634 return -EBUSY; 635 } 636 entry = &e820_reserve.entry[index++]; 637 638 entry->address = cpu_to_le64(address); 639 entry->length = cpu_to_le64(length); 640 entry->type = cpu_to_le32(type); 641 642 e820_reserve.count = cpu_to_le32(index); 643 } 644 645 /* new "etc/e820" file -- include ram too */ 646 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 647 e820_table[e820_entries].address = cpu_to_le64(address); 648 e820_table[e820_entries].length = cpu_to_le64(length); 649 e820_table[e820_entries].type = cpu_to_le32(type); 650 e820_entries++; 651 652 return e820_entries; 653 } 654 655 int e820_get_num_entries(void) 656 { 657 return e820_entries; 658 } 659 660 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 661 { 662 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 663 *address = le64_to_cpu(e820_table[idx].address); 664 *length = le64_to_cpu(e820_table[idx].length); 665 return true; 666 } 667 return false; 668 } 669 670 /* Enables contiguous-apic-ID mode, for compatibility */ 671 static bool compat_apic_id_mode; 672 673 void enable_compat_apic_id_mode(void) 674 { 675 compat_apic_id_mode = true; 676 } 677 678 /* Calculates initial APIC ID for a specific CPU index 679 * 680 * Currently we need to be able to calculate the APIC ID from the CPU index 681 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 682 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 683 * all CPUs up to max_cpus. 684 */ 685 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 686 { 687 uint32_t correct_id; 688 static bool warned; 689 690 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 691 if (compat_apic_id_mode) { 692 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 693 error_report("APIC IDs set in compatibility mode, " 694 "CPU topology won't match the configuration"); 695 warned = true; 696 } 697 return cpu_index; 698 } else { 699 return correct_id; 700 } 701 } 702 703 /* Calculates the limit to CPU APIC ID values 704 * 705 * This function returns the limit for the APIC ID value, so that all 706 * CPU APIC IDs are < pc_apic_id_limit(). 707 * 708 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 709 */ 710 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 711 { 712 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 713 } 714 715 static void pc_build_smbios(FWCfgState *fw_cfg) 716 { 717 uint8_t *smbios_tables, *smbios_anchor; 718 size_t smbios_tables_len, smbios_anchor_len; 719 struct smbios_phys_mem_area *mem_array; 720 unsigned i, array_count; 721 722 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 723 if (smbios_tables) { 724 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 725 smbios_tables, smbios_tables_len); 726 } 727 728 /* build the array of physical mem area from e820 table */ 729 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 730 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 731 uint64_t addr, len; 732 733 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 734 mem_array[array_count].address = addr; 735 mem_array[array_count].length = len; 736 array_count++; 737 } 738 } 739 smbios_get_tables(mem_array, array_count, 740 &smbios_tables, &smbios_tables_len, 741 &smbios_anchor, &smbios_anchor_len); 742 g_free(mem_array); 743 744 if (smbios_anchor) { 745 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 746 smbios_tables, smbios_tables_len); 747 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 748 smbios_anchor, smbios_anchor_len); 749 } 750 } 751 752 static FWCfgState *bochs_bios_init(AddressSpace *as) 753 { 754 FWCfgState *fw_cfg; 755 uint64_t *numa_fw_cfg; 756 int i, j; 757 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 758 759 fw_cfg = fw_cfg_init_io_dma(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 4, as); 760 761 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 762 * 763 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 764 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 765 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 766 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 767 * may see". 768 * 769 * So, this means we must not use max_cpus, here, but the maximum possible 770 * APIC ID value, plus one. 771 * 772 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 773 * the APIC ID, not the "CPU index" 774 */ 775 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 776 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 777 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 778 acpi_tables, acpi_tables_len); 779 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 780 781 pc_build_smbios(fw_cfg); 782 783 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 784 &e820_reserve, sizeof(e820_reserve)); 785 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 786 sizeof(struct e820_entry) * e820_entries); 787 788 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 789 /* allocate memory for the NUMA channel: one (64bit) word for the number 790 * of nodes, one word for each VCPU->node and one word for each node to 791 * hold the amount of memory. 792 */ 793 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 794 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 795 for (i = 0; i < max_cpus; i++) { 796 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 797 assert(apic_id < apic_id_limit); 798 for (j = 0; j < nb_numa_nodes; j++) { 799 if (test_bit(i, numa_info[j].node_cpu)) { 800 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 801 break; 802 } 803 } 804 } 805 for (i = 0; i < nb_numa_nodes; i++) { 806 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 807 } 808 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 809 (1 + apic_id_limit + nb_numa_nodes) * 810 sizeof(*numa_fw_cfg)); 811 812 return fw_cfg; 813 } 814 815 static long get_file_size(FILE *f) 816 { 817 long where, size; 818 819 /* XXX: on Unix systems, using fstat() probably makes more sense */ 820 821 where = ftell(f); 822 fseek(f, 0, SEEK_END); 823 size = ftell(f); 824 fseek(f, where, SEEK_SET); 825 826 return size; 827 } 828 829 static void load_linux(PCMachineState *pcms, 830 FWCfgState *fw_cfg) 831 { 832 uint16_t protocol; 833 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 834 uint32_t initrd_max; 835 uint8_t header[8192], *setup, *kernel, *initrd_data; 836 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 837 FILE *f; 838 char *vmode; 839 MachineState *machine = MACHINE(pcms); 840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 841 const char *kernel_filename = machine->kernel_filename; 842 const char *initrd_filename = machine->initrd_filename; 843 const char *kernel_cmdline = machine->kernel_cmdline; 844 845 /* Align to 16 bytes as a paranoia measure */ 846 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 847 848 /* load the kernel header */ 849 f = fopen(kernel_filename, "rb"); 850 if (!f || !(kernel_size = get_file_size(f)) || 851 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 852 MIN(ARRAY_SIZE(header), kernel_size)) { 853 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 854 kernel_filename, strerror(errno)); 855 exit(1); 856 } 857 858 /* kernel protocol version */ 859 #if 0 860 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 861 #endif 862 if (ldl_p(header+0x202) == 0x53726448) { 863 protocol = lduw_p(header+0x206); 864 } else { 865 /* This looks like a multiboot kernel. If it is, let's stop 866 treating it like a Linux kernel. */ 867 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 868 kernel_cmdline, kernel_size, header)) { 869 return; 870 } 871 protocol = 0; 872 } 873 874 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 875 /* Low kernel */ 876 real_addr = 0x90000; 877 cmdline_addr = 0x9a000 - cmdline_size; 878 prot_addr = 0x10000; 879 } else if (protocol < 0x202) { 880 /* High but ancient kernel */ 881 real_addr = 0x90000; 882 cmdline_addr = 0x9a000 - cmdline_size; 883 prot_addr = 0x100000; 884 } else { 885 /* High and recent kernel */ 886 real_addr = 0x10000; 887 cmdline_addr = 0x20000; 888 prot_addr = 0x100000; 889 } 890 891 #if 0 892 fprintf(stderr, 893 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 894 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 895 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 896 real_addr, 897 cmdline_addr, 898 prot_addr); 899 #endif 900 901 /* highest address for loading the initrd */ 902 if (protocol >= 0x203) { 903 initrd_max = ldl_p(header+0x22c); 904 } else { 905 initrd_max = 0x37ffffff; 906 } 907 908 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 909 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 910 } 911 912 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 913 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 914 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 915 916 if (protocol >= 0x202) { 917 stl_p(header+0x228, cmdline_addr); 918 } else { 919 stw_p(header+0x20, 0xA33F); 920 stw_p(header+0x22, cmdline_addr-real_addr); 921 } 922 923 /* handle vga= parameter */ 924 vmode = strstr(kernel_cmdline, "vga="); 925 if (vmode) { 926 unsigned int video_mode; 927 /* skip "vga=" */ 928 vmode += 4; 929 if (!strncmp(vmode, "normal", 6)) { 930 video_mode = 0xffff; 931 } else if (!strncmp(vmode, "ext", 3)) { 932 video_mode = 0xfffe; 933 } else if (!strncmp(vmode, "ask", 3)) { 934 video_mode = 0xfffd; 935 } else { 936 video_mode = strtol(vmode, NULL, 0); 937 } 938 stw_p(header+0x1fa, video_mode); 939 } 940 941 /* loader type */ 942 /* High nybble = B reserved for QEMU; low nybble is revision number. 943 If this code is substantially changed, you may want to consider 944 incrementing the revision. */ 945 if (protocol >= 0x200) { 946 header[0x210] = 0xB0; 947 } 948 /* heap */ 949 if (protocol >= 0x201) { 950 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 951 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 952 } 953 954 /* load initrd */ 955 if (initrd_filename) { 956 if (protocol < 0x200) { 957 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 958 exit(1); 959 } 960 961 initrd_size = get_image_size(initrd_filename); 962 if (initrd_size < 0) { 963 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 964 initrd_filename, strerror(errno)); 965 exit(1); 966 } 967 968 initrd_addr = (initrd_max-initrd_size) & ~4095; 969 970 initrd_data = g_malloc(initrd_size); 971 load_image(initrd_filename, initrd_data); 972 973 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 974 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 975 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 976 977 stl_p(header+0x218, initrd_addr); 978 stl_p(header+0x21c, initrd_size); 979 } 980 981 /* load kernel and setup */ 982 setup_size = header[0x1f1]; 983 if (setup_size == 0) { 984 setup_size = 4; 985 } 986 setup_size = (setup_size+1)*512; 987 if (setup_size > kernel_size) { 988 fprintf(stderr, "qemu: invalid kernel header\n"); 989 exit(1); 990 } 991 kernel_size -= setup_size; 992 993 setup = g_malloc(setup_size); 994 kernel = g_malloc(kernel_size); 995 fseek(f, 0, SEEK_SET); 996 if (fread(setup, 1, setup_size, f) != setup_size) { 997 fprintf(stderr, "fread() failed\n"); 998 exit(1); 999 } 1000 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1001 fprintf(stderr, "fread() failed\n"); 1002 exit(1); 1003 } 1004 fclose(f); 1005 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1006 1007 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1008 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1009 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1010 1011 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1012 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1013 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1014 1015 option_rom[nb_option_roms].name = "linuxboot.bin"; 1016 option_rom[nb_option_roms].bootindex = 0; 1017 nb_option_roms++; 1018 } 1019 1020 #define NE2000_NB_MAX 6 1021 1022 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1023 0x280, 0x380 }; 1024 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1025 1026 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1027 { 1028 static int nb_ne2k = 0; 1029 1030 if (nb_ne2k == NE2000_NB_MAX) 1031 return; 1032 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1033 ne2000_irq[nb_ne2k], nd); 1034 nb_ne2k++; 1035 } 1036 1037 DeviceState *cpu_get_current_apic(void) 1038 { 1039 if (current_cpu) { 1040 X86CPU *cpu = X86_CPU(current_cpu); 1041 return cpu->apic_state; 1042 } else { 1043 return NULL; 1044 } 1045 } 1046 1047 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1048 { 1049 X86CPU *cpu = opaque; 1050 1051 if (level) { 1052 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1053 } 1054 } 1055 1056 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1057 Error **errp) 1058 { 1059 X86CPU *cpu = NULL; 1060 Error *local_err = NULL; 1061 1062 cpu = cpu_x86_create(cpu_model, &local_err); 1063 if (local_err != NULL) { 1064 goto out; 1065 } 1066 1067 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1068 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1069 1070 out: 1071 if (local_err) { 1072 error_propagate(errp, local_err); 1073 object_unref(OBJECT(cpu)); 1074 cpu = NULL; 1075 } 1076 return cpu; 1077 } 1078 1079 void pc_hot_add_cpu(const int64_t id, Error **errp) 1080 { 1081 X86CPU *cpu; 1082 MachineState *machine = MACHINE(qdev_get_machine()); 1083 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1084 Error *local_err = NULL; 1085 1086 if (id < 0) { 1087 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1088 return; 1089 } 1090 1091 if (cpu_exists(apic_id)) { 1092 error_setg(errp, "Unable to add CPU: %" PRIi64 1093 ", it already exists", id); 1094 return; 1095 } 1096 1097 if (id >= max_cpus) { 1098 error_setg(errp, "Unable to add CPU: %" PRIi64 1099 ", max allowed: %d", id, max_cpus - 1); 1100 return; 1101 } 1102 1103 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1104 error_setg(errp, "Unable to add CPU: %" PRIi64 1105 ", resulting APIC ID (%" PRIi64 ") is too large", 1106 id, apic_id); 1107 return; 1108 } 1109 1110 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1111 if (local_err) { 1112 error_propagate(errp, local_err); 1113 return; 1114 } 1115 object_unref(OBJECT(cpu)); 1116 } 1117 1118 void pc_cpus_init(PCMachineState *pcms) 1119 { 1120 int i; 1121 X86CPU *cpu = NULL; 1122 MachineState *machine = MACHINE(pcms); 1123 unsigned long apic_id_limit; 1124 1125 /* init CPUs */ 1126 if (machine->cpu_model == NULL) { 1127 #ifdef TARGET_X86_64 1128 machine->cpu_model = "qemu64"; 1129 #else 1130 machine->cpu_model = "qemu32"; 1131 #endif 1132 } 1133 1134 apic_id_limit = pc_apic_id_limit(max_cpus); 1135 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1136 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1137 apic_id_limit - 1); 1138 exit(1); 1139 } 1140 1141 for (i = 0; i < smp_cpus; i++) { 1142 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1143 &error_fatal); 1144 object_unref(OBJECT(cpu)); 1145 } 1146 1147 /* tell smbios about cpuid version and features */ 1148 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1149 } 1150 1151 /* pci-info ROM file. Little endian format */ 1152 typedef struct PcRomPciInfo { 1153 uint64_t w32_min; 1154 uint64_t w32_max; 1155 uint64_t w64_min; 1156 uint64_t w64_max; 1157 } PcRomPciInfo; 1158 1159 typedef struct PcGuestInfoState { 1160 PcGuestInfo info; 1161 Notifier machine_done; 1162 } PcGuestInfoState; 1163 1164 static 1165 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1166 { 1167 PcGuestInfoState *guest_info_state = container_of(notifier, 1168 PcGuestInfoState, 1169 machine_done); 1170 PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; 1171 1172 if (bus) { 1173 int extra_hosts = 0; 1174 1175 QLIST_FOREACH(bus, &bus->child, sibling) { 1176 /* look for expander root buses */ 1177 if (pci_bus_is_root(bus)) { 1178 extra_hosts++; 1179 } 1180 } 1181 if (extra_hosts && guest_info_state->info.fw_cfg) { 1182 uint64_t *val = g_malloc(sizeof(*val)); 1183 *val = cpu_to_le64(extra_hosts); 1184 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1185 "etc/extra-pci-roots", val, sizeof(*val)); 1186 } 1187 } 1188 1189 acpi_setup(&guest_info_state->info); 1190 } 1191 1192 PcGuestInfo *pc_guest_info_init(PCMachineState *pcms) 1193 { 1194 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1195 PcGuestInfo *guest_info = &guest_info_state->info; 1196 int i, j; 1197 1198 guest_info->ram_size_below_4g = pcms->below_4g_mem_size; 1199 guest_info->ram_size = pcms->below_4g_mem_size + pcms->above_4g_mem_size; 1200 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1201 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1202 guest_info->numa_nodes = nb_numa_nodes; 1203 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1204 sizeof *guest_info->node_mem); 1205 for (i = 0; i < nb_numa_nodes; i++) { 1206 guest_info->node_mem[i] = numa_info[i].node_mem; 1207 } 1208 1209 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1210 sizeof *guest_info->node_cpu); 1211 1212 for (i = 0; i < max_cpus; i++) { 1213 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1214 assert(apic_id < guest_info->apic_id_limit); 1215 for (j = 0; j < nb_numa_nodes; j++) { 1216 if (test_bit(i, numa_info[j].node_cpu)) { 1217 guest_info->node_cpu[apic_id] = j; 1218 break; 1219 } 1220 } 1221 } 1222 1223 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1224 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1225 return guest_info; 1226 } 1227 1228 /* setup pci memory address space mapping into system address space */ 1229 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1230 MemoryRegion *pci_address_space) 1231 { 1232 /* Set to lower priority than RAM */ 1233 memory_region_add_subregion_overlap(system_memory, 0x0, 1234 pci_address_space, -1); 1235 } 1236 1237 void pc_acpi_init(const char *default_dsdt) 1238 { 1239 char *filename; 1240 1241 if (acpi_tables != NULL) { 1242 /* manually set via -acpitable, leave it alone */ 1243 return; 1244 } 1245 1246 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1247 if (filename == NULL) { 1248 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1249 } else { 1250 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1251 &error_abort); 1252 Error *err = NULL; 1253 1254 qemu_opt_set(opts, "file", filename, &error_abort); 1255 1256 acpi_table_add_builtin(opts, &err); 1257 if (err) { 1258 error_reportf_err(err, "WARNING: failed to load %s: ", 1259 filename); 1260 } 1261 g_free(filename); 1262 } 1263 } 1264 1265 FWCfgState *xen_load_linux(PCMachineState *pcms, 1266 PcGuestInfo *guest_info) 1267 { 1268 int i; 1269 FWCfgState *fw_cfg; 1270 1271 assert(MACHINE(pcms)->kernel_filename != NULL); 1272 1273 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1274 rom_set_fw(fw_cfg); 1275 1276 load_linux(pcms, fw_cfg); 1277 for (i = 0; i < nb_option_roms; i++) { 1278 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1279 !strcmp(option_rom[i].name, "multiboot.bin")); 1280 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1281 } 1282 guest_info->fw_cfg = fw_cfg; 1283 return fw_cfg; 1284 } 1285 1286 FWCfgState *pc_memory_init(PCMachineState *pcms, 1287 MemoryRegion *system_memory, 1288 MemoryRegion *rom_memory, 1289 MemoryRegion **ram_memory, 1290 PcGuestInfo *guest_info) 1291 { 1292 int linux_boot, i; 1293 MemoryRegion *ram, *option_rom_mr; 1294 MemoryRegion *ram_below_4g, *ram_above_4g; 1295 FWCfgState *fw_cfg; 1296 MachineState *machine = MACHINE(pcms); 1297 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1298 1299 assert(machine->ram_size == pcms->below_4g_mem_size + 1300 pcms->above_4g_mem_size); 1301 1302 linux_boot = (machine->kernel_filename != NULL); 1303 1304 /* Allocate RAM. We allocate it as a single memory region and use 1305 * aliases to address portions of it, mostly for backwards compatibility 1306 * with older qemus that used qemu_ram_alloc(). 1307 */ 1308 ram = g_malloc(sizeof(*ram)); 1309 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1310 machine->ram_size); 1311 *ram_memory = ram; 1312 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1313 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1314 0, pcms->below_4g_mem_size); 1315 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1316 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1317 if (pcms->above_4g_mem_size > 0) { 1318 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1319 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1320 pcms->below_4g_mem_size, 1321 pcms->above_4g_mem_size); 1322 memory_region_add_subregion(system_memory, 0x100000000ULL, 1323 ram_above_4g); 1324 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1325 } 1326 1327 if (!guest_info->has_reserved_memory && 1328 (machine->ram_slots || 1329 (machine->maxram_size > machine->ram_size))) { 1330 MachineClass *mc = MACHINE_GET_CLASS(machine); 1331 1332 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1333 mc->name); 1334 exit(EXIT_FAILURE); 1335 } 1336 1337 /* initialize hotplug memory address space */ 1338 if (guest_info->has_reserved_memory && 1339 (machine->ram_size < machine->maxram_size)) { 1340 ram_addr_t hotplug_mem_size = 1341 machine->maxram_size - machine->ram_size; 1342 1343 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1344 error_report("unsupported amount of memory slots: %"PRIu64, 1345 machine->ram_slots); 1346 exit(EXIT_FAILURE); 1347 } 1348 1349 if (QEMU_ALIGN_UP(machine->maxram_size, 1350 TARGET_PAGE_SIZE) != machine->maxram_size) { 1351 error_report("maximum memory size must by aligned to multiple of " 1352 "%d bytes", TARGET_PAGE_SIZE); 1353 exit(EXIT_FAILURE); 1354 } 1355 1356 pcms->hotplug_memory.base = 1357 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1358 1359 if (pcmc->enforce_aligned_dimm) { 1360 /* size hotplug region assuming 1G page max alignment per slot */ 1361 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1362 } 1363 1364 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1365 hotplug_mem_size) { 1366 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1367 machine->maxram_size); 1368 exit(EXIT_FAILURE); 1369 } 1370 1371 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1372 "hotplug-memory", hotplug_mem_size); 1373 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1374 &pcms->hotplug_memory.mr); 1375 } 1376 1377 /* Initialize PC system firmware */ 1378 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1379 1380 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1381 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1382 &error_fatal); 1383 vmstate_register_ram_global(option_rom_mr); 1384 memory_region_add_subregion_overlap(rom_memory, 1385 PC_ROM_MIN_VGA, 1386 option_rom_mr, 1387 1); 1388 1389 fw_cfg = bochs_bios_init(&address_space_memory); 1390 1391 rom_set_fw(fw_cfg); 1392 1393 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1394 uint64_t *val = g_malloc(sizeof(*val)); 1395 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1396 uint64_t res_mem_end = pcms->hotplug_memory.base; 1397 1398 if (!pcmc->broken_reserved_end) { 1399 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1400 } 1401 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1402 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1403 } 1404 1405 if (linux_boot) { 1406 load_linux(pcms, fw_cfg); 1407 } 1408 1409 for (i = 0; i < nb_option_roms; i++) { 1410 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1411 } 1412 guest_info->fw_cfg = fw_cfg; 1413 return fw_cfg; 1414 } 1415 1416 qemu_irq pc_allocate_cpu_irq(void) 1417 { 1418 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1419 } 1420 1421 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1422 { 1423 DeviceState *dev = NULL; 1424 1425 if (pci_bus) { 1426 PCIDevice *pcidev = pci_vga_init(pci_bus); 1427 dev = pcidev ? &pcidev->qdev : NULL; 1428 } else if (isa_bus) { 1429 ISADevice *isadev = isa_vga_init(isa_bus); 1430 dev = isadev ? DEVICE(isadev) : NULL; 1431 } 1432 return dev; 1433 } 1434 1435 static const MemoryRegionOps ioport80_io_ops = { 1436 .write = ioport80_write, 1437 .read = ioport80_read, 1438 .endianness = DEVICE_NATIVE_ENDIAN, 1439 .impl = { 1440 .min_access_size = 1, 1441 .max_access_size = 1, 1442 }, 1443 }; 1444 1445 static const MemoryRegionOps ioportF0_io_ops = { 1446 .write = ioportF0_write, 1447 .read = ioportF0_read, 1448 .endianness = DEVICE_NATIVE_ENDIAN, 1449 .impl = { 1450 .min_access_size = 1, 1451 .max_access_size = 1, 1452 }, 1453 }; 1454 1455 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1456 ISADevice **rtc_state, 1457 bool create_fdctrl, 1458 bool no_vmport, 1459 uint32_t hpet_irqs) 1460 { 1461 int i; 1462 DriveInfo *fd[MAX_FD]; 1463 DeviceState *hpet = NULL; 1464 int pit_isa_irq = 0; 1465 qemu_irq pit_alt_irq = NULL; 1466 qemu_irq rtc_irq = NULL; 1467 qemu_irq *a20_line; 1468 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1469 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1470 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1471 1472 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1473 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1474 1475 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1476 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1477 1478 /* 1479 * Check if an HPET shall be created. 1480 * 1481 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1482 * when the HPET wants to take over. Thus we have to disable the latter. 1483 */ 1484 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1485 /* In order to set property, here not using sysbus_try_create_simple */ 1486 hpet = qdev_try_create(NULL, TYPE_HPET); 1487 if (hpet) { 1488 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1489 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1490 * IRQ8 and IRQ2. 1491 */ 1492 uint8_t compat = object_property_get_int(OBJECT(hpet), 1493 HPET_INTCAP, NULL); 1494 if (!compat) { 1495 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1496 } 1497 qdev_init_nofail(hpet); 1498 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1499 1500 for (i = 0; i < GSI_NUM_PINS; i++) { 1501 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1502 } 1503 pit_isa_irq = -1; 1504 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1505 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1506 } 1507 } 1508 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1509 1510 qemu_register_boot_set(pc_boot_set, *rtc_state); 1511 1512 if (!xen_enabled()) { 1513 if (kvm_pit_in_kernel()) { 1514 pit = kvm_pit_init(isa_bus, 0x40); 1515 } else { 1516 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1517 } 1518 if (hpet) { 1519 /* connect PIT to output control line of the HPET */ 1520 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1521 } 1522 pcspk_init(isa_bus, pit); 1523 } 1524 1525 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1526 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1527 1528 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1529 i8042 = isa_create_simple(isa_bus, "i8042"); 1530 i8042_setup_a20_line(i8042, &a20_line[0]); 1531 if (!no_vmport) { 1532 vmport_init(isa_bus); 1533 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1534 } else { 1535 vmmouse = NULL; 1536 } 1537 if (vmmouse) { 1538 DeviceState *dev = DEVICE(vmmouse); 1539 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1540 qdev_init_nofail(dev); 1541 } 1542 port92 = isa_create_simple(isa_bus, "port92"); 1543 port92_init(port92, &a20_line[1]); 1544 1545 DMA_init(0); 1546 1547 for(i = 0; i < MAX_FD; i++) { 1548 fd[i] = drive_get(IF_FLOPPY, 0, i); 1549 create_fdctrl |= !!fd[i]; 1550 } 1551 if (create_fdctrl) { 1552 fdctrl_init_isa(isa_bus, fd); 1553 } 1554 } 1555 1556 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1557 { 1558 int i; 1559 1560 for (i = 0; i < nb_nics; i++) { 1561 NICInfo *nd = &nd_table[i]; 1562 1563 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1564 pc_init_ne2k_isa(isa_bus, nd); 1565 } else { 1566 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1567 } 1568 } 1569 } 1570 1571 void pc_pci_device_init(PCIBus *pci_bus) 1572 { 1573 int max_bus; 1574 int bus; 1575 1576 max_bus = drive_get_max_bus(IF_SCSI); 1577 for (bus = 0; bus <= max_bus; bus++) { 1578 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1579 } 1580 } 1581 1582 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1583 { 1584 DeviceState *dev; 1585 SysBusDevice *d; 1586 unsigned int i; 1587 1588 if (kvm_ioapic_in_kernel()) { 1589 dev = qdev_create(NULL, "kvm-ioapic"); 1590 } else { 1591 dev = qdev_create(NULL, "ioapic"); 1592 } 1593 if (parent_name) { 1594 object_property_add_child(object_resolve_path(parent_name, NULL), 1595 "ioapic", OBJECT(dev), NULL); 1596 } 1597 qdev_init_nofail(dev); 1598 d = SYS_BUS_DEVICE(dev); 1599 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1600 1601 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1602 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1603 } 1604 } 1605 1606 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1607 DeviceState *dev, Error **errp) 1608 { 1609 HotplugHandlerClass *hhc; 1610 Error *local_err = NULL; 1611 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1612 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1613 PCDIMMDevice *dimm = PC_DIMM(dev); 1614 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1615 MemoryRegion *mr = ddc->get_memory_region(dimm); 1616 uint64_t align = TARGET_PAGE_SIZE; 1617 1618 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1619 align = memory_region_get_alignment(mr); 1620 } 1621 1622 if (!pcms->acpi_dev) { 1623 error_setg(&local_err, 1624 "memory hotplug is not enabled: missing acpi device"); 1625 goto out; 1626 } 1627 1628 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1629 if (local_err) { 1630 goto out; 1631 } 1632 1633 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1634 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1635 out: 1636 error_propagate(errp, local_err); 1637 } 1638 1639 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1640 DeviceState *dev, Error **errp) 1641 { 1642 HotplugHandlerClass *hhc; 1643 Error *local_err = NULL; 1644 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1645 1646 if (!pcms->acpi_dev) { 1647 error_setg(&local_err, 1648 "memory hotplug is not enabled: missing acpi device"); 1649 goto out; 1650 } 1651 1652 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1653 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1654 1655 out: 1656 error_propagate(errp, local_err); 1657 } 1658 1659 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1660 DeviceState *dev, Error **errp) 1661 { 1662 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1663 PCDIMMDevice *dimm = PC_DIMM(dev); 1664 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1665 MemoryRegion *mr = ddc->get_memory_region(dimm); 1666 HotplugHandlerClass *hhc; 1667 Error *local_err = NULL; 1668 1669 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1670 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1671 1672 if (local_err) { 1673 goto out; 1674 } 1675 1676 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1677 object_unparent(OBJECT(dev)); 1678 1679 out: 1680 error_propagate(errp, local_err); 1681 } 1682 1683 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1684 DeviceState *dev, Error **errp) 1685 { 1686 HotplugHandlerClass *hhc; 1687 Error *local_err = NULL; 1688 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1689 1690 if (!dev->hotplugged) { 1691 goto out; 1692 } 1693 1694 if (!pcms->acpi_dev) { 1695 error_setg(&local_err, 1696 "cpu hotplug is not enabled: missing acpi device"); 1697 goto out; 1698 } 1699 1700 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1701 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1702 if (local_err) { 1703 goto out; 1704 } 1705 1706 /* increment the number of CPUs */ 1707 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1708 out: 1709 error_propagate(errp, local_err); 1710 } 1711 1712 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1713 DeviceState *dev, Error **errp) 1714 { 1715 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1716 pc_dimm_plug(hotplug_dev, dev, errp); 1717 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1718 pc_cpu_plug(hotplug_dev, dev, errp); 1719 } 1720 } 1721 1722 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1723 DeviceState *dev, Error **errp) 1724 { 1725 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1726 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1727 } else { 1728 error_setg(errp, "acpi: device unplug request for not supported device" 1729 " type: %s", object_get_typename(OBJECT(dev))); 1730 } 1731 } 1732 1733 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1734 DeviceState *dev, Error **errp) 1735 { 1736 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1737 pc_dimm_unplug(hotplug_dev, dev, errp); 1738 } else { 1739 error_setg(errp, "acpi: device unplug for not supported device" 1740 " type: %s", object_get_typename(OBJECT(dev))); 1741 } 1742 } 1743 1744 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1745 DeviceState *dev) 1746 { 1747 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1748 1749 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1750 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1751 return HOTPLUG_HANDLER(machine); 1752 } 1753 1754 return pcmc->get_hotplug_handler ? 1755 pcmc->get_hotplug_handler(machine, dev) : NULL; 1756 } 1757 1758 static void 1759 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1760 const char *name, Error **errp) 1761 { 1762 PCMachineState *pcms = PC_MACHINE(obj); 1763 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1764 1765 visit_type_int(v, &value, name, errp); 1766 } 1767 1768 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1769 void *opaque, const char *name, 1770 Error **errp) 1771 { 1772 PCMachineState *pcms = PC_MACHINE(obj); 1773 uint64_t value = pcms->max_ram_below_4g; 1774 1775 visit_type_size(v, &value, name, errp); 1776 } 1777 1778 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1779 void *opaque, const char *name, 1780 Error **errp) 1781 { 1782 PCMachineState *pcms = PC_MACHINE(obj); 1783 Error *error = NULL; 1784 uint64_t value; 1785 1786 visit_type_size(v, &value, name, &error); 1787 if (error) { 1788 error_propagate(errp, error); 1789 return; 1790 } 1791 if (value > (1ULL << 32)) { 1792 error_setg(&error, 1793 "Machine option 'max-ram-below-4g=%"PRIu64 1794 "' expects size less than or equal to 4G", value); 1795 error_propagate(errp, error); 1796 return; 1797 } 1798 1799 if (value < (1ULL << 20)) { 1800 error_report("Warning: small max_ram_below_4g(%"PRIu64 1801 ") less than 1M. BIOS may not work..", 1802 value); 1803 } 1804 1805 pcms->max_ram_below_4g = value; 1806 } 1807 1808 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1809 const char *name, Error **errp) 1810 { 1811 PCMachineState *pcms = PC_MACHINE(obj); 1812 OnOffAuto vmport = pcms->vmport; 1813 1814 visit_type_OnOffAuto(v, &vmport, name, errp); 1815 } 1816 1817 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1818 const char *name, Error **errp) 1819 { 1820 PCMachineState *pcms = PC_MACHINE(obj); 1821 1822 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1823 } 1824 1825 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1826 { 1827 bool smm_available = false; 1828 1829 if (pcms->smm == ON_OFF_AUTO_OFF) { 1830 return false; 1831 } 1832 1833 if (tcg_enabled() || qtest_enabled()) { 1834 smm_available = true; 1835 } else if (kvm_enabled()) { 1836 smm_available = kvm_has_smm(); 1837 } 1838 1839 if (smm_available) { 1840 return true; 1841 } 1842 1843 if (pcms->smm == ON_OFF_AUTO_ON) { 1844 error_report("System Management Mode not supported by this hypervisor."); 1845 exit(1); 1846 } 1847 return false; 1848 } 1849 1850 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1851 const char *name, Error **errp) 1852 { 1853 PCMachineState *pcms = PC_MACHINE(obj); 1854 OnOffAuto smm = pcms->smm; 1855 1856 visit_type_OnOffAuto(v, &smm, name, errp); 1857 } 1858 1859 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1860 const char *name, Error **errp) 1861 { 1862 PCMachineState *pcms = PC_MACHINE(obj); 1863 1864 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1865 } 1866 1867 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 1868 { 1869 PCMachineState *pcms = PC_MACHINE(obj); 1870 1871 return pcms->nvdimm; 1872 } 1873 1874 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 1875 { 1876 PCMachineState *pcms = PC_MACHINE(obj); 1877 1878 pcms->nvdimm = value; 1879 } 1880 1881 static void pc_machine_initfn(Object *obj) 1882 { 1883 PCMachineState *pcms = PC_MACHINE(obj); 1884 1885 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1886 pc_machine_get_hotplug_memory_region_size, 1887 NULL, NULL, NULL, &error_abort); 1888 1889 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1890 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1891 pc_machine_get_max_ram_below_4g, 1892 pc_machine_set_max_ram_below_4g, 1893 NULL, NULL, &error_abort); 1894 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1895 "Maximum ram below the 4G boundary (32bit boundary)", 1896 &error_abort); 1897 1898 pcms->smm = ON_OFF_AUTO_AUTO; 1899 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1900 pc_machine_get_smm, 1901 pc_machine_set_smm, 1902 NULL, NULL, &error_abort); 1903 object_property_set_description(obj, PC_MACHINE_SMM, 1904 "Enable SMM (pc & q35)", 1905 &error_abort); 1906 1907 pcms->vmport = ON_OFF_AUTO_AUTO; 1908 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1909 pc_machine_get_vmport, 1910 pc_machine_set_vmport, 1911 NULL, NULL, &error_abort); 1912 object_property_set_description(obj, PC_MACHINE_VMPORT, 1913 "Enable vmport (pc & q35)", 1914 &error_abort); 1915 1916 /* nvdimm is disabled on default. */ 1917 pcms->nvdimm = false; 1918 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, 1919 pc_machine_set_nvdimm, &error_abort); 1920 } 1921 1922 static void pc_machine_reset(void) 1923 { 1924 CPUState *cs; 1925 X86CPU *cpu; 1926 1927 qemu_devices_reset(); 1928 1929 /* Reset APIC after devices have been reset to cancel 1930 * any changes that qemu_devices_reset() might have done. 1931 */ 1932 CPU_FOREACH(cs) { 1933 cpu = X86_CPU(cs); 1934 1935 if (cpu->apic_state) { 1936 device_reset(cpu->apic_state); 1937 } 1938 } 1939 } 1940 1941 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1942 { 1943 X86CPUTopoInfo topo; 1944 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1945 &topo); 1946 return topo.pkg_id; 1947 } 1948 1949 static void pc_machine_class_init(ObjectClass *oc, void *data) 1950 { 1951 MachineClass *mc = MACHINE_CLASS(oc); 1952 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1953 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1954 1955 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1956 pcmc->pci_enabled = true; 1957 pcmc->has_acpi_build = true; 1958 pcmc->rsdp_in_ram = true; 1959 pcmc->smbios_defaults = true; 1960 pcmc->smbios_uuid_encoded = true; 1961 pcmc->gigabyte_align = true; 1962 pcmc->has_reserved_memory = true; 1963 pcmc->kvmclock_enabled = true; 1964 pcmc->enforce_aligned_dimm = true; 1965 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1966 * to be used at the moment, 32K should be enough for a while. */ 1967 pcmc->acpi_data_size = 0x20000 + 0x8000; 1968 pcmc->save_tsc_khz = true; 1969 mc->get_hotplug_handler = pc_get_hotpug_handler; 1970 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1971 mc->default_boot_order = "cad"; 1972 mc->hot_add_cpu = pc_hot_add_cpu; 1973 mc->max_cpus = 255; 1974 mc->reset = pc_machine_reset; 1975 hc->plug = pc_machine_device_plug_cb; 1976 hc->unplug_request = pc_machine_device_unplug_request_cb; 1977 hc->unplug = pc_machine_device_unplug_cb; 1978 } 1979 1980 static const TypeInfo pc_machine_info = { 1981 .name = TYPE_PC_MACHINE, 1982 .parent = TYPE_MACHINE, 1983 .abstract = true, 1984 .instance_size = sizeof(PCMachineState), 1985 .instance_init = pc_machine_initfn, 1986 .class_size = sizeof(PCMachineClass), 1987 .class_init = pc_machine_class_init, 1988 .interfaces = (InterfaceInfo[]) { 1989 { TYPE_HOTPLUG_HANDLER }, 1990 { } 1991 }, 1992 }; 1993 1994 static void pc_machine_register_types(void) 1995 { 1996 type_register_static(&pc_machine_info); 1997 } 1998 1999 type_init(pc_machine_register_types) 2000