1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_8_2[] = {}; 82 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 83 84 GlobalProperty pc_compat_8_1[] = {}; 85 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 86 87 GlobalProperty pc_compat_8_0[] = { 88 { "virtio-mem", "unplugged-inaccessible", "auto" }, 89 }; 90 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 91 92 GlobalProperty pc_compat_7_2[] = { 93 { "ICH9-LPC", "noreboot", "true" }, 94 }; 95 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 96 97 GlobalProperty pc_compat_7_1[] = {}; 98 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 99 100 GlobalProperty pc_compat_7_0[] = {}; 101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 102 103 GlobalProperty pc_compat_6_2[] = { 104 { "virtio-mem", "unplugged-inaccessible", "off" }, 105 }; 106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 107 108 GlobalProperty pc_compat_6_1[] = { 109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 113 }; 114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 115 116 GlobalProperty pc_compat_6_0[] = { 117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 123 }; 124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 125 126 GlobalProperty pc_compat_5_2[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 128 }; 129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 130 131 GlobalProperty pc_compat_5_1[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 134 }; 135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 136 137 GlobalProperty pc_compat_5_0[] = { 138 }; 139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 140 141 GlobalProperty pc_compat_4_2[] = { 142 { "mch", "smbase-smram", "off" }, 143 }; 144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 145 146 GlobalProperty pc_compat_4_1[] = {}; 147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 148 149 GlobalProperty pc_compat_4_0[] = {}; 150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 151 152 GlobalProperty pc_compat_3_1[] = { 153 { "intel-iommu", "dma-drain", "off" }, 154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 174 }; 175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 176 177 GlobalProperty pc_compat_3_0[] = { 178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 181 }; 182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 183 184 GlobalProperty pc_compat_2_12[] = { 185 { TYPE_X86_CPU, "legacy-cache", "on" }, 186 { TYPE_X86_CPU, "topoext", "off" }, 187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 }; 190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 191 192 GlobalProperty pc_compat_2_11[] = { 193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 195 }; 196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 197 198 GlobalProperty pc_compat_2_10[] = { 199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 201 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 202 }; 203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 204 205 GlobalProperty pc_compat_2_9[] = { 206 { "mch", "extended-tseg-mbytes", "0" }, 207 }; 208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 209 210 GlobalProperty pc_compat_2_8[] = { 211 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 213 { "ICH9-LPC", "x-smi-broadcast", "off" }, 214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 216 }; 217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 218 219 GlobalProperty pc_compat_2_7[] = { 220 { TYPE_X86_CPU, "l3-cache", "off" }, 221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 225 { "isa-pcspk", "migrate", "off" }, 226 }; 227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 228 229 GlobalProperty pc_compat_2_6[] = { 230 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 231 { "vmxnet3", "romfile", "" }, 232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 233 { "apic-common", "legacy-instance-id", "on", } 234 }; 235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 236 237 GlobalProperty pc_compat_2_5[] = {}; 238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 239 240 GlobalProperty pc_compat_2_4[] = { 241 PC_CPU_MODEL_IDS("2.4.0") 242 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 247 { TYPE_X86_CPU, "check", "off" }, 248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 256 }; 257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 258 259 GlobalProperty pc_compat_2_3[] = { 260 PC_CPU_MODEL_IDS("2.3.0") 261 { TYPE_X86_CPU, "arat", "off" }, 262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 281 }; 282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 283 284 GlobalProperty pc_compat_2_2[] = { 285 PC_CPU_MODEL_IDS("2.2.0") 286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 304 }; 305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 306 307 GlobalProperty pc_compat_2_1[] = { 308 PC_CPU_MODEL_IDS("2.1.0") 309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 }; 312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 313 314 GlobalProperty pc_compat_2_0[] = { 315 PC_CPU_MODEL_IDS("2.0.0") 316 { "virtio-scsi-pci", "any_layout", "off" }, 317 { "PIIX4_PM", "memory-hotplug-support", "off" }, 318 { "apic", "version", "0x11" }, 319 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 320 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 321 { "pci-serial", "prog_if", "0" }, 322 { "pci-serial-2x", "prog_if", "0" }, 323 { "pci-serial-4x", "prog_if", "0" }, 324 { "virtio-net-pci", "guest_announce", "off" }, 325 { "ICH9-LPC", "memory-hotplug-support", "off" }, 326 }; 327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 328 329 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 330 { 331 GSIState *s; 332 333 s = g_new0(GSIState, 1); 334 if (kvm_ioapic_in_kernel()) { 335 kvm_pc_setup_irq_routing(pci_enabled); 336 } 337 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 338 339 return s; 340 } 341 342 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 343 unsigned size) 344 { 345 } 346 347 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 348 { 349 return 0xffffffffffffffffULL; 350 } 351 352 /* MS-DOS compatibility mode FPU exception support */ 353 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 354 unsigned size) 355 { 356 if (tcg_enabled()) { 357 cpu_set_ignne(); 358 } 359 } 360 361 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 362 { 363 return 0xffffffffffffffffULL; 364 } 365 366 /* PC cmos mappings */ 367 368 #define REG_EQUIPMENT_BYTE 0x14 369 370 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 371 int16_t cylinders, int8_t heads, int8_t sectors) 372 { 373 mc146818rtc_set_cmos_data(s, type_ofs, 47); 374 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 375 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 376 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 377 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 378 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 379 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 380 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 381 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 382 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 383 } 384 385 /* convert boot_device letter to something recognizable by the bios */ 386 static int boot_device2nibble(char boot_device) 387 { 388 switch(boot_device) { 389 case 'a': 390 case 'b': 391 return 0x01; /* floppy boot */ 392 case 'c': 393 return 0x02; /* hard drive boot */ 394 case 'd': 395 return 0x03; /* CD-ROM boot */ 396 case 'n': 397 return 0x04; /* Network boot */ 398 } 399 return 0; 400 } 401 402 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 403 const char *boot_device, Error **errp) 404 { 405 #define PC_MAX_BOOT_DEVICES 3 406 int nbds, bds[3] = { 0, }; 407 int i; 408 409 nbds = strlen(boot_device); 410 if (nbds > PC_MAX_BOOT_DEVICES) { 411 error_setg(errp, "Too many boot devices for PC"); 412 return; 413 } 414 for (i = 0; i < nbds; i++) { 415 bds[i] = boot_device2nibble(boot_device[i]); 416 if (bds[i] == 0) { 417 error_setg(errp, "Invalid boot device for PC: '%c'", 418 boot_device[i]); 419 return; 420 } 421 } 422 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 423 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 424 } 425 426 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 427 { 428 PCMachineState *pcms = opaque; 429 X86MachineState *x86ms = X86_MACHINE(pcms); 430 431 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 432 } 433 434 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 435 { 436 int val, nb, i; 437 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 438 FLOPPY_DRIVE_TYPE_NONE }; 439 440 /* floppy type */ 441 if (floppy) { 442 for (i = 0; i < 2; i++) { 443 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 444 } 445 } 446 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 447 cmos_get_fd_drive_type(fd_type[1]); 448 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 449 450 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 451 nb = 0; 452 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 453 nb++; 454 } 455 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 456 nb++; 457 } 458 switch (nb) { 459 case 0: 460 break; 461 case 1: 462 val |= 0x01; /* 1 drive, ready for boot */ 463 break; 464 case 2: 465 val |= 0x41; /* 2 drives, ready for boot */ 466 break; 467 } 468 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 469 } 470 471 typedef struct check_fdc_state { 472 ISADevice *floppy; 473 bool multiple; 474 } CheckFdcState; 475 476 static int check_fdc(Object *obj, void *opaque) 477 { 478 CheckFdcState *state = opaque; 479 Object *fdc; 480 uint32_t iobase; 481 Error *local_err = NULL; 482 483 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 484 if (!fdc) { 485 return 0; 486 } 487 488 iobase = object_property_get_uint(obj, "iobase", &local_err); 489 if (local_err || iobase != 0x3f0) { 490 error_free(local_err); 491 return 0; 492 } 493 494 if (state->floppy) { 495 state->multiple = true; 496 } else { 497 state->floppy = ISA_DEVICE(obj); 498 } 499 return 0; 500 } 501 502 static const char * const fdc_container_path[] = { 503 "/unattached", "/peripheral", "/peripheral-anon" 504 }; 505 506 /* 507 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 508 * and ACPI objects. 509 */ 510 static ISADevice *pc_find_fdc0(void) 511 { 512 int i; 513 Object *container; 514 CheckFdcState state = { 0 }; 515 516 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 517 container = container_get(qdev_get_machine(), fdc_container_path[i]); 518 object_child_foreach(container, check_fdc, &state); 519 } 520 521 if (state.multiple) { 522 warn_report("multiple floppy disk controllers with " 523 "iobase=0x3f0 have been found"); 524 error_printf("the one being picked for CMOS setup might not reflect " 525 "your intent"); 526 } 527 528 return state.floppy; 529 } 530 531 static void pc_cmos_init_late(PCMachineState *pcms) 532 { 533 X86MachineState *x86ms = X86_MACHINE(pcms); 534 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 535 int16_t cylinders; 536 int8_t heads, sectors; 537 int val; 538 int i, trans; 539 540 val = 0; 541 if (pcms->idebus[0] && 542 ide_get_geometry(pcms->idebus[0], 0, 543 &cylinders, &heads, §ors) >= 0) { 544 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 545 val |= 0xf0; 546 } 547 if (pcms->idebus[0] && 548 ide_get_geometry(pcms->idebus[0], 1, 549 &cylinders, &heads, §ors) >= 0) { 550 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 551 val |= 0x0f; 552 } 553 mc146818rtc_set_cmos_data(s, 0x12, val); 554 555 val = 0; 556 for (i = 0; i < 4; i++) { 557 /* NOTE: ide_get_geometry() returns the physical 558 geometry. It is always such that: 1 <= sects <= 63, 1 559 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 560 geometry can be different if a translation is done. */ 561 BusState *idebus = pcms->idebus[i / 2]; 562 if (idebus && 563 ide_get_geometry(idebus, i % 2, 564 &cylinders, &heads, §ors) >= 0) { 565 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 566 assert((trans & ~3) == 0); 567 val |= trans << (i * 2); 568 } 569 } 570 mc146818rtc_set_cmos_data(s, 0x39, val); 571 572 pc_cmos_init_floppy(s, pc_find_fdc0()); 573 574 /* various important CMOS locations needed by PC/Bochs bios */ 575 576 /* memory size */ 577 /* base memory (first MiB) */ 578 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 579 mc146818rtc_set_cmos_data(s, 0x15, val); 580 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 581 /* extended memory (next 64MiB) */ 582 if (x86ms->below_4g_mem_size > 1 * MiB) { 583 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 584 } else { 585 val = 0; 586 } 587 if (val > 65535) 588 val = 65535; 589 mc146818rtc_set_cmos_data(s, 0x17, val); 590 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 591 mc146818rtc_set_cmos_data(s, 0x30, val); 592 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 593 /* memory between 16MiB and 4GiB */ 594 if (x86ms->below_4g_mem_size > 16 * MiB) { 595 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 596 } else { 597 val = 0; 598 } 599 if (val > 65535) 600 val = 65535; 601 mc146818rtc_set_cmos_data(s, 0x34, val); 602 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 603 /* memory above 4GiB */ 604 val = x86ms->above_4g_mem_size / 65536; 605 mc146818rtc_set_cmos_data(s, 0x5b, val); 606 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 607 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 608 609 val = 0; 610 val |= 0x02; /* FPU is there */ 611 val |= 0x04; /* PS/2 mouse installed */ 612 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 613 } 614 615 static void handle_a20_line_change(void *opaque, int irq, int level) 616 { 617 X86CPU *cpu = opaque; 618 619 /* XXX: send to all CPUs ? */ 620 /* XXX: add logic to handle multiple A20 line sources */ 621 x86_cpu_set_a20(cpu, level); 622 } 623 624 #define NE2000_NB_MAX 6 625 626 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 627 0x280, 0x380 }; 628 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 629 630 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 631 { 632 static int nb_ne2k = 0; 633 634 if (nb_ne2k == NE2000_NB_MAX) { 635 error_setg(errp, 636 "maximum number of ISA NE2000 devices exceeded"); 637 return false; 638 } 639 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 640 ne2000_irq[nb_ne2k], nd); 641 nb_ne2k++; 642 return true; 643 } 644 645 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 646 { 647 X86CPU *cpu = opaque; 648 649 if (level) { 650 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 651 } 652 } 653 654 static 655 void pc_machine_done(Notifier *notifier, void *data) 656 { 657 PCMachineState *pcms = container_of(notifier, 658 PCMachineState, machine_done); 659 X86MachineState *x86ms = X86_MACHINE(pcms); 660 661 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 662 &error_fatal); 663 664 if (pcms->cxl_devices_state.is_enabled) { 665 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 666 } 667 668 /* set the number of CPUs */ 669 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 670 671 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 672 673 acpi_setup(); 674 if (x86ms->fw_cfg) { 675 fw_cfg_build_smbios(pcms, x86ms->fw_cfg); 676 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 677 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 678 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 679 } 680 681 pc_cmos_init_late(pcms); 682 } 683 684 /* setup pci memory address space mapping into system address space */ 685 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 686 MemoryRegion *pci_address_space) 687 { 688 /* Set to lower priority than RAM */ 689 memory_region_add_subregion_overlap(system_memory, 0x0, 690 pci_address_space, -1); 691 } 692 693 void xen_load_linux(PCMachineState *pcms) 694 { 695 int i; 696 FWCfgState *fw_cfg; 697 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 698 X86MachineState *x86ms = X86_MACHINE(pcms); 699 700 assert(MACHINE(pcms)->kernel_filename != NULL); 701 702 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 703 &address_space_memory); 704 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 705 rom_set_fw(fw_cfg); 706 707 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 708 pcmc->pvh_enabled); 709 for (i = 0; i < nb_option_roms; i++) { 710 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 711 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 712 !strcmp(option_rom[i].name, "pvh.bin") || 713 !strcmp(option_rom[i].name, "multiboot.bin") || 714 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 715 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 716 } 717 x86ms->fw_cfg = fw_cfg; 718 } 719 720 #define PC_ROM_MIN_VGA 0xc0000 721 #define PC_ROM_MIN_OPTION 0xc8000 722 #define PC_ROM_MAX 0xe0000 723 #define PC_ROM_ALIGN 0x800 724 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 725 726 static hwaddr pc_above_4g_end(PCMachineState *pcms) 727 { 728 X86MachineState *x86ms = X86_MACHINE(pcms); 729 730 if (pcms->sgx_epc.size != 0) { 731 return sgx_epc_above_4g_end(&pcms->sgx_epc); 732 } 733 734 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 735 } 736 737 static void pc_get_device_memory_range(PCMachineState *pcms, 738 hwaddr *base, 739 ram_addr_t *device_mem_size) 740 { 741 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 742 MachineState *machine = MACHINE(pcms); 743 ram_addr_t size; 744 hwaddr addr; 745 746 size = machine->maxram_size - machine->ram_size; 747 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 748 749 if (pcmc->enforce_aligned_dimm) { 750 /* size device region assuming 1G page max alignment per slot */ 751 size += (1 * GiB) * machine->ram_slots; 752 } 753 754 *base = addr; 755 *device_mem_size = size; 756 } 757 758 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 759 { 760 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 761 MachineState *ms = MACHINE(pcms); 762 hwaddr cxl_base; 763 ram_addr_t size; 764 765 if (pcmc->has_reserved_memory && 766 (ms->ram_size < ms->maxram_size)) { 767 pc_get_device_memory_range(pcms, &cxl_base, &size); 768 cxl_base += size; 769 } else { 770 cxl_base = pc_above_4g_end(pcms); 771 } 772 773 return cxl_base; 774 } 775 776 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 777 { 778 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 779 780 if (pcms->cxl_devices_state.fixed_windows) { 781 GList *it; 782 783 start = ROUND_UP(start, 256 * MiB); 784 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 785 CXLFixedWindow *fw = it->data; 786 start += fw->size; 787 } 788 } 789 790 return start; 791 } 792 793 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 794 { 795 X86CPU *cpu = X86_CPU(first_cpu); 796 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 797 MachineState *ms = MACHINE(pcms); 798 799 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 800 /* 64-bit systems */ 801 return pc_pci_hole64_start() + pci_hole64_size - 1; 802 } 803 804 /* 32-bit systems */ 805 if (pcmc->broken_32bit_mem_addr_check) { 806 /* old value for compatibility reasons */ 807 return ((hwaddr)1 << cpu->phys_bits) - 1; 808 } 809 810 /* 811 * 32-bit systems don't have hole64 but they might have a region for 812 * memory devices. Even if additional hotplugged memory devices might 813 * not be usable by most guest OSes, we need to still consider them for 814 * calculating the highest possible GPA so that we can properly report 815 * if someone configures them on a CPU that cannot possibly address them. 816 */ 817 if (pcmc->has_reserved_memory && 818 (ms->ram_size < ms->maxram_size)) { 819 hwaddr devmem_start; 820 ram_addr_t devmem_size; 821 822 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 823 devmem_start += devmem_size; 824 return devmem_start - 1; 825 } 826 827 /* configuration without any memory hotplug */ 828 return pc_above_4g_end(pcms) - 1; 829 } 830 831 /* 832 * AMD systems with an IOMMU have an additional hole close to the 833 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 834 * on kernel version, VFIO may or may not let you DMA map those ranges. 835 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 836 * with certain memory sizes. It's also wrong to use those IOVA ranges 837 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 838 * The ranges reserved for Hyper-Transport are: 839 * 840 * FD_0000_0000h - FF_FFFF_FFFFh 841 * 842 * The ranges represent the following: 843 * 844 * Base Address Top Address Use 845 * 846 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 847 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 848 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 849 * FD_F910_0000h FD_F91F_FFFFh System Management 850 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 851 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 852 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 853 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 854 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 855 * FE_2000_0000h FF_FFFF_FFFFh Reserved 856 * 857 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 858 * Table 3: Special Address Controls (GPA) for more information. 859 */ 860 #define AMD_HT_START 0xfd00000000UL 861 #define AMD_HT_END 0xffffffffffUL 862 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 863 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 864 865 void pc_memory_init(PCMachineState *pcms, 866 MemoryRegion *system_memory, 867 MemoryRegion *rom_memory, 868 uint64_t pci_hole64_size) 869 { 870 int linux_boot, i; 871 MemoryRegion *option_rom_mr; 872 MemoryRegion *ram_below_4g, *ram_above_4g; 873 FWCfgState *fw_cfg; 874 MachineState *machine = MACHINE(pcms); 875 MachineClass *mc = MACHINE_GET_CLASS(machine); 876 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 877 X86MachineState *x86ms = X86_MACHINE(pcms); 878 hwaddr maxphysaddr, maxusedaddr; 879 hwaddr cxl_base, cxl_resv_end = 0; 880 X86CPU *cpu = X86_CPU(first_cpu); 881 882 assert(machine->ram_size == x86ms->below_4g_mem_size + 883 x86ms->above_4g_mem_size); 884 885 linux_boot = (machine->kernel_filename != NULL); 886 887 /* 888 * The HyperTransport range close to the 1T boundary is unique to AMD 889 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 890 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 891 * older machine types (<= 7.0) for compatibility purposes. 892 */ 893 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 894 /* Bail out if max possible address does not cross HT range */ 895 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 896 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 897 } 898 899 /* 900 * Advertise the HT region if address space covers the reserved 901 * region or if we relocate. 902 */ 903 if (cpu->phys_bits >= 40) { 904 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 905 } 906 } 907 908 /* 909 * phys-bits is required to be appropriately configured 910 * to make sure max used GPA is reachable. 911 */ 912 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 913 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 914 if (maxphysaddr < maxusedaddr) { 915 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 916 " phys-bits too low (%u)", 917 maxphysaddr, maxusedaddr, cpu->phys_bits); 918 exit(EXIT_FAILURE); 919 } 920 921 /* 922 * Split single memory region and use aliases to address portions of it, 923 * done for backwards compatibility with older qemus. 924 */ 925 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 926 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 927 0, x86ms->below_4g_mem_size); 928 memory_region_add_subregion(system_memory, 0, ram_below_4g); 929 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 930 if (x86ms->above_4g_mem_size > 0) { 931 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 932 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 933 machine->ram, 934 x86ms->below_4g_mem_size, 935 x86ms->above_4g_mem_size); 936 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 937 ram_above_4g); 938 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 939 E820_RAM); 940 } 941 942 if (pcms->sgx_epc.size != 0) { 943 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 944 } 945 946 if (!pcmc->has_reserved_memory && 947 (machine->ram_slots || 948 (machine->maxram_size > machine->ram_size))) { 949 950 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 951 mc->name); 952 exit(EXIT_FAILURE); 953 } 954 955 /* initialize device memory address space */ 956 if (pcmc->has_reserved_memory && 957 (machine->ram_size < machine->maxram_size)) { 958 ram_addr_t device_mem_size; 959 hwaddr device_mem_base; 960 961 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 962 error_report("unsupported amount of memory slots: %"PRIu64, 963 machine->ram_slots); 964 exit(EXIT_FAILURE); 965 } 966 967 if (QEMU_ALIGN_UP(machine->maxram_size, 968 TARGET_PAGE_SIZE) != machine->maxram_size) { 969 error_report("maximum memory size must by aligned to multiple of " 970 "%d bytes", TARGET_PAGE_SIZE); 971 exit(EXIT_FAILURE); 972 } 973 974 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 975 976 if (device_mem_base + device_mem_size < device_mem_size) { 977 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 978 machine->maxram_size); 979 exit(EXIT_FAILURE); 980 } 981 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 982 } 983 984 if (pcms->cxl_devices_state.is_enabled) { 985 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 986 hwaddr cxl_size = MiB; 987 988 cxl_base = pc_get_cxl_range_start(pcms); 989 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 990 memory_region_add_subregion(system_memory, cxl_base, mr); 991 cxl_resv_end = cxl_base + cxl_size; 992 if (pcms->cxl_devices_state.fixed_windows) { 993 hwaddr cxl_fmw_base; 994 GList *it; 995 996 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 997 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 998 CXLFixedWindow *fw = it->data; 999 1000 fw->base = cxl_fmw_base; 1001 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1002 "cxl-fixed-memory-region", fw->size); 1003 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1004 cxl_fmw_base += fw->size; 1005 cxl_resv_end = cxl_fmw_base; 1006 } 1007 } 1008 } 1009 1010 /* Initialize PC system firmware */ 1011 pc_system_firmware_init(pcms, rom_memory); 1012 1013 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1014 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1015 &error_fatal); 1016 if (pcmc->pci_enabled) { 1017 memory_region_set_readonly(option_rom_mr, true); 1018 } 1019 memory_region_add_subregion_overlap(rom_memory, 1020 PC_ROM_MIN_VGA, 1021 option_rom_mr, 1022 1); 1023 1024 fw_cfg = fw_cfg_arch_create(machine, 1025 x86ms->boot_cpus, x86ms->apic_id_limit); 1026 1027 rom_set_fw(fw_cfg); 1028 1029 if (machine->device_memory) { 1030 uint64_t *val = g_malloc(sizeof(*val)); 1031 uint64_t res_mem_end = machine->device_memory->base; 1032 1033 if (!pcmc->broken_reserved_end) { 1034 res_mem_end += memory_region_size(&machine->device_memory->mr); 1035 } 1036 1037 if (pcms->cxl_devices_state.is_enabled) { 1038 res_mem_end = cxl_resv_end; 1039 } 1040 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1041 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1042 } 1043 1044 if (linux_boot) { 1045 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1046 pcmc->pvh_enabled); 1047 } 1048 1049 for (i = 0; i < nb_option_roms; i++) { 1050 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1051 } 1052 x86ms->fw_cfg = fw_cfg; 1053 1054 /* Init default IOAPIC address space */ 1055 x86ms->ioapic_as = &address_space_memory; 1056 1057 /* Init ACPI memory hotplug IO base address */ 1058 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1059 } 1060 1061 /* 1062 * The 64bit pci hole starts after "above 4G RAM" and 1063 * potentially the space reserved for memory hotplug. 1064 */ 1065 uint64_t pc_pci_hole64_start(void) 1066 { 1067 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1068 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1069 MachineState *ms = MACHINE(pcms); 1070 uint64_t hole64_start = 0; 1071 ram_addr_t size = 0; 1072 1073 if (pcms->cxl_devices_state.is_enabled) { 1074 hole64_start = pc_get_cxl_range_end(pcms); 1075 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1076 pc_get_device_memory_range(pcms, &hole64_start, &size); 1077 if (!pcmc->broken_reserved_end) { 1078 hole64_start += size; 1079 } 1080 } else { 1081 hole64_start = pc_above_4g_end(pcms); 1082 } 1083 1084 return ROUND_UP(hole64_start, 1 * GiB); 1085 } 1086 1087 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1088 { 1089 DeviceState *dev = NULL; 1090 1091 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1092 if (pci_bus) { 1093 PCIDevice *pcidev = pci_vga_init(pci_bus); 1094 dev = pcidev ? &pcidev->qdev : NULL; 1095 } else if (isa_bus) { 1096 ISADevice *isadev = isa_vga_init(isa_bus); 1097 dev = isadev ? DEVICE(isadev) : NULL; 1098 } 1099 rom_reset_order_override(); 1100 return dev; 1101 } 1102 1103 static const MemoryRegionOps ioport80_io_ops = { 1104 .write = ioport80_write, 1105 .read = ioport80_read, 1106 .endianness = DEVICE_NATIVE_ENDIAN, 1107 .impl = { 1108 .min_access_size = 1, 1109 .max_access_size = 1, 1110 }, 1111 }; 1112 1113 static const MemoryRegionOps ioportF0_io_ops = { 1114 .write = ioportF0_write, 1115 .read = ioportF0_read, 1116 .endianness = DEVICE_NATIVE_ENDIAN, 1117 .impl = { 1118 .min_access_size = 1, 1119 .max_access_size = 1, 1120 }, 1121 }; 1122 1123 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1124 bool create_i8042, bool no_vmport) 1125 { 1126 int i; 1127 DriveInfo *fd[MAX_FD]; 1128 qemu_irq *a20_line; 1129 ISADevice *fdc, *i8042, *port92, *vmmouse; 1130 1131 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1132 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1133 1134 for (i = 0; i < MAX_FD; i++) { 1135 fd[i] = drive_get(IF_FLOPPY, 0, i); 1136 create_fdctrl |= !!fd[i]; 1137 } 1138 if (create_fdctrl) { 1139 fdc = isa_new(TYPE_ISA_FDC); 1140 if (fdc) { 1141 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1142 isa_fdc_init_drives(fdc, fd); 1143 } 1144 } 1145 1146 if (!create_i8042) { 1147 return; 1148 } 1149 1150 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1151 if (!no_vmport) { 1152 isa_create_simple(isa_bus, TYPE_VMPORT); 1153 vmmouse = isa_try_new("vmmouse"); 1154 } else { 1155 vmmouse = NULL; 1156 } 1157 if (vmmouse) { 1158 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1159 &error_abort); 1160 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1161 } 1162 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1163 1164 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1165 qdev_connect_gpio_out_named(DEVICE(i8042), 1166 I8042_A20_LINE, 0, a20_line[0]); 1167 qdev_connect_gpio_out_named(DEVICE(port92), 1168 PORT92_A20_LINE, 0, a20_line[1]); 1169 g_free(a20_line); 1170 } 1171 1172 void pc_basic_device_init(struct PCMachineState *pcms, 1173 ISABus *isa_bus, qemu_irq *gsi, 1174 ISADevice *rtc_state, 1175 bool create_fdctrl, 1176 uint32_t hpet_irqs) 1177 { 1178 int i; 1179 DeviceState *hpet = NULL; 1180 int pit_isa_irq = 0; 1181 qemu_irq pit_alt_irq = NULL; 1182 ISADevice *pit = NULL; 1183 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1184 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1185 X86MachineState *x86ms = X86_MACHINE(pcms); 1186 1187 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1188 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1189 1190 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1191 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1192 1193 /* 1194 * Check if an HPET shall be created. 1195 */ 1196 if (pcms->hpet_enabled) { 1197 qemu_irq rtc_irq; 1198 1199 hpet = qdev_try_new(TYPE_HPET); 1200 if (!hpet) { 1201 error_report("couldn't create HPET device"); 1202 exit(1); 1203 } 1204 /* 1205 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1206 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1207 * the property, use whatever mask they specified. 1208 */ 1209 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1210 HPET_INTCAP, NULL); 1211 if (!compat) { 1212 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1213 } 1214 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1215 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1216 1217 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1218 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1219 } 1220 pit_isa_irq = -1; 1221 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1222 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1223 1224 /* overwrite connection created by south bridge */ 1225 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1226 } 1227 1228 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1229 "date"); 1230 1231 #ifdef CONFIG_XEN_EMU 1232 if (xen_mode == XEN_EMULATE) { 1233 xen_overlay_create(); 1234 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1235 xen_gnttab_create(); 1236 xen_xenstore_create(); 1237 if (pcms->pcibus) { 1238 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1239 } 1240 xen_bus_init(); 1241 xen_be_init(); 1242 } 1243 #endif 1244 1245 qemu_register_boot_set(pc_boot_set, pcms); 1246 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1247 MACHINE(pcms)->boot_config.order, &error_fatal); 1248 1249 if (!xen_enabled() && 1250 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1251 if (kvm_pit_in_kernel()) { 1252 pit = kvm_pit_init(isa_bus, 0x40); 1253 } else { 1254 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1255 } 1256 if (hpet) { 1257 /* connect PIT to output control line of the HPET */ 1258 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1259 } 1260 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1261 OBJECT(pit), &error_fatal); 1262 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1263 } 1264 1265 /* Super I/O */ 1266 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1267 pcms->vmport != ON_OFF_AUTO_ON); 1268 } 1269 1270 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1271 { 1272 MachineClass *mc = MACHINE_CLASS(pcmc); 1273 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1274 NICInfo *nd; 1275 1276 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1277 1278 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1279 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1280 } 1281 1282 /* Anything remaining should be a PCI NIC */ 1283 pci_init_nic_devices(pci_bus, mc->default_nic); 1284 1285 rom_reset_order_override(); 1286 } 1287 1288 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1289 { 1290 qemu_irq *i8259; 1291 1292 if (kvm_pic_in_kernel()) { 1293 i8259 = kvm_i8259_init(isa_bus); 1294 } else if (xen_enabled()) { 1295 i8259 = xen_interrupt_controller_init(); 1296 } else { 1297 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1298 } 1299 1300 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1301 i8259_irqs[i] = i8259[i]; 1302 } 1303 1304 g_free(i8259); 1305 } 1306 1307 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1308 Error **errp) 1309 { 1310 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1311 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1312 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1313 const MachineState *ms = MACHINE(hotplug_dev); 1314 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1315 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1316 Error *local_err = NULL; 1317 1318 /* 1319 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1320 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1321 * addition to cover this case. 1322 */ 1323 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1324 error_setg(errp, 1325 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1326 return; 1327 } 1328 1329 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1330 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1331 return; 1332 } 1333 1334 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1335 if (local_err) { 1336 error_propagate(errp, local_err); 1337 return; 1338 } 1339 1340 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1341 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1342 } 1343 1344 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1345 DeviceState *dev, Error **errp) 1346 { 1347 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1348 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1349 MachineState *ms = MACHINE(hotplug_dev); 1350 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1351 1352 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1353 1354 if (is_nvdimm) { 1355 nvdimm_plug(ms->nvdimms_state); 1356 } 1357 1358 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1359 } 1360 1361 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1362 DeviceState *dev, Error **errp) 1363 { 1364 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1365 1366 /* 1367 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1368 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1369 * addition to cover this case. 1370 */ 1371 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1372 error_setg(errp, 1373 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1374 return; 1375 } 1376 1377 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1378 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1379 return; 1380 } 1381 1382 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1383 errp); 1384 } 1385 1386 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1387 DeviceState *dev, Error **errp) 1388 { 1389 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1390 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1391 Error *local_err = NULL; 1392 1393 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1394 if (local_err) { 1395 goto out; 1396 } 1397 1398 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1399 qdev_unrealize(dev); 1400 out: 1401 error_propagate(errp, local_err); 1402 } 1403 1404 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1405 DeviceState *dev, Error **errp) 1406 { 1407 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1408 g_assert(!dev->hotplugged); 1409 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1410 errp); 1411 } 1412 1413 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1414 DeviceState *dev, Error **errp) 1415 { 1416 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1417 } 1418 1419 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1420 DeviceState *dev, Error **errp) 1421 { 1422 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1423 pc_memory_pre_plug(hotplug_dev, dev, errp); 1424 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1425 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1426 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1427 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1428 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1429 /* Declare the APIC range as the reserved MSI region */ 1430 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1431 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1432 QList *reserved_regions = qlist_new(); 1433 1434 qlist_append_str(reserved_regions, resv_prop_str); 1435 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1436 1437 g_free(resv_prop_str); 1438 } 1439 1440 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1441 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1442 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1443 1444 if (pcms->iommu) { 1445 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1446 "for x86 yet."); 1447 return; 1448 } 1449 pcms->iommu = dev; 1450 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1451 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1452 } 1453 } 1454 1455 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1456 DeviceState *dev, Error **errp) 1457 { 1458 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1459 pc_memory_plug(hotplug_dev, dev, errp); 1460 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1461 x86_cpu_plug(hotplug_dev, dev, errp); 1462 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1463 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1464 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1465 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1466 } 1467 } 1468 1469 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1470 DeviceState *dev, Error **errp) 1471 { 1472 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1473 pc_memory_unplug_request(hotplug_dev, dev, errp); 1474 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1475 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1476 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1477 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1478 errp); 1479 } else { 1480 error_setg(errp, "acpi: device unplug request for not supported device" 1481 " type: %s", object_get_typename(OBJECT(dev))); 1482 } 1483 } 1484 1485 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1486 DeviceState *dev, Error **errp) 1487 { 1488 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1489 pc_memory_unplug(hotplug_dev, dev, errp); 1490 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1491 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1492 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1493 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1494 } else { 1495 error_setg(errp, "acpi: device unplug for not supported device" 1496 " type: %s", object_get_typename(OBJECT(dev))); 1497 } 1498 } 1499 1500 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1501 DeviceState *dev) 1502 { 1503 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1504 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1505 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1506 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1507 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1508 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1509 return HOTPLUG_HANDLER(machine); 1510 } 1511 1512 return NULL; 1513 } 1514 1515 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1516 void *opaque, Error **errp) 1517 { 1518 PCMachineState *pcms = PC_MACHINE(obj); 1519 OnOffAuto vmport = pcms->vmport; 1520 1521 visit_type_OnOffAuto(v, name, &vmport, errp); 1522 } 1523 1524 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1525 void *opaque, Error **errp) 1526 { 1527 PCMachineState *pcms = PC_MACHINE(obj); 1528 1529 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1530 } 1531 1532 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1533 { 1534 PCMachineState *pcms = PC_MACHINE(obj); 1535 1536 return pcms->fd_bootchk; 1537 } 1538 1539 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1540 { 1541 PCMachineState *pcms = PC_MACHINE(obj); 1542 1543 pcms->fd_bootchk = value; 1544 } 1545 1546 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1547 { 1548 PCMachineState *pcms = PC_MACHINE(obj); 1549 1550 return pcms->smbus_enabled; 1551 } 1552 1553 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1554 { 1555 PCMachineState *pcms = PC_MACHINE(obj); 1556 1557 pcms->smbus_enabled = value; 1558 } 1559 1560 static bool pc_machine_get_sata(Object *obj, Error **errp) 1561 { 1562 PCMachineState *pcms = PC_MACHINE(obj); 1563 1564 return pcms->sata_enabled; 1565 } 1566 1567 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1568 { 1569 PCMachineState *pcms = PC_MACHINE(obj); 1570 1571 pcms->sata_enabled = value; 1572 } 1573 1574 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1575 { 1576 PCMachineState *pcms = PC_MACHINE(obj); 1577 1578 return pcms->hpet_enabled; 1579 } 1580 1581 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1582 { 1583 PCMachineState *pcms = PC_MACHINE(obj); 1584 1585 pcms->hpet_enabled = value; 1586 } 1587 1588 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1589 { 1590 PCMachineState *pcms = PC_MACHINE(obj); 1591 1592 return pcms->i8042_enabled; 1593 } 1594 1595 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1596 { 1597 PCMachineState *pcms = PC_MACHINE(obj); 1598 1599 pcms->i8042_enabled = value; 1600 } 1601 1602 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1603 { 1604 PCMachineState *pcms = PC_MACHINE(obj); 1605 1606 return pcms->default_bus_bypass_iommu; 1607 } 1608 1609 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1610 Error **errp) 1611 { 1612 PCMachineState *pcms = PC_MACHINE(obj); 1613 1614 pcms->default_bus_bypass_iommu = value; 1615 } 1616 1617 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1618 void *opaque, Error **errp) 1619 { 1620 PCMachineState *pcms = PC_MACHINE(obj); 1621 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1622 1623 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1624 } 1625 1626 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1627 void *opaque, Error **errp) 1628 { 1629 PCMachineState *pcms = PC_MACHINE(obj); 1630 1631 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1632 } 1633 1634 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1635 const char *name, void *opaque, 1636 Error **errp) 1637 { 1638 PCMachineState *pcms = PC_MACHINE(obj); 1639 uint64_t value = pcms->max_ram_below_4g; 1640 1641 visit_type_size(v, name, &value, errp); 1642 } 1643 1644 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1645 const char *name, void *opaque, 1646 Error **errp) 1647 { 1648 PCMachineState *pcms = PC_MACHINE(obj); 1649 uint64_t value; 1650 1651 if (!visit_type_size(v, name, &value, errp)) { 1652 return; 1653 } 1654 if (value > 4 * GiB) { 1655 error_setg(errp, 1656 "Machine option 'max-ram-below-4g=%"PRIu64 1657 "' expects size less than or equal to 4G", value); 1658 return; 1659 } 1660 1661 if (value < 1 * MiB) { 1662 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1663 "BIOS may not work with less than 1MiB", value); 1664 } 1665 1666 pcms->max_ram_below_4g = value; 1667 } 1668 1669 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1670 const char *name, void *opaque, 1671 Error **errp) 1672 { 1673 PCMachineState *pcms = PC_MACHINE(obj); 1674 uint64_t value = pcms->max_fw_size; 1675 1676 visit_type_size(v, name, &value, errp); 1677 } 1678 1679 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1680 const char *name, void *opaque, 1681 Error **errp) 1682 { 1683 PCMachineState *pcms = PC_MACHINE(obj); 1684 uint64_t value; 1685 1686 if (!visit_type_size(v, name, &value, errp)) { 1687 return; 1688 } 1689 1690 /* 1691 * We don't have a theoretically justifiable exact lower bound on the base 1692 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1693 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1694 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1695 * 16MiB in size. 1696 */ 1697 if (value > 16 * MiB) { 1698 error_setg(errp, 1699 "User specified max allowed firmware size %" PRIu64 " is " 1700 "greater than 16MiB. If combined firmware size exceeds " 1701 "16MiB the system may not boot, or experience intermittent" 1702 "stability issues.", 1703 value); 1704 return; 1705 } 1706 1707 pcms->max_fw_size = value; 1708 } 1709 1710 1711 static void pc_machine_initfn(Object *obj) 1712 { 1713 PCMachineState *pcms = PC_MACHINE(obj); 1714 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1715 1716 #ifdef CONFIG_VMPORT 1717 pcms->vmport = ON_OFF_AUTO_AUTO; 1718 #else 1719 pcms->vmport = ON_OFF_AUTO_OFF; 1720 #endif /* CONFIG_VMPORT */ 1721 pcms->max_ram_below_4g = 0; /* use default */ 1722 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1723 pcms->south_bridge = pcmc->default_south_bridge; 1724 1725 /* acpi build is enabled by default if machine supports it */ 1726 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1727 pcms->smbus_enabled = true; 1728 pcms->sata_enabled = true; 1729 pcms->i8042_enabled = true; 1730 pcms->max_fw_size = 8 * MiB; 1731 #ifdef CONFIG_HPET 1732 pcms->hpet_enabled = true; 1733 #endif 1734 pcms->fd_bootchk = true; 1735 pcms->default_bus_bypass_iommu = false; 1736 1737 pc_system_flash_create(pcms); 1738 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1739 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1740 OBJECT(pcms->pcspk), "audiodev"); 1741 cxl_machine_init(obj, &pcms->cxl_devices_state); 1742 1743 pcms->machine_done.notify = pc_machine_done; 1744 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1745 } 1746 1747 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1748 { 1749 CPUState *cs; 1750 X86CPU *cpu; 1751 1752 qemu_devices_reset(reason); 1753 1754 /* Reset APIC after devices have been reset to cancel 1755 * any changes that qemu_devices_reset() might have done. 1756 */ 1757 CPU_FOREACH(cs) { 1758 cpu = X86_CPU(cs); 1759 1760 x86_cpu_after_reset(cpu); 1761 } 1762 } 1763 1764 static void pc_machine_wakeup(MachineState *machine) 1765 { 1766 cpu_synchronize_all_states(); 1767 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1768 cpu_synchronize_all_post_reset(); 1769 } 1770 1771 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1772 { 1773 X86IOMMUState *iommu = x86_iommu_get_default(); 1774 IntelIOMMUState *intel_iommu; 1775 1776 if (iommu && 1777 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1778 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1779 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1780 if (!intel_iommu->caching_mode) { 1781 error_setg(errp, "Device assignment is not allowed without " 1782 "enabling caching-mode=on for Intel IOMMU."); 1783 return false; 1784 } 1785 } 1786 1787 return true; 1788 } 1789 1790 static void pc_machine_class_init(ObjectClass *oc, void *data) 1791 { 1792 MachineClass *mc = MACHINE_CLASS(oc); 1793 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1794 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1795 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1796 1797 pcmc->pci_enabled = true; 1798 pcmc->has_acpi_build = true; 1799 pcmc->rsdp_in_ram = true; 1800 pcmc->smbios_defaults = true; 1801 pcmc->smbios_uuid_encoded = true; 1802 pcmc->gigabyte_align = true; 1803 pcmc->has_reserved_memory = true; 1804 pcmc->enforce_aligned_dimm = true; 1805 pcmc->enforce_amd_1tb_hole = true; 1806 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1807 * to be used at the moment, 32K should be enough for a while. */ 1808 pcmc->acpi_data_size = 0x20000 + 0x8000; 1809 pcmc->pvh_enabled = true; 1810 pcmc->kvmclock_create_always = true; 1811 pcmc->resizable_acpi_blob = true; 1812 x86mc->apic_xrupt_override = true; 1813 assert(!mc->get_hotplug_handler); 1814 mc->get_hotplug_handler = pc_get_hotplug_handler; 1815 mc->hotplug_allowed = pc_hotplug_allowed; 1816 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1817 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1818 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1819 mc->auto_enable_numa_with_memhp = true; 1820 mc->auto_enable_numa_with_memdev = true; 1821 mc->has_hotpluggable_cpus = true; 1822 mc->default_boot_order = "cad"; 1823 mc->block_default_type = IF_IDE; 1824 mc->max_cpus = 255; 1825 mc->reset = pc_machine_reset; 1826 mc->wakeup = pc_machine_wakeup; 1827 hc->pre_plug = pc_machine_device_pre_plug_cb; 1828 hc->plug = pc_machine_device_plug_cb; 1829 hc->unplug_request = pc_machine_device_unplug_request_cb; 1830 hc->unplug = pc_machine_device_unplug_cb; 1831 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1832 mc->nvdimm_supported = true; 1833 mc->smp_props.dies_supported = true; 1834 mc->default_ram_id = "pc.ram"; 1835 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 1836 1837 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1838 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1839 NULL, NULL); 1840 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1841 "Maximum ram below the 4G boundary (32bit boundary)"); 1842 1843 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1844 pc_machine_get_vmport, pc_machine_set_vmport, 1845 NULL, NULL); 1846 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1847 "Enable vmport (pc & q35)"); 1848 1849 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1850 pc_machine_get_smbus, pc_machine_set_smbus); 1851 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1852 "Enable/disable system management bus"); 1853 1854 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1855 pc_machine_get_sata, pc_machine_set_sata); 1856 object_class_property_set_description(oc, PC_MACHINE_SATA, 1857 "Enable/disable Serial ATA bus"); 1858 1859 object_class_property_add_bool(oc, "hpet", 1860 pc_machine_get_hpet, pc_machine_set_hpet); 1861 object_class_property_set_description(oc, "hpet", 1862 "Enable/disable high precision event timer emulation"); 1863 1864 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1865 pc_machine_get_i8042, pc_machine_set_i8042); 1866 1867 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1868 pc_machine_get_default_bus_bypass_iommu, 1869 pc_machine_set_default_bus_bypass_iommu); 1870 1871 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1872 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1873 NULL, NULL); 1874 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1875 "Maximum combined firmware size"); 1876 1877 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1878 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1879 NULL, NULL); 1880 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1881 "SMBIOS Entry Point type [32, 64]"); 1882 1883 object_class_property_add_bool(oc, "fd-bootchk", 1884 pc_machine_get_fd_bootchk, 1885 pc_machine_set_fd_bootchk); 1886 } 1887 1888 static const TypeInfo pc_machine_info = { 1889 .name = TYPE_PC_MACHINE, 1890 .parent = TYPE_X86_MACHINE, 1891 .abstract = true, 1892 .instance_size = sizeof(PCMachineState), 1893 .instance_init = pc_machine_initfn, 1894 .class_size = sizeof(PCMachineClass), 1895 .class_init = pc_machine_class_init, 1896 .interfaces = (InterfaceInfo[]) { 1897 { TYPE_HOTPLUG_HANDLER }, 1898 { } 1899 }, 1900 }; 1901 1902 static void pc_machine_register_types(void) 1903 { 1904 type_register_static(&pc_machine_info); 1905 } 1906 1907 type_init(pc_machine_register_types) 1908