1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/block-backend.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/acpi/cpu_hotplug.h" 57 #include "hw/cpu/icc_bus.h" 58 #include "hw/boards.h" 59 #include "hw/pci/pci_host.h" 60 #include "acpi-build.h" 61 #include "hw/mem/pc-dimm.h" 62 #include "trace.h" 63 #include "qapi/visitor.h" 64 65 /* debug PC/ISA interrupts */ 66 //#define DEBUG_IRQ 67 68 #ifdef DEBUG_IRQ 69 #define DPRINTF(fmt, ...) \ 70 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 71 #else 72 #define DPRINTF(fmt, ...) 73 #endif 74 75 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 76 * (128K) and other BIOS datastructures (less than 4K reported to be used at 77 * the moment, 32K should be enough for a while). */ 78 static unsigned acpi_data_size = 0x20000 + 0x8000; 79 void pc_set_legacy_acpi_data_size(void) 80 { 81 acpi_data_size = 0x10000; 82 } 83 84 #define BIOS_CFG_IOPORT 0x510 85 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 86 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 87 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 88 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 89 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 90 91 #define E820_NR_ENTRIES 16 92 93 struct e820_entry { 94 uint64_t address; 95 uint64_t length; 96 uint32_t type; 97 } QEMU_PACKED __attribute((__aligned__(4))); 98 99 struct e820_table { 100 uint32_t count; 101 struct e820_entry entry[E820_NR_ENTRIES]; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 static struct e820_table e820_reserve; 105 static struct e820_entry *e820_table; 106 static unsigned e820_entries; 107 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 108 109 void gsi_handler(void *opaque, int n, int level) 110 { 111 GSIState *s = opaque; 112 113 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 114 if (n < ISA_NUM_IRQS) { 115 qemu_set_irq(s->i8259_irq[n], level); 116 } 117 qemu_set_irq(s->ioapic_irq[n], level); 118 } 119 120 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 121 unsigned size) 122 { 123 } 124 125 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 126 { 127 return 0xffffffffffffffffULL; 128 } 129 130 /* MSDOS compatibility mode FPU exception support */ 131 static qemu_irq ferr_irq; 132 133 void pc_register_ferr_irq(qemu_irq irq) 134 { 135 ferr_irq = irq; 136 } 137 138 /* XXX: add IGNNE support */ 139 void cpu_set_ferr(CPUX86State *s) 140 { 141 qemu_irq_raise(ferr_irq); 142 } 143 144 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 145 unsigned size) 146 { 147 qemu_irq_lower(ferr_irq); 148 } 149 150 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 151 { 152 return 0xffffffffffffffffULL; 153 } 154 155 /* TSC handling */ 156 uint64_t cpu_get_tsc(CPUX86State *env) 157 { 158 return cpu_get_ticks(); 159 } 160 161 /* SMM support */ 162 163 static cpu_set_smm_t smm_set; 164 static void *smm_arg; 165 166 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 167 { 168 assert(smm_set == NULL); 169 assert(smm_arg == NULL); 170 smm_set = callback; 171 smm_arg = arg; 172 } 173 174 void cpu_smm_update(CPUX86State *env) 175 { 176 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 177 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 178 } 179 } 180 181 182 /* IRQ handling */ 183 int cpu_get_pic_interrupt(CPUX86State *env) 184 { 185 X86CPU *cpu = x86_env_get_cpu(env); 186 int intno; 187 188 intno = apic_get_interrupt(cpu->apic_state); 189 if (intno >= 0) { 190 return intno; 191 } 192 /* read the irq from the PIC */ 193 if (!apic_accept_pic_intr(cpu->apic_state)) { 194 return -1; 195 } 196 197 intno = pic_read_irq(isa_pic); 198 return intno; 199 } 200 201 static void pic_irq_request(void *opaque, int irq, int level) 202 { 203 CPUState *cs = first_cpu; 204 X86CPU *cpu = X86_CPU(cs); 205 206 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 207 if (cpu->apic_state) { 208 CPU_FOREACH(cs) { 209 cpu = X86_CPU(cs); 210 if (apic_accept_pic_intr(cpu->apic_state)) { 211 apic_deliver_pic_intr(cpu->apic_state, level); 212 } 213 } 214 } else { 215 if (level) { 216 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 217 } else { 218 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 219 } 220 } 221 } 222 223 /* PC cmos mappings */ 224 225 #define REG_EQUIPMENT_BYTE 0x14 226 227 static int cmos_get_fd_drive_type(FDriveType fd0) 228 { 229 int val; 230 231 switch (fd0) { 232 case FDRIVE_DRV_144: 233 /* 1.44 Mb 3"5 drive */ 234 val = 4; 235 break; 236 case FDRIVE_DRV_288: 237 /* 2.88 Mb 3"5 drive */ 238 val = 5; 239 break; 240 case FDRIVE_DRV_120: 241 /* 1.2 Mb 5"5 drive */ 242 val = 2; 243 break; 244 case FDRIVE_DRV_NONE: 245 default: 246 val = 0; 247 break; 248 } 249 return val; 250 } 251 252 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 253 int16_t cylinders, int8_t heads, int8_t sectors) 254 { 255 rtc_set_memory(s, type_ofs, 47); 256 rtc_set_memory(s, info_ofs, cylinders); 257 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 258 rtc_set_memory(s, info_ofs + 2, heads); 259 rtc_set_memory(s, info_ofs + 3, 0xff); 260 rtc_set_memory(s, info_ofs + 4, 0xff); 261 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 262 rtc_set_memory(s, info_ofs + 6, cylinders); 263 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 264 rtc_set_memory(s, info_ofs + 8, sectors); 265 } 266 267 /* convert boot_device letter to something recognizable by the bios */ 268 static int boot_device2nibble(char boot_device) 269 { 270 switch(boot_device) { 271 case 'a': 272 case 'b': 273 return 0x01; /* floppy boot */ 274 case 'c': 275 return 0x02; /* hard drive boot */ 276 case 'd': 277 return 0x03; /* CD-ROM boot */ 278 case 'n': 279 return 0x04; /* Network boot */ 280 } 281 return 0; 282 } 283 284 static int set_boot_dev(ISADevice *s, const char *boot_device) 285 { 286 #define PC_MAX_BOOT_DEVICES 3 287 int nbds, bds[3] = { 0, }; 288 int i; 289 290 nbds = strlen(boot_device); 291 if (nbds > PC_MAX_BOOT_DEVICES) { 292 error_report("Too many boot devices for PC"); 293 return(1); 294 } 295 for (i = 0; i < nbds; i++) { 296 bds[i] = boot_device2nibble(boot_device[i]); 297 if (bds[i] == 0) { 298 error_report("Invalid boot device for PC: '%c'", 299 boot_device[i]); 300 return(1); 301 } 302 } 303 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 304 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 305 return(0); 306 } 307 308 static int pc_boot_set(void *opaque, const char *boot_device) 309 { 310 return set_boot_dev(opaque, boot_device); 311 } 312 313 typedef struct pc_cmos_init_late_arg { 314 ISADevice *rtc_state; 315 BusState *idebus[2]; 316 } pc_cmos_init_late_arg; 317 318 static void pc_cmos_init_late(void *opaque) 319 { 320 pc_cmos_init_late_arg *arg = opaque; 321 ISADevice *s = arg->rtc_state; 322 int16_t cylinders; 323 int8_t heads, sectors; 324 int val; 325 int i, trans; 326 327 val = 0; 328 if (ide_get_geometry(arg->idebus[0], 0, 329 &cylinders, &heads, §ors) >= 0) { 330 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 331 val |= 0xf0; 332 } 333 if (ide_get_geometry(arg->idebus[0], 1, 334 &cylinders, &heads, §ors) >= 0) { 335 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 336 val |= 0x0f; 337 } 338 rtc_set_memory(s, 0x12, val); 339 340 val = 0; 341 for (i = 0; i < 4; i++) { 342 /* NOTE: ide_get_geometry() returns the physical 343 geometry. It is always such that: 1 <= sects <= 63, 1 344 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 345 geometry can be different if a translation is done. */ 346 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 347 &cylinders, &heads, §ors) >= 0) { 348 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 349 assert((trans & ~3) == 0); 350 val |= trans << (i * 2); 351 } 352 } 353 rtc_set_memory(s, 0x39, val); 354 355 qemu_unregister_reset(pc_cmos_init_late, opaque); 356 } 357 358 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 359 const char *boot_device, MachineState *machine, 360 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 361 ISADevice *s) 362 { 363 int val, nb, i; 364 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 365 static pc_cmos_init_late_arg arg; 366 PCMachineState *pc_machine = PC_MACHINE(machine); 367 368 /* various important CMOS locations needed by PC/Bochs bios */ 369 370 /* memory size */ 371 /* base memory (first MiB) */ 372 val = MIN(ram_size / 1024, 640); 373 rtc_set_memory(s, 0x15, val); 374 rtc_set_memory(s, 0x16, val >> 8); 375 /* extended memory (next 64MiB) */ 376 if (ram_size > 1024 * 1024) { 377 val = (ram_size - 1024 * 1024) / 1024; 378 } else { 379 val = 0; 380 } 381 if (val > 65535) 382 val = 65535; 383 rtc_set_memory(s, 0x17, val); 384 rtc_set_memory(s, 0x18, val >> 8); 385 rtc_set_memory(s, 0x30, val); 386 rtc_set_memory(s, 0x31, val >> 8); 387 /* memory between 16MiB and 4GiB */ 388 if (ram_size > 16 * 1024 * 1024) { 389 val = (ram_size - 16 * 1024 * 1024) / 65536; 390 } else { 391 val = 0; 392 } 393 if (val > 65535) 394 val = 65535; 395 rtc_set_memory(s, 0x34, val); 396 rtc_set_memory(s, 0x35, val >> 8); 397 /* memory above 4GiB */ 398 val = above_4g_mem_size / 65536; 399 rtc_set_memory(s, 0x5b, val); 400 rtc_set_memory(s, 0x5c, val >> 8); 401 rtc_set_memory(s, 0x5d, val >> 16); 402 403 /* set the number of CPU */ 404 rtc_set_memory(s, 0x5f, smp_cpus - 1); 405 406 object_property_add_link(OBJECT(machine), "rtc_state", 407 TYPE_ISA_DEVICE, 408 (Object **)&pc_machine->rtc, 409 object_property_allow_set_link, 410 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 411 object_property_set_link(OBJECT(machine), OBJECT(s), 412 "rtc_state", &error_abort); 413 414 if (set_boot_dev(s, boot_device)) { 415 exit(1); 416 } 417 418 /* floppy type */ 419 if (floppy) { 420 for (i = 0; i < 2; i++) { 421 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 422 } 423 } 424 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 425 cmos_get_fd_drive_type(fd_type[1]); 426 rtc_set_memory(s, 0x10, val); 427 428 val = 0; 429 nb = 0; 430 if (fd_type[0] < FDRIVE_DRV_NONE) { 431 nb++; 432 } 433 if (fd_type[1] < FDRIVE_DRV_NONE) { 434 nb++; 435 } 436 switch (nb) { 437 case 0: 438 break; 439 case 1: 440 val |= 0x01; /* 1 drive, ready for boot */ 441 break; 442 case 2: 443 val |= 0x41; /* 2 drives, ready for boot */ 444 break; 445 } 446 val |= 0x02; /* FPU is there */ 447 val |= 0x04; /* PS/2 mouse installed */ 448 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 449 450 /* hard drives */ 451 arg.rtc_state = s; 452 arg.idebus[0] = idebus0; 453 arg.idebus[1] = idebus1; 454 qemu_register_reset(pc_cmos_init_late, &arg); 455 } 456 457 #define TYPE_PORT92 "port92" 458 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 459 460 /* port 92 stuff: could be split off */ 461 typedef struct Port92State { 462 ISADevice parent_obj; 463 464 MemoryRegion io; 465 uint8_t outport; 466 qemu_irq *a20_out; 467 } Port92State; 468 469 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 470 unsigned size) 471 { 472 Port92State *s = opaque; 473 int oldval = s->outport; 474 475 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 476 s->outport = val; 477 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 478 if ((val & 1) && !(oldval & 1)) { 479 qemu_system_reset_request(); 480 } 481 } 482 483 static uint64_t port92_read(void *opaque, hwaddr addr, 484 unsigned size) 485 { 486 Port92State *s = opaque; 487 uint32_t ret; 488 489 ret = s->outport; 490 DPRINTF("port92: read 0x%02x\n", ret); 491 return ret; 492 } 493 494 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 495 { 496 Port92State *s = PORT92(dev); 497 498 s->a20_out = a20_out; 499 } 500 501 static const VMStateDescription vmstate_port92_isa = { 502 .name = "port92", 503 .version_id = 1, 504 .minimum_version_id = 1, 505 .fields = (VMStateField[]) { 506 VMSTATE_UINT8(outport, Port92State), 507 VMSTATE_END_OF_LIST() 508 } 509 }; 510 511 static void port92_reset(DeviceState *d) 512 { 513 Port92State *s = PORT92(d); 514 515 s->outport &= ~1; 516 } 517 518 static const MemoryRegionOps port92_ops = { 519 .read = port92_read, 520 .write = port92_write, 521 .impl = { 522 .min_access_size = 1, 523 .max_access_size = 1, 524 }, 525 .endianness = DEVICE_LITTLE_ENDIAN, 526 }; 527 528 static void port92_initfn(Object *obj) 529 { 530 Port92State *s = PORT92(obj); 531 532 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 533 534 s->outport = 0; 535 } 536 537 static void port92_realizefn(DeviceState *dev, Error **errp) 538 { 539 ISADevice *isadev = ISA_DEVICE(dev); 540 Port92State *s = PORT92(dev); 541 542 isa_register_ioport(isadev, &s->io, 0x92); 543 } 544 545 static void port92_class_initfn(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 549 dc->realize = port92_realizefn; 550 dc->reset = port92_reset; 551 dc->vmsd = &vmstate_port92_isa; 552 /* 553 * Reason: unlike ordinary ISA devices, this one needs additional 554 * wiring: its A20 output line needs to be wired up by 555 * port92_init(). 556 */ 557 dc->cannot_instantiate_with_device_add_yet = true; 558 } 559 560 static const TypeInfo port92_info = { 561 .name = TYPE_PORT92, 562 .parent = TYPE_ISA_DEVICE, 563 .instance_size = sizeof(Port92State), 564 .instance_init = port92_initfn, 565 .class_init = port92_class_initfn, 566 }; 567 568 static void port92_register_types(void) 569 { 570 type_register_static(&port92_info); 571 } 572 573 type_init(port92_register_types) 574 575 static void handle_a20_line_change(void *opaque, int irq, int level) 576 { 577 X86CPU *cpu = opaque; 578 579 /* XXX: send to all CPUs ? */ 580 /* XXX: add logic to handle multiple A20 line sources */ 581 x86_cpu_set_a20(cpu, level); 582 } 583 584 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 585 { 586 int index = le32_to_cpu(e820_reserve.count); 587 struct e820_entry *entry; 588 589 if (type != E820_RAM) { 590 /* old FW_CFG_E820_TABLE entry -- reservations only */ 591 if (index >= E820_NR_ENTRIES) { 592 return -EBUSY; 593 } 594 entry = &e820_reserve.entry[index++]; 595 596 entry->address = cpu_to_le64(address); 597 entry->length = cpu_to_le64(length); 598 entry->type = cpu_to_le32(type); 599 600 e820_reserve.count = cpu_to_le32(index); 601 } 602 603 /* new "etc/e820" file -- include ram too */ 604 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 605 e820_table[e820_entries].address = cpu_to_le64(address); 606 e820_table[e820_entries].length = cpu_to_le64(length); 607 e820_table[e820_entries].type = cpu_to_le32(type); 608 e820_entries++; 609 610 return e820_entries; 611 } 612 613 int e820_get_num_entries(void) 614 { 615 return e820_entries; 616 } 617 618 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 619 { 620 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 621 *address = le64_to_cpu(e820_table[idx].address); 622 *length = le64_to_cpu(e820_table[idx].length); 623 return true; 624 } 625 return false; 626 } 627 628 /* Calculates the limit to CPU APIC ID values 629 * 630 * This function returns the limit for the APIC ID value, so that all 631 * CPU APIC IDs are < pc_apic_id_limit(). 632 * 633 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 634 */ 635 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 636 { 637 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 638 } 639 640 static FWCfgState *bochs_bios_init(void) 641 { 642 FWCfgState *fw_cfg; 643 uint8_t *smbios_tables, *smbios_anchor; 644 size_t smbios_tables_len, smbios_anchor_len; 645 uint64_t *numa_fw_cfg; 646 int i, j; 647 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 648 649 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 650 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 651 * 652 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 653 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 654 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 655 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 656 * may see". 657 * 658 * So, this means we must not use max_cpus, here, but the maximum possible 659 * APIC ID value, plus one. 660 * 661 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 662 * the APIC ID, not the "CPU index" 663 */ 664 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 665 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 666 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 667 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 668 acpi_tables, acpi_tables_len); 669 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 670 671 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 672 if (smbios_tables) { 673 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 674 smbios_tables, smbios_tables_len); 675 } 676 677 smbios_get_tables(&smbios_tables, &smbios_tables_len, 678 &smbios_anchor, &smbios_anchor_len); 679 if (smbios_anchor) { 680 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 681 smbios_tables, smbios_tables_len); 682 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 683 smbios_anchor, smbios_anchor_len); 684 } 685 686 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 687 &e820_reserve, sizeof(e820_reserve)); 688 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 689 sizeof(struct e820_entry) * e820_entries); 690 691 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 692 /* allocate memory for the NUMA channel: one (64bit) word for the number 693 * of nodes, one word for each VCPU->node and one word for each node to 694 * hold the amount of memory. 695 */ 696 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 697 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 698 for (i = 0; i < max_cpus; i++) { 699 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 700 assert(apic_id < apic_id_limit); 701 for (j = 0; j < nb_numa_nodes; j++) { 702 if (test_bit(i, numa_info[j].node_cpu)) { 703 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 704 break; 705 } 706 } 707 } 708 for (i = 0; i < nb_numa_nodes; i++) { 709 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 710 } 711 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 712 (1 + apic_id_limit + nb_numa_nodes) * 713 sizeof(*numa_fw_cfg)); 714 715 return fw_cfg; 716 } 717 718 static long get_file_size(FILE *f) 719 { 720 long where, size; 721 722 /* XXX: on Unix systems, using fstat() probably makes more sense */ 723 724 where = ftell(f); 725 fseek(f, 0, SEEK_END); 726 size = ftell(f); 727 fseek(f, where, SEEK_SET); 728 729 return size; 730 } 731 732 static void load_linux(FWCfgState *fw_cfg, 733 const char *kernel_filename, 734 const char *initrd_filename, 735 const char *kernel_cmdline, 736 hwaddr max_ram_size) 737 { 738 uint16_t protocol; 739 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 740 uint32_t initrd_max; 741 uint8_t header[8192], *setup, *kernel, *initrd_data; 742 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 743 FILE *f; 744 char *vmode; 745 746 /* Align to 16 bytes as a paranoia measure */ 747 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 748 749 /* load the kernel header */ 750 f = fopen(kernel_filename, "rb"); 751 if (!f || !(kernel_size = get_file_size(f)) || 752 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 753 MIN(ARRAY_SIZE(header), kernel_size)) { 754 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 755 kernel_filename, strerror(errno)); 756 exit(1); 757 } 758 759 /* kernel protocol version */ 760 #if 0 761 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 762 #endif 763 if (ldl_p(header+0x202) == 0x53726448) { 764 protocol = lduw_p(header+0x206); 765 } else { 766 /* This looks like a multiboot kernel. If it is, let's stop 767 treating it like a Linux kernel. */ 768 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 769 kernel_cmdline, kernel_size, header)) { 770 return; 771 } 772 protocol = 0; 773 } 774 775 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 776 /* Low kernel */ 777 real_addr = 0x90000; 778 cmdline_addr = 0x9a000 - cmdline_size; 779 prot_addr = 0x10000; 780 } else if (protocol < 0x202) { 781 /* High but ancient kernel */ 782 real_addr = 0x90000; 783 cmdline_addr = 0x9a000 - cmdline_size; 784 prot_addr = 0x100000; 785 } else { 786 /* High and recent kernel */ 787 real_addr = 0x10000; 788 cmdline_addr = 0x20000; 789 prot_addr = 0x100000; 790 } 791 792 #if 0 793 fprintf(stderr, 794 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 795 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 796 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 797 real_addr, 798 cmdline_addr, 799 prot_addr); 800 #endif 801 802 /* highest address for loading the initrd */ 803 if (protocol >= 0x203) { 804 initrd_max = ldl_p(header+0x22c); 805 } else { 806 initrd_max = 0x37ffffff; 807 } 808 809 if (initrd_max >= max_ram_size - acpi_data_size) { 810 initrd_max = max_ram_size - acpi_data_size - 1; 811 } 812 813 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 814 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 815 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 816 817 if (protocol >= 0x202) { 818 stl_p(header+0x228, cmdline_addr); 819 } else { 820 stw_p(header+0x20, 0xA33F); 821 stw_p(header+0x22, cmdline_addr-real_addr); 822 } 823 824 /* handle vga= parameter */ 825 vmode = strstr(kernel_cmdline, "vga="); 826 if (vmode) { 827 unsigned int video_mode; 828 /* skip "vga=" */ 829 vmode += 4; 830 if (!strncmp(vmode, "normal", 6)) { 831 video_mode = 0xffff; 832 } else if (!strncmp(vmode, "ext", 3)) { 833 video_mode = 0xfffe; 834 } else if (!strncmp(vmode, "ask", 3)) { 835 video_mode = 0xfffd; 836 } else { 837 video_mode = strtol(vmode, NULL, 0); 838 } 839 stw_p(header+0x1fa, video_mode); 840 } 841 842 /* loader type */ 843 /* High nybble = B reserved for QEMU; low nybble is revision number. 844 If this code is substantially changed, you may want to consider 845 incrementing the revision. */ 846 if (protocol >= 0x200) { 847 header[0x210] = 0xB0; 848 } 849 /* heap */ 850 if (protocol >= 0x201) { 851 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 852 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 853 } 854 855 /* load initrd */ 856 if (initrd_filename) { 857 if (protocol < 0x200) { 858 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 859 exit(1); 860 } 861 862 initrd_size = get_image_size(initrd_filename); 863 if (initrd_size < 0) { 864 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 865 initrd_filename, strerror(errno)); 866 exit(1); 867 } 868 869 initrd_addr = (initrd_max-initrd_size) & ~4095; 870 871 initrd_data = g_malloc(initrd_size); 872 load_image(initrd_filename, initrd_data); 873 874 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 875 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 876 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 877 878 stl_p(header+0x218, initrd_addr); 879 stl_p(header+0x21c, initrd_size); 880 } 881 882 /* load kernel and setup */ 883 setup_size = header[0x1f1]; 884 if (setup_size == 0) { 885 setup_size = 4; 886 } 887 setup_size = (setup_size+1)*512; 888 kernel_size -= setup_size; 889 890 setup = g_malloc(setup_size); 891 kernel = g_malloc(kernel_size); 892 fseek(f, 0, SEEK_SET); 893 if (fread(setup, 1, setup_size, f) != setup_size) { 894 fprintf(stderr, "fread() failed\n"); 895 exit(1); 896 } 897 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 898 fprintf(stderr, "fread() failed\n"); 899 exit(1); 900 } 901 fclose(f); 902 memcpy(setup, header, MIN(sizeof(header), setup_size)); 903 904 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 905 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 906 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 907 908 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 909 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 910 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 911 912 option_rom[nb_option_roms].name = "linuxboot.bin"; 913 option_rom[nb_option_roms].bootindex = 0; 914 nb_option_roms++; 915 } 916 917 #define NE2000_NB_MAX 6 918 919 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 920 0x280, 0x380 }; 921 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 922 923 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 924 { 925 static int nb_ne2k = 0; 926 927 if (nb_ne2k == NE2000_NB_MAX) 928 return; 929 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 930 ne2000_irq[nb_ne2k], nd); 931 nb_ne2k++; 932 } 933 934 DeviceState *cpu_get_current_apic(void) 935 { 936 if (current_cpu) { 937 X86CPU *cpu = X86_CPU(current_cpu); 938 return cpu->apic_state; 939 } else { 940 return NULL; 941 } 942 } 943 944 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 945 { 946 X86CPU *cpu = opaque; 947 948 if (level) { 949 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 950 } 951 } 952 953 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 954 DeviceState *icc_bridge, Error **errp) 955 { 956 X86CPU *cpu; 957 Error *local_err = NULL; 958 959 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 960 if (local_err != NULL) { 961 error_propagate(errp, local_err); 962 return NULL; 963 } 964 965 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 966 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 967 968 if (local_err) { 969 error_propagate(errp, local_err); 970 object_unref(OBJECT(cpu)); 971 cpu = NULL; 972 } 973 return cpu; 974 } 975 976 static const char *current_cpu_model; 977 978 void pc_hot_add_cpu(const int64_t id, Error **errp) 979 { 980 DeviceState *icc_bridge; 981 int64_t apic_id = x86_cpu_apic_id_from_index(id); 982 983 if (id < 0) { 984 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 985 return; 986 } 987 988 if (cpu_exists(apic_id)) { 989 error_setg(errp, "Unable to add CPU: %" PRIi64 990 ", it already exists", id); 991 return; 992 } 993 994 if (id >= max_cpus) { 995 error_setg(errp, "Unable to add CPU: %" PRIi64 996 ", max allowed: %d", id, max_cpus - 1); 997 return; 998 } 999 1000 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1001 error_setg(errp, "Unable to add CPU: %" PRIi64 1002 ", resulting APIC ID (%" PRIi64 ") is too large", 1003 id, apic_id); 1004 return; 1005 } 1006 1007 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1008 TYPE_ICC_BRIDGE, NULL)); 1009 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1010 } 1011 1012 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1013 { 1014 int i; 1015 X86CPU *cpu = NULL; 1016 Error *error = NULL; 1017 unsigned long apic_id_limit; 1018 1019 /* init CPUs */ 1020 if (cpu_model == NULL) { 1021 #ifdef TARGET_X86_64 1022 cpu_model = "qemu64"; 1023 #else 1024 cpu_model = "qemu32"; 1025 #endif 1026 } 1027 current_cpu_model = cpu_model; 1028 1029 apic_id_limit = pc_apic_id_limit(max_cpus); 1030 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1031 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1032 apic_id_limit - 1); 1033 exit(1); 1034 } 1035 1036 for (i = 0; i < smp_cpus; i++) { 1037 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1038 icc_bridge, &error); 1039 if (error) { 1040 error_report("%s", error_get_pretty(error)); 1041 error_free(error); 1042 exit(1); 1043 } 1044 } 1045 1046 /* map APIC MMIO area if CPU has APIC */ 1047 if (cpu && cpu->apic_state) { 1048 /* XXX: what if the base changes? */ 1049 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1050 APIC_DEFAULT_ADDRESS, 0x1000); 1051 } 1052 1053 /* tell smbios about cpuid version and features */ 1054 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1055 } 1056 1057 /* pci-info ROM file. Little endian format */ 1058 typedef struct PcRomPciInfo { 1059 uint64_t w32_min; 1060 uint64_t w32_max; 1061 uint64_t w64_min; 1062 uint64_t w64_max; 1063 } PcRomPciInfo; 1064 1065 typedef struct PcGuestInfoState { 1066 PcGuestInfo info; 1067 Notifier machine_done; 1068 } PcGuestInfoState; 1069 1070 static 1071 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1072 { 1073 PcGuestInfoState *guest_info_state = container_of(notifier, 1074 PcGuestInfoState, 1075 machine_done); 1076 acpi_setup(&guest_info_state->info); 1077 } 1078 1079 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1080 ram_addr_t above_4g_mem_size) 1081 { 1082 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1083 PcGuestInfo *guest_info = &guest_info_state->info; 1084 int i, j; 1085 1086 guest_info->ram_size_below_4g = below_4g_mem_size; 1087 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1088 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1089 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1090 guest_info->numa_nodes = nb_numa_nodes; 1091 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1092 sizeof *guest_info->node_mem); 1093 for (i = 0; i < nb_numa_nodes; i++) { 1094 guest_info->node_mem[i] = numa_info[i].node_mem; 1095 } 1096 1097 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1098 sizeof *guest_info->node_cpu); 1099 1100 for (i = 0; i < max_cpus; i++) { 1101 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1102 assert(apic_id < guest_info->apic_id_limit); 1103 for (j = 0; j < nb_numa_nodes; j++) { 1104 if (test_bit(i, numa_info[j].node_cpu)) { 1105 guest_info->node_cpu[apic_id] = j; 1106 break; 1107 } 1108 } 1109 } 1110 1111 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1112 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1113 return guest_info; 1114 } 1115 1116 /* setup pci memory address space mapping into system address space */ 1117 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1118 MemoryRegion *pci_address_space) 1119 { 1120 /* Set to lower priority than RAM */ 1121 memory_region_add_subregion_overlap(system_memory, 0x0, 1122 pci_address_space, -1); 1123 } 1124 1125 void pc_acpi_init(const char *default_dsdt) 1126 { 1127 char *filename; 1128 1129 if (acpi_tables != NULL) { 1130 /* manually set via -acpitable, leave it alone */ 1131 return; 1132 } 1133 1134 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1135 if (filename == NULL) { 1136 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1137 } else { 1138 char *arg; 1139 QemuOpts *opts; 1140 Error *err = NULL; 1141 1142 arg = g_strdup_printf("file=%s", filename); 1143 1144 /* creates a deep copy of "arg" */ 1145 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1146 g_assert(opts != NULL); 1147 1148 acpi_table_add_builtin(opts, &err); 1149 if (err) { 1150 error_report("WARNING: failed to load %s: %s", filename, 1151 error_get_pretty(err)); 1152 error_free(err); 1153 } 1154 g_free(arg); 1155 g_free(filename); 1156 } 1157 } 1158 1159 FWCfgState *xen_load_linux(const char *kernel_filename, 1160 const char *kernel_cmdline, 1161 const char *initrd_filename, 1162 ram_addr_t below_4g_mem_size, 1163 PcGuestInfo *guest_info) 1164 { 1165 int i; 1166 FWCfgState *fw_cfg; 1167 1168 assert(kernel_filename != NULL); 1169 1170 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 1171 rom_set_fw(fw_cfg); 1172 1173 load_linux(fw_cfg, kernel_filename, initrd_filename, 1174 kernel_cmdline, below_4g_mem_size); 1175 for (i = 0; i < nb_option_roms; i++) { 1176 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1177 !strcmp(option_rom[i].name, "multiboot.bin")); 1178 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1179 } 1180 guest_info->fw_cfg = fw_cfg; 1181 return fw_cfg; 1182 } 1183 1184 FWCfgState *pc_memory_init(MachineState *machine, 1185 MemoryRegion *system_memory, 1186 ram_addr_t below_4g_mem_size, 1187 ram_addr_t above_4g_mem_size, 1188 MemoryRegion *rom_memory, 1189 MemoryRegion **ram_memory, 1190 PcGuestInfo *guest_info) 1191 { 1192 int linux_boot, i; 1193 MemoryRegion *ram, *option_rom_mr; 1194 MemoryRegion *ram_below_4g, *ram_above_4g; 1195 FWCfgState *fw_cfg; 1196 PCMachineState *pcms = PC_MACHINE(machine); 1197 1198 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1199 1200 linux_boot = (machine->kernel_filename != NULL); 1201 1202 /* Allocate RAM. We allocate it as a single memory region and use 1203 * aliases to address portions of it, mostly for backwards compatibility 1204 * with older qemus that used qemu_ram_alloc(). 1205 */ 1206 ram = g_malloc(sizeof(*ram)); 1207 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1208 machine->ram_size); 1209 *ram_memory = ram; 1210 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1211 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1212 0, below_4g_mem_size); 1213 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1214 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1215 if (above_4g_mem_size > 0) { 1216 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1217 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1218 below_4g_mem_size, above_4g_mem_size); 1219 memory_region_add_subregion(system_memory, 0x100000000ULL, 1220 ram_above_4g); 1221 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1222 } 1223 1224 if (!guest_info->has_reserved_memory && 1225 (machine->ram_slots || 1226 (machine->maxram_size > machine->ram_size))) { 1227 MachineClass *mc = MACHINE_GET_CLASS(machine); 1228 1229 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1230 mc->name); 1231 exit(EXIT_FAILURE); 1232 } 1233 1234 /* initialize hotplug memory address space */ 1235 if (guest_info->has_reserved_memory && 1236 (machine->ram_size < machine->maxram_size)) { 1237 ram_addr_t hotplug_mem_size = 1238 machine->maxram_size - machine->ram_size; 1239 1240 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1241 error_report("unsupported amount of memory slots: %"PRIu64, 1242 machine->ram_slots); 1243 exit(EXIT_FAILURE); 1244 } 1245 1246 pcms->hotplug_memory_base = 1247 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1248 1249 if (pcms->enforce_aligned_dimm) { 1250 /* size hotplug region assuming 1G page max alignment per slot */ 1251 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1252 } 1253 1254 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1255 hotplug_mem_size) { 1256 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1257 machine->maxram_size); 1258 exit(EXIT_FAILURE); 1259 } 1260 1261 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1262 "hotplug-memory", hotplug_mem_size); 1263 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1264 &pcms->hotplug_memory); 1265 } 1266 1267 /* Initialize PC system firmware */ 1268 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1269 1270 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1271 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1272 &error_abort); 1273 vmstate_register_ram_global(option_rom_mr); 1274 memory_region_add_subregion_overlap(rom_memory, 1275 PC_ROM_MIN_VGA, 1276 option_rom_mr, 1277 1); 1278 1279 fw_cfg = bochs_bios_init(); 1280 rom_set_fw(fw_cfg); 1281 1282 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1283 uint64_t *val = g_malloc(sizeof(*val)); 1284 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1285 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1286 } 1287 1288 if (linux_boot) { 1289 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1290 machine->kernel_cmdline, below_4g_mem_size); 1291 } 1292 1293 for (i = 0; i < nb_option_roms; i++) { 1294 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1295 } 1296 guest_info->fw_cfg = fw_cfg; 1297 return fw_cfg; 1298 } 1299 1300 qemu_irq *pc_allocate_cpu_irq(void) 1301 { 1302 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1303 } 1304 1305 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1306 { 1307 DeviceState *dev = NULL; 1308 1309 if (pci_bus) { 1310 PCIDevice *pcidev = pci_vga_init(pci_bus); 1311 dev = pcidev ? &pcidev->qdev : NULL; 1312 } else if (isa_bus) { 1313 ISADevice *isadev = isa_vga_init(isa_bus); 1314 dev = isadev ? DEVICE(isadev) : NULL; 1315 } 1316 return dev; 1317 } 1318 1319 static void cpu_request_exit(void *opaque, int irq, int level) 1320 { 1321 CPUState *cpu = current_cpu; 1322 1323 if (cpu && level) { 1324 cpu_exit(cpu); 1325 } 1326 } 1327 1328 static const MemoryRegionOps ioport80_io_ops = { 1329 .write = ioport80_write, 1330 .read = ioport80_read, 1331 .endianness = DEVICE_NATIVE_ENDIAN, 1332 .impl = { 1333 .min_access_size = 1, 1334 .max_access_size = 1, 1335 }, 1336 }; 1337 1338 static const MemoryRegionOps ioportF0_io_ops = { 1339 .write = ioportF0_write, 1340 .read = ioportF0_read, 1341 .endianness = DEVICE_NATIVE_ENDIAN, 1342 .impl = { 1343 .min_access_size = 1, 1344 .max_access_size = 1, 1345 }, 1346 }; 1347 1348 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1349 ISADevice **rtc_state, 1350 ISADevice **floppy, 1351 bool no_vmport, 1352 uint32 hpet_irqs) 1353 { 1354 int i; 1355 DriveInfo *fd[MAX_FD]; 1356 DeviceState *hpet = NULL; 1357 int pit_isa_irq = 0; 1358 qemu_irq pit_alt_irq = NULL; 1359 qemu_irq rtc_irq = NULL; 1360 qemu_irq *a20_line; 1361 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1362 qemu_irq *cpu_exit_irq; 1363 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1364 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1365 1366 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1367 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1368 1369 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1370 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1371 1372 /* 1373 * Check if an HPET shall be created. 1374 * 1375 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1376 * when the HPET wants to take over. Thus we have to disable the latter. 1377 */ 1378 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1379 /* In order to set property, here not using sysbus_try_create_simple */ 1380 hpet = qdev_try_create(NULL, TYPE_HPET); 1381 if (hpet) { 1382 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1383 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1384 * IRQ8 and IRQ2. 1385 */ 1386 uint8_t compat = object_property_get_int(OBJECT(hpet), 1387 HPET_INTCAP, NULL); 1388 if (!compat) { 1389 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1390 } 1391 qdev_init_nofail(hpet); 1392 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1393 1394 for (i = 0; i < GSI_NUM_PINS; i++) { 1395 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1396 } 1397 pit_isa_irq = -1; 1398 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1399 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1400 } 1401 } 1402 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1403 1404 qemu_register_boot_set(pc_boot_set, *rtc_state); 1405 1406 if (!xen_enabled()) { 1407 if (kvm_irqchip_in_kernel()) { 1408 pit = kvm_pit_init(isa_bus, 0x40); 1409 } else { 1410 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1411 } 1412 if (hpet) { 1413 /* connect PIT to output control line of the HPET */ 1414 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1415 } 1416 pcspk_init(isa_bus, pit); 1417 } 1418 1419 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1420 if (serial_hds[i]) { 1421 serial_isa_init(isa_bus, i, serial_hds[i]); 1422 } 1423 } 1424 1425 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1426 if (parallel_hds[i]) { 1427 parallel_init(isa_bus, i, parallel_hds[i]); 1428 } 1429 } 1430 1431 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1432 i8042 = isa_create_simple(isa_bus, "i8042"); 1433 i8042_setup_a20_line(i8042, &a20_line[0]); 1434 if (!no_vmport) { 1435 vmport_init(isa_bus); 1436 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1437 } else { 1438 vmmouse = NULL; 1439 } 1440 if (vmmouse) { 1441 DeviceState *dev = DEVICE(vmmouse); 1442 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1443 qdev_init_nofail(dev); 1444 } 1445 port92 = isa_create_simple(isa_bus, "port92"); 1446 port92_init(port92, &a20_line[1]); 1447 1448 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1449 DMA_init(0, cpu_exit_irq); 1450 1451 for(i = 0; i < MAX_FD; i++) { 1452 fd[i] = drive_get(IF_FLOPPY, 0, i); 1453 } 1454 *floppy = fdctrl_init_isa(isa_bus, fd); 1455 } 1456 1457 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1458 { 1459 int i; 1460 1461 for (i = 0; i < nb_nics; i++) { 1462 NICInfo *nd = &nd_table[i]; 1463 1464 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1465 pc_init_ne2k_isa(isa_bus, nd); 1466 } else { 1467 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1468 } 1469 } 1470 } 1471 1472 void pc_pci_device_init(PCIBus *pci_bus) 1473 { 1474 int max_bus; 1475 int bus; 1476 1477 max_bus = drive_get_max_bus(IF_SCSI); 1478 for (bus = 0; bus <= max_bus; bus++) { 1479 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1480 } 1481 } 1482 1483 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1484 { 1485 DeviceState *dev; 1486 SysBusDevice *d; 1487 unsigned int i; 1488 1489 if (kvm_irqchip_in_kernel()) { 1490 dev = qdev_create(NULL, "kvm-ioapic"); 1491 } else { 1492 dev = qdev_create(NULL, "ioapic"); 1493 } 1494 if (parent_name) { 1495 object_property_add_child(object_resolve_path(parent_name, NULL), 1496 "ioapic", OBJECT(dev), NULL); 1497 } 1498 qdev_init_nofail(dev); 1499 d = SYS_BUS_DEVICE(dev); 1500 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1501 1502 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1503 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1504 } 1505 } 1506 1507 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1508 { 1509 MachineClass *mc = MACHINE_CLASS(oc); 1510 QEMUMachine *qm = data; 1511 1512 mc->family = qm->family; 1513 mc->name = qm->name; 1514 mc->alias = qm->alias; 1515 mc->desc = qm->desc; 1516 mc->init = qm->init; 1517 mc->reset = qm->reset; 1518 mc->hot_add_cpu = qm->hot_add_cpu; 1519 mc->kvm_type = qm->kvm_type; 1520 mc->block_default_type = qm->block_default_type; 1521 mc->units_per_default_bus = qm->units_per_default_bus; 1522 mc->max_cpus = qm->max_cpus; 1523 mc->no_serial = qm->no_serial; 1524 mc->no_parallel = qm->no_parallel; 1525 mc->use_virtcon = qm->use_virtcon; 1526 mc->use_sclp = qm->use_sclp; 1527 mc->no_floppy = qm->no_floppy; 1528 mc->no_cdrom = qm->no_cdrom; 1529 mc->no_sdcard = qm->no_sdcard; 1530 mc->is_default = qm->is_default; 1531 mc->default_machine_opts = qm->default_machine_opts; 1532 mc->default_boot_order = qm->default_boot_order; 1533 mc->default_display = qm->default_display; 1534 mc->compat_props = qm->compat_props; 1535 mc->hw_version = qm->hw_version; 1536 } 1537 1538 void qemu_register_pc_machine(QEMUMachine *m) 1539 { 1540 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1541 TypeInfo ti = { 1542 .name = name, 1543 .parent = TYPE_PC_MACHINE, 1544 .class_init = pc_generic_machine_class_init, 1545 .class_data = (void *)m, 1546 }; 1547 1548 type_register(&ti); 1549 g_free(name); 1550 } 1551 1552 static int pc_dimm_count(Object *obj, void *opaque) 1553 { 1554 int *count = opaque; 1555 1556 if (object_dynamic_cast(obj, TYPE_PC_DIMM)) { 1557 (*count)++; 1558 } 1559 1560 object_child_foreach(obj, pc_dimm_count, opaque); 1561 return 0; 1562 } 1563 1564 static int pc_existing_dimms_capacity(Object *obj, void *opaque) 1565 { 1566 Error *local_err = NULL; 1567 uint64_t *size = opaque; 1568 1569 if (object_dynamic_cast(obj, TYPE_PC_DIMM)) { 1570 (*size) += object_property_get_int(obj, PC_DIMM_SIZE_PROP, &local_err); 1571 1572 if (local_err) { 1573 qerror_report_err(local_err); 1574 error_free(local_err); 1575 return 1; 1576 } 1577 } 1578 1579 object_child_foreach(obj, pc_dimm_count, opaque); 1580 return 0; 1581 } 1582 1583 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1584 DeviceState *dev, Error **errp) 1585 { 1586 int slot; 1587 HotplugHandlerClass *hhc; 1588 Error *local_err = NULL; 1589 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1590 MachineState *machine = MACHINE(hotplug_dev); 1591 PCDIMMDevice *dimm = PC_DIMM(dev); 1592 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1593 MemoryRegion *mr = ddc->get_memory_region(dimm); 1594 uint64_t existing_dimms_capacity = 0; 1595 uint64_t align = TARGET_PAGE_SIZE; 1596 uint64_t addr; 1597 1598 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 1599 if (local_err) { 1600 goto out; 1601 } 1602 1603 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1604 align = memory_region_get_alignment(mr); 1605 } 1606 1607 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1608 memory_region_size(&pcms->hotplug_memory), 1609 !addr ? NULL : &addr, align, 1610 memory_region_size(mr), &local_err); 1611 if (local_err) { 1612 goto out; 1613 } 1614 1615 if (pc_existing_dimms_capacity(OBJECT(machine), &existing_dimms_capacity)) { 1616 error_setg(&local_err, "failed to get total size of existing DIMMs"); 1617 goto out; 1618 } 1619 1620 if (existing_dimms_capacity + memory_region_size(mr) > 1621 machine->maxram_size - machine->ram_size) { 1622 error_setg(&local_err, "not enough space, currently 0x%" PRIx64 1623 " in use of total 0x" RAM_ADDR_FMT, 1624 existing_dimms_capacity, machine->maxram_size); 1625 goto out; 1626 } 1627 1628 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1629 if (local_err) { 1630 goto out; 1631 } 1632 trace_mhp_pc_dimm_assigned_address(addr); 1633 1634 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1635 if (local_err) { 1636 goto out; 1637 } 1638 1639 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1640 machine->ram_slots, &local_err); 1641 if (local_err) { 1642 goto out; 1643 } 1644 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1645 if (local_err) { 1646 goto out; 1647 } 1648 trace_mhp_pc_dimm_assigned_slot(slot); 1649 1650 if (!pcms->acpi_dev) { 1651 error_setg(&local_err, 1652 "memory hotplug is not enabled: missing acpi device"); 1653 goto out; 1654 } 1655 1656 if (kvm_enabled() && !kvm_has_free_slot(machine)) { 1657 error_setg(&local_err, "hypervisor has no free memory slots left"); 1658 goto out; 1659 } 1660 1661 memory_region_add_subregion(&pcms->hotplug_memory, 1662 addr - pcms->hotplug_memory_base, mr); 1663 vmstate_register_ram(mr, dev); 1664 1665 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1666 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1667 out: 1668 error_propagate(errp, local_err); 1669 } 1670 1671 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1672 DeviceState *dev, Error **errp) 1673 { 1674 HotplugHandlerClass *hhc; 1675 Error *local_err = NULL; 1676 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1677 1678 if (!dev->hotplugged) { 1679 goto out; 1680 } 1681 1682 if (!pcms->acpi_dev) { 1683 error_setg(&local_err, 1684 "cpu hotplug is not enabled: missing acpi device"); 1685 goto out; 1686 } 1687 1688 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1689 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1690 if (local_err) { 1691 goto out; 1692 } 1693 1694 /* increment the number of CPUs */ 1695 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1696 out: 1697 error_propagate(errp, local_err); 1698 } 1699 1700 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1701 DeviceState *dev, Error **errp) 1702 { 1703 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1704 pc_dimm_plug(hotplug_dev, dev, errp); 1705 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1706 pc_cpu_plug(hotplug_dev, dev, errp); 1707 } 1708 } 1709 1710 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1711 DeviceState *dev) 1712 { 1713 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1714 1715 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1716 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1717 return HOTPLUG_HANDLER(machine); 1718 } 1719 1720 return pcmc->get_hotplug_handler ? 1721 pcmc->get_hotplug_handler(machine, dev) : NULL; 1722 } 1723 1724 static void 1725 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1726 const char *name, Error **errp) 1727 { 1728 PCMachineState *pcms = PC_MACHINE(obj); 1729 int64_t value = memory_region_size(&pcms->hotplug_memory); 1730 1731 visit_type_int(v, &value, name, errp); 1732 } 1733 1734 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1735 void *opaque, const char *name, 1736 Error **errp) 1737 { 1738 PCMachineState *pcms = PC_MACHINE(obj); 1739 uint64_t value = pcms->max_ram_below_4g; 1740 1741 visit_type_size(v, &value, name, errp); 1742 } 1743 1744 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1745 void *opaque, const char *name, 1746 Error **errp) 1747 { 1748 PCMachineState *pcms = PC_MACHINE(obj); 1749 Error *error = NULL; 1750 uint64_t value; 1751 1752 visit_type_size(v, &value, name, &error); 1753 if (error) { 1754 error_propagate(errp, error); 1755 return; 1756 } 1757 if (value > (1ULL << 32)) { 1758 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1759 "Machine option 'max-ram-below-4g=%"PRIu64 1760 "' expects size less than or equal to 4G", value); 1761 error_propagate(errp, error); 1762 return; 1763 } 1764 1765 if (value < (1ULL << 20)) { 1766 error_report("Warning: small max_ram_below_4g(%"PRIu64 1767 ") less than 1M. BIOS may not work..", 1768 value); 1769 } 1770 1771 pcms->max_ram_below_4g = value; 1772 } 1773 1774 static bool pc_machine_get_vmport(Object *obj, Error **errp) 1775 { 1776 PCMachineState *pcms = PC_MACHINE(obj); 1777 1778 return pcms->vmport; 1779 } 1780 1781 static void pc_machine_set_vmport(Object *obj, bool value, Error **errp) 1782 { 1783 PCMachineState *pcms = PC_MACHINE(obj); 1784 1785 pcms->vmport = value; 1786 } 1787 1788 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1789 { 1790 PCMachineState *pcms = PC_MACHINE(obj); 1791 1792 return pcms->enforce_aligned_dimm; 1793 } 1794 1795 static void pc_machine_initfn(Object *obj) 1796 { 1797 PCMachineState *pcms = PC_MACHINE(obj); 1798 1799 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1800 pc_machine_get_hotplug_memory_region_size, 1801 NULL, NULL, NULL, NULL); 1802 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1803 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1804 pc_machine_get_max_ram_below_4g, 1805 pc_machine_set_max_ram_below_4g, 1806 NULL, NULL, NULL); 1807 1808 pcms->vmport = !xen_enabled(); 1809 object_property_add_bool(obj, PC_MACHINE_VMPORT, 1810 pc_machine_get_vmport, 1811 pc_machine_set_vmport, 1812 NULL); 1813 1814 pcms->enforce_aligned_dimm = true; 1815 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1816 pc_machine_get_aligned_dimm, 1817 NULL, NULL); 1818 } 1819 1820 static void pc_machine_class_init(ObjectClass *oc, void *data) 1821 { 1822 MachineClass *mc = MACHINE_CLASS(oc); 1823 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1824 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1825 1826 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1827 mc->get_hotplug_handler = pc_get_hotpug_handler; 1828 hc->plug = pc_machine_device_plug_cb; 1829 } 1830 1831 static const TypeInfo pc_machine_info = { 1832 .name = TYPE_PC_MACHINE, 1833 .parent = TYPE_MACHINE, 1834 .abstract = true, 1835 .instance_size = sizeof(PCMachineState), 1836 .instance_init = pc_machine_initfn, 1837 .class_size = sizeof(PCMachineClass), 1838 .class_init = pc_machine_class_init, 1839 .interfaces = (InterfaceInfo[]) { 1840 { TYPE_HOTPLUG_HANDLER }, 1841 { } 1842 }, 1843 }; 1844 1845 static void pc_machine_register_types(void) 1846 { 1847 type_register_static(&pc_machine_info); 1848 } 1849 1850 type_init(pc_machine_register_types) 1851