1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_8_2[] = {}; 82 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 83 84 GlobalProperty pc_compat_8_1[] = {}; 85 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 86 87 GlobalProperty pc_compat_8_0[] = { 88 { "virtio-mem", "unplugged-inaccessible", "auto" }, 89 }; 90 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 91 92 GlobalProperty pc_compat_7_2[] = { 93 { "ICH9-LPC", "noreboot", "true" }, 94 }; 95 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 96 97 GlobalProperty pc_compat_7_1[] = {}; 98 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 99 100 GlobalProperty pc_compat_7_0[] = {}; 101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 102 103 GlobalProperty pc_compat_6_2[] = { 104 { "virtio-mem", "unplugged-inaccessible", "off" }, 105 }; 106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 107 108 GlobalProperty pc_compat_6_1[] = { 109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 113 }; 114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 115 116 GlobalProperty pc_compat_6_0[] = { 117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 123 }; 124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 125 126 GlobalProperty pc_compat_5_2[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 128 }; 129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 130 131 GlobalProperty pc_compat_5_1[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 134 }; 135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 136 137 GlobalProperty pc_compat_5_0[] = { 138 }; 139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 140 141 GlobalProperty pc_compat_4_2[] = { 142 { "mch", "smbase-smram", "off" }, 143 }; 144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 145 146 GlobalProperty pc_compat_4_1[] = {}; 147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 148 149 GlobalProperty pc_compat_4_0[] = {}; 150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 151 152 GlobalProperty pc_compat_3_1[] = { 153 { "intel-iommu", "dma-drain", "off" }, 154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 174 }; 175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 176 177 GlobalProperty pc_compat_3_0[] = { 178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 181 }; 182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 183 184 GlobalProperty pc_compat_2_12[] = { 185 { TYPE_X86_CPU, "legacy-cache", "on" }, 186 { TYPE_X86_CPU, "topoext", "off" }, 187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 }; 190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 191 192 GlobalProperty pc_compat_2_11[] = { 193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 195 }; 196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 197 198 GlobalProperty pc_compat_2_10[] = { 199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 201 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 202 }; 203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 204 205 GlobalProperty pc_compat_2_9[] = { 206 { "mch", "extended-tseg-mbytes", "0" }, 207 }; 208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 209 210 GlobalProperty pc_compat_2_8[] = { 211 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 213 { "ICH9-LPC", "x-smi-broadcast", "off" }, 214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 216 }; 217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 218 219 GlobalProperty pc_compat_2_7[] = { 220 { TYPE_X86_CPU, "l3-cache", "off" }, 221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 225 { "isa-pcspk", "migrate", "off" }, 226 }; 227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 228 229 GlobalProperty pc_compat_2_6[] = { 230 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 231 { "vmxnet3", "romfile", "" }, 232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 233 { "apic-common", "legacy-instance-id", "on", } 234 }; 235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 236 237 GlobalProperty pc_compat_2_5[] = {}; 238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 239 240 GlobalProperty pc_compat_2_4[] = { 241 PC_CPU_MODEL_IDS("2.4.0") 242 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 247 { TYPE_X86_CPU, "check", "off" }, 248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 256 }; 257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 258 259 GlobalProperty pc_compat_2_3[] = { 260 PC_CPU_MODEL_IDS("2.3.0") 261 { TYPE_X86_CPU, "arat", "off" }, 262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 281 }; 282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 283 284 GlobalProperty pc_compat_2_2[] = { 285 PC_CPU_MODEL_IDS("2.2.0") 286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 304 }; 305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 306 307 GlobalProperty pc_compat_2_1[] = { 308 PC_CPU_MODEL_IDS("2.1.0") 309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 }; 312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 313 314 GlobalProperty pc_compat_2_0[] = { 315 PC_CPU_MODEL_IDS("2.0.0") 316 { "virtio-scsi-pci", "any_layout", "off" }, 317 { "PIIX4_PM", "memory-hotplug-support", "off" }, 318 { "apic", "version", "0x11" }, 319 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 320 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 321 { "pci-serial", "prog_if", "0" }, 322 { "pci-serial-2x", "prog_if", "0" }, 323 { "pci-serial-4x", "prog_if", "0" }, 324 { "virtio-net-pci", "guest_announce", "off" }, 325 { "ICH9-LPC", "memory-hotplug-support", "off" }, 326 }; 327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 328 329 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 330 { 331 GSIState *s; 332 333 s = g_new0(GSIState, 1); 334 if (kvm_ioapic_in_kernel()) { 335 kvm_pc_setup_irq_routing(pci_enabled); 336 } 337 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 338 339 return s; 340 } 341 342 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 343 unsigned size) 344 { 345 } 346 347 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 348 { 349 return 0xffffffffffffffffULL; 350 } 351 352 /* MS-DOS compatibility mode FPU exception support */ 353 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 354 unsigned size) 355 { 356 if (tcg_enabled()) { 357 cpu_set_ignne(); 358 } 359 } 360 361 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 362 { 363 return 0xffffffffffffffffULL; 364 } 365 366 /* PC cmos mappings */ 367 368 #define REG_EQUIPMENT_BYTE 0x14 369 370 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 371 int16_t cylinders, int8_t heads, int8_t sectors) 372 { 373 mc146818rtc_set_cmos_data(s, type_ofs, 47); 374 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 375 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 376 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 377 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 378 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 379 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 380 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 381 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 382 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 383 } 384 385 /* convert boot_device letter to something recognizable by the bios */ 386 static int boot_device2nibble(char boot_device) 387 { 388 switch(boot_device) { 389 case 'a': 390 case 'b': 391 return 0x01; /* floppy boot */ 392 case 'c': 393 return 0x02; /* hard drive boot */ 394 case 'd': 395 return 0x03; /* CD-ROM boot */ 396 case 'n': 397 return 0x04; /* Network boot */ 398 } 399 return 0; 400 } 401 402 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 403 const char *boot_device, Error **errp) 404 { 405 #define PC_MAX_BOOT_DEVICES 3 406 int nbds, bds[3] = { 0, }; 407 int i; 408 409 nbds = strlen(boot_device); 410 if (nbds > PC_MAX_BOOT_DEVICES) { 411 error_setg(errp, "Too many boot devices for PC"); 412 return; 413 } 414 for (i = 0; i < nbds; i++) { 415 bds[i] = boot_device2nibble(boot_device[i]); 416 if (bds[i] == 0) { 417 error_setg(errp, "Invalid boot device for PC: '%c'", 418 boot_device[i]); 419 return; 420 } 421 } 422 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 423 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 424 } 425 426 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 427 { 428 PCMachineState *pcms = PC_MACHINE(current_machine); 429 430 set_boot_dev(pcms, opaque, boot_device, errp); 431 } 432 433 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 434 { 435 int val, nb, i; 436 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 437 FLOPPY_DRIVE_TYPE_NONE }; 438 439 /* floppy type */ 440 if (floppy) { 441 for (i = 0; i < 2; i++) { 442 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 443 } 444 } 445 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 446 cmos_get_fd_drive_type(fd_type[1]); 447 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 448 449 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 450 nb = 0; 451 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 452 nb++; 453 } 454 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 455 nb++; 456 } 457 switch (nb) { 458 case 0: 459 break; 460 case 1: 461 val |= 0x01; /* 1 drive, ready for boot */ 462 break; 463 case 2: 464 val |= 0x41; /* 2 drives, ready for boot */ 465 break; 466 } 467 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 468 } 469 470 typedef struct check_fdc_state { 471 ISADevice *floppy; 472 bool multiple; 473 } CheckFdcState; 474 475 static int check_fdc(Object *obj, void *opaque) 476 { 477 CheckFdcState *state = opaque; 478 Object *fdc; 479 uint32_t iobase; 480 Error *local_err = NULL; 481 482 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 483 if (!fdc) { 484 return 0; 485 } 486 487 iobase = object_property_get_uint(obj, "iobase", &local_err); 488 if (local_err || iobase != 0x3f0) { 489 error_free(local_err); 490 return 0; 491 } 492 493 if (state->floppy) { 494 state->multiple = true; 495 } else { 496 state->floppy = ISA_DEVICE(obj); 497 } 498 return 0; 499 } 500 501 static const char * const fdc_container_path[] = { 502 "/unattached", "/peripheral", "/peripheral-anon" 503 }; 504 505 /* 506 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 507 * and ACPI objects. 508 */ 509 static ISADevice *pc_find_fdc0(void) 510 { 511 int i; 512 Object *container; 513 CheckFdcState state = { 0 }; 514 515 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 516 container = container_get(qdev_get_machine(), fdc_container_path[i]); 517 object_child_foreach(container, check_fdc, &state); 518 } 519 520 if (state.multiple) { 521 warn_report("multiple floppy disk controllers with " 522 "iobase=0x3f0 have been found"); 523 error_printf("the one being picked for CMOS setup might not reflect " 524 "your intent"); 525 } 526 527 return state.floppy; 528 } 529 530 static void pc_cmos_init_late(PCMachineState *pcms) 531 { 532 X86MachineState *x86ms = X86_MACHINE(pcms); 533 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 534 int16_t cylinders; 535 int8_t heads, sectors; 536 int val; 537 int i, trans; 538 539 val = 0; 540 if (pcms->idebus[0] && 541 ide_get_geometry(pcms->idebus[0], 0, 542 &cylinders, &heads, §ors) >= 0) { 543 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 544 val |= 0xf0; 545 } 546 if (pcms->idebus[0] && 547 ide_get_geometry(pcms->idebus[0], 1, 548 &cylinders, &heads, §ors) >= 0) { 549 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 550 val |= 0x0f; 551 } 552 mc146818rtc_set_cmos_data(s, 0x12, val); 553 554 val = 0; 555 for (i = 0; i < 4; i++) { 556 /* NOTE: ide_get_geometry() returns the physical 557 geometry. It is always such that: 1 <= sects <= 63, 1 558 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 559 geometry can be different if a translation is done. */ 560 BusState *idebus = pcms->idebus[i / 2]; 561 if (idebus && 562 ide_get_geometry(idebus, i % 2, 563 &cylinders, &heads, §ors) >= 0) { 564 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 565 assert((trans & ~3) == 0); 566 val |= trans << (i * 2); 567 } 568 } 569 mc146818rtc_set_cmos_data(s, 0x39, val); 570 571 pc_cmos_init_floppy(s, pc_find_fdc0()); 572 } 573 574 void pc_cmos_init(PCMachineState *pcms, 575 ISADevice *rtc) 576 { 577 int val; 578 X86MachineState *x86ms = X86_MACHINE(pcms); 579 MC146818RtcState *s = MC146818_RTC(rtc); 580 581 /* various important CMOS locations needed by PC/Bochs bios */ 582 583 /* memory size */ 584 /* base memory (first MiB) */ 585 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 586 mc146818rtc_set_cmos_data(s, 0x15, val); 587 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 588 /* extended memory (next 64MiB) */ 589 if (x86ms->below_4g_mem_size > 1 * MiB) { 590 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 591 } else { 592 val = 0; 593 } 594 if (val > 65535) 595 val = 65535; 596 mc146818rtc_set_cmos_data(s, 0x17, val); 597 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 598 mc146818rtc_set_cmos_data(s, 0x30, val); 599 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 600 /* memory between 16MiB and 4GiB */ 601 if (x86ms->below_4g_mem_size > 16 * MiB) { 602 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 603 } else { 604 val = 0; 605 } 606 if (val > 65535) 607 val = 65535; 608 mc146818rtc_set_cmos_data(s, 0x34, val); 609 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 610 /* memory above 4GiB */ 611 val = x86ms->above_4g_mem_size / 65536; 612 mc146818rtc_set_cmos_data(s, 0x5b, val); 613 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 614 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 615 616 object_property_add_link(OBJECT(pcms), "rtc_state", 617 TYPE_ISA_DEVICE, 618 (Object **)&x86ms->rtc, 619 object_property_allow_set_link, 620 OBJ_PROP_LINK_STRONG); 621 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 622 &error_abort); 623 624 set_boot_dev(pcms, s, MACHINE(pcms)->boot_config.order, &error_fatal); 625 626 val = 0; 627 val |= 0x02; /* FPU is there */ 628 val |= 0x04; /* PS/2 mouse installed */ 629 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 630 631 /* hard drives and FDC are handled by pc_cmos_init_late() */ 632 } 633 634 static void handle_a20_line_change(void *opaque, int irq, int level) 635 { 636 X86CPU *cpu = opaque; 637 638 /* XXX: send to all CPUs ? */ 639 /* XXX: add logic to handle multiple A20 line sources */ 640 x86_cpu_set_a20(cpu, level); 641 } 642 643 #define NE2000_NB_MAX 6 644 645 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 646 0x280, 0x380 }; 647 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 648 649 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 650 { 651 static int nb_ne2k = 0; 652 653 if (nb_ne2k == NE2000_NB_MAX) { 654 error_setg(errp, 655 "maximum number of ISA NE2000 devices exceeded"); 656 return false; 657 } 658 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 659 ne2000_irq[nb_ne2k], nd); 660 nb_ne2k++; 661 return true; 662 } 663 664 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 665 { 666 X86CPU *cpu = opaque; 667 668 if (level) { 669 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 670 } 671 } 672 673 static 674 void pc_machine_done(Notifier *notifier, void *data) 675 { 676 PCMachineState *pcms = container_of(notifier, 677 PCMachineState, machine_done); 678 X86MachineState *x86ms = X86_MACHINE(pcms); 679 680 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 681 &error_fatal); 682 683 if (pcms->cxl_devices_state.is_enabled) { 684 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 685 } 686 687 /* set the number of CPUs */ 688 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 689 690 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 691 692 acpi_setup(); 693 if (x86ms->fw_cfg) { 694 fw_cfg_build_smbios(pcms, x86ms->fw_cfg); 695 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 696 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 697 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 698 } 699 700 pc_cmos_init_late(pcms); 701 } 702 703 /* setup pci memory address space mapping into system address space */ 704 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 705 MemoryRegion *pci_address_space) 706 { 707 /* Set to lower priority than RAM */ 708 memory_region_add_subregion_overlap(system_memory, 0x0, 709 pci_address_space, -1); 710 } 711 712 void xen_load_linux(PCMachineState *pcms) 713 { 714 int i; 715 FWCfgState *fw_cfg; 716 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 717 X86MachineState *x86ms = X86_MACHINE(pcms); 718 719 assert(MACHINE(pcms)->kernel_filename != NULL); 720 721 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 722 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 723 rom_set_fw(fw_cfg); 724 725 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 726 pcmc->pvh_enabled); 727 for (i = 0; i < nb_option_roms; i++) { 728 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 729 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 730 !strcmp(option_rom[i].name, "pvh.bin") || 731 !strcmp(option_rom[i].name, "multiboot.bin") || 732 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 733 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 734 } 735 x86ms->fw_cfg = fw_cfg; 736 } 737 738 #define PC_ROM_MIN_VGA 0xc0000 739 #define PC_ROM_MIN_OPTION 0xc8000 740 #define PC_ROM_MAX 0xe0000 741 #define PC_ROM_ALIGN 0x800 742 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 743 744 static hwaddr pc_above_4g_end(PCMachineState *pcms) 745 { 746 X86MachineState *x86ms = X86_MACHINE(pcms); 747 748 if (pcms->sgx_epc.size != 0) { 749 return sgx_epc_above_4g_end(&pcms->sgx_epc); 750 } 751 752 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 753 } 754 755 static void pc_get_device_memory_range(PCMachineState *pcms, 756 hwaddr *base, 757 ram_addr_t *device_mem_size) 758 { 759 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 760 MachineState *machine = MACHINE(pcms); 761 ram_addr_t size; 762 hwaddr addr; 763 764 size = machine->maxram_size - machine->ram_size; 765 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 766 767 if (pcmc->enforce_aligned_dimm) { 768 /* size device region assuming 1G page max alignment per slot */ 769 size += (1 * GiB) * machine->ram_slots; 770 } 771 772 *base = addr; 773 *device_mem_size = size; 774 } 775 776 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 777 { 778 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 779 MachineState *ms = MACHINE(pcms); 780 hwaddr cxl_base; 781 ram_addr_t size; 782 783 if (pcmc->has_reserved_memory && 784 (ms->ram_size < ms->maxram_size)) { 785 pc_get_device_memory_range(pcms, &cxl_base, &size); 786 cxl_base += size; 787 } else { 788 cxl_base = pc_above_4g_end(pcms); 789 } 790 791 return cxl_base; 792 } 793 794 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 795 { 796 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 797 798 if (pcms->cxl_devices_state.fixed_windows) { 799 GList *it; 800 801 start = ROUND_UP(start, 256 * MiB); 802 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 803 CXLFixedWindow *fw = it->data; 804 start += fw->size; 805 } 806 } 807 808 return start; 809 } 810 811 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 812 { 813 X86CPU *cpu = X86_CPU(first_cpu); 814 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 815 MachineState *ms = MACHINE(pcms); 816 817 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 818 /* 64-bit systems */ 819 return pc_pci_hole64_start() + pci_hole64_size - 1; 820 } 821 822 /* 32-bit systems */ 823 if (pcmc->broken_32bit_mem_addr_check) { 824 /* old value for compatibility reasons */ 825 return ((hwaddr)1 << cpu->phys_bits) - 1; 826 } 827 828 /* 829 * 32-bit systems don't have hole64 but they might have a region for 830 * memory devices. Even if additional hotplugged memory devices might 831 * not be usable by most guest OSes, we need to still consider them for 832 * calculating the highest possible GPA so that we can properly report 833 * if someone configures them on a CPU that cannot possibly address them. 834 */ 835 if (pcmc->has_reserved_memory && 836 (ms->ram_size < ms->maxram_size)) { 837 hwaddr devmem_start; 838 ram_addr_t devmem_size; 839 840 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 841 devmem_start += devmem_size; 842 return devmem_start - 1; 843 } 844 845 /* configuration without any memory hotplug */ 846 return pc_above_4g_end(pcms) - 1; 847 } 848 849 /* 850 * AMD systems with an IOMMU have an additional hole close to the 851 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 852 * on kernel version, VFIO may or may not let you DMA map those ranges. 853 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 854 * with certain memory sizes. It's also wrong to use those IOVA ranges 855 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 856 * The ranges reserved for Hyper-Transport are: 857 * 858 * FD_0000_0000h - FF_FFFF_FFFFh 859 * 860 * The ranges represent the following: 861 * 862 * Base Address Top Address Use 863 * 864 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 865 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 866 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 867 * FD_F910_0000h FD_F91F_FFFFh System Management 868 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 869 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 870 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 871 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 872 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 873 * FE_2000_0000h FF_FFFF_FFFFh Reserved 874 * 875 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 876 * Table 3: Special Address Controls (GPA) for more information. 877 */ 878 #define AMD_HT_START 0xfd00000000UL 879 #define AMD_HT_END 0xffffffffffUL 880 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 881 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 882 883 void pc_memory_init(PCMachineState *pcms, 884 MemoryRegion *system_memory, 885 MemoryRegion *rom_memory, 886 uint64_t pci_hole64_size) 887 { 888 int linux_boot, i; 889 MemoryRegion *option_rom_mr; 890 MemoryRegion *ram_below_4g, *ram_above_4g; 891 FWCfgState *fw_cfg; 892 MachineState *machine = MACHINE(pcms); 893 MachineClass *mc = MACHINE_GET_CLASS(machine); 894 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 895 X86MachineState *x86ms = X86_MACHINE(pcms); 896 hwaddr maxphysaddr, maxusedaddr; 897 hwaddr cxl_base, cxl_resv_end = 0; 898 X86CPU *cpu = X86_CPU(first_cpu); 899 900 assert(machine->ram_size == x86ms->below_4g_mem_size + 901 x86ms->above_4g_mem_size); 902 903 linux_boot = (machine->kernel_filename != NULL); 904 905 /* 906 * The HyperTransport range close to the 1T boundary is unique to AMD 907 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 908 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 909 * older machine types (<= 7.0) for compatibility purposes. 910 */ 911 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 912 /* Bail out if max possible address does not cross HT range */ 913 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 914 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 915 } 916 917 /* 918 * Advertise the HT region if address space covers the reserved 919 * region or if we relocate. 920 */ 921 if (cpu->phys_bits >= 40) { 922 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 923 } 924 } 925 926 /* 927 * phys-bits is required to be appropriately configured 928 * to make sure max used GPA is reachable. 929 */ 930 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 931 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 932 if (maxphysaddr < maxusedaddr) { 933 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 934 " phys-bits too low (%u)", 935 maxphysaddr, maxusedaddr, cpu->phys_bits); 936 exit(EXIT_FAILURE); 937 } 938 939 /* 940 * Split single memory region and use aliases to address portions of it, 941 * done for backwards compatibility with older qemus. 942 */ 943 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 944 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 945 0, x86ms->below_4g_mem_size); 946 memory_region_add_subregion(system_memory, 0, ram_below_4g); 947 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 948 if (x86ms->above_4g_mem_size > 0) { 949 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 950 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 951 machine->ram, 952 x86ms->below_4g_mem_size, 953 x86ms->above_4g_mem_size); 954 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 955 ram_above_4g); 956 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 957 E820_RAM); 958 } 959 960 if (pcms->sgx_epc.size != 0) { 961 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 962 } 963 964 if (!pcmc->has_reserved_memory && 965 (machine->ram_slots || 966 (machine->maxram_size > machine->ram_size))) { 967 968 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 969 mc->name); 970 exit(EXIT_FAILURE); 971 } 972 973 /* initialize device memory address space */ 974 if (pcmc->has_reserved_memory && 975 (machine->ram_size < machine->maxram_size)) { 976 ram_addr_t device_mem_size; 977 hwaddr device_mem_base; 978 979 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 980 error_report("unsupported amount of memory slots: %"PRIu64, 981 machine->ram_slots); 982 exit(EXIT_FAILURE); 983 } 984 985 if (QEMU_ALIGN_UP(machine->maxram_size, 986 TARGET_PAGE_SIZE) != machine->maxram_size) { 987 error_report("maximum memory size must by aligned to multiple of " 988 "%d bytes", TARGET_PAGE_SIZE); 989 exit(EXIT_FAILURE); 990 } 991 992 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 993 994 if (device_mem_base + device_mem_size < device_mem_size) { 995 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 996 machine->maxram_size); 997 exit(EXIT_FAILURE); 998 } 999 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 1000 } 1001 1002 if (pcms->cxl_devices_state.is_enabled) { 1003 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1004 hwaddr cxl_size = MiB; 1005 1006 cxl_base = pc_get_cxl_range_start(pcms); 1007 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1008 memory_region_add_subregion(system_memory, cxl_base, mr); 1009 cxl_resv_end = cxl_base + cxl_size; 1010 if (pcms->cxl_devices_state.fixed_windows) { 1011 hwaddr cxl_fmw_base; 1012 GList *it; 1013 1014 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1015 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1016 CXLFixedWindow *fw = it->data; 1017 1018 fw->base = cxl_fmw_base; 1019 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1020 "cxl-fixed-memory-region", fw->size); 1021 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1022 cxl_fmw_base += fw->size; 1023 cxl_resv_end = cxl_fmw_base; 1024 } 1025 } 1026 } 1027 1028 /* Initialize PC system firmware */ 1029 pc_system_firmware_init(pcms, rom_memory); 1030 1031 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1032 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1033 &error_fatal); 1034 if (pcmc->pci_enabled) { 1035 memory_region_set_readonly(option_rom_mr, true); 1036 } 1037 memory_region_add_subregion_overlap(rom_memory, 1038 PC_ROM_MIN_VGA, 1039 option_rom_mr, 1040 1); 1041 1042 fw_cfg = fw_cfg_arch_create(machine, 1043 x86ms->boot_cpus, x86ms->apic_id_limit); 1044 1045 rom_set_fw(fw_cfg); 1046 1047 if (machine->device_memory) { 1048 uint64_t *val = g_malloc(sizeof(*val)); 1049 uint64_t res_mem_end = machine->device_memory->base; 1050 1051 if (!pcmc->broken_reserved_end) { 1052 res_mem_end += memory_region_size(&machine->device_memory->mr); 1053 } 1054 1055 if (pcms->cxl_devices_state.is_enabled) { 1056 res_mem_end = cxl_resv_end; 1057 } 1058 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1059 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1060 } 1061 1062 if (linux_boot) { 1063 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1064 pcmc->pvh_enabled); 1065 } 1066 1067 for (i = 0; i < nb_option_roms; i++) { 1068 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1069 } 1070 x86ms->fw_cfg = fw_cfg; 1071 1072 /* Init default IOAPIC address space */ 1073 x86ms->ioapic_as = &address_space_memory; 1074 1075 /* Init ACPI memory hotplug IO base address */ 1076 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1077 } 1078 1079 /* 1080 * The 64bit pci hole starts after "above 4G RAM" and 1081 * potentially the space reserved for memory hotplug. 1082 */ 1083 uint64_t pc_pci_hole64_start(void) 1084 { 1085 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1086 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1087 MachineState *ms = MACHINE(pcms); 1088 uint64_t hole64_start = 0; 1089 ram_addr_t size = 0; 1090 1091 if (pcms->cxl_devices_state.is_enabled) { 1092 hole64_start = pc_get_cxl_range_end(pcms); 1093 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1094 pc_get_device_memory_range(pcms, &hole64_start, &size); 1095 if (!pcmc->broken_reserved_end) { 1096 hole64_start += size; 1097 } 1098 } else { 1099 hole64_start = pc_above_4g_end(pcms); 1100 } 1101 1102 return ROUND_UP(hole64_start, 1 * GiB); 1103 } 1104 1105 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1106 { 1107 DeviceState *dev = NULL; 1108 1109 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1110 if (pci_bus) { 1111 PCIDevice *pcidev = pci_vga_init(pci_bus); 1112 dev = pcidev ? &pcidev->qdev : NULL; 1113 } else if (isa_bus) { 1114 ISADevice *isadev = isa_vga_init(isa_bus); 1115 dev = isadev ? DEVICE(isadev) : NULL; 1116 } 1117 rom_reset_order_override(); 1118 return dev; 1119 } 1120 1121 static const MemoryRegionOps ioport80_io_ops = { 1122 .write = ioport80_write, 1123 .read = ioport80_read, 1124 .endianness = DEVICE_NATIVE_ENDIAN, 1125 .impl = { 1126 .min_access_size = 1, 1127 .max_access_size = 1, 1128 }, 1129 }; 1130 1131 static const MemoryRegionOps ioportF0_io_ops = { 1132 .write = ioportF0_write, 1133 .read = ioportF0_read, 1134 .endianness = DEVICE_NATIVE_ENDIAN, 1135 .impl = { 1136 .min_access_size = 1, 1137 .max_access_size = 1, 1138 }, 1139 }; 1140 1141 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1142 bool create_i8042, bool no_vmport) 1143 { 1144 int i; 1145 DriveInfo *fd[MAX_FD]; 1146 qemu_irq *a20_line; 1147 ISADevice *fdc, *i8042, *port92, *vmmouse; 1148 1149 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1150 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1151 1152 for (i = 0; i < MAX_FD; i++) { 1153 fd[i] = drive_get(IF_FLOPPY, 0, i); 1154 create_fdctrl |= !!fd[i]; 1155 } 1156 if (create_fdctrl) { 1157 fdc = isa_new(TYPE_ISA_FDC); 1158 if (fdc) { 1159 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1160 isa_fdc_init_drives(fdc, fd); 1161 } 1162 } 1163 1164 if (!create_i8042) { 1165 return; 1166 } 1167 1168 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1169 if (!no_vmport) { 1170 isa_create_simple(isa_bus, TYPE_VMPORT); 1171 vmmouse = isa_try_new("vmmouse"); 1172 } else { 1173 vmmouse = NULL; 1174 } 1175 if (vmmouse) { 1176 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1177 &error_abort); 1178 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1179 } 1180 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1181 1182 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1183 qdev_connect_gpio_out_named(DEVICE(i8042), 1184 I8042_A20_LINE, 0, a20_line[0]); 1185 qdev_connect_gpio_out_named(DEVICE(port92), 1186 PORT92_A20_LINE, 0, a20_line[1]); 1187 g_free(a20_line); 1188 } 1189 1190 void pc_basic_device_init(struct PCMachineState *pcms, 1191 ISABus *isa_bus, qemu_irq *gsi, 1192 ISADevice *rtc_state, 1193 bool create_fdctrl, 1194 uint32_t hpet_irqs) 1195 { 1196 int i; 1197 DeviceState *hpet = NULL; 1198 int pit_isa_irq = 0; 1199 qemu_irq pit_alt_irq = NULL; 1200 ISADevice *pit = NULL; 1201 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1202 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1203 X86MachineState *x86ms = X86_MACHINE(pcms); 1204 1205 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1206 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1207 1208 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1209 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1210 1211 /* 1212 * Check if an HPET shall be created. 1213 */ 1214 if (pcms->hpet_enabled) { 1215 qemu_irq rtc_irq; 1216 1217 hpet = qdev_try_new(TYPE_HPET); 1218 if (!hpet) { 1219 error_report("couldn't create HPET device"); 1220 exit(1); 1221 } 1222 /* 1223 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1224 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1225 * the property, use whatever mask they specified. 1226 */ 1227 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1228 HPET_INTCAP, NULL); 1229 if (!compat) { 1230 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1231 } 1232 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1233 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1234 1235 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1236 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1237 } 1238 pit_isa_irq = -1; 1239 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1240 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1241 1242 /* overwrite connection created by south bridge */ 1243 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1244 } 1245 1246 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1247 "date"); 1248 1249 #ifdef CONFIG_XEN_EMU 1250 if (xen_mode == XEN_EMULATE) { 1251 xen_overlay_create(); 1252 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1253 xen_gnttab_create(); 1254 xen_xenstore_create(); 1255 if (pcms->pcibus) { 1256 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1257 } 1258 xen_bus_init(); 1259 xen_be_init(); 1260 } 1261 #endif 1262 1263 qemu_register_boot_set(pc_boot_set, rtc_state); 1264 1265 if (!xen_enabled() && 1266 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1267 if (kvm_pit_in_kernel()) { 1268 pit = kvm_pit_init(isa_bus, 0x40); 1269 } else { 1270 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1271 } 1272 if (hpet) { 1273 /* connect PIT to output control line of the HPET */ 1274 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1275 } 1276 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1277 OBJECT(pit), &error_fatal); 1278 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1279 } 1280 1281 /* Super I/O */ 1282 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1283 pcms->vmport != ON_OFF_AUTO_ON); 1284 } 1285 1286 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1287 { 1288 MachineClass *mc = MACHINE_CLASS(pcmc); 1289 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1290 NICInfo *nd; 1291 1292 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1293 1294 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1295 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1296 } 1297 1298 /* Anything remaining should be a PCI NIC */ 1299 pci_init_nic_devices(pci_bus, mc->default_nic); 1300 1301 rom_reset_order_override(); 1302 } 1303 1304 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1305 { 1306 qemu_irq *i8259; 1307 1308 if (kvm_pic_in_kernel()) { 1309 i8259 = kvm_i8259_init(isa_bus); 1310 } else if (xen_enabled()) { 1311 i8259 = xen_interrupt_controller_init(); 1312 } else { 1313 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1314 } 1315 1316 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1317 i8259_irqs[i] = i8259[i]; 1318 } 1319 1320 g_free(i8259); 1321 } 1322 1323 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1324 Error **errp) 1325 { 1326 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1327 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1328 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1329 const MachineState *ms = MACHINE(hotplug_dev); 1330 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1331 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1332 Error *local_err = NULL; 1333 1334 /* 1335 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1336 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1337 * addition to cover this case. 1338 */ 1339 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1340 error_setg(errp, 1341 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1342 return; 1343 } 1344 1345 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1346 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1347 return; 1348 } 1349 1350 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1351 if (local_err) { 1352 error_propagate(errp, local_err); 1353 return; 1354 } 1355 1356 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1357 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1358 } 1359 1360 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1361 DeviceState *dev, Error **errp) 1362 { 1363 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1364 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1365 MachineState *ms = MACHINE(hotplug_dev); 1366 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1367 1368 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1369 1370 if (is_nvdimm) { 1371 nvdimm_plug(ms->nvdimms_state); 1372 } 1373 1374 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1375 } 1376 1377 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1378 DeviceState *dev, Error **errp) 1379 { 1380 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1381 1382 /* 1383 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1384 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1385 * addition to cover this case. 1386 */ 1387 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1388 error_setg(errp, 1389 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1390 return; 1391 } 1392 1393 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1394 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1395 return; 1396 } 1397 1398 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1399 errp); 1400 } 1401 1402 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1403 DeviceState *dev, Error **errp) 1404 { 1405 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1406 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1407 Error *local_err = NULL; 1408 1409 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1410 if (local_err) { 1411 goto out; 1412 } 1413 1414 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1415 qdev_unrealize(dev); 1416 out: 1417 error_propagate(errp, local_err); 1418 } 1419 1420 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1421 DeviceState *dev, Error **errp) 1422 { 1423 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1424 g_assert(!dev->hotplugged); 1425 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1426 errp); 1427 } 1428 1429 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1430 DeviceState *dev, Error **errp) 1431 { 1432 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1433 } 1434 1435 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1436 DeviceState *dev, Error **errp) 1437 { 1438 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1439 pc_memory_pre_plug(hotplug_dev, dev, errp); 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1441 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1442 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1443 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1444 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1445 /* Declare the APIC range as the reserved MSI region */ 1446 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1447 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1448 QList *reserved_regions = qlist_new(); 1449 1450 qlist_append_str(reserved_regions, resv_prop_str); 1451 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1452 1453 g_free(resv_prop_str); 1454 } 1455 1456 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1457 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1458 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1459 1460 if (pcms->iommu) { 1461 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1462 "for x86 yet."); 1463 return; 1464 } 1465 pcms->iommu = dev; 1466 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1467 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1468 } 1469 } 1470 1471 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1472 DeviceState *dev, Error **errp) 1473 { 1474 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1475 pc_memory_plug(hotplug_dev, dev, errp); 1476 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1477 x86_cpu_plug(hotplug_dev, dev, errp); 1478 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1479 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1480 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1481 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1482 } 1483 } 1484 1485 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1486 DeviceState *dev, Error **errp) 1487 { 1488 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1489 pc_memory_unplug_request(hotplug_dev, dev, errp); 1490 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1491 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1492 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1493 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1494 errp); 1495 } else { 1496 error_setg(errp, "acpi: device unplug request for not supported device" 1497 " type: %s", object_get_typename(OBJECT(dev))); 1498 } 1499 } 1500 1501 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1502 DeviceState *dev, Error **errp) 1503 { 1504 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1505 pc_memory_unplug(hotplug_dev, dev, errp); 1506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1507 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1508 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1509 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1510 } else { 1511 error_setg(errp, "acpi: device unplug for not supported device" 1512 " type: %s", object_get_typename(OBJECT(dev))); 1513 } 1514 } 1515 1516 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1517 DeviceState *dev) 1518 { 1519 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1520 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1521 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1522 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1523 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1524 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1525 return HOTPLUG_HANDLER(machine); 1526 } 1527 1528 return NULL; 1529 } 1530 1531 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1532 void *opaque, Error **errp) 1533 { 1534 PCMachineState *pcms = PC_MACHINE(obj); 1535 OnOffAuto vmport = pcms->vmport; 1536 1537 visit_type_OnOffAuto(v, name, &vmport, errp); 1538 } 1539 1540 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1541 void *opaque, Error **errp) 1542 { 1543 PCMachineState *pcms = PC_MACHINE(obj); 1544 1545 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1546 } 1547 1548 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1549 { 1550 PCMachineState *pcms = PC_MACHINE(obj); 1551 1552 return pcms->fd_bootchk; 1553 } 1554 1555 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1556 { 1557 PCMachineState *pcms = PC_MACHINE(obj); 1558 1559 pcms->fd_bootchk = value; 1560 } 1561 1562 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1563 { 1564 PCMachineState *pcms = PC_MACHINE(obj); 1565 1566 return pcms->smbus_enabled; 1567 } 1568 1569 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1570 { 1571 PCMachineState *pcms = PC_MACHINE(obj); 1572 1573 pcms->smbus_enabled = value; 1574 } 1575 1576 static bool pc_machine_get_sata(Object *obj, Error **errp) 1577 { 1578 PCMachineState *pcms = PC_MACHINE(obj); 1579 1580 return pcms->sata_enabled; 1581 } 1582 1583 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1584 { 1585 PCMachineState *pcms = PC_MACHINE(obj); 1586 1587 pcms->sata_enabled = value; 1588 } 1589 1590 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 1594 return pcms->hpet_enabled; 1595 } 1596 1597 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1598 { 1599 PCMachineState *pcms = PC_MACHINE(obj); 1600 1601 pcms->hpet_enabled = value; 1602 } 1603 1604 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1605 { 1606 PCMachineState *pcms = PC_MACHINE(obj); 1607 1608 return pcms->i8042_enabled; 1609 } 1610 1611 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1612 { 1613 PCMachineState *pcms = PC_MACHINE(obj); 1614 1615 pcms->i8042_enabled = value; 1616 } 1617 1618 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1619 { 1620 PCMachineState *pcms = PC_MACHINE(obj); 1621 1622 return pcms->default_bus_bypass_iommu; 1623 } 1624 1625 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1626 Error **errp) 1627 { 1628 PCMachineState *pcms = PC_MACHINE(obj); 1629 1630 pcms->default_bus_bypass_iommu = value; 1631 } 1632 1633 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1634 void *opaque, Error **errp) 1635 { 1636 PCMachineState *pcms = PC_MACHINE(obj); 1637 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1638 1639 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1640 } 1641 1642 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1643 void *opaque, Error **errp) 1644 { 1645 PCMachineState *pcms = PC_MACHINE(obj); 1646 1647 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1648 } 1649 1650 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1651 const char *name, void *opaque, 1652 Error **errp) 1653 { 1654 PCMachineState *pcms = PC_MACHINE(obj); 1655 uint64_t value = pcms->max_ram_below_4g; 1656 1657 visit_type_size(v, name, &value, errp); 1658 } 1659 1660 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1661 const char *name, void *opaque, 1662 Error **errp) 1663 { 1664 PCMachineState *pcms = PC_MACHINE(obj); 1665 uint64_t value; 1666 1667 if (!visit_type_size(v, name, &value, errp)) { 1668 return; 1669 } 1670 if (value > 4 * GiB) { 1671 error_setg(errp, 1672 "Machine option 'max-ram-below-4g=%"PRIu64 1673 "' expects size less than or equal to 4G", value); 1674 return; 1675 } 1676 1677 if (value < 1 * MiB) { 1678 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1679 "BIOS may not work with less than 1MiB", value); 1680 } 1681 1682 pcms->max_ram_below_4g = value; 1683 } 1684 1685 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1686 const char *name, void *opaque, 1687 Error **errp) 1688 { 1689 PCMachineState *pcms = PC_MACHINE(obj); 1690 uint64_t value = pcms->max_fw_size; 1691 1692 visit_type_size(v, name, &value, errp); 1693 } 1694 1695 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1696 const char *name, void *opaque, 1697 Error **errp) 1698 { 1699 PCMachineState *pcms = PC_MACHINE(obj); 1700 uint64_t value; 1701 1702 if (!visit_type_size(v, name, &value, errp)) { 1703 return; 1704 } 1705 1706 /* 1707 * We don't have a theoretically justifiable exact lower bound on the base 1708 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1709 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1710 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1711 * 16MiB in size. 1712 */ 1713 if (value > 16 * MiB) { 1714 error_setg(errp, 1715 "User specified max allowed firmware size %" PRIu64 " is " 1716 "greater than 16MiB. If combined firmware size exceeds " 1717 "16MiB the system may not boot, or experience intermittent" 1718 "stability issues.", 1719 value); 1720 return; 1721 } 1722 1723 pcms->max_fw_size = value; 1724 } 1725 1726 1727 static void pc_machine_initfn(Object *obj) 1728 { 1729 PCMachineState *pcms = PC_MACHINE(obj); 1730 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1731 1732 #ifdef CONFIG_VMPORT 1733 pcms->vmport = ON_OFF_AUTO_AUTO; 1734 #else 1735 pcms->vmport = ON_OFF_AUTO_OFF; 1736 #endif /* CONFIG_VMPORT */ 1737 pcms->max_ram_below_4g = 0; /* use default */ 1738 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1739 pcms->south_bridge = pcmc->default_south_bridge; 1740 1741 /* acpi build is enabled by default if machine supports it */ 1742 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1743 pcms->smbus_enabled = true; 1744 pcms->sata_enabled = true; 1745 pcms->i8042_enabled = true; 1746 pcms->max_fw_size = 8 * MiB; 1747 #ifdef CONFIG_HPET 1748 pcms->hpet_enabled = true; 1749 #endif 1750 pcms->fd_bootchk = true; 1751 pcms->default_bus_bypass_iommu = false; 1752 1753 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1754 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1755 OBJECT(pcms->pcspk), "audiodev"); 1756 cxl_machine_init(obj, &pcms->cxl_devices_state); 1757 1758 pcms->machine_done.notify = pc_machine_done; 1759 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1760 } 1761 1762 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1763 { 1764 CPUState *cs; 1765 X86CPU *cpu; 1766 1767 qemu_devices_reset(reason); 1768 1769 /* Reset APIC after devices have been reset to cancel 1770 * any changes that qemu_devices_reset() might have done. 1771 */ 1772 CPU_FOREACH(cs) { 1773 cpu = X86_CPU(cs); 1774 1775 x86_cpu_after_reset(cpu); 1776 } 1777 } 1778 1779 static void pc_machine_wakeup(MachineState *machine) 1780 { 1781 cpu_synchronize_all_states(); 1782 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1783 cpu_synchronize_all_post_reset(); 1784 } 1785 1786 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1787 { 1788 X86IOMMUState *iommu = x86_iommu_get_default(); 1789 IntelIOMMUState *intel_iommu; 1790 1791 if (iommu && 1792 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1793 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1794 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1795 if (!intel_iommu->caching_mode) { 1796 error_setg(errp, "Device assignment is not allowed without " 1797 "enabling caching-mode=on for Intel IOMMU."); 1798 return false; 1799 } 1800 } 1801 1802 return true; 1803 } 1804 1805 static void pc_machine_class_init(ObjectClass *oc, void *data) 1806 { 1807 MachineClass *mc = MACHINE_CLASS(oc); 1808 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1809 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1810 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1811 1812 pcmc->pci_enabled = true; 1813 pcmc->has_acpi_build = true; 1814 pcmc->rsdp_in_ram = true; 1815 pcmc->smbios_defaults = true; 1816 pcmc->smbios_uuid_encoded = true; 1817 pcmc->gigabyte_align = true; 1818 pcmc->has_reserved_memory = true; 1819 pcmc->enforce_aligned_dimm = true; 1820 pcmc->enforce_amd_1tb_hole = true; 1821 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1822 * to be used at the moment, 32K should be enough for a while. */ 1823 pcmc->acpi_data_size = 0x20000 + 0x8000; 1824 pcmc->pvh_enabled = true; 1825 pcmc->kvmclock_create_always = true; 1826 pcmc->resizable_acpi_blob = true; 1827 x86mc->apic_xrupt_override = true; 1828 assert(!mc->get_hotplug_handler); 1829 mc->get_hotplug_handler = pc_get_hotplug_handler; 1830 mc->hotplug_allowed = pc_hotplug_allowed; 1831 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1832 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1833 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1834 mc->auto_enable_numa_with_memhp = true; 1835 mc->auto_enable_numa_with_memdev = true; 1836 mc->has_hotpluggable_cpus = true; 1837 mc->default_boot_order = "cad"; 1838 mc->block_default_type = IF_IDE; 1839 mc->max_cpus = 255; 1840 mc->reset = pc_machine_reset; 1841 mc->wakeup = pc_machine_wakeup; 1842 hc->pre_plug = pc_machine_device_pre_plug_cb; 1843 hc->plug = pc_machine_device_plug_cb; 1844 hc->unplug_request = pc_machine_device_unplug_request_cb; 1845 hc->unplug = pc_machine_device_unplug_cb; 1846 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1847 mc->nvdimm_supported = true; 1848 mc->smp_props.dies_supported = true; 1849 mc->default_ram_id = "pc.ram"; 1850 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 1851 1852 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1853 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1854 NULL, NULL); 1855 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1856 "Maximum ram below the 4G boundary (32bit boundary)"); 1857 1858 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1859 pc_machine_get_vmport, pc_machine_set_vmport, 1860 NULL, NULL); 1861 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1862 "Enable vmport (pc & q35)"); 1863 1864 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1865 pc_machine_get_smbus, pc_machine_set_smbus); 1866 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1867 "Enable/disable system management bus"); 1868 1869 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1870 pc_machine_get_sata, pc_machine_set_sata); 1871 object_class_property_set_description(oc, PC_MACHINE_SATA, 1872 "Enable/disable Serial ATA bus"); 1873 1874 object_class_property_add_bool(oc, "hpet", 1875 pc_machine_get_hpet, pc_machine_set_hpet); 1876 object_class_property_set_description(oc, "hpet", 1877 "Enable/disable high precision event timer emulation"); 1878 1879 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1880 pc_machine_get_i8042, pc_machine_set_i8042); 1881 1882 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1883 pc_machine_get_default_bus_bypass_iommu, 1884 pc_machine_set_default_bus_bypass_iommu); 1885 1886 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1887 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1888 NULL, NULL); 1889 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1890 "Maximum combined firmware size"); 1891 1892 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1893 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1894 NULL, NULL); 1895 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1896 "SMBIOS Entry Point type [32, 64]"); 1897 1898 object_class_property_add_bool(oc, "fd-bootchk", 1899 pc_machine_get_fd_bootchk, 1900 pc_machine_set_fd_bootchk); 1901 } 1902 1903 static const TypeInfo pc_machine_info = { 1904 .name = TYPE_PC_MACHINE, 1905 .parent = TYPE_X86_MACHINE, 1906 .abstract = true, 1907 .instance_size = sizeof(PCMachineState), 1908 .instance_init = pc_machine_initfn, 1909 .class_size = sizeof(PCMachineClass), 1910 .class_init = pc_machine_class_init, 1911 .interfaces = (InterfaceInfo[]) { 1912 { TYPE_HOTPLUG_HANDLER }, 1913 { } 1914 }, 1915 }; 1916 1917 static void pc_machine_register_types(void) 1918 { 1919 type_register_static(&pc_machine_info); 1920 } 1921 1922 type_init(pc_machine_register_types) 1923