1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/cpu/icc_bus.h" 57 #include "hw/boards.h" 58 59 /* debug PC/ISA interrupts */ 60 //#define DEBUG_IRQ 61 62 #ifdef DEBUG_IRQ 63 #define DPRINTF(fmt, ...) \ 64 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 65 #else 66 #define DPRINTF(fmt, ...) 67 #endif 68 69 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 70 #define ACPI_DATA_SIZE 0x10000 71 #define BIOS_CFG_IOPORT 0x510 72 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 73 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 74 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 75 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 76 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 77 78 #define E820_NR_ENTRIES 16 79 80 struct e820_entry { 81 uint64_t address; 82 uint64_t length; 83 uint32_t type; 84 } QEMU_PACKED __attribute((__aligned__(4))); 85 86 struct e820_table { 87 uint32_t count; 88 struct e820_entry entry[E820_NR_ENTRIES]; 89 } QEMU_PACKED __attribute((__aligned__(4))); 90 91 static struct e820_table e820_table; 92 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 93 94 void gsi_handler(void *opaque, int n, int level) 95 { 96 GSIState *s = opaque; 97 98 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 99 if (n < ISA_NUM_IRQS) { 100 qemu_set_irq(s->i8259_irq[n], level); 101 } 102 qemu_set_irq(s->ioapic_irq[n], level); 103 } 104 105 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 106 unsigned size) 107 { 108 } 109 110 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 111 { 112 return 0xffffffffffffffffULL; 113 } 114 115 /* MSDOS compatibility mode FPU exception support */ 116 static qemu_irq ferr_irq; 117 118 void pc_register_ferr_irq(qemu_irq irq) 119 { 120 ferr_irq = irq; 121 } 122 123 /* XXX: add IGNNE support */ 124 void cpu_set_ferr(CPUX86State *s) 125 { 126 qemu_irq_raise(ferr_irq); 127 } 128 129 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 130 unsigned size) 131 { 132 qemu_irq_lower(ferr_irq); 133 } 134 135 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 136 { 137 return 0xffffffffffffffffULL; 138 } 139 140 /* TSC handling */ 141 uint64_t cpu_get_tsc(CPUX86State *env) 142 { 143 return cpu_get_ticks(); 144 } 145 146 /* SMM support */ 147 148 static cpu_set_smm_t smm_set; 149 static void *smm_arg; 150 151 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 152 { 153 assert(smm_set == NULL); 154 assert(smm_arg == NULL); 155 smm_set = callback; 156 smm_arg = arg; 157 } 158 159 void cpu_smm_update(CPUX86State *env) 160 { 161 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 162 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 163 } 164 } 165 166 167 /* IRQ handling */ 168 int cpu_get_pic_interrupt(CPUX86State *env) 169 { 170 int intno; 171 172 intno = apic_get_interrupt(env->apic_state); 173 if (intno >= 0) { 174 return intno; 175 } 176 /* read the irq from the PIC */ 177 if (!apic_accept_pic_intr(env->apic_state)) { 178 return -1; 179 } 180 181 intno = pic_read_irq(isa_pic); 182 return intno; 183 } 184 185 static void pic_irq_request(void *opaque, int irq, int level) 186 { 187 CPUState *cs = first_cpu; 188 X86CPU *cpu = X86_CPU(cs); 189 CPUX86State *env = &cpu->env; 190 191 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 192 if (env->apic_state) { 193 while (cs) { 194 cpu = X86_CPU(cs); 195 env = &cpu->env; 196 if (apic_accept_pic_intr(env->apic_state)) { 197 apic_deliver_pic_intr(env->apic_state, level); 198 } 199 cs = cs->next_cpu; 200 } 201 } else { 202 if (level) { 203 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 204 } else { 205 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 206 } 207 } 208 } 209 210 /* PC cmos mappings */ 211 212 #define REG_EQUIPMENT_BYTE 0x14 213 214 static int cmos_get_fd_drive_type(FDriveType fd0) 215 { 216 int val; 217 218 switch (fd0) { 219 case FDRIVE_DRV_144: 220 /* 1.44 Mb 3"5 drive */ 221 val = 4; 222 break; 223 case FDRIVE_DRV_288: 224 /* 2.88 Mb 3"5 drive */ 225 val = 5; 226 break; 227 case FDRIVE_DRV_120: 228 /* 1.2 Mb 5"5 drive */ 229 val = 2; 230 break; 231 case FDRIVE_DRV_NONE: 232 default: 233 val = 0; 234 break; 235 } 236 return val; 237 } 238 239 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 240 int16_t cylinders, int8_t heads, int8_t sectors) 241 { 242 rtc_set_memory(s, type_ofs, 47); 243 rtc_set_memory(s, info_ofs, cylinders); 244 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 245 rtc_set_memory(s, info_ofs + 2, heads); 246 rtc_set_memory(s, info_ofs + 3, 0xff); 247 rtc_set_memory(s, info_ofs + 4, 0xff); 248 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 249 rtc_set_memory(s, info_ofs + 6, cylinders); 250 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 251 rtc_set_memory(s, info_ofs + 8, sectors); 252 } 253 254 /* convert boot_device letter to something recognizable by the bios */ 255 static int boot_device2nibble(char boot_device) 256 { 257 switch(boot_device) { 258 case 'a': 259 case 'b': 260 return 0x01; /* floppy boot */ 261 case 'c': 262 return 0x02; /* hard drive boot */ 263 case 'd': 264 return 0x03; /* CD-ROM boot */ 265 case 'n': 266 return 0x04; /* Network boot */ 267 } 268 return 0; 269 } 270 271 static int set_boot_dev(ISADevice *s, const char *boot_device) 272 { 273 #define PC_MAX_BOOT_DEVICES 3 274 int nbds, bds[3] = { 0, }; 275 int i; 276 277 nbds = strlen(boot_device); 278 if (nbds > PC_MAX_BOOT_DEVICES) { 279 error_report("Too many boot devices for PC"); 280 return(1); 281 } 282 for (i = 0; i < nbds; i++) { 283 bds[i] = boot_device2nibble(boot_device[i]); 284 if (bds[i] == 0) { 285 error_report("Invalid boot device for PC: '%c'", 286 boot_device[i]); 287 return(1); 288 } 289 } 290 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 291 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 292 return(0); 293 } 294 295 static int pc_boot_set(void *opaque, const char *boot_device) 296 { 297 return set_boot_dev(opaque, boot_device); 298 } 299 300 typedef struct pc_cmos_init_late_arg { 301 ISADevice *rtc_state; 302 BusState *idebus[2]; 303 } pc_cmos_init_late_arg; 304 305 static void pc_cmos_init_late(void *opaque) 306 { 307 pc_cmos_init_late_arg *arg = opaque; 308 ISADevice *s = arg->rtc_state; 309 int16_t cylinders; 310 int8_t heads, sectors; 311 int val; 312 int i, trans; 313 314 val = 0; 315 if (ide_get_geometry(arg->idebus[0], 0, 316 &cylinders, &heads, §ors) >= 0) { 317 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 318 val |= 0xf0; 319 } 320 if (ide_get_geometry(arg->idebus[0], 1, 321 &cylinders, &heads, §ors) >= 0) { 322 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 323 val |= 0x0f; 324 } 325 rtc_set_memory(s, 0x12, val); 326 327 val = 0; 328 for (i = 0; i < 4; i++) { 329 /* NOTE: ide_get_geometry() returns the physical 330 geometry. It is always such that: 1 <= sects <= 63, 1 331 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 332 geometry can be different if a translation is done. */ 333 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 334 &cylinders, &heads, §ors) >= 0) { 335 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 336 assert((trans & ~3) == 0); 337 val |= trans << (i * 2); 338 } 339 } 340 rtc_set_memory(s, 0x39, val); 341 342 qemu_unregister_reset(pc_cmos_init_late, opaque); 343 } 344 345 typedef struct RTCCPUHotplugArg { 346 Notifier cpu_added_notifier; 347 ISADevice *rtc_state; 348 } RTCCPUHotplugArg; 349 350 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 351 { 352 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 353 cpu_added_notifier); 354 ISADevice *s = arg->rtc_state; 355 356 /* increment the number of CPUs */ 357 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 358 } 359 360 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 361 const char *boot_device, 362 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 363 ISADevice *s) 364 { 365 int val, nb, i; 366 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 367 static pc_cmos_init_late_arg arg; 368 static RTCCPUHotplugArg cpu_hotplug_cb; 369 370 /* various important CMOS locations needed by PC/Bochs bios */ 371 372 /* memory size */ 373 /* base memory (first MiB) */ 374 val = MIN(ram_size / 1024, 640); 375 rtc_set_memory(s, 0x15, val); 376 rtc_set_memory(s, 0x16, val >> 8); 377 /* extended memory (next 64MiB) */ 378 if (ram_size > 1024 * 1024) { 379 val = (ram_size - 1024 * 1024) / 1024; 380 } else { 381 val = 0; 382 } 383 if (val > 65535) 384 val = 65535; 385 rtc_set_memory(s, 0x17, val); 386 rtc_set_memory(s, 0x18, val >> 8); 387 rtc_set_memory(s, 0x30, val); 388 rtc_set_memory(s, 0x31, val >> 8); 389 /* memory between 16MiB and 4GiB */ 390 if (ram_size > 16 * 1024 * 1024) { 391 val = (ram_size - 16 * 1024 * 1024) / 65536; 392 } else { 393 val = 0; 394 } 395 if (val > 65535) 396 val = 65535; 397 rtc_set_memory(s, 0x34, val); 398 rtc_set_memory(s, 0x35, val >> 8); 399 /* memory above 4GiB */ 400 val = above_4g_mem_size / 65536; 401 rtc_set_memory(s, 0x5b, val); 402 rtc_set_memory(s, 0x5c, val >> 8); 403 rtc_set_memory(s, 0x5d, val >> 16); 404 405 /* set the number of CPU */ 406 rtc_set_memory(s, 0x5f, smp_cpus - 1); 407 /* init CPU hotplug notifier */ 408 cpu_hotplug_cb.rtc_state = s; 409 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 410 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 411 412 if (set_boot_dev(s, boot_device)) { 413 exit(1); 414 } 415 416 /* floppy type */ 417 if (floppy) { 418 for (i = 0; i < 2; i++) { 419 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 420 } 421 } 422 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 423 cmos_get_fd_drive_type(fd_type[1]); 424 rtc_set_memory(s, 0x10, val); 425 426 val = 0; 427 nb = 0; 428 if (fd_type[0] < FDRIVE_DRV_NONE) { 429 nb++; 430 } 431 if (fd_type[1] < FDRIVE_DRV_NONE) { 432 nb++; 433 } 434 switch (nb) { 435 case 0: 436 break; 437 case 1: 438 val |= 0x01; /* 1 drive, ready for boot */ 439 break; 440 case 2: 441 val |= 0x41; /* 2 drives, ready for boot */ 442 break; 443 } 444 val |= 0x02; /* FPU is there */ 445 val |= 0x04; /* PS/2 mouse installed */ 446 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 447 448 /* hard drives */ 449 arg.rtc_state = s; 450 arg.idebus[0] = idebus0; 451 arg.idebus[1] = idebus1; 452 qemu_register_reset(pc_cmos_init_late, &arg); 453 } 454 455 #define TYPE_PORT92 "port92" 456 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 457 458 /* port 92 stuff: could be split off */ 459 typedef struct Port92State { 460 ISADevice parent_obj; 461 462 MemoryRegion io; 463 uint8_t outport; 464 qemu_irq *a20_out; 465 } Port92State; 466 467 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 468 unsigned size) 469 { 470 Port92State *s = opaque; 471 472 DPRINTF("port92: write 0x%02x\n", val); 473 s->outport = val; 474 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 475 if (val & 1) { 476 qemu_system_reset_request(); 477 } 478 } 479 480 static uint64_t port92_read(void *opaque, hwaddr addr, 481 unsigned size) 482 { 483 Port92State *s = opaque; 484 uint32_t ret; 485 486 ret = s->outport; 487 DPRINTF("port92: read 0x%02x\n", ret); 488 return ret; 489 } 490 491 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 492 { 493 Port92State *s = PORT92(dev); 494 495 s->a20_out = a20_out; 496 } 497 498 static const VMStateDescription vmstate_port92_isa = { 499 .name = "port92", 500 .version_id = 1, 501 .minimum_version_id = 1, 502 .minimum_version_id_old = 1, 503 .fields = (VMStateField []) { 504 VMSTATE_UINT8(outport, Port92State), 505 VMSTATE_END_OF_LIST() 506 } 507 }; 508 509 static void port92_reset(DeviceState *d) 510 { 511 Port92State *s = PORT92(d); 512 513 s->outport &= ~1; 514 } 515 516 static const MemoryRegionOps port92_ops = { 517 .read = port92_read, 518 .write = port92_write, 519 .impl = { 520 .min_access_size = 1, 521 .max_access_size = 1, 522 }, 523 .endianness = DEVICE_LITTLE_ENDIAN, 524 }; 525 526 static void port92_initfn(Object *obj) 527 { 528 Port92State *s = PORT92(obj); 529 530 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 531 532 s->outport = 0; 533 } 534 535 static void port92_realizefn(DeviceState *dev, Error **errp) 536 { 537 ISADevice *isadev = ISA_DEVICE(dev); 538 Port92State *s = PORT92(dev); 539 540 isa_register_ioport(isadev, &s->io, 0x92); 541 } 542 543 static void port92_class_initfn(ObjectClass *klass, void *data) 544 { 545 DeviceClass *dc = DEVICE_CLASS(klass); 546 547 dc->no_user = 1; 548 dc->realize = port92_realizefn; 549 dc->reset = port92_reset; 550 dc->vmsd = &vmstate_port92_isa; 551 } 552 553 static const TypeInfo port92_info = { 554 .name = TYPE_PORT92, 555 .parent = TYPE_ISA_DEVICE, 556 .instance_size = sizeof(Port92State), 557 .instance_init = port92_initfn, 558 .class_init = port92_class_initfn, 559 }; 560 561 static void port92_register_types(void) 562 { 563 type_register_static(&port92_info); 564 } 565 566 type_init(port92_register_types) 567 568 static void handle_a20_line_change(void *opaque, int irq, int level) 569 { 570 X86CPU *cpu = opaque; 571 572 /* XXX: send to all CPUs ? */ 573 /* XXX: add logic to handle multiple A20 line sources */ 574 x86_cpu_set_a20(cpu, level); 575 } 576 577 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 578 { 579 int index = le32_to_cpu(e820_table.count); 580 struct e820_entry *entry; 581 582 if (index >= E820_NR_ENTRIES) 583 return -EBUSY; 584 entry = &e820_table.entry[index++]; 585 586 entry->address = cpu_to_le64(address); 587 entry->length = cpu_to_le64(length); 588 entry->type = cpu_to_le32(type); 589 590 e820_table.count = cpu_to_le32(index); 591 return index; 592 } 593 594 /* Calculates the limit to CPU APIC ID values 595 * 596 * This function returns the limit for the APIC ID value, so that all 597 * CPU APIC IDs are < pc_apic_id_limit(). 598 * 599 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 600 */ 601 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 602 { 603 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 604 } 605 606 static FWCfgState *bochs_bios_init(void) 607 { 608 FWCfgState *fw_cfg; 609 uint8_t *smbios_table; 610 size_t smbios_len; 611 uint64_t *numa_fw_cfg; 612 int i, j; 613 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 614 615 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 616 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 617 * 618 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 619 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 620 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 621 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 622 * may see". 623 * 624 * So, this means we must not use max_cpus, here, but the maximum possible 625 * APIC ID value, plus one. 626 * 627 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 628 * the APIC ID, not the "CPU index" 629 */ 630 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 631 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 632 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 633 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 634 acpi_tables, acpi_tables_len); 635 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 636 637 smbios_table = smbios_get_table(&smbios_len); 638 if (smbios_table) 639 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 640 smbios_table, smbios_len); 641 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 642 &e820_table, sizeof(e820_table)); 643 644 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 645 /* allocate memory for the NUMA channel: one (64bit) word for the number 646 * of nodes, one word for each VCPU->node and one word for each node to 647 * hold the amount of memory. 648 */ 649 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 650 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 651 for (i = 0; i < max_cpus; i++) { 652 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 653 assert(apic_id < apic_id_limit); 654 for (j = 0; j < nb_numa_nodes; j++) { 655 if (test_bit(i, node_cpumask[j])) { 656 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 657 break; 658 } 659 } 660 } 661 for (i = 0; i < nb_numa_nodes; i++) { 662 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(node_mem[i]); 663 } 664 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 665 (1 + apic_id_limit + nb_numa_nodes) * 666 sizeof(*numa_fw_cfg)); 667 668 return fw_cfg; 669 } 670 671 static long get_file_size(FILE *f) 672 { 673 long where, size; 674 675 /* XXX: on Unix systems, using fstat() probably makes more sense */ 676 677 where = ftell(f); 678 fseek(f, 0, SEEK_END); 679 size = ftell(f); 680 fseek(f, where, SEEK_SET); 681 682 return size; 683 } 684 685 static void load_linux(FWCfgState *fw_cfg, 686 const char *kernel_filename, 687 const char *initrd_filename, 688 const char *kernel_cmdline, 689 hwaddr max_ram_size) 690 { 691 uint16_t protocol; 692 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 693 uint32_t initrd_max; 694 uint8_t header[8192], *setup, *kernel, *initrd_data; 695 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 696 FILE *f; 697 char *vmode; 698 699 /* Align to 16 bytes as a paranoia measure */ 700 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 701 702 /* load the kernel header */ 703 f = fopen(kernel_filename, "rb"); 704 if (!f || !(kernel_size = get_file_size(f)) || 705 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 706 MIN(ARRAY_SIZE(header), kernel_size)) { 707 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 708 kernel_filename, strerror(errno)); 709 exit(1); 710 } 711 712 /* kernel protocol version */ 713 #if 0 714 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 715 #endif 716 if (ldl_p(header+0x202) == 0x53726448) { 717 protocol = lduw_p(header+0x206); 718 } else { 719 /* This looks like a multiboot kernel. If it is, let's stop 720 treating it like a Linux kernel. */ 721 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 722 kernel_cmdline, kernel_size, header)) { 723 return; 724 } 725 protocol = 0; 726 } 727 728 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 729 /* Low kernel */ 730 real_addr = 0x90000; 731 cmdline_addr = 0x9a000 - cmdline_size; 732 prot_addr = 0x10000; 733 } else if (protocol < 0x202) { 734 /* High but ancient kernel */ 735 real_addr = 0x90000; 736 cmdline_addr = 0x9a000 - cmdline_size; 737 prot_addr = 0x100000; 738 } else { 739 /* High and recent kernel */ 740 real_addr = 0x10000; 741 cmdline_addr = 0x20000; 742 prot_addr = 0x100000; 743 } 744 745 #if 0 746 fprintf(stderr, 747 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 748 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 749 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 750 real_addr, 751 cmdline_addr, 752 prot_addr); 753 #endif 754 755 /* highest address for loading the initrd */ 756 if (protocol >= 0x203) { 757 initrd_max = ldl_p(header+0x22c); 758 } else { 759 initrd_max = 0x37ffffff; 760 } 761 762 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE) 763 initrd_max = max_ram_size-ACPI_DATA_SIZE-1; 764 765 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 766 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 767 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 768 769 if (protocol >= 0x202) { 770 stl_p(header+0x228, cmdline_addr); 771 } else { 772 stw_p(header+0x20, 0xA33F); 773 stw_p(header+0x22, cmdline_addr-real_addr); 774 } 775 776 /* handle vga= parameter */ 777 vmode = strstr(kernel_cmdline, "vga="); 778 if (vmode) { 779 unsigned int video_mode; 780 /* skip "vga=" */ 781 vmode += 4; 782 if (!strncmp(vmode, "normal", 6)) { 783 video_mode = 0xffff; 784 } else if (!strncmp(vmode, "ext", 3)) { 785 video_mode = 0xfffe; 786 } else if (!strncmp(vmode, "ask", 3)) { 787 video_mode = 0xfffd; 788 } else { 789 video_mode = strtol(vmode, NULL, 0); 790 } 791 stw_p(header+0x1fa, video_mode); 792 } 793 794 /* loader type */ 795 /* High nybble = B reserved for QEMU; low nybble is revision number. 796 If this code is substantially changed, you may want to consider 797 incrementing the revision. */ 798 if (protocol >= 0x200) { 799 header[0x210] = 0xB0; 800 } 801 /* heap */ 802 if (protocol >= 0x201) { 803 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 804 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 805 } 806 807 /* load initrd */ 808 if (initrd_filename) { 809 if (protocol < 0x200) { 810 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 811 exit(1); 812 } 813 814 initrd_size = get_image_size(initrd_filename); 815 if (initrd_size < 0) { 816 fprintf(stderr, "qemu: error reading initrd %s\n", 817 initrd_filename); 818 exit(1); 819 } 820 821 initrd_addr = (initrd_max-initrd_size) & ~4095; 822 823 initrd_data = g_malloc(initrd_size); 824 load_image(initrd_filename, initrd_data); 825 826 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 827 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 828 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 829 830 stl_p(header+0x218, initrd_addr); 831 stl_p(header+0x21c, initrd_size); 832 } 833 834 /* load kernel and setup */ 835 setup_size = header[0x1f1]; 836 if (setup_size == 0) { 837 setup_size = 4; 838 } 839 setup_size = (setup_size+1)*512; 840 kernel_size -= setup_size; 841 842 setup = g_malloc(setup_size); 843 kernel = g_malloc(kernel_size); 844 fseek(f, 0, SEEK_SET); 845 if (fread(setup, 1, setup_size, f) != setup_size) { 846 fprintf(stderr, "fread() failed\n"); 847 exit(1); 848 } 849 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 850 fprintf(stderr, "fread() failed\n"); 851 exit(1); 852 } 853 fclose(f); 854 memcpy(setup, header, MIN(sizeof(header), setup_size)); 855 856 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 857 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 858 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 859 860 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 861 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 862 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 863 864 option_rom[nb_option_roms].name = "linuxboot.bin"; 865 option_rom[nb_option_roms].bootindex = 0; 866 nb_option_roms++; 867 } 868 869 #define NE2000_NB_MAX 6 870 871 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 872 0x280, 0x380 }; 873 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 874 875 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; 876 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; 877 878 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 879 { 880 static int nb_ne2k = 0; 881 882 if (nb_ne2k == NE2000_NB_MAX) 883 return; 884 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 885 ne2000_irq[nb_ne2k], nd); 886 nb_ne2k++; 887 } 888 889 DeviceState *cpu_get_current_apic(void) 890 { 891 if (current_cpu) { 892 X86CPU *cpu = X86_CPU(current_cpu); 893 return cpu->env.apic_state; 894 } else { 895 return NULL; 896 } 897 } 898 899 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 900 { 901 X86CPU *cpu = opaque; 902 903 if (level) { 904 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 905 } 906 } 907 908 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 909 DeviceState *icc_bridge, Error **errp) 910 { 911 X86CPU *cpu; 912 Error *local_err = NULL; 913 914 cpu = cpu_x86_create(cpu_model, icc_bridge, errp); 915 if (!cpu) { 916 return cpu; 917 } 918 919 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 920 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 921 922 if (local_err) { 923 if (cpu != NULL) { 924 object_unref(OBJECT(cpu)); 925 cpu = NULL; 926 } 927 error_propagate(errp, local_err); 928 } 929 return cpu; 930 } 931 932 static const char *current_cpu_model; 933 934 void pc_hot_add_cpu(const int64_t id, Error **errp) 935 { 936 DeviceState *icc_bridge; 937 int64_t apic_id = x86_cpu_apic_id_from_index(id); 938 939 if (id < 0) { 940 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 941 return; 942 } 943 944 if (cpu_exists(apic_id)) { 945 error_setg(errp, "Unable to add CPU: %" PRIi64 946 ", it already exists", id); 947 return; 948 } 949 950 if (id >= max_cpus) { 951 error_setg(errp, "Unable to add CPU: %" PRIi64 952 ", max allowed: %d", id, max_cpus - 1); 953 return; 954 } 955 956 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 957 TYPE_ICC_BRIDGE, NULL)); 958 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 959 } 960 961 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 962 { 963 int i; 964 X86CPU *cpu = NULL; 965 Error *error = NULL; 966 967 /* init CPUs */ 968 if (cpu_model == NULL) { 969 #ifdef TARGET_X86_64 970 cpu_model = "qemu64"; 971 #else 972 cpu_model = "qemu32"; 973 #endif 974 } 975 current_cpu_model = cpu_model; 976 977 for (i = 0; i < smp_cpus; i++) { 978 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 979 icc_bridge, &error); 980 if (error) { 981 fprintf(stderr, "%s\n", error_get_pretty(error)); 982 error_free(error); 983 exit(1); 984 } 985 } 986 987 /* map APIC MMIO area if CPU has APIC */ 988 if (cpu && cpu->env.apic_state) { 989 /* XXX: what if the base changes? */ 990 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 991 APIC_DEFAULT_ADDRESS, 0x1000); 992 } 993 } 994 995 /* pci-info ROM file. Little endian format */ 996 typedef struct PcRomPciInfo { 997 uint64_t w32_min; 998 uint64_t w32_max; 999 uint64_t w64_min; 1000 uint64_t w64_max; 1001 } PcRomPciInfo; 1002 1003 static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info) 1004 { 1005 PcRomPciInfo *info; 1006 if (!guest_info->has_pci_info || !guest_info->fw_cfg) { 1007 return; 1008 } 1009 1010 info = g_malloc(sizeof *info); 1011 info->w32_min = cpu_to_le64(guest_info->pci_info.w32.begin); 1012 info->w32_max = cpu_to_le64(guest_info->pci_info.w32.end); 1013 info->w64_min = cpu_to_le64(guest_info->pci_info.w64.begin); 1014 info->w64_max = cpu_to_le64(guest_info->pci_info.w64.end); 1015 /* Pass PCI hole info to guest via a side channel. 1016 * Required so guest PCI enumeration does the right thing. */ 1017 fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info); 1018 } 1019 1020 typedef struct PcGuestInfoState { 1021 PcGuestInfo info; 1022 Notifier machine_done; 1023 } PcGuestInfoState; 1024 1025 static 1026 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1027 { 1028 PcGuestInfoState *guest_info_state = container_of(notifier, 1029 PcGuestInfoState, 1030 machine_done); 1031 pc_fw_cfg_guest_info(&guest_info_state->info); 1032 } 1033 1034 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1035 ram_addr_t above_4g_mem_size) 1036 { 1037 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1038 PcGuestInfo *guest_info = &guest_info_state->info; 1039 1040 guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 1041 if (sizeof(hwaddr) == 4) { 1042 guest_info->pci_info.w64.begin = 0; 1043 guest_info->pci_info.w64.end = 0; 1044 } else { 1045 /* 1046 * BIOS does not set MTRR entries for the 64 bit window, so no need to 1047 * align address to power of two. Align address at 1G, this makes sure 1048 * it can be exactly covered with a PAT entry even when using huge 1049 * pages. 1050 */ 1051 guest_info->pci_info.w64.begin = 1052 ROUND_UP((0x1ULL << 32) + above_4g_mem_size, 0x1ULL << 30); 1053 guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin + 1054 (0x1ULL << 62); 1055 assert(guest_info->pci_info.w64.begin <= guest_info->pci_info.w64.end); 1056 } 1057 1058 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1059 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1060 return guest_info; 1061 } 1062 1063 void pc_acpi_init(const char *default_dsdt) 1064 { 1065 char *filename; 1066 1067 if (acpi_tables != NULL) { 1068 /* manually set via -acpitable, leave it alone */ 1069 return; 1070 } 1071 1072 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1073 if (filename == NULL) { 1074 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1075 } else { 1076 char *arg; 1077 QemuOpts *opts; 1078 Error *err = NULL; 1079 1080 arg = g_strdup_printf("file=%s", filename); 1081 1082 /* creates a deep copy of "arg" */ 1083 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1084 g_assert(opts != NULL); 1085 1086 acpi_table_add(opts, &err); 1087 if (err) { 1088 fprintf(stderr, "WARNING: failed to load %s: %s\n", filename, 1089 error_get_pretty(err)); 1090 error_free(err); 1091 } 1092 g_free(arg); 1093 g_free(filename); 1094 } 1095 } 1096 1097 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 1098 const char *kernel_filename, 1099 const char *kernel_cmdline, 1100 const char *initrd_filename, 1101 ram_addr_t below_4g_mem_size, 1102 ram_addr_t above_4g_mem_size, 1103 MemoryRegion *rom_memory, 1104 MemoryRegion **ram_memory, 1105 PcGuestInfo *guest_info) 1106 { 1107 int linux_boot, i; 1108 MemoryRegion *ram, *option_rom_mr; 1109 MemoryRegion *ram_below_4g, *ram_above_4g; 1110 FWCfgState *fw_cfg; 1111 1112 linux_boot = (kernel_filename != NULL); 1113 1114 /* Allocate RAM. We allocate it as a single memory region and use 1115 * aliases to address portions of it, mostly for backwards compatibility 1116 * with older qemus that used qemu_ram_alloc(). 1117 */ 1118 ram = g_malloc(sizeof(*ram)); 1119 memory_region_init_ram(ram, NULL, "pc.ram", 1120 below_4g_mem_size + above_4g_mem_size); 1121 vmstate_register_ram_global(ram); 1122 *ram_memory = ram; 1123 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1124 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1125 0, below_4g_mem_size); 1126 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1127 if (above_4g_mem_size > 0) { 1128 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1129 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1130 below_4g_mem_size, above_4g_mem_size); 1131 memory_region_add_subregion(system_memory, 0x100000000ULL, 1132 ram_above_4g); 1133 } 1134 1135 1136 /* Initialize PC system firmware */ 1137 pc_system_firmware_init(rom_memory); 1138 1139 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1140 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); 1141 vmstate_register_ram_global(option_rom_mr); 1142 memory_region_add_subregion_overlap(rom_memory, 1143 PC_ROM_MIN_VGA, 1144 option_rom_mr, 1145 1); 1146 1147 fw_cfg = bochs_bios_init(); 1148 rom_set_fw(fw_cfg); 1149 1150 if (linux_boot) { 1151 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); 1152 } 1153 1154 for (i = 0; i < nb_option_roms; i++) { 1155 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1156 } 1157 guest_info->fw_cfg = fw_cfg; 1158 return fw_cfg; 1159 } 1160 1161 qemu_irq *pc_allocate_cpu_irq(void) 1162 { 1163 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1164 } 1165 1166 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1167 { 1168 DeviceState *dev = NULL; 1169 1170 if (pci_bus) { 1171 PCIDevice *pcidev = pci_vga_init(pci_bus); 1172 dev = pcidev ? &pcidev->qdev : NULL; 1173 } else if (isa_bus) { 1174 ISADevice *isadev = isa_vga_init(isa_bus); 1175 dev = isadev ? DEVICE(isadev) : NULL; 1176 } 1177 return dev; 1178 } 1179 1180 static void cpu_request_exit(void *opaque, int irq, int level) 1181 { 1182 CPUState *cpu = current_cpu; 1183 1184 if (cpu && level) { 1185 cpu_exit(cpu); 1186 } 1187 } 1188 1189 static const MemoryRegionOps ioport80_io_ops = { 1190 .write = ioport80_write, 1191 .read = ioport80_read, 1192 .endianness = DEVICE_NATIVE_ENDIAN, 1193 .impl = { 1194 .min_access_size = 1, 1195 .max_access_size = 1, 1196 }, 1197 }; 1198 1199 static const MemoryRegionOps ioportF0_io_ops = { 1200 .write = ioportF0_write, 1201 .read = ioportF0_read, 1202 .endianness = DEVICE_NATIVE_ENDIAN, 1203 .impl = { 1204 .min_access_size = 1, 1205 .max_access_size = 1, 1206 }, 1207 }; 1208 1209 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1210 ISADevice **rtc_state, 1211 ISADevice **floppy, 1212 bool no_vmport) 1213 { 1214 int i; 1215 DriveInfo *fd[MAX_FD]; 1216 DeviceState *hpet = NULL; 1217 int pit_isa_irq = 0; 1218 qemu_irq pit_alt_irq = NULL; 1219 qemu_irq rtc_irq = NULL; 1220 qemu_irq *a20_line; 1221 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1222 qemu_irq *cpu_exit_irq; 1223 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1224 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1225 1226 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1227 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1228 1229 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1230 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1231 1232 /* 1233 * Check if an HPET shall be created. 1234 * 1235 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1236 * when the HPET wants to take over. Thus we have to disable the latter. 1237 */ 1238 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1239 hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); 1240 1241 if (hpet) { 1242 for (i = 0; i < GSI_NUM_PINS; i++) { 1243 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1244 } 1245 pit_isa_irq = -1; 1246 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1247 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1248 } 1249 } 1250 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1251 1252 qemu_register_boot_set(pc_boot_set, *rtc_state); 1253 1254 if (!xen_enabled()) { 1255 if (kvm_irqchip_in_kernel()) { 1256 pit = kvm_pit_init(isa_bus, 0x40); 1257 } else { 1258 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1259 } 1260 if (hpet) { 1261 /* connect PIT to output control line of the HPET */ 1262 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1263 } 1264 pcspk_init(isa_bus, pit); 1265 } 1266 1267 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1268 if (serial_hds[i]) { 1269 serial_isa_init(isa_bus, i, serial_hds[i]); 1270 } 1271 } 1272 1273 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1274 if (parallel_hds[i]) { 1275 parallel_init(isa_bus, i, parallel_hds[i]); 1276 } 1277 } 1278 1279 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1280 i8042 = isa_create_simple(isa_bus, "i8042"); 1281 i8042_setup_a20_line(i8042, &a20_line[0]); 1282 if (!no_vmport) { 1283 vmport_init(isa_bus); 1284 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1285 } else { 1286 vmmouse = NULL; 1287 } 1288 if (vmmouse) { 1289 DeviceState *dev = DEVICE(vmmouse); 1290 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1291 qdev_init_nofail(dev); 1292 } 1293 port92 = isa_create_simple(isa_bus, "port92"); 1294 port92_init(port92, &a20_line[1]); 1295 1296 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1297 DMA_init(0, cpu_exit_irq); 1298 1299 for(i = 0; i < MAX_FD; i++) { 1300 fd[i] = drive_get(IF_FLOPPY, 0, i); 1301 } 1302 *floppy = fdctrl_init_isa(isa_bus, fd); 1303 } 1304 1305 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1306 { 1307 int i; 1308 1309 for (i = 0; i < nb_nics; i++) { 1310 NICInfo *nd = &nd_table[i]; 1311 1312 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1313 pc_init_ne2k_isa(isa_bus, nd); 1314 } else { 1315 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1316 } 1317 } 1318 } 1319 1320 void pc_pci_device_init(PCIBus *pci_bus) 1321 { 1322 int max_bus; 1323 int bus; 1324 1325 max_bus = drive_get_max_bus(IF_SCSI); 1326 for (bus = 0; bus <= max_bus; bus++) { 1327 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1328 } 1329 } 1330 1331 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1332 { 1333 DeviceState *dev; 1334 SysBusDevice *d; 1335 unsigned int i; 1336 1337 if (kvm_irqchip_in_kernel()) { 1338 dev = qdev_create(NULL, "kvm-ioapic"); 1339 } else { 1340 dev = qdev_create(NULL, "ioapic"); 1341 } 1342 if (parent_name) { 1343 object_property_add_child(object_resolve_path(parent_name, NULL), 1344 "ioapic", OBJECT(dev), NULL); 1345 } 1346 qdev_init_nofail(dev); 1347 d = SYS_BUS_DEVICE(dev); 1348 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1349 1350 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1351 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1352 } 1353 } 1354