1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/i386/fw_cfg.h" 31 #include "hw/i386/vmport.h" 32 #include "sysemu/cpus.h" 33 #include "hw/ide/internal.h" 34 #include "hw/timer/hpet.h" 35 #include "hw/loader.h" 36 #include "hw/rtc/mc146818rtc.h" 37 #include "hw/intc/i8259.h" 38 #include "hw/timer/i8254.h" 39 #include "hw/input/i8042.h" 40 #include "hw/audio/pcspk.h" 41 #include "sysemu/sysemu.h" 42 #include "sysemu/xen.h" 43 #include "sysemu/reset.h" 44 #include "kvm/kvm_i386.h" 45 #include "hw/xen/xen.h" 46 #include "qemu/error-report.h" 47 #include "hw/acpi/cpu_hotplug.h" 48 #include "acpi-build.h" 49 #include "hw/mem/nvdimm.h" 50 #include "hw/cxl/cxl_host.h" 51 #include "hw/usb.h" 52 #include "hw/i386/intel_iommu.h" 53 #include "hw/net/ne2000-isa.h" 54 #include "hw/virtio/virtio-iommu.h" 55 #include "hw/virtio/virtio-md-pci.h" 56 #include "hw/i386/kvm/xen_overlay.h" 57 #include "hw/i386/kvm/xen_evtchn.h" 58 #include "hw/i386/kvm/xen_gnttab.h" 59 #include "hw/i386/kvm/xen_xenstore.h" 60 #include "e820_memory_layout.h" 61 #include "trace.h" 62 #include CONFIG_DEVICES 63 64 #ifdef CONFIG_XEN_EMU 65 #include "hw/xen/xen-legacy-backend.h" 66 #include "hw/xen/xen-bus.h" 67 #endif 68 69 /* 70 * Helper for setting model-id for CPU models that changed model-id 71 * depending on QEMU versions up to QEMU 2.4. 72 */ 73 #define PC_CPU_MODEL_IDS(v) \ 74 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 75 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 76 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 77 78 GlobalProperty pc_compat_8_1[] = {}; 79 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 80 81 GlobalProperty pc_compat_8_0[] = { 82 { "virtio-mem", "unplugged-inaccessible", "auto" }, 83 }; 84 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 85 86 GlobalProperty pc_compat_7_2[] = { 87 { "ICH9-LPC", "noreboot", "true" }, 88 }; 89 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 90 91 GlobalProperty pc_compat_7_1[] = {}; 92 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 93 94 GlobalProperty pc_compat_7_0[] = {}; 95 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 96 97 GlobalProperty pc_compat_6_2[] = { 98 { "virtio-mem", "unplugged-inaccessible", "off" }, 99 }; 100 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 101 102 GlobalProperty pc_compat_6_1[] = { 103 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 104 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 105 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 106 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 107 }; 108 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 109 110 GlobalProperty pc_compat_6_0[] = { 111 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 112 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 113 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 114 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 115 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 116 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 117 }; 118 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 119 120 GlobalProperty pc_compat_5_2[] = { 121 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 122 }; 123 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 124 125 GlobalProperty pc_compat_5_1[] = { 126 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 127 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 128 }; 129 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 130 131 GlobalProperty pc_compat_5_0[] = { 132 }; 133 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 134 135 GlobalProperty pc_compat_4_2[] = { 136 { "mch", "smbase-smram", "off" }, 137 }; 138 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 139 140 GlobalProperty pc_compat_4_1[] = {}; 141 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 142 143 GlobalProperty pc_compat_4_0[] = {}; 144 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 145 146 GlobalProperty pc_compat_3_1[] = { 147 { "intel-iommu", "dma-drain", "off" }, 148 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 149 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 150 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 151 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 152 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 153 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 154 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 155 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 156 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 157 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 158 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 159 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 160 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 161 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 162 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 163 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 164 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 165 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 167 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 168 }; 169 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 170 171 GlobalProperty pc_compat_3_0[] = { 172 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 173 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 174 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 175 }; 176 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 177 178 GlobalProperty pc_compat_2_12[] = { 179 { TYPE_X86_CPU, "legacy-cache", "on" }, 180 { TYPE_X86_CPU, "topoext", "off" }, 181 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 182 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 183 }; 184 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 185 186 GlobalProperty pc_compat_2_11[] = { 187 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 188 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 189 }; 190 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 191 192 GlobalProperty pc_compat_2_10[] = { 193 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 194 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 195 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 196 }; 197 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 198 199 GlobalProperty pc_compat_2_9[] = { 200 { "mch", "extended-tseg-mbytes", "0" }, 201 }; 202 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 203 204 GlobalProperty pc_compat_2_8[] = { 205 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 206 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 207 { "ICH9-LPC", "x-smi-broadcast", "off" }, 208 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 209 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 210 }; 211 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 212 213 GlobalProperty pc_compat_2_7[] = { 214 { TYPE_X86_CPU, "l3-cache", "off" }, 215 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 216 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 217 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 218 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 219 { "isa-pcspk", "migrate", "off" }, 220 }; 221 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 222 223 GlobalProperty pc_compat_2_6[] = { 224 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 225 { "vmxnet3", "romfile", "" }, 226 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 227 { "apic-common", "legacy-instance-id", "on", } 228 }; 229 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 230 231 GlobalProperty pc_compat_2_5[] = {}; 232 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 233 234 GlobalProperty pc_compat_2_4[] = { 235 PC_CPU_MODEL_IDS("2.4.0") 236 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 237 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 238 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 239 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 240 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 241 { TYPE_X86_CPU, "check", "off" }, 242 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 243 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 244 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 245 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 246 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 247 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 248 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 249 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 250 }; 251 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 252 253 GlobalProperty pc_compat_2_3[] = { 254 PC_CPU_MODEL_IDS("2.3.0") 255 { TYPE_X86_CPU, "arat", "off" }, 256 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 257 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 258 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 259 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 260 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 261 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 262 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 264 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 265 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 266 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 267 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 268 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 269 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 275 }; 276 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 277 278 GlobalProperty pc_compat_2_2[] = { 279 PC_CPU_MODEL_IDS("2.2.0") 280 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 281 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 282 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 283 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 284 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 285 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 286 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 295 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 296 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 297 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 298 }; 299 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 300 301 GlobalProperty pc_compat_2_1[] = { 302 PC_CPU_MODEL_IDS("2.1.0") 303 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 304 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 305 }; 306 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 307 308 GlobalProperty pc_compat_2_0[] = { 309 PC_CPU_MODEL_IDS("2.0.0") 310 { "virtio-scsi-pci", "any_layout", "off" }, 311 { "PIIX4_PM", "memory-hotplug-support", "off" }, 312 { "apic", "version", "0x11" }, 313 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 314 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 315 { "pci-serial", "prog_if", "0" }, 316 { "pci-serial-2x", "prog_if", "0" }, 317 { "pci-serial-4x", "prog_if", "0" }, 318 { "virtio-net-pci", "guest_announce", "off" }, 319 { "ICH9-LPC", "memory-hotplug-support", "off" }, 320 }; 321 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 322 323 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 324 { 325 GSIState *s; 326 327 s = g_new0(GSIState, 1); 328 if (kvm_ioapic_in_kernel()) { 329 kvm_pc_setup_irq_routing(pci_enabled); 330 } 331 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 332 333 return s; 334 } 335 336 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 337 unsigned size) 338 { 339 } 340 341 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 342 { 343 return 0xffffffffffffffffULL; 344 } 345 346 /* MS-DOS compatibility mode FPU exception support */ 347 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 348 unsigned size) 349 { 350 if (tcg_enabled()) { 351 cpu_set_ignne(); 352 } 353 } 354 355 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 356 { 357 return 0xffffffffffffffffULL; 358 } 359 360 /* PC cmos mappings */ 361 362 #define REG_EQUIPMENT_BYTE 0x14 363 364 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 365 int16_t cylinders, int8_t heads, int8_t sectors) 366 { 367 mc146818rtc_set_cmos_data(s, type_ofs, 47); 368 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 369 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 370 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 371 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 372 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 373 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 374 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 375 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 376 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 377 } 378 379 /* convert boot_device letter to something recognizable by the bios */ 380 static int boot_device2nibble(char boot_device) 381 { 382 switch(boot_device) { 383 case 'a': 384 case 'b': 385 return 0x01; /* floppy boot */ 386 case 'c': 387 return 0x02; /* hard drive boot */ 388 case 'd': 389 return 0x03; /* CD-ROM boot */ 390 case 'n': 391 return 0x04; /* Network boot */ 392 } 393 return 0; 394 } 395 396 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 397 Error **errp) 398 { 399 #define PC_MAX_BOOT_DEVICES 3 400 int nbds, bds[3] = { 0, }; 401 int i; 402 403 nbds = strlen(boot_device); 404 if (nbds > PC_MAX_BOOT_DEVICES) { 405 error_setg(errp, "Too many boot devices for PC"); 406 return; 407 } 408 for (i = 0; i < nbds; i++) { 409 bds[i] = boot_device2nibble(boot_device[i]); 410 if (bds[i] == 0) { 411 error_setg(errp, "Invalid boot device for PC: '%c'", 412 boot_device[i]); 413 return; 414 } 415 } 416 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 417 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 418 } 419 420 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 421 { 422 set_boot_dev(opaque, boot_device, errp); 423 } 424 425 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 426 { 427 int val, nb, i; 428 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 429 FLOPPY_DRIVE_TYPE_NONE }; 430 431 /* floppy type */ 432 if (floppy) { 433 for (i = 0; i < 2; i++) { 434 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 435 } 436 } 437 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 438 cmos_get_fd_drive_type(fd_type[1]); 439 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 440 441 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 442 nb = 0; 443 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 444 nb++; 445 } 446 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 447 nb++; 448 } 449 switch (nb) { 450 case 0: 451 break; 452 case 1: 453 val |= 0x01; /* 1 drive, ready for boot */ 454 break; 455 case 2: 456 val |= 0x41; /* 2 drives, ready for boot */ 457 break; 458 } 459 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 460 } 461 462 typedef struct pc_cmos_init_late_arg { 463 MC146818RtcState *rtc_state; 464 BusState *idebus[2]; 465 } pc_cmos_init_late_arg; 466 467 typedef struct check_fdc_state { 468 ISADevice *floppy; 469 bool multiple; 470 } CheckFdcState; 471 472 static int check_fdc(Object *obj, void *opaque) 473 { 474 CheckFdcState *state = opaque; 475 Object *fdc; 476 uint32_t iobase; 477 Error *local_err = NULL; 478 479 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 480 if (!fdc) { 481 return 0; 482 } 483 484 iobase = object_property_get_uint(obj, "iobase", &local_err); 485 if (local_err || iobase != 0x3f0) { 486 error_free(local_err); 487 return 0; 488 } 489 490 if (state->floppy) { 491 state->multiple = true; 492 } else { 493 state->floppy = ISA_DEVICE(obj); 494 } 495 return 0; 496 } 497 498 static const char * const fdc_container_path[] = { 499 "/unattached", "/peripheral", "/peripheral-anon" 500 }; 501 502 /* 503 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 504 * and ACPI objects. 505 */ 506 static ISADevice *pc_find_fdc0(void) 507 { 508 int i; 509 Object *container; 510 CheckFdcState state = { 0 }; 511 512 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 513 container = container_get(qdev_get_machine(), fdc_container_path[i]); 514 object_child_foreach(container, check_fdc, &state); 515 } 516 517 if (state.multiple) { 518 warn_report("multiple floppy disk controllers with " 519 "iobase=0x3f0 have been found"); 520 error_printf("the one being picked for CMOS setup might not reflect " 521 "your intent"); 522 } 523 524 return state.floppy; 525 } 526 527 static void pc_cmos_init_late(void *opaque) 528 { 529 pc_cmos_init_late_arg *arg = opaque; 530 MC146818RtcState *s = arg->rtc_state; 531 int16_t cylinders; 532 int8_t heads, sectors; 533 int val; 534 int i, trans; 535 536 val = 0; 537 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 538 &cylinders, &heads, §ors) >= 0) { 539 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 540 val |= 0xf0; 541 } 542 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 543 &cylinders, &heads, §ors) >= 0) { 544 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 545 val |= 0x0f; 546 } 547 mc146818rtc_set_cmos_data(s, 0x12, val); 548 549 val = 0; 550 for (i = 0; i < 4; i++) { 551 /* NOTE: ide_get_geometry() returns the physical 552 geometry. It is always such that: 1 <= sects <= 63, 1 553 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 554 geometry can be different if a translation is done. */ 555 if (arg->idebus[i / 2] && 556 ide_get_geometry(arg->idebus[i / 2], i % 2, 557 &cylinders, &heads, §ors) >= 0) { 558 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 559 assert((trans & ~3) == 0); 560 val |= trans << (i * 2); 561 } 562 } 563 mc146818rtc_set_cmos_data(s, 0x39, val); 564 565 pc_cmos_init_floppy(s, pc_find_fdc0()); 566 567 qemu_unregister_reset(pc_cmos_init_late, opaque); 568 } 569 570 void pc_cmos_init(PCMachineState *pcms, 571 BusState *idebus0, BusState *idebus1, 572 ISADevice *rtc) 573 { 574 int val; 575 static pc_cmos_init_late_arg arg; 576 X86MachineState *x86ms = X86_MACHINE(pcms); 577 MC146818RtcState *s = MC146818_RTC(rtc); 578 579 /* various important CMOS locations needed by PC/Bochs bios */ 580 581 /* memory size */ 582 /* base memory (first MiB) */ 583 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 584 mc146818rtc_set_cmos_data(s, 0x15, val); 585 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 586 /* extended memory (next 64MiB) */ 587 if (x86ms->below_4g_mem_size > 1 * MiB) { 588 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 589 } else { 590 val = 0; 591 } 592 if (val > 65535) 593 val = 65535; 594 mc146818rtc_set_cmos_data(s, 0x17, val); 595 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 596 mc146818rtc_set_cmos_data(s, 0x30, val); 597 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 598 /* memory between 16MiB and 4GiB */ 599 if (x86ms->below_4g_mem_size > 16 * MiB) { 600 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 601 } else { 602 val = 0; 603 } 604 if (val > 65535) 605 val = 65535; 606 mc146818rtc_set_cmos_data(s, 0x34, val); 607 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 608 /* memory above 4GiB */ 609 val = x86ms->above_4g_mem_size / 65536; 610 mc146818rtc_set_cmos_data(s, 0x5b, val); 611 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 612 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 613 614 object_property_add_link(OBJECT(pcms), "rtc_state", 615 TYPE_ISA_DEVICE, 616 (Object **)&x86ms->rtc, 617 object_property_allow_set_link, 618 OBJ_PROP_LINK_STRONG); 619 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 620 &error_abort); 621 622 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 623 624 val = 0; 625 val |= 0x02; /* FPU is there */ 626 val |= 0x04; /* PS/2 mouse installed */ 627 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 628 629 /* hard drives and FDC */ 630 arg.rtc_state = s; 631 arg.idebus[0] = idebus0; 632 arg.idebus[1] = idebus1; 633 qemu_register_reset(pc_cmos_init_late, &arg); 634 } 635 636 static void handle_a20_line_change(void *opaque, int irq, int level) 637 { 638 X86CPU *cpu = opaque; 639 640 /* XXX: send to all CPUs ? */ 641 /* XXX: add logic to handle multiple A20 line sources */ 642 x86_cpu_set_a20(cpu, level); 643 } 644 645 #define NE2000_NB_MAX 6 646 647 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 648 0x280, 0x380 }; 649 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 650 651 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 652 { 653 static int nb_ne2k = 0; 654 655 if (nb_ne2k == NE2000_NB_MAX) 656 return; 657 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 658 ne2000_irq[nb_ne2k], nd); 659 nb_ne2k++; 660 } 661 662 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 663 { 664 X86CPU *cpu = opaque; 665 666 if (level) { 667 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 668 } 669 } 670 671 static 672 void pc_machine_done(Notifier *notifier, void *data) 673 { 674 PCMachineState *pcms = container_of(notifier, 675 PCMachineState, machine_done); 676 X86MachineState *x86ms = X86_MACHINE(pcms); 677 678 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 679 &error_fatal); 680 681 if (pcms->cxl_devices_state.is_enabled) { 682 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 683 } 684 685 /* set the number of CPUs */ 686 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 687 688 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 689 690 acpi_setup(); 691 if (x86ms->fw_cfg) { 692 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 693 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 694 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 695 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 696 } 697 } 698 699 void pc_guest_info_init(PCMachineState *pcms) 700 { 701 X86MachineState *x86ms = X86_MACHINE(pcms); 702 703 x86ms->apic_xrupt_override = true; 704 pcms->machine_done.notify = pc_machine_done; 705 qemu_add_machine_init_done_notifier(&pcms->machine_done); 706 } 707 708 /* setup pci memory address space mapping into system address space */ 709 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 710 MemoryRegion *pci_address_space) 711 { 712 /* Set to lower priority than RAM */ 713 memory_region_add_subregion_overlap(system_memory, 0x0, 714 pci_address_space, -1); 715 } 716 717 void xen_load_linux(PCMachineState *pcms) 718 { 719 int i; 720 FWCfgState *fw_cfg; 721 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 722 X86MachineState *x86ms = X86_MACHINE(pcms); 723 724 assert(MACHINE(pcms)->kernel_filename != NULL); 725 726 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 727 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 728 rom_set_fw(fw_cfg); 729 730 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 731 pcmc->pvh_enabled); 732 for (i = 0; i < nb_option_roms; i++) { 733 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 734 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 735 !strcmp(option_rom[i].name, "pvh.bin") || 736 !strcmp(option_rom[i].name, "multiboot.bin") || 737 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 738 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 739 } 740 x86ms->fw_cfg = fw_cfg; 741 } 742 743 #define PC_ROM_MIN_VGA 0xc0000 744 #define PC_ROM_MIN_OPTION 0xc8000 745 #define PC_ROM_MAX 0xe0000 746 #define PC_ROM_ALIGN 0x800 747 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 748 749 static hwaddr pc_above_4g_end(PCMachineState *pcms) 750 { 751 X86MachineState *x86ms = X86_MACHINE(pcms); 752 753 if (pcms->sgx_epc.size != 0) { 754 return sgx_epc_above_4g_end(&pcms->sgx_epc); 755 } 756 757 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 758 } 759 760 static void pc_get_device_memory_range(PCMachineState *pcms, 761 hwaddr *base, 762 ram_addr_t *device_mem_size) 763 { 764 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 765 MachineState *machine = MACHINE(pcms); 766 ram_addr_t size; 767 hwaddr addr; 768 769 size = machine->maxram_size - machine->ram_size; 770 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 771 772 if (pcmc->enforce_aligned_dimm) { 773 /* size device region assuming 1G page max alignment per slot */ 774 size += (1 * GiB) * machine->ram_slots; 775 } 776 777 *base = addr; 778 *device_mem_size = size; 779 } 780 781 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 782 { 783 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 784 MachineState *ms = MACHINE(pcms); 785 hwaddr cxl_base; 786 ram_addr_t size; 787 788 if (pcmc->has_reserved_memory && 789 (ms->ram_size < ms->maxram_size)) { 790 pc_get_device_memory_range(pcms, &cxl_base, &size); 791 cxl_base += size; 792 } else { 793 cxl_base = pc_above_4g_end(pcms); 794 } 795 796 return cxl_base; 797 } 798 799 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 800 { 801 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 802 803 if (pcms->cxl_devices_state.fixed_windows) { 804 GList *it; 805 806 start = ROUND_UP(start, 256 * MiB); 807 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 808 CXLFixedWindow *fw = it->data; 809 start += fw->size; 810 } 811 } 812 813 return start; 814 } 815 816 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 817 { 818 X86CPU *cpu = X86_CPU(first_cpu); 819 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 820 MachineState *ms = MACHINE(pcms); 821 822 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 823 /* 64-bit systems */ 824 return pc_pci_hole64_start() + pci_hole64_size - 1; 825 } 826 827 /* 32-bit systems */ 828 if (pcmc->broken_32bit_mem_addr_check) { 829 /* old value for compatibility reasons */ 830 return ((hwaddr)1 << cpu->phys_bits) - 1; 831 } 832 833 /* 834 * 32-bit systems don't have hole64 but they might have a region for 835 * memory devices. Even if additional hotplugged memory devices might 836 * not be usable by most guest OSes, we need to still consider them for 837 * calculating the highest possible GPA so that we can properly report 838 * if someone configures them on a CPU that cannot possibly address them. 839 */ 840 if (pcmc->has_reserved_memory && 841 (ms->ram_size < ms->maxram_size)) { 842 hwaddr devmem_start; 843 ram_addr_t devmem_size; 844 845 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 846 devmem_start += devmem_size; 847 return devmem_start - 1; 848 } 849 850 /* configuration without any memory hotplug */ 851 return pc_above_4g_end(pcms) - 1; 852 } 853 854 /* 855 * AMD systems with an IOMMU have an additional hole close to the 856 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 857 * on kernel version, VFIO may or may not let you DMA map those ranges. 858 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 859 * with certain memory sizes. It's also wrong to use those IOVA ranges 860 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 861 * The ranges reserved for Hyper-Transport are: 862 * 863 * FD_0000_0000h - FF_FFFF_FFFFh 864 * 865 * The ranges represent the following: 866 * 867 * Base Address Top Address Use 868 * 869 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 870 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 871 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 872 * FD_F910_0000h FD_F91F_FFFFh System Management 873 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 874 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 875 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 876 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 877 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 878 * FE_2000_0000h FF_FFFF_FFFFh Reserved 879 * 880 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 881 * Table 3: Special Address Controls (GPA) for more information. 882 */ 883 #define AMD_HT_START 0xfd00000000UL 884 #define AMD_HT_END 0xffffffffffUL 885 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 886 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 887 888 void pc_memory_init(PCMachineState *pcms, 889 MemoryRegion *system_memory, 890 MemoryRegion *rom_memory, 891 uint64_t pci_hole64_size) 892 { 893 int linux_boot, i; 894 MemoryRegion *option_rom_mr; 895 MemoryRegion *ram_below_4g, *ram_above_4g; 896 FWCfgState *fw_cfg; 897 MachineState *machine = MACHINE(pcms); 898 MachineClass *mc = MACHINE_GET_CLASS(machine); 899 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 900 X86MachineState *x86ms = X86_MACHINE(pcms); 901 hwaddr maxphysaddr, maxusedaddr; 902 hwaddr cxl_base, cxl_resv_end = 0; 903 X86CPU *cpu = X86_CPU(first_cpu); 904 905 assert(machine->ram_size == x86ms->below_4g_mem_size + 906 x86ms->above_4g_mem_size); 907 908 linux_boot = (machine->kernel_filename != NULL); 909 910 /* 911 * The HyperTransport range close to the 1T boundary is unique to AMD 912 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 913 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 914 * older machine types (<= 7.0) for compatibility purposes. 915 */ 916 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 917 /* Bail out if max possible address does not cross HT range */ 918 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 919 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 920 } 921 922 /* 923 * Advertise the HT region if address space covers the reserved 924 * region or if we relocate. 925 */ 926 if (cpu->phys_bits >= 40) { 927 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 928 } 929 } 930 931 /* 932 * phys-bits is required to be appropriately configured 933 * to make sure max used GPA is reachable. 934 */ 935 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 936 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 937 if (maxphysaddr < maxusedaddr) { 938 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 939 " phys-bits too low (%u)", 940 maxphysaddr, maxusedaddr, cpu->phys_bits); 941 exit(EXIT_FAILURE); 942 } 943 944 /* 945 * Split single memory region and use aliases to address portions of it, 946 * done for backwards compatibility with older qemus. 947 */ 948 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 949 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 950 0, x86ms->below_4g_mem_size); 951 memory_region_add_subregion(system_memory, 0, ram_below_4g); 952 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 953 if (x86ms->above_4g_mem_size > 0) { 954 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 955 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 956 machine->ram, 957 x86ms->below_4g_mem_size, 958 x86ms->above_4g_mem_size); 959 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 960 ram_above_4g); 961 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 962 E820_RAM); 963 } 964 965 if (pcms->sgx_epc.size != 0) { 966 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 967 } 968 969 if (!pcmc->has_reserved_memory && 970 (machine->ram_slots || 971 (machine->maxram_size > machine->ram_size))) { 972 973 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 974 mc->name); 975 exit(EXIT_FAILURE); 976 } 977 978 /* initialize device memory address space */ 979 if (pcmc->has_reserved_memory && 980 (machine->ram_size < machine->maxram_size)) { 981 ram_addr_t device_mem_size; 982 hwaddr device_mem_base; 983 984 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 985 error_report("unsupported amount of memory slots: %"PRIu64, 986 machine->ram_slots); 987 exit(EXIT_FAILURE); 988 } 989 990 if (QEMU_ALIGN_UP(machine->maxram_size, 991 TARGET_PAGE_SIZE) != machine->maxram_size) { 992 error_report("maximum memory size must by aligned to multiple of " 993 "%d bytes", TARGET_PAGE_SIZE); 994 exit(EXIT_FAILURE); 995 } 996 997 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 998 999 if (device_mem_base + device_mem_size < device_mem_size) { 1000 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1001 machine->maxram_size); 1002 exit(EXIT_FAILURE); 1003 } 1004 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 1005 } 1006 1007 if (pcms->cxl_devices_state.is_enabled) { 1008 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1009 hwaddr cxl_size = MiB; 1010 1011 cxl_base = pc_get_cxl_range_start(pcms); 1012 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1013 memory_region_add_subregion(system_memory, cxl_base, mr); 1014 cxl_resv_end = cxl_base + cxl_size; 1015 if (pcms->cxl_devices_state.fixed_windows) { 1016 hwaddr cxl_fmw_base; 1017 GList *it; 1018 1019 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1020 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1021 CXLFixedWindow *fw = it->data; 1022 1023 fw->base = cxl_fmw_base; 1024 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1025 "cxl-fixed-memory-region", fw->size); 1026 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1027 cxl_fmw_base += fw->size; 1028 cxl_resv_end = cxl_fmw_base; 1029 } 1030 } 1031 } 1032 1033 /* Initialize PC system firmware */ 1034 pc_system_firmware_init(pcms, rom_memory); 1035 1036 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1037 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1038 &error_fatal); 1039 if (pcmc->pci_enabled) { 1040 memory_region_set_readonly(option_rom_mr, true); 1041 } 1042 memory_region_add_subregion_overlap(rom_memory, 1043 PC_ROM_MIN_VGA, 1044 option_rom_mr, 1045 1); 1046 1047 fw_cfg = fw_cfg_arch_create(machine, 1048 x86ms->boot_cpus, x86ms->apic_id_limit); 1049 1050 rom_set_fw(fw_cfg); 1051 1052 if (machine->device_memory) { 1053 uint64_t *val = g_malloc(sizeof(*val)); 1054 uint64_t res_mem_end = machine->device_memory->base; 1055 1056 if (!pcmc->broken_reserved_end) { 1057 res_mem_end += memory_region_size(&machine->device_memory->mr); 1058 } 1059 1060 if (pcms->cxl_devices_state.is_enabled) { 1061 res_mem_end = cxl_resv_end; 1062 } 1063 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1064 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1065 } 1066 1067 if (linux_boot) { 1068 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1069 pcmc->pvh_enabled); 1070 } 1071 1072 for (i = 0; i < nb_option_roms; i++) { 1073 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1074 } 1075 x86ms->fw_cfg = fw_cfg; 1076 1077 /* Init default IOAPIC address space */ 1078 x86ms->ioapic_as = &address_space_memory; 1079 1080 /* Init ACPI memory hotplug IO base address */ 1081 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1082 } 1083 1084 /* 1085 * The 64bit pci hole starts after "above 4G RAM" and 1086 * potentially the space reserved for memory hotplug. 1087 */ 1088 uint64_t pc_pci_hole64_start(void) 1089 { 1090 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1091 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1092 MachineState *ms = MACHINE(pcms); 1093 uint64_t hole64_start = 0; 1094 ram_addr_t size = 0; 1095 1096 if (pcms->cxl_devices_state.is_enabled) { 1097 hole64_start = pc_get_cxl_range_end(pcms); 1098 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1099 pc_get_device_memory_range(pcms, &hole64_start, &size); 1100 if (!pcmc->broken_reserved_end) { 1101 hole64_start += size; 1102 } 1103 } else { 1104 hole64_start = pc_above_4g_end(pcms); 1105 } 1106 1107 return ROUND_UP(hole64_start, 1 * GiB); 1108 } 1109 1110 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1111 { 1112 DeviceState *dev = NULL; 1113 1114 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1115 if (pci_bus) { 1116 PCIDevice *pcidev = pci_vga_init(pci_bus); 1117 dev = pcidev ? &pcidev->qdev : NULL; 1118 } else if (isa_bus) { 1119 ISADevice *isadev = isa_vga_init(isa_bus); 1120 dev = isadev ? DEVICE(isadev) : NULL; 1121 } 1122 rom_reset_order_override(); 1123 return dev; 1124 } 1125 1126 static const MemoryRegionOps ioport80_io_ops = { 1127 .write = ioport80_write, 1128 .read = ioport80_read, 1129 .endianness = DEVICE_NATIVE_ENDIAN, 1130 .impl = { 1131 .min_access_size = 1, 1132 .max_access_size = 1, 1133 }, 1134 }; 1135 1136 static const MemoryRegionOps ioportF0_io_ops = { 1137 .write = ioportF0_write, 1138 .read = ioportF0_read, 1139 .endianness = DEVICE_NATIVE_ENDIAN, 1140 .impl = { 1141 .min_access_size = 1, 1142 .max_access_size = 1, 1143 }, 1144 }; 1145 1146 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1147 bool create_i8042, bool no_vmport) 1148 { 1149 int i; 1150 DriveInfo *fd[MAX_FD]; 1151 qemu_irq *a20_line; 1152 ISADevice *fdc, *i8042, *port92, *vmmouse; 1153 1154 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1155 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1156 1157 for (i = 0; i < MAX_FD; i++) { 1158 fd[i] = drive_get(IF_FLOPPY, 0, i); 1159 create_fdctrl |= !!fd[i]; 1160 } 1161 if (create_fdctrl) { 1162 fdc = isa_new(TYPE_ISA_FDC); 1163 if (fdc) { 1164 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1165 isa_fdc_init_drives(fdc, fd); 1166 } 1167 } 1168 1169 if (!create_i8042) { 1170 return; 1171 } 1172 1173 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1174 if (!no_vmport) { 1175 isa_create_simple(isa_bus, TYPE_VMPORT); 1176 vmmouse = isa_try_new("vmmouse"); 1177 } else { 1178 vmmouse = NULL; 1179 } 1180 if (vmmouse) { 1181 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1182 &error_abort); 1183 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1184 } 1185 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1186 1187 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1188 i8042_setup_a20_line(i8042, a20_line[0]); 1189 qdev_connect_gpio_out_named(DEVICE(port92), 1190 PORT92_A20_LINE, 0, a20_line[1]); 1191 g_free(a20_line); 1192 } 1193 1194 void pc_basic_device_init(struct PCMachineState *pcms, 1195 ISABus *isa_bus, qemu_irq *gsi, 1196 ISADevice *rtc_state, 1197 bool create_fdctrl, 1198 uint32_t hpet_irqs) 1199 { 1200 int i; 1201 DeviceState *hpet = NULL; 1202 int pit_isa_irq = 0; 1203 qemu_irq pit_alt_irq = NULL; 1204 ISADevice *pit = NULL; 1205 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1206 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1207 X86MachineState *x86ms = X86_MACHINE(pcms); 1208 1209 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1210 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1211 1212 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1213 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1214 1215 /* 1216 * Check if an HPET shall be created. 1217 * 1218 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1219 * when the HPET wants to take over. Thus we have to disable the latter. 1220 */ 1221 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1222 kvm_has_pit_state2())) { 1223 qemu_irq rtc_irq; 1224 1225 hpet = qdev_try_new(TYPE_HPET); 1226 if (!hpet) { 1227 error_report("couldn't create HPET device"); 1228 exit(1); 1229 } 1230 /* 1231 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1232 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1233 * the property, use whatever mask they specified. 1234 */ 1235 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1236 HPET_INTCAP, NULL); 1237 if (!compat) { 1238 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1239 } 1240 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1241 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1242 1243 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1244 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1245 } 1246 pit_isa_irq = -1; 1247 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1248 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1249 1250 /* overwrite connection created by south bridge */ 1251 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1252 } 1253 1254 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1255 "date"); 1256 1257 #ifdef CONFIG_XEN_EMU 1258 if (xen_mode == XEN_EMULATE) { 1259 xen_overlay_create(); 1260 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1261 xen_gnttab_create(); 1262 xen_xenstore_create(); 1263 if (pcms->bus) { 1264 pci_create_simple(pcms->bus, -1, "xen-platform"); 1265 } 1266 xen_bus_init(); 1267 xen_be_init(); 1268 } 1269 #endif 1270 1271 qemu_register_boot_set(pc_boot_set, rtc_state); 1272 1273 if (!xen_enabled() && 1274 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1275 if (kvm_pit_in_kernel()) { 1276 pit = kvm_pit_init(isa_bus, 0x40); 1277 } else { 1278 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1279 } 1280 if (hpet) { 1281 /* connect PIT to output control line of the HPET */ 1282 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1283 } 1284 pcspk_init(pcms->pcspk, isa_bus, pit); 1285 } 1286 1287 /* Super I/O */ 1288 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1289 pcms->vmport != ON_OFF_AUTO_ON); 1290 } 1291 1292 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1293 { 1294 MachineClass *mc = MACHINE_CLASS(pcmc); 1295 int i; 1296 1297 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1298 for (i = 0; i < nb_nics; i++) { 1299 NICInfo *nd = &nd_table[i]; 1300 const char *model = nd->model ? nd->model : mc->default_nic; 1301 1302 if (g_str_equal(model, "ne2k_isa")) { 1303 pc_init_ne2k_isa(isa_bus, nd); 1304 } else { 1305 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1306 } 1307 } 1308 rom_reset_order_override(); 1309 } 1310 1311 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1312 { 1313 qemu_irq *i8259; 1314 1315 if (kvm_pic_in_kernel()) { 1316 i8259 = kvm_i8259_init(isa_bus); 1317 } else if (xen_enabled()) { 1318 i8259 = xen_interrupt_controller_init(); 1319 } else { 1320 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1321 } 1322 1323 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1324 i8259_irqs[i] = i8259[i]; 1325 } 1326 1327 g_free(i8259); 1328 } 1329 1330 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1331 Error **errp) 1332 { 1333 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1334 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1335 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1336 const MachineState *ms = MACHINE(hotplug_dev); 1337 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1338 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1339 Error *local_err = NULL; 1340 1341 /* 1342 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1343 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1344 * addition to cover this case. 1345 */ 1346 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1347 error_setg(errp, 1348 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1349 return; 1350 } 1351 1352 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1353 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1354 return; 1355 } 1356 1357 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1358 if (local_err) { 1359 error_propagate(errp, local_err); 1360 return; 1361 } 1362 1363 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1364 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1365 } 1366 1367 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1371 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1372 MachineState *ms = MACHINE(hotplug_dev); 1373 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1374 1375 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1376 1377 if (is_nvdimm) { 1378 nvdimm_plug(ms->nvdimms_state); 1379 } 1380 1381 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1382 } 1383 1384 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1385 DeviceState *dev, Error **errp) 1386 { 1387 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1388 1389 /* 1390 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1391 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1392 * addition to cover this case. 1393 */ 1394 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1395 error_setg(errp, 1396 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1397 return; 1398 } 1399 1400 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1401 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1402 return; 1403 } 1404 1405 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1406 errp); 1407 } 1408 1409 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1410 DeviceState *dev, Error **errp) 1411 { 1412 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1413 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1414 Error *local_err = NULL; 1415 1416 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1417 if (local_err) { 1418 goto out; 1419 } 1420 1421 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1422 qdev_unrealize(dev); 1423 out: 1424 error_propagate(errp, local_err); 1425 } 1426 1427 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1428 DeviceState *dev, Error **errp) 1429 { 1430 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1431 pc_memory_pre_plug(hotplug_dev, dev, errp); 1432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1433 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1435 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1437 /* Declare the APIC range as the reserved MSI region */ 1438 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1439 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1440 1441 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1442 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1443 resv_prop_str, errp); 1444 g_free(resv_prop_str); 1445 } 1446 1447 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1448 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1449 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1450 1451 if (pcms->iommu) { 1452 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1453 "for x86 yet."); 1454 return; 1455 } 1456 pcms->iommu = dev; 1457 } 1458 } 1459 1460 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1461 DeviceState *dev, Error **errp) 1462 { 1463 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1464 pc_memory_plug(hotplug_dev, dev, errp); 1465 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1466 x86_cpu_plug(hotplug_dev, dev, errp); 1467 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1468 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1469 } 1470 } 1471 1472 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1473 DeviceState *dev, Error **errp) 1474 { 1475 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1476 pc_memory_unplug_request(hotplug_dev, dev, errp); 1477 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1478 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1479 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1480 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1481 errp); 1482 } else { 1483 error_setg(errp, "acpi: device unplug request for not supported device" 1484 " type: %s", object_get_typename(OBJECT(dev))); 1485 } 1486 } 1487 1488 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1489 DeviceState *dev, Error **errp) 1490 { 1491 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1492 pc_memory_unplug(hotplug_dev, dev, errp); 1493 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1494 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1495 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1496 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1497 } else { 1498 error_setg(errp, "acpi: device unplug for not supported device" 1499 " type: %s", object_get_typename(OBJECT(dev))); 1500 } 1501 } 1502 1503 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1504 DeviceState *dev) 1505 { 1506 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1507 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1508 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1509 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1510 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1511 return HOTPLUG_HANDLER(machine); 1512 } 1513 1514 return NULL; 1515 } 1516 1517 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1518 void *opaque, Error **errp) 1519 { 1520 PCMachineState *pcms = PC_MACHINE(obj); 1521 OnOffAuto vmport = pcms->vmport; 1522 1523 visit_type_OnOffAuto(v, name, &vmport, errp); 1524 } 1525 1526 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1527 void *opaque, Error **errp) 1528 { 1529 PCMachineState *pcms = PC_MACHINE(obj); 1530 1531 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1532 } 1533 1534 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1535 { 1536 PCMachineState *pcms = PC_MACHINE(obj); 1537 1538 return pcms->smbus_enabled; 1539 } 1540 1541 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1542 { 1543 PCMachineState *pcms = PC_MACHINE(obj); 1544 1545 pcms->smbus_enabled = value; 1546 } 1547 1548 static bool pc_machine_get_sata(Object *obj, Error **errp) 1549 { 1550 PCMachineState *pcms = PC_MACHINE(obj); 1551 1552 return pcms->sata_enabled; 1553 } 1554 1555 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1556 { 1557 PCMachineState *pcms = PC_MACHINE(obj); 1558 1559 pcms->sata_enabled = value; 1560 } 1561 1562 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1563 { 1564 PCMachineState *pcms = PC_MACHINE(obj); 1565 1566 return pcms->hpet_enabled; 1567 } 1568 1569 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1570 { 1571 PCMachineState *pcms = PC_MACHINE(obj); 1572 1573 pcms->hpet_enabled = value; 1574 } 1575 1576 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1577 { 1578 PCMachineState *pcms = PC_MACHINE(obj); 1579 1580 return pcms->i8042_enabled; 1581 } 1582 1583 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1584 { 1585 PCMachineState *pcms = PC_MACHINE(obj); 1586 1587 pcms->i8042_enabled = value; 1588 } 1589 1590 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 1594 return pcms->default_bus_bypass_iommu; 1595 } 1596 1597 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1598 Error **errp) 1599 { 1600 PCMachineState *pcms = PC_MACHINE(obj); 1601 1602 pcms->default_bus_bypass_iommu = value; 1603 } 1604 1605 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1606 void *opaque, Error **errp) 1607 { 1608 PCMachineState *pcms = PC_MACHINE(obj); 1609 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1610 1611 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1612 } 1613 1614 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1615 void *opaque, Error **errp) 1616 { 1617 PCMachineState *pcms = PC_MACHINE(obj); 1618 1619 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1620 } 1621 1622 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1623 const char *name, void *opaque, 1624 Error **errp) 1625 { 1626 PCMachineState *pcms = PC_MACHINE(obj); 1627 uint64_t value = pcms->max_ram_below_4g; 1628 1629 visit_type_size(v, name, &value, errp); 1630 } 1631 1632 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1633 const char *name, void *opaque, 1634 Error **errp) 1635 { 1636 PCMachineState *pcms = PC_MACHINE(obj); 1637 uint64_t value; 1638 1639 if (!visit_type_size(v, name, &value, errp)) { 1640 return; 1641 } 1642 if (value > 4 * GiB) { 1643 error_setg(errp, 1644 "Machine option 'max-ram-below-4g=%"PRIu64 1645 "' expects size less than or equal to 4G", value); 1646 return; 1647 } 1648 1649 if (value < 1 * MiB) { 1650 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1651 "BIOS may not work with less than 1MiB", value); 1652 } 1653 1654 pcms->max_ram_below_4g = value; 1655 } 1656 1657 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1658 const char *name, void *opaque, 1659 Error **errp) 1660 { 1661 PCMachineState *pcms = PC_MACHINE(obj); 1662 uint64_t value = pcms->max_fw_size; 1663 1664 visit_type_size(v, name, &value, errp); 1665 } 1666 1667 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1668 const char *name, void *opaque, 1669 Error **errp) 1670 { 1671 PCMachineState *pcms = PC_MACHINE(obj); 1672 uint64_t value; 1673 1674 if (!visit_type_size(v, name, &value, errp)) { 1675 return; 1676 } 1677 1678 /* 1679 * We don't have a theoretically justifiable exact lower bound on the base 1680 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1681 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1682 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1683 * 16MiB in size. 1684 */ 1685 if (value > 16 * MiB) { 1686 error_setg(errp, 1687 "User specified max allowed firmware size %" PRIu64 " is " 1688 "greater than 16MiB. If combined firmware size exceeds " 1689 "16MiB the system may not boot, or experience intermittent" 1690 "stability issues.", 1691 value); 1692 return; 1693 } 1694 1695 pcms->max_fw_size = value; 1696 } 1697 1698 1699 static void pc_machine_initfn(Object *obj) 1700 { 1701 PCMachineState *pcms = PC_MACHINE(obj); 1702 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1703 1704 #ifdef CONFIG_VMPORT 1705 pcms->vmport = ON_OFF_AUTO_AUTO; 1706 #else 1707 pcms->vmport = ON_OFF_AUTO_OFF; 1708 #endif /* CONFIG_VMPORT */ 1709 pcms->max_ram_below_4g = 0; /* use default */ 1710 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1711 pcms->south_bridge = pcmc->default_south_bridge; 1712 1713 /* acpi build is enabled by default if machine supports it */ 1714 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1715 pcms->smbus_enabled = true; 1716 pcms->sata_enabled = true; 1717 pcms->i8042_enabled = true; 1718 pcms->max_fw_size = 8 * MiB; 1719 #ifdef CONFIG_HPET 1720 pcms->hpet_enabled = true; 1721 #endif 1722 pcms->default_bus_bypass_iommu = false; 1723 1724 pc_system_flash_create(pcms); 1725 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1726 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1727 OBJECT(pcms->pcspk), "audiodev"); 1728 cxl_machine_init(obj, &pcms->cxl_devices_state); 1729 } 1730 1731 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) 1732 { 1733 return 0; 1734 } 1735 1736 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1737 { 1738 CPUState *cs; 1739 X86CPU *cpu; 1740 1741 qemu_devices_reset(reason); 1742 1743 /* Reset APIC after devices have been reset to cancel 1744 * any changes that qemu_devices_reset() might have done. 1745 */ 1746 CPU_FOREACH(cs) { 1747 cpu = X86_CPU(cs); 1748 1749 x86_cpu_after_reset(cpu); 1750 } 1751 } 1752 1753 static void pc_machine_wakeup(MachineState *machine) 1754 { 1755 cpu_synchronize_all_states(); 1756 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1757 cpu_synchronize_all_post_reset(); 1758 } 1759 1760 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1761 { 1762 X86IOMMUState *iommu = x86_iommu_get_default(); 1763 IntelIOMMUState *intel_iommu; 1764 1765 if (iommu && 1766 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1767 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1768 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1769 if (!intel_iommu->caching_mode) { 1770 error_setg(errp, "Device assignment is not allowed without " 1771 "enabling caching-mode=on for Intel IOMMU."); 1772 return false; 1773 } 1774 } 1775 1776 return true; 1777 } 1778 1779 static void pc_machine_class_init(ObjectClass *oc, void *data) 1780 { 1781 MachineClass *mc = MACHINE_CLASS(oc); 1782 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1783 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1784 1785 pcmc->pci_enabled = true; 1786 pcmc->has_acpi_build = true; 1787 pcmc->rsdp_in_ram = true; 1788 pcmc->smbios_defaults = true; 1789 pcmc->smbios_uuid_encoded = true; 1790 pcmc->gigabyte_align = true; 1791 pcmc->has_reserved_memory = true; 1792 pcmc->kvmclock_enabled = true; 1793 pcmc->enforce_aligned_dimm = true; 1794 pcmc->enforce_amd_1tb_hole = true; 1795 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1796 * to be used at the moment, 32K should be enough for a while. */ 1797 pcmc->acpi_data_size = 0x20000 + 0x8000; 1798 pcmc->pvh_enabled = true; 1799 pcmc->kvmclock_create_always = true; 1800 pcmc->resizable_acpi_blob = true; 1801 assert(!mc->get_hotplug_handler); 1802 mc->get_hotplug_handler = pc_get_hotplug_handler; 1803 mc->hotplug_allowed = pc_hotplug_allowed; 1804 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1805 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1806 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1807 mc->auto_enable_numa_with_memhp = true; 1808 mc->auto_enable_numa_with_memdev = true; 1809 mc->has_hotpluggable_cpus = true; 1810 mc->default_boot_order = "cad"; 1811 mc->block_default_type = IF_IDE; 1812 mc->max_cpus = 255; 1813 mc->reset = pc_machine_reset; 1814 mc->wakeup = pc_machine_wakeup; 1815 hc->pre_plug = pc_machine_device_pre_plug_cb; 1816 hc->plug = pc_machine_device_plug_cb; 1817 hc->unplug_request = pc_machine_device_unplug_request_cb; 1818 hc->unplug = pc_machine_device_unplug_cb; 1819 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1820 mc->nvdimm_supported = true; 1821 mc->smp_props.dies_supported = true; 1822 mc->default_ram_id = "pc.ram"; 1823 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 1824 1825 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1826 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1827 NULL, NULL); 1828 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1829 "Maximum ram below the 4G boundary (32bit boundary)"); 1830 1831 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1832 pc_machine_get_vmport, pc_machine_set_vmport, 1833 NULL, NULL); 1834 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1835 "Enable vmport (pc & q35)"); 1836 1837 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1838 pc_machine_get_smbus, pc_machine_set_smbus); 1839 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1840 "Enable/disable system management bus"); 1841 1842 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1843 pc_machine_get_sata, pc_machine_set_sata); 1844 object_class_property_set_description(oc, PC_MACHINE_SATA, 1845 "Enable/disable Serial ATA bus"); 1846 1847 object_class_property_add_bool(oc, "hpet", 1848 pc_machine_get_hpet, pc_machine_set_hpet); 1849 object_class_property_set_description(oc, "hpet", 1850 "Enable/disable high precision event timer emulation"); 1851 1852 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1853 pc_machine_get_i8042, pc_machine_set_i8042); 1854 1855 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1856 pc_machine_get_default_bus_bypass_iommu, 1857 pc_machine_set_default_bus_bypass_iommu); 1858 1859 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1860 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1861 NULL, NULL); 1862 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1863 "Maximum combined firmware size"); 1864 1865 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1866 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1867 NULL, NULL); 1868 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1869 "SMBIOS Entry Point type [32, 64]"); 1870 } 1871 1872 static const TypeInfo pc_machine_info = { 1873 .name = TYPE_PC_MACHINE, 1874 .parent = TYPE_X86_MACHINE, 1875 .abstract = true, 1876 .instance_size = sizeof(PCMachineState), 1877 .instance_init = pc_machine_initfn, 1878 .class_size = sizeof(PCMachineClass), 1879 .class_init = pc_machine_class_init, 1880 .interfaces = (InterfaceInfo[]) { 1881 { TYPE_HOTPLUG_HANDLER }, 1882 { } 1883 }, 1884 }; 1885 1886 static void pc_machine_register_types(void) 1887 { 1888 type_register_static(&pc_machine_info); 1889 } 1890 1891 type_init(pc_machine_register_types) 1892