1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "migration/vmstate.h" 45 #include "multiboot.h" 46 #include "hw/rtc/mc146818rtc.h" 47 #include "hw/intc/i8259.h" 48 #include "hw/dma/i8257.h" 49 #include "hw/timer/i8254.h" 50 #include "hw/input/i8042.h" 51 #include "hw/irq.h" 52 #include "hw/audio/pcspk.h" 53 #include "hw/pci/msi.h" 54 #include "hw/sysbus.h" 55 #include "sysemu/sysemu.h" 56 #include "sysemu/tcg.h" 57 #include "sysemu/numa.h" 58 #include "sysemu/kvm.h" 59 #include "sysemu/qtest.h" 60 #include "sysemu/reset.h" 61 #include "sysemu/runstate.h" 62 #include "kvm_i386.h" 63 #include "hw/xen/xen.h" 64 #include "hw/xen/start_info.h" 65 #include "ui/qemu-spice.h" 66 #include "exec/memory.h" 67 #include "exec/address-spaces.h" 68 #include "sysemu/arch_init.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "hw/boards.h" 77 #include "acpi-build.h" 78 #include "hw/mem/pc-dimm.h" 79 #include "qapi/error.h" 80 #include "qapi/qapi-visit-common.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/mem/memory-device.h" 89 #include "sysemu/replay.h" 90 #include "qapi/qmp/qerror.h" 91 #include "config-devices.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 96 GlobalProperty pc_compat_4_2[] = {}; 97 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 98 99 GlobalProperty pc_compat_4_1[] = {}; 100 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 101 102 GlobalProperty pc_compat_4_0[] = {}; 103 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 104 105 GlobalProperty pc_compat_3_1[] = { 106 { "intel-iommu", "dma-drain", "off" }, 107 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 108 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 109 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 110 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 111 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 112 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 113 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 114 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 115 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 116 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 117 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 118 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 119 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 120 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 121 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 122 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 123 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 124 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 125 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 126 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 127 }; 128 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 129 130 GlobalProperty pc_compat_3_0[] = { 131 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 132 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 133 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 134 }; 135 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 136 137 GlobalProperty pc_compat_2_12[] = { 138 { TYPE_X86_CPU, "legacy-cache", "on" }, 139 { TYPE_X86_CPU, "topoext", "off" }, 140 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 141 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 142 }; 143 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 144 145 GlobalProperty pc_compat_2_11[] = { 146 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 147 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 148 }; 149 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 150 151 GlobalProperty pc_compat_2_10[] = { 152 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 153 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 154 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 155 }; 156 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 157 158 GlobalProperty pc_compat_2_9[] = { 159 { "mch", "extended-tseg-mbytes", "0" }, 160 }; 161 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 162 163 GlobalProperty pc_compat_2_8[] = { 164 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 165 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 166 { "ICH9-LPC", "x-smi-broadcast", "off" }, 167 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 168 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 169 }; 170 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 171 172 GlobalProperty pc_compat_2_7[] = { 173 { TYPE_X86_CPU, "l3-cache", "off" }, 174 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 175 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 176 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 177 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 178 { "isa-pcspk", "migrate", "off" }, 179 }; 180 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 181 182 GlobalProperty pc_compat_2_6[] = { 183 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 184 { "vmxnet3", "romfile", "" }, 185 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 186 { "apic-common", "legacy-instance-id", "on", } 187 }; 188 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 189 190 GlobalProperty pc_compat_2_5[] = {}; 191 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 192 193 GlobalProperty pc_compat_2_4[] = { 194 PC_CPU_MODEL_IDS("2.4.0") 195 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 196 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 197 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 198 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 199 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 200 { TYPE_X86_CPU, "check", "off" }, 201 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 202 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 203 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 204 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 205 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 206 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 207 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 208 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 209 }; 210 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 211 212 GlobalProperty pc_compat_2_3[] = { 213 PC_CPU_MODEL_IDS("2.3.0") 214 { TYPE_X86_CPU, "arat", "off" }, 215 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 216 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 217 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 218 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 219 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 220 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 221 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 222 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 223 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 224 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 225 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 226 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 227 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 228 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 229 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 230 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 231 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 232 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 233 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 234 }; 235 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 236 237 GlobalProperty pc_compat_2_2[] = { 238 PC_CPU_MODEL_IDS("2.2.0") 239 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 240 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 241 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 242 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 243 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 244 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 245 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 246 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 247 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 248 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 249 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 250 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 251 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 252 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 254 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 255 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 256 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 257 }; 258 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 259 260 GlobalProperty pc_compat_2_1[] = { 261 PC_CPU_MODEL_IDS("2.1.0") 262 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 263 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 264 }; 265 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 266 267 GlobalProperty pc_compat_2_0[] = { 268 PC_CPU_MODEL_IDS("2.0.0") 269 { "virtio-scsi-pci", "any_layout", "off" }, 270 { "PIIX4_PM", "memory-hotplug-support", "off" }, 271 { "apic", "version", "0x11" }, 272 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 273 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 274 { "pci-serial", "prog_if", "0" }, 275 { "pci-serial-2x", "prog_if", "0" }, 276 { "pci-serial-4x", "prog_if", "0" }, 277 { "virtio-net-pci", "guest_announce", "off" }, 278 { "ICH9-LPC", "memory-hotplug-support", "off" }, 279 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 280 { "ioh3420", COMPAT_PROP_PCP, "off" }, 281 }; 282 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 283 284 GlobalProperty pc_compat_1_7[] = { 285 PC_CPU_MODEL_IDS("1.7.0") 286 { TYPE_USB_DEVICE, "msos-desc", "no" }, 287 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 288 { "hpet", HPET_INTCAP, "4" }, 289 }; 290 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 291 292 GlobalProperty pc_compat_1_6[] = { 293 PC_CPU_MODEL_IDS("1.6.0") 294 { "e1000", "mitigation", "off" }, 295 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 296 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 297 { "i440FX-pcihost", "short_root_bus", "1" }, 298 { "q35-pcihost", "short_root_bus", "1" }, 299 }; 300 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 301 302 GlobalProperty pc_compat_1_5[] = { 303 PC_CPU_MODEL_IDS("1.5.0") 304 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 305 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 306 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 307 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 308 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 309 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 310 { "virtio-net-pci", "any_layout", "off" }, 311 { TYPE_X86_CPU, "pmu", "on" }, 312 { "i440FX-pcihost", "short_root_bus", "0" }, 313 { "q35-pcihost", "short_root_bus", "0" }, 314 }; 315 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 316 317 GlobalProperty pc_compat_1_4[] = { 318 PC_CPU_MODEL_IDS("1.4.0") 319 { "scsi-hd", "discard_granularity", "0" }, 320 { "scsi-cd", "discard_granularity", "0" }, 321 { "scsi-disk", "discard_granularity", "0" }, 322 { "ide-hd", "discard_granularity", "0" }, 323 { "ide-cd", "discard_granularity", "0" }, 324 { "ide-drive", "discard_granularity", "0" }, 325 { "virtio-blk-pci", "discard_granularity", "0" }, 326 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 327 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 328 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 329 { "e1000", "romfile", "pxe-e1000.rom" }, 330 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 331 { "pcnet", "romfile", "pxe-pcnet.rom" }, 332 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 333 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 334 { "486-" TYPE_X86_CPU, "model", "0" }, 335 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 336 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 337 }; 338 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 339 340 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 341 { 342 GSIState *s; 343 344 s = g_new0(GSIState, 1); 345 if (kvm_ioapic_in_kernel()) { 346 kvm_pc_setup_irq_routing(pci_enabled); 347 *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS); 348 } else { 349 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 350 } 351 352 return s; 353 } 354 355 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 356 unsigned size) 357 { 358 } 359 360 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 361 { 362 return 0xffffffffffffffffULL; 363 } 364 365 /* MSDOS compatibility mode FPU exception support */ 366 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 367 unsigned size) 368 { 369 if (tcg_enabled()) { 370 cpu_set_ignne(); 371 } 372 } 373 374 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 375 { 376 return 0xffffffffffffffffULL; 377 } 378 379 /* PC cmos mappings */ 380 381 #define REG_EQUIPMENT_BYTE 0x14 382 383 int cmos_get_fd_drive_type(FloppyDriveType fd0) 384 { 385 int val; 386 387 switch (fd0) { 388 case FLOPPY_DRIVE_TYPE_144: 389 /* 1.44 Mb 3"5 drive */ 390 val = 4; 391 break; 392 case FLOPPY_DRIVE_TYPE_288: 393 /* 2.88 Mb 3"5 drive */ 394 val = 5; 395 break; 396 case FLOPPY_DRIVE_TYPE_120: 397 /* 1.2 Mb 5"5 drive */ 398 val = 2; 399 break; 400 case FLOPPY_DRIVE_TYPE_NONE: 401 default: 402 val = 0; 403 break; 404 } 405 return val; 406 } 407 408 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 409 int16_t cylinders, int8_t heads, int8_t sectors) 410 { 411 rtc_set_memory(s, type_ofs, 47); 412 rtc_set_memory(s, info_ofs, cylinders); 413 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 414 rtc_set_memory(s, info_ofs + 2, heads); 415 rtc_set_memory(s, info_ofs + 3, 0xff); 416 rtc_set_memory(s, info_ofs + 4, 0xff); 417 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 418 rtc_set_memory(s, info_ofs + 6, cylinders); 419 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 420 rtc_set_memory(s, info_ofs + 8, sectors); 421 } 422 423 /* convert boot_device letter to something recognizable by the bios */ 424 static int boot_device2nibble(char boot_device) 425 { 426 switch(boot_device) { 427 case 'a': 428 case 'b': 429 return 0x01; /* floppy boot */ 430 case 'c': 431 return 0x02; /* hard drive boot */ 432 case 'd': 433 return 0x03; /* CD-ROM boot */ 434 case 'n': 435 return 0x04; /* Network boot */ 436 } 437 return 0; 438 } 439 440 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 441 { 442 #define PC_MAX_BOOT_DEVICES 3 443 int nbds, bds[3] = { 0, }; 444 int i; 445 446 nbds = strlen(boot_device); 447 if (nbds > PC_MAX_BOOT_DEVICES) { 448 error_setg(errp, "Too many boot devices for PC"); 449 return; 450 } 451 for (i = 0; i < nbds; i++) { 452 bds[i] = boot_device2nibble(boot_device[i]); 453 if (bds[i] == 0) { 454 error_setg(errp, "Invalid boot device for PC: '%c'", 455 boot_device[i]); 456 return; 457 } 458 } 459 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 460 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 461 } 462 463 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 464 { 465 set_boot_dev(opaque, boot_device, errp); 466 } 467 468 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 469 { 470 int val, nb, i; 471 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 472 FLOPPY_DRIVE_TYPE_NONE }; 473 474 /* floppy type */ 475 if (floppy) { 476 for (i = 0; i < 2; i++) { 477 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 478 } 479 } 480 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 481 cmos_get_fd_drive_type(fd_type[1]); 482 rtc_set_memory(rtc_state, 0x10, val); 483 484 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 485 nb = 0; 486 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 487 nb++; 488 } 489 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 490 nb++; 491 } 492 switch (nb) { 493 case 0: 494 break; 495 case 1: 496 val |= 0x01; /* 1 drive, ready for boot */ 497 break; 498 case 2: 499 val |= 0x41; /* 2 drives, ready for boot */ 500 break; 501 } 502 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 503 } 504 505 typedef struct pc_cmos_init_late_arg { 506 ISADevice *rtc_state; 507 BusState *idebus[2]; 508 } pc_cmos_init_late_arg; 509 510 typedef struct check_fdc_state { 511 ISADevice *floppy; 512 bool multiple; 513 } CheckFdcState; 514 515 static int check_fdc(Object *obj, void *opaque) 516 { 517 CheckFdcState *state = opaque; 518 Object *fdc; 519 uint32_t iobase; 520 Error *local_err = NULL; 521 522 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 523 if (!fdc) { 524 return 0; 525 } 526 527 iobase = object_property_get_uint(obj, "iobase", &local_err); 528 if (local_err || iobase != 0x3f0) { 529 error_free(local_err); 530 return 0; 531 } 532 533 if (state->floppy) { 534 state->multiple = true; 535 } else { 536 state->floppy = ISA_DEVICE(obj); 537 } 538 return 0; 539 } 540 541 static const char * const fdc_container_path[] = { 542 "/unattached", "/peripheral", "/peripheral-anon" 543 }; 544 545 /* 546 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 547 * and ACPI objects. 548 */ 549 ISADevice *pc_find_fdc0(void) 550 { 551 int i; 552 Object *container; 553 CheckFdcState state = { 0 }; 554 555 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 556 container = container_get(qdev_get_machine(), fdc_container_path[i]); 557 object_child_foreach(container, check_fdc, &state); 558 } 559 560 if (state.multiple) { 561 warn_report("multiple floppy disk controllers with " 562 "iobase=0x3f0 have been found"); 563 error_printf("the one being picked for CMOS setup might not reflect " 564 "your intent"); 565 } 566 567 return state.floppy; 568 } 569 570 static void pc_cmos_init_late(void *opaque) 571 { 572 pc_cmos_init_late_arg *arg = opaque; 573 ISADevice *s = arg->rtc_state; 574 int16_t cylinders; 575 int8_t heads, sectors; 576 int val; 577 int i, trans; 578 579 val = 0; 580 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 581 &cylinders, &heads, §ors) >= 0) { 582 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 583 val |= 0xf0; 584 } 585 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 586 &cylinders, &heads, §ors) >= 0) { 587 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 588 val |= 0x0f; 589 } 590 rtc_set_memory(s, 0x12, val); 591 592 val = 0; 593 for (i = 0; i < 4; i++) { 594 /* NOTE: ide_get_geometry() returns the physical 595 geometry. It is always such that: 1 <= sects <= 63, 1 596 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 597 geometry can be different if a translation is done. */ 598 if (arg->idebus[i / 2] && 599 ide_get_geometry(arg->idebus[i / 2], i % 2, 600 &cylinders, &heads, §ors) >= 0) { 601 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 602 assert((trans & ~3) == 0); 603 val |= trans << (i * 2); 604 } 605 } 606 rtc_set_memory(s, 0x39, val); 607 608 pc_cmos_init_floppy(s, pc_find_fdc0()); 609 610 qemu_unregister_reset(pc_cmos_init_late, opaque); 611 } 612 613 void pc_cmos_init(PCMachineState *pcms, 614 BusState *idebus0, BusState *idebus1, 615 ISADevice *s) 616 { 617 int val; 618 static pc_cmos_init_late_arg arg; 619 X86MachineState *x86ms = X86_MACHINE(pcms); 620 621 /* various important CMOS locations needed by PC/Bochs bios */ 622 623 /* memory size */ 624 /* base memory (first MiB) */ 625 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 626 rtc_set_memory(s, 0x15, val); 627 rtc_set_memory(s, 0x16, val >> 8); 628 /* extended memory (next 64MiB) */ 629 if (x86ms->below_4g_mem_size > 1 * MiB) { 630 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 631 } else { 632 val = 0; 633 } 634 if (val > 65535) 635 val = 65535; 636 rtc_set_memory(s, 0x17, val); 637 rtc_set_memory(s, 0x18, val >> 8); 638 rtc_set_memory(s, 0x30, val); 639 rtc_set_memory(s, 0x31, val >> 8); 640 /* memory between 16MiB and 4GiB */ 641 if (x86ms->below_4g_mem_size > 16 * MiB) { 642 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 643 } else { 644 val = 0; 645 } 646 if (val > 65535) 647 val = 65535; 648 rtc_set_memory(s, 0x34, val); 649 rtc_set_memory(s, 0x35, val >> 8); 650 /* memory above 4GiB */ 651 val = x86ms->above_4g_mem_size / 65536; 652 rtc_set_memory(s, 0x5b, val); 653 rtc_set_memory(s, 0x5c, val >> 8); 654 rtc_set_memory(s, 0x5d, val >> 16); 655 656 object_property_add_link(OBJECT(pcms), "rtc_state", 657 TYPE_ISA_DEVICE, 658 (Object **)&x86ms->rtc, 659 object_property_allow_set_link, 660 OBJ_PROP_LINK_STRONG, &error_abort); 661 object_property_set_link(OBJECT(pcms), OBJECT(s), 662 "rtc_state", &error_abort); 663 664 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 665 666 val = 0; 667 val |= 0x02; /* FPU is there */ 668 val |= 0x04; /* PS/2 mouse installed */ 669 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 670 671 /* hard drives and FDC */ 672 arg.rtc_state = s; 673 arg.idebus[0] = idebus0; 674 arg.idebus[1] = idebus1; 675 qemu_register_reset(pc_cmos_init_late, &arg); 676 } 677 678 #define TYPE_PORT92 "port92" 679 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 680 681 /* port 92 stuff: could be split off */ 682 typedef struct Port92State { 683 ISADevice parent_obj; 684 685 MemoryRegion io; 686 uint8_t outport; 687 qemu_irq a20_out; 688 } Port92State; 689 690 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 691 unsigned size) 692 { 693 Port92State *s = opaque; 694 int oldval = s->outport; 695 696 trace_port92_write(val); 697 s->outport = val; 698 qemu_set_irq(s->a20_out, (val >> 1) & 1); 699 if ((val & 1) && !(oldval & 1)) { 700 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 701 } 702 } 703 704 static uint64_t port92_read(void *opaque, hwaddr addr, 705 unsigned size) 706 { 707 Port92State *s = opaque; 708 uint32_t ret; 709 710 ret = s->outport; 711 trace_port92_read(ret); 712 return ret; 713 } 714 715 static void port92_init(ISADevice *dev, qemu_irq a20_out) 716 { 717 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 718 } 719 720 static const VMStateDescription vmstate_port92_isa = { 721 .name = "port92", 722 .version_id = 1, 723 .minimum_version_id = 1, 724 .fields = (VMStateField[]) { 725 VMSTATE_UINT8(outport, Port92State), 726 VMSTATE_END_OF_LIST() 727 } 728 }; 729 730 static void port92_reset(DeviceState *d) 731 { 732 Port92State *s = PORT92(d); 733 734 s->outport &= ~1; 735 } 736 737 static const MemoryRegionOps port92_ops = { 738 .read = port92_read, 739 .write = port92_write, 740 .impl = { 741 .min_access_size = 1, 742 .max_access_size = 1, 743 }, 744 .endianness = DEVICE_LITTLE_ENDIAN, 745 }; 746 747 static void port92_initfn(Object *obj) 748 { 749 Port92State *s = PORT92(obj); 750 751 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 752 753 s->outport = 0; 754 755 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 756 } 757 758 static void port92_realizefn(DeviceState *dev, Error **errp) 759 { 760 ISADevice *isadev = ISA_DEVICE(dev); 761 Port92State *s = PORT92(dev); 762 763 isa_register_ioport(isadev, &s->io, 0x92); 764 } 765 766 static void port92_class_initfn(ObjectClass *klass, void *data) 767 { 768 DeviceClass *dc = DEVICE_CLASS(klass); 769 770 dc->realize = port92_realizefn; 771 dc->reset = port92_reset; 772 dc->vmsd = &vmstate_port92_isa; 773 /* 774 * Reason: unlike ordinary ISA devices, this one needs additional 775 * wiring: its A20 output line needs to be wired up by 776 * port92_init(). 777 */ 778 dc->user_creatable = false; 779 } 780 781 static const TypeInfo port92_info = { 782 .name = TYPE_PORT92, 783 .parent = TYPE_ISA_DEVICE, 784 .instance_size = sizeof(Port92State), 785 .instance_init = port92_initfn, 786 .class_init = port92_class_initfn, 787 }; 788 789 static void port92_register_types(void) 790 { 791 type_register_static(&port92_info); 792 } 793 794 type_init(port92_register_types) 795 796 static void handle_a20_line_change(void *opaque, int irq, int level) 797 { 798 X86CPU *cpu = opaque; 799 800 /* XXX: send to all CPUs ? */ 801 /* XXX: add logic to handle multiple A20 line sources */ 802 x86_cpu_set_a20(cpu, level); 803 } 804 805 #define NE2000_NB_MAX 6 806 807 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 808 0x280, 0x380 }; 809 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 810 811 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 812 { 813 static int nb_ne2k = 0; 814 815 if (nb_ne2k == NE2000_NB_MAX) 816 return; 817 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 818 ne2000_irq[nb_ne2k], nd); 819 nb_ne2k++; 820 } 821 822 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 823 { 824 X86CPU *cpu = opaque; 825 826 if (level) { 827 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 828 } 829 } 830 831 /* 832 * This function is very similar to smp_parse() 833 * in hw/core/machine.c but includes CPU die support. 834 */ 835 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 836 { 837 X86MachineState *x86ms = X86_MACHINE(ms); 838 839 if (opts) { 840 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 841 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 842 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 843 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 844 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 845 846 /* compute missing values, prefer sockets over cores over threads */ 847 if (cpus == 0 || sockets == 0) { 848 cores = cores > 0 ? cores : 1; 849 threads = threads > 0 ? threads : 1; 850 if (cpus == 0) { 851 sockets = sockets > 0 ? sockets : 1; 852 cpus = cores * threads * dies * sockets; 853 } else { 854 ms->smp.max_cpus = 855 qemu_opt_get_number(opts, "maxcpus", cpus); 856 sockets = ms->smp.max_cpus / (cores * threads * dies); 857 } 858 } else if (cores == 0) { 859 threads = threads > 0 ? threads : 1; 860 cores = cpus / (sockets * dies * threads); 861 cores = cores > 0 ? cores : 1; 862 } else if (threads == 0) { 863 threads = cpus / (cores * dies * sockets); 864 threads = threads > 0 ? threads : 1; 865 } else if (sockets * dies * cores * threads < cpus) { 866 error_report("cpu topology: " 867 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 868 "smp_cpus (%u)", 869 sockets, dies, cores, threads, cpus); 870 exit(1); 871 } 872 873 ms->smp.max_cpus = 874 qemu_opt_get_number(opts, "maxcpus", cpus); 875 876 if (ms->smp.max_cpus < cpus) { 877 error_report("maxcpus must be equal to or greater than smp"); 878 exit(1); 879 } 880 881 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 882 error_report("cpu topology: " 883 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 884 "maxcpus (%u)", 885 sockets, dies, cores, threads, 886 ms->smp.max_cpus); 887 exit(1); 888 } 889 890 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 891 warn_report("Invalid CPU topology deprecated: " 892 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 893 "!= maxcpus (%u)", 894 sockets, dies, cores, threads, 895 ms->smp.max_cpus); 896 } 897 898 ms->smp.cpus = cpus; 899 ms->smp.cores = cores; 900 ms->smp.threads = threads; 901 x86ms->smp_dies = dies; 902 } 903 904 if (ms->smp.cpus > 1) { 905 Error *blocker = NULL; 906 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 907 replay_add_blocker(blocker); 908 } 909 } 910 911 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 912 { 913 X86MachineState *x86ms = X86_MACHINE(ms); 914 int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); 915 Error *local_err = NULL; 916 917 if (id < 0) { 918 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 919 return; 920 } 921 922 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 923 error_setg(errp, "Unable to add CPU: %" PRIi64 924 ", resulting APIC ID (%" PRIi64 ") is too large", 925 id, apic_id); 926 return; 927 } 928 929 930 x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); 931 if (local_err) { 932 error_propagate(errp, local_err); 933 return; 934 } 935 } 936 937 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 938 { 939 if (cpus_count > 0xff) { 940 /* If the number of CPUs can't be represented in 8 bits, the 941 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 942 * to make old BIOSes fail more predictably. 943 */ 944 rtc_set_memory(rtc, 0x5f, 0); 945 } else { 946 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 947 } 948 } 949 950 static 951 void pc_machine_done(Notifier *notifier, void *data) 952 { 953 PCMachineState *pcms = container_of(notifier, 954 PCMachineState, machine_done); 955 X86MachineState *x86ms = X86_MACHINE(pcms); 956 PCIBus *bus = pcms->bus; 957 958 /* set the number of CPUs */ 959 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 960 961 if (bus) { 962 int extra_hosts = 0; 963 964 QLIST_FOREACH(bus, &bus->child, sibling) { 965 /* look for expander root buses */ 966 if (pci_bus_is_root(bus)) { 967 extra_hosts++; 968 } 969 } 970 if (extra_hosts && x86ms->fw_cfg) { 971 uint64_t *val = g_malloc(sizeof(*val)); 972 *val = cpu_to_le64(extra_hosts); 973 fw_cfg_add_file(x86ms->fw_cfg, 974 "etc/extra-pci-roots", val, sizeof(*val)); 975 } 976 } 977 978 acpi_setup(); 979 if (x86ms->fw_cfg) { 980 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 981 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 982 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 983 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 984 } 985 986 if (x86ms->apic_id_limit > 255 && !xen_enabled()) { 987 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 988 989 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 990 iommu->intr_eim != ON_OFF_AUTO_ON) { 991 error_report("current -smp configuration requires " 992 "Extended Interrupt Mode enabled. " 993 "You can add an IOMMU using: " 994 "-device intel-iommu,intremap=on,eim=on"); 995 exit(EXIT_FAILURE); 996 } 997 } 998 } 999 1000 void pc_guest_info_init(PCMachineState *pcms) 1001 { 1002 int i; 1003 MachineState *ms = MACHINE(pcms); 1004 X86MachineState *x86ms = X86_MACHINE(pcms); 1005 1006 x86ms->apic_xrupt_override = kvm_allows_irq0_override(); 1007 pcms->numa_nodes = ms->numa_state->num_nodes; 1008 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1009 sizeof *pcms->node_mem); 1010 for (i = 0; i < ms->numa_state->num_nodes; i++) { 1011 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 1012 } 1013 1014 pcms->machine_done.notify = pc_machine_done; 1015 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1016 } 1017 1018 /* setup pci memory address space mapping into system address space */ 1019 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1020 MemoryRegion *pci_address_space) 1021 { 1022 /* Set to lower priority than RAM */ 1023 memory_region_add_subregion_overlap(system_memory, 0x0, 1024 pci_address_space, -1); 1025 } 1026 1027 void xen_load_linux(PCMachineState *pcms) 1028 { 1029 int i; 1030 FWCfgState *fw_cfg; 1031 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1032 X86MachineState *x86ms = X86_MACHINE(pcms); 1033 1034 assert(MACHINE(pcms)->kernel_filename != NULL); 1035 1036 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1037 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1038 rom_set_fw(fw_cfg); 1039 1040 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1041 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 1042 for (i = 0; i < nb_option_roms; i++) { 1043 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1044 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1045 !strcmp(option_rom[i].name, "pvh.bin") || 1046 !strcmp(option_rom[i].name, "multiboot.bin")); 1047 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1048 } 1049 x86ms->fw_cfg = fw_cfg; 1050 } 1051 1052 void pc_memory_init(PCMachineState *pcms, 1053 MemoryRegion *system_memory, 1054 MemoryRegion *rom_memory, 1055 MemoryRegion **ram_memory) 1056 { 1057 int linux_boot, i; 1058 MemoryRegion *ram, *option_rom_mr; 1059 MemoryRegion *ram_below_4g, *ram_above_4g; 1060 FWCfgState *fw_cfg; 1061 MachineState *machine = MACHINE(pcms); 1062 MachineClass *mc = MACHINE_GET_CLASS(machine); 1063 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1064 X86MachineState *x86ms = X86_MACHINE(pcms); 1065 1066 assert(machine->ram_size == x86ms->below_4g_mem_size + 1067 x86ms->above_4g_mem_size); 1068 1069 linux_boot = (machine->kernel_filename != NULL); 1070 1071 /* Allocate RAM. We allocate it as a single memory region and use 1072 * aliases to address portions of it, mostly for backwards compatibility 1073 * with older qemus that used qemu_ram_alloc(). 1074 */ 1075 ram = g_malloc(sizeof(*ram)); 1076 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1077 machine->ram_size); 1078 *ram_memory = ram; 1079 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1080 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1081 0, x86ms->below_4g_mem_size); 1082 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1083 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1084 if (x86ms->above_4g_mem_size > 0) { 1085 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1086 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1087 x86ms->below_4g_mem_size, 1088 x86ms->above_4g_mem_size); 1089 memory_region_add_subregion(system_memory, 0x100000000ULL, 1090 ram_above_4g); 1091 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 1092 } 1093 1094 if (!pcmc->has_reserved_memory && 1095 (machine->ram_slots || 1096 (machine->maxram_size > machine->ram_size))) { 1097 1098 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1099 mc->name); 1100 exit(EXIT_FAILURE); 1101 } 1102 1103 /* always allocate the device memory information */ 1104 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1105 1106 /* initialize device memory address space */ 1107 if (pcmc->has_reserved_memory && 1108 (machine->ram_size < machine->maxram_size)) { 1109 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1110 1111 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1112 error_report("unsupported amount of memory slots: %"PRIu64, 1113 machine->ram_slots); 1114 exit(EXIT_FAILURE); 1115 } 1116 1117 if (QEMU_ALIGN_UP(machine->maxram_size, 1118 TARGET_PAGE_SIZE) != machine->maxram_size) { 1119 error_report("maximum memory size must by aligned to multiple of " 1120 "%d bytes", TARGET_PAGE_SIZE); 1121 exit(EXIT_FAILURE); 1122 } 1123 1124 machine->device_memory->base = 1125 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 1126 1127 if (pcmc->enforce_aligned_dimm) { 1128 /* size device region assuming 1G page max alignment per slot */ 1129 device_mem_size += (1 * GiB) * machine->ram_slots; 1130 } 1131 1132 if ((machine->device_memory->base + device_mem_size) < 1133 device_mem_size) { 1134 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1135 machine->maxram_size); 1136 exit(EXIT_FAILURE); 1137 } 1138 1139 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1140 "device-memory", device_mem_size); 1141 memory_region_add_subregion(system_memory, machine->device_memory->base, 1142 &machine->device_memory->mr); 1143 } 1144 1145 /* Initialize PC system firmware */ 1146 pc_system_firmware_init(pcms, rom_memory); 1147 1148 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1149 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1150 &error_fatal); 1151 if (pcmc->pci_enabled) { 1152 memory_region_set_readonly(option_rom_mr, true); 1153 } 1154 memory_region_add_subregion_overlap(rom_memory, 1155 PC_ROM_MIN_VGA, 1156 option_rom_mr, 1157 1); 1158 1159 fw_cfg = fw_cfg_arch_create(machine, 1160 x86ms->boot_cpus, x86ms->apic_id_limit); 1161 1162 rom_set_fw(fw_cfg); 1163 1164 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1165 uint64_t *val = g_malloc(sizeof(*val)); 1166 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1167 uint64_t res_mem_end = machine->device_memory->base; 1168 1169 if (!pcmc->broken_reserved_end) { 1170 res_mem_end += memory_region_size(&machine->device_memory->mr); 1171 } 1172 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1173 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1174 } 1175 1176 if (linux_boot) { 1177 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1178 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 1179 } 1180 1181 for (i = 0; i < nb_option_roms; i++) { 1182 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1183 } 1184 x86ms->fw_cfg = fw_cfg; 1185 1186 /* Init default IOAPIC address space */ 1187 x86ms->ioapic_as = &address_space_memory; 1188 1189 /* Init ACPI memory hotplug IO base address */ 1190 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1191 } 1192 1193 /* 1194 * The 64bit pci hole starts after "above 4G RAM" and 1195 * potentially the space reserved for memory hotplug. 1196 */ 1197 uint64_t pc_pci_hole64_start(void) 1198 { 1199 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1200 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1201 MachineState *ms = MACHINE(pcms); 1202 X86MachineState *x86ms = X86_MACHINE(pcms); 1203 uint64_t hole64_start = 0; 1204 1205 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1206 hole64_start = ms->device_memory->base; 1207 if (!pcmc->broken_reserved_end) { 1208 hole64_start += memory_region_size(&ms->device_memory->mr); 1209 } 1210 } else { 1211 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1212 } 1213 1214 return ROUND_UP(hole64_start, 1 * GiB); 1215 } 1216 1217 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1218 { 1219 DeviceState *dev = NULL; 1220 1221 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1222 if (pci_bus) { 1223 PCIDevice *pcidev = pci_vga_init(pci_bus); 1224 dev = pcidev ? &pcidev->qdev : NULL; 1225 } else if (isa_bus) { 1226 ISADevice *isadev = isa_vga_init(isa_bus); 1227 dev = isadev ? DEVICE(isadev) : NULL; 1228 } 1229 rom_reset_order_override(); 1230 return dev; 1231 } 1232 1233 static const MemoryRegionOps ioport80_io_ops = { 1234 .write = ioport80_write, 1235 .read = ioport80_read, 1236 .endianness = DEVICE_NATIVE_ENDIAN, 1237 .impl = { 1238 .min_access_size = 1, 1239 .max_access_size = 1, 1240 }, 1241 }; 1242 1243 static const MemoryRegionOps ioportF0_io_ops = { 1244 .write = ioportF0_write, 1245 .read = ioportF0_read, 1246 .endianness = DEVICE_NATIVE_ENDIAN, 1247 .impl = { 1248 .min_access_size = 1, 1249 .max_access_size = 1, 1250 }, 1251 }; 1252 1253 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1254 { 1255 int i; 1256 DriveInfo *fd[MAX_FD]; 1257 qemu_irq *a20_line; 1258 ISADevice *i8042, *port92, *vmmouse; 1259 1260 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1261 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1262 1263 for (i = 0; i < MAX_FD; i++) { 1264 fd[i] = drive_get(IF_FLOPPY, 0, i); 1265 create_fdctrl |= !!fd[i]; 1266 } 1267 if (create_fdctrl) { 1268 fdctrl_init_isa(isa_bus, fd); 1269 } 1270 1271 i8042 = isa_create_simple(isa_bus, "i8042"); 1272 if (!no_vmport) { 1273 vmport_init(isa_bus); 1274 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1275 } else { 1276 vmmouse = NULL; 1277 } 1278 if (vmmouse) { 1279 DeviceState *dev = DEVICE(vmmouse); 1280 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1281 qdev_init_nofail(dev); 1282 } 1283 port92 = isa_create_simple(isa_bus, "port92"); 1284 1285 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1286 i8042_setup_a20_line(i8042, a20_line[0]); 1287 port92_init(port92, a20_line[1]); 1288 g_free(a20_line); 1289 } 1290 1291 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1292 ISADevice **rtc_state, 1293 bool create_fdctrl, 1294 bool no_vmport, 1295 bool has_pit, 1296 uint32_t hpet_irqs) 1297 { 1298 int i; 1299 DeviceState *hpet = NULL; 1300 int pit_isa_irq = 0; 1301 qemu_irq pit_alt_irq = NULL; 1302 qemu_irq rtc_irq = NULL; 1303 ISADevice *pit = NULL; 1304 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1305 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1306 1307 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1308 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1309 1310 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1311 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1312 1313 /* 1314 * Check if an HPET shall be created. 1315 * 1316 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1317 * when the HPET wants to take over. Thus we have to disable the latter. 1318 */ 1319 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1320 /* In order to set property, here not using sysbus_try_create_simple */ 1321 hpet = qdev_try_create(NULL, TYPE_HPET); 1322 if (hpet) { 1323 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1324 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1325 * IRQ8 and IRQ2. 1326 */ 1327 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1328 HPET_INTCAP, NULL); 1329 if (!compat) { 1330 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1331 } 1332 qdev_init_nofail(hpet); 1333 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1334 1335 for (i = 0; i < GSI_NUM_PINS; i++) { 1336 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1337 } 1338 pit_isa_irq = -1; 1339 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1340 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1341 } 1342 } 1343 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1344 1345 qemu_register_boot_set(pc_boot_set, *rtc_state); 1346 1347 if (!xen_enabled() && has_pit) { 1348 if (kvm_pit_in_kernel()) { 1349 pit = kvm_pit_init(isa_bus, 0x40); 1350 } else { 1351 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1352 } 1353 if (hpet) { 1354 /* connect PIT to output control line of the HPET */ 1355 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1356 } 1357 pcspk_init(isa_bus, pit); 1358 } 1359 1360 i8257_dma_init(isa_bus, 0); 1361 1362 /* Super I/O */ 1363 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 1364 } 1365 1366 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1367 { 1368 int i; 1369 1370 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1371 for (i = 0; i < nb_nics; i++) { 1372 NICInfo *nd = &nd_table[i]; 1373 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1374 1375 if (g_str_equal(model, "ne2k_isa")) { 1376 pc_init_ne2k_isa(isa_bus, nd); 1377 } else { 1378 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1379 } 1380 } 1381 rom_reset_order_override(); 1382 } 1383 1384 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1385 { 1386 qemu_irq *i8259; 1387 1388 if (kvm_pic_in_kernel()) { 1389 i8259 = kvm_i8259_init(isa_bus); 1390 } else if (xen_enabled()) { 1391 i8259 = xen_interrupt_controller_init(); 1392 } else { 1393 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1394 } 1395 1396 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1397 i8259_irqs[i] = i8259[i]; 1398 } 1399 1400 g_free(i8259); 1401 } 1402 1403 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1404 Error **errp) 1405 { 1406 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1407 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1408 const MachineState *ms = MACHINE(hotplug_dev); 1409 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1410 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1411 Error *local_err = NULL; 1412 1413 /* 1414 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1415 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1416 * addition to cover this case. 1417 */ 1418 if (!pcms->acpi_dev || !acpi_enabled) { 1419 error_setg(errp, 1420 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1421 return; 1422 } 1423 1424 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1425 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1426 return; 1427 } 1428 1429 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 1430 if (local_err) { 1431 error_propagate(errp, local_err); 1432 return; 1433 } 1434 1435 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1436 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1437 } 1438 1439 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1440 DeviceState *dev, Error **errp) 1441 { 1442 Error *local_err = NULL; 1443 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1444 MachineState *ms = MACHINE(hotplug_dev); 1445 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1446 1447 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 1448 if (local_err) { 1449 goto out; 1450 } 1451 1452 if (is_nvdimm) { 1453 nvdimm_plug(ms->nvdimms_state); 1454 } 1455 1456 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1457 out: 1458 error_propagate(errp, local_err); 1459 } 1460 1461 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1462 DeviceState *dev, Error **errp) 1463 { 1464 Error *local_err = NULL; 1465 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1466 1467 /* 1468 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1469 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1470 * addition to cover this case. 1471 */ 1472 if (!pcms->acpi_dev || !acpi_enabled) { 1473 error_setg(&local_err, 1474 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1475 goto out; 1476 } 1477 1478 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1479 error_setg(&local_err, 1480 "nvdimm device hot unplug is not supported yet."); 1481 goto out; 1482 } 1483 1484 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 1485 &local_err); 1486 out: 1487 error_propagate(errp, local_err); 1488 } 1489 1490 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1491 DeviceState *dev, Error **errp) 1492 { 1493 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1494 Error *local_err = NULL; 1495 1496 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1497 if (local_err) { 1498 goto out; 1499 } 1500 1501 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1502 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 1503 out: 1504 error_propagate(errp, local_err); 1505 } 1506 1507 static int pc_apic_cmp(const void *a, const void *b) 1508 { 1509 CPUArchId *apic_a = (CPUArchId *)a; 1510 CPUArchId *apic_b = (CPUArchId *)b; 1511 1512 return apic_a->arch_id - apic_b->arch_id; 1513 } 1514 1515 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1516 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 1517 * entry corresponding to CPU's apic_id returns NULL. 1518 */ 1519 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1520 { 1521 CPUArchId apic_id, *found_cpu; 1522 1523 apic_id.arch_id = id; 1524 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 1525 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 1526 pc_apic_cmp); 1527 if (found_cpu && idx) { 1528 *idx = found_cpu - ms->possible_cpus->cpus; 1529 } 1530 return found_cpu; 1531 } 1532 1533 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1534 DeviceState *dev, Error **errp) 1535 { 1536 CPUArchId *found_cpu; 1537 Error *local_err = NULL; 1538 X86CPU *cpu = X86_CPU(dev); 1539 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1540 X86MachineState *x86ms = X86_MACHINE(pcms); 1541 1542 if (pcms->acpi_dev) { 1543 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1544 if (local_err) { 1545 goto out; 1546 } 1547 } 1548 1549 /* increment the number of CPUs */ 1550 x86ms->boot_cpus++; 1551 if (x86ms->rtc) { 1552 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1553 } 1554 if (x86ms->fw_cfg) { 1555 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1556 } 1557 1558 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1559 found_cpu->cpu = OBJECT(dev); 1560 out: 1561 error_propagate(errp, local_err); 1562 } 1563 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1564 DeviceState *dev, Error **errp) 1565 { 1566 int idx = -1; 1567 Error *local_err = NULL; 1568 X86CPU *cpu = X86_CPU(dev); 1569 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1570 1571 if (!pcms->acpi_dev) { 1572 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 1573 goto out; 1574 } 1575 1576 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1577 assert(idx != -1); 1578 if (idx == 0) { 1579 error_setg(&local_err, "Boot CPU is unpluggable"); 1580 goto out; 1581 } 1582 1583 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 1584 &local_err); 1585 if (local_err) { 1586 goto out; 1587 } 1588 1589 out: 1590 error_propagate(errp, local_err); 1591 1592 } 1593 1594 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1595 DeviceState *dev, Error **errp) 1596 { 1597 CPUArchId *found_cpu; 1598 Error *local_err = NULL; 1599 X86CPU *cpu = X86_CPU(dev); 1600 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1601 X86MachineState *x86ms = X86_MACHINE(pcms); 1602 1603 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1604 if (local_err) { 1605 goto out; 1606 } 1607 1608 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1609 found_cpu->cpu = NULL; 1610 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 1611 1612 /* decrement the number of CPUs */ 1613 x86ms->boot_cpus--; 1614 /* Update the number of CPUs in CMOS */ 1615 rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 1616 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 1617 out: 1618 error_propagate(errp, local_err); 1619 } 1620 1621 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1622 DeviceState *dev, Error **errp) 1623 { 1624 int idx; 1625 CPUState *cs; 1626 CPUArchId *cpu_slot; 1627 X86CPUTopoInfo topo; 1628 X86CPU *cpu = X86_CPU(dev); 1629 CPUX86State *env = &cpu->env; 1630 MachineState *ms = MACHINE(hotplug_dev); 1631 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1632 X86MachineState *x86ms = X86_MACHINE(pcms); 1633 unsigned int smp_cores = ms->smp.cores; 1634 unsigned int smp_threads = ms->smp.threads; 1635 1636 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 1637 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 1638 ms->cpu_type); 1639 return; 1640 } 1641 1642 env->nr_dies = x86ms->smp_dies; 1643 1644 /* 1645 * If APIC ID is not set, 1646 * set it based on socket/die/core/thread properties. 1647 */ 1648 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1649 int max_socket = (ms->smp.max_cpus - 1) / 1650 smp_threads / smp_cores / x86ms->smp_dies; 1651 1652 /* 1653 * die-id was optional in QEMU 4.0 and older, so keep it optional 1654 * if there's only one die per socket. 1655 */ 1656 if (cpu->die_id < 0 && x86ms->smp_dies == 1) { 1657 cpu->die_id = 0; 1658 } 1659 1660 if (cpu->socket_id < 0) { 1661 error_setg(errp, "CPU socket-id is not set"); 1662 return; 1663 } else if (cpu->socket_id > max_socket) { 1664 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1665 cpu->socket_id, max_socket); 1666 return; 1667 } 1668 if (cpu->die_id < 0) { 1669 error_setg(errp, "CPU die-id is not set"); 1670 return; 1671 } else if (cpu->die_id > x86ms->smp_dies - 1) { 1672 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 1673 cpu->die_id, x86ms->smp_dies - 1); 1674 return; 1675 } 1676 if (cpu->core_id < 0) { 1677 error_setg(errp, "CPU core-id is not set"); 1678 return; 1679 } else if (cpu->core_id > (smp_cores - 1)) { 1680 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1681 cpu->core_id, smp_cores - 1); 1682 return; 1683 } 1684 if (cpu->thread_id < 0) { 1685 error_setg(errp, "CPU thread-id is not set"); 1686 return; 1687 } else if (cpu->thread_id > (smp_threads - 1)) { 1688 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1689 cpu->thread_id, smp_threads - 1); 1690 return; 1691 } 1692 1693 topo.pkg_id = cpu->socket_id; 1694 topo.die_id = cpu->die_id; 1695 topo.core_id = cpu->core_id; 1696 topo.smt_id = cpu->thread_id; 1697 cpu->apic_id = apicid_from_topo_ids(x86ms->smp_dies, smp_cores, 1698 smp_threads, &topo); 1699 } 1700 1701 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1702 if (!cpu_slot) { 1703 MachineState *ms = MACHINE(pcms); 1704 1705 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, 1706 smp_cores, smp_threads, &topo); 1707 error_setg(errp, 1708 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 1709 " APIC ID %" PRIu32 ", valid index range 0:%d", 1710 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 1711 cpu->apic_id, ms->possible_cpus->len - 1); 1712 return; 1713 } 1714 1715 if (cpu_slot->cpu) { 1716 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1717 idx, cpu->apic_id); 1718 return; 1719 } 1720 1721 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1722 * so that machine_query_hotpluggable_cpus would show correct values 1723 */ 1724 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1725 * once -smp refactoring is complete and there will be CPU private 1726 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1727 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, 1728 smp_cores, smp_threads, &topo); 1729 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1730 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1731 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1732 return; 1733 } 1734 cpu->socket_id = topo.pkg_id; 1735 1736 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 1737 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 1738 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 1739 return; 1740 } 1741 cpu->die_id = topo.die_id; 1742 1743 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1744 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1745 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1746 return; 1747 } 1748 cpu->core_id = topo.core_id; 1749 1750 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1751 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1752 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1753 return; 1754 } 1755 cpu->thread_id = topo.smt_id; 1756 1757 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 1758 !kvm_hv_vpindex_settable()) { 1759 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 1760 return; 1761 } 1762 1763 cs = CPU(cpu); 1764 cs->cpu_index = idx; 1765 1766 numa_cpu_pre_plug(cpu_slot, dev, errp); 1767 } 1768 1769 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 1770 DeviceState *dev, Error **errp) 1771 { 1772 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1773 Error *local_err = NULL; 1774 1775 if (!hotplug_dev2) { 1776 /* 1777 * Without a bus hotplug handler, we cannot control the plug/unplug 1778 * order. This should never be the case on x86, however better add 1779 * a safety net. 1780 */ 1781 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 1782 return; 1783 } 1784 /* 1785 * First, see if we can plug this memory device at all. If that 1786 * succeeds, branch of to the actual hotplug handler. 1787 */ 1788 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1789 &local_err); 1790 if (!local_err) { 1791 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1792 } 1793 error_propagate(errp, local_err); 1794 } 1795 1796 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 1797 DeviceState *dev, Error **errp) 1798 { 1799 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1800 Error *local_err = NULL; 1801 1802 /* 1803 * Plug the memory device first and then branch off to the actual 1804 * hotplug handler. If that one fails, we can easily undo the memory 1805 * device bits. 1806 */ 1807 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1808 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1809 if (local_err) { 1810 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1811 } 1812 error_propagate(errp, local_err); 1813 } 1814 1815 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 1816 DeviceState *dev, Error **errp) 1817 { 1818 /* We don't support virtio pmem hot unplug */ 1819 error_setg(errp, "virtio pmem device unplug not supported."); 1820 } 1821 1822 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 1823 DeviceState *dev, Error **errp) 1824 { 1825 /* We don't support virtio pmem hot unplug */ 1826 } 1827 1828 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1829 DeviceState *dev, Error **errp) 1830 { 1831 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1832 pc_memory_pre_plug(hotplug_dev, dev, errp); 1833 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1834 pc_cpu_pre_plug(hotplug_dev, dev, errp); 1835 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1836 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 1837 } 1838 } 1839 1840 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1841 DeviceState *dev, Error **errp) 1842 { 1843 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1844 pc_memory_plug(hotplug_dev, dev, errp); 1845 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1846 pc_cpu_plug(hotplug_dev, dev, errp); 1847 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1848 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 1849 } 1850 } 1851 1852 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1853 DeviceState *dev, Error **errp) 1854 { 1855 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1856 pc_memory_unplug_request(hotplug_dev, dev, errp); 1857 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1858 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1859 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1860 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 1861 } else { 1862 error_setg(errp, "acpi: device unplug request for not supported device" 1863 " type: %s", object_get_typename(OBJECT(dev))); 1864 } 1865 } 1866 1867 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1868 DeviceState *dev, Error **errp) 1869 { 1870 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1871 pc_memory_unplug(hotplug_dev, dev, errp); 1872 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1873 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 1874 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1875 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 1876 } else { 1877 error_setg(errp, "acpi: device unplug for not supported device" 1878 " type: %s", object_get_typename(OBJECT(dev))); 1879 } 1880 } 1881 1882 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1883 DeviceState *dev) 1884 { 1885 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1886 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1887 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 1888 return HOTPLUG_HANDLER(machine); 1889 } 1890 1891 return NULL; 1892 } 1893 1894 static void 1895 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1896 const char *name, void *opaque, 1897 Error **errp) 1898 { 1899 MachineState *ms = MACHINE(obj); 1900 int64_t value = 0; 1901 1902 if (ms->device_memory) { 1903 value = memory_region_size(&ms->device_memory->mr); 1904 } 1905 1906 visit_type_int(v, name, &value, errp); 1907 } 1908 1909 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1910 void *opaque, Error **errp) 1911 { 1912 PCMachineState *pcms = PC_MACHINE(obj); 1913 OnOffAuto vmport = pcms->vmport; 1914 1915 visit_type_OnOffAuto(v, name, &vmport, errp); 1916 } 1917 1918 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1919 void *opaque, Error **errp) 1920 { 1921 PCMachineState *pcms = PC_MACHINE(obj); 1922 1923 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1924 } 1925 1926 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1927 { 1928 PCMachineState *pcms = PC_MACHINE(obj); 1929 1930 return pcms->smbus_enabled; 1931 } 1932 1933 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1934 { 1935 PCMachineState *pcms = PC_MACHINE(obj); 1936 1937 pcms->smbus_enabled = value; 1938 } 1939 1940 static bool pc_machine_get_sata(Object *obj, Error **errp) 1941 { 1942 PCMachineState *pcms = PC_MACHINE(obj); 1943 1944 return pcms->sata_enabled; 1945 } 1946 1947 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1948 { 1949 PCMachineState *pcms = PC_MACHINE(obj); 1950 1951 pcms->sata_enabled = value; 1952 } 1953 1954 static bool pc_machine_get_pit(Object *obj, Error **errp) 1955 { 1956 PCMachineState *pcms = PC_MACHINE(obj); 1957 1958 return pcms->pit_enabled; 1959 } 1960 1961 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1962 { 1963 PCMachineState *pcms = PC_MACHINE(obj); 1964 1965 pcms->pit_enabled = value; 1966 } 1967 1968 static void pc_machine_initfn(Object *obj) 1969 { 1970 PCMachineState *pcms = PC_MACHINE(obj); 1971 1972 #ifdef CONFIG_VMPORT 1973 pcms->vmport = ON_OFF_AUTO_AUTO; 1974 #else 1975 pcms->vmport = ON_OFF_AUTO_OFF; 1976 #endif /* CONFIG_VMPORT */ 1977 /* acpi build is enabled by default if machine supports it */ 1978 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1979 pcms->smbus_enabled = true; 1980 pcms->sata_enabled = true; 1981 pcms->pit_enabled = true; 1982 1983 pc_system_flash_create(pcms); 1984 } 1985 1986 static void pc_machine_reset(MachineState *machine) 1987 { 1988 CPUState *cs; 1989 X86CPU *cpu; 1990 1991 qemu_devices_reset(); 1992 1993 /* Reset APIC after devices have been reset to cancel 1994 * any changes that qemu_devices_reset() might have done. 1995 */ 1996 CPU_FOREACH(cs) { 1997 cpu = X86_CPU(cs); 1998 1999 if (cpu->apic_state) { 2000 device_reset(cpu->apic_state); 2001 } 2002 } 2003 } 2004 2005 static void pc_machine_wakeup(MachineState *machine) 2006 { 2007 cpu_synchronize_all_states(); 2008 pc_machine_reset(machine); 2009 cpu_synchronize_all_post_reset(); 2010 } 2011 2012 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 2013 { 2014 X86IOMMUState *iommu = x86_iommu_get_default(); 2015 IntelIOMMUState *intel_iommu; 2016 2017 if (iommu && 2018 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 2019 object_dynamic_cast((Object *)dev, "vfio-pci")) { 2020 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2021 if (!intel_iommu->caching_mode) { 2022 error_setg(errp, "Device assignment is not allowed without " 2023 "enabling caching-mode=on for Intel IOMMU."); 2024 return false; 2025 } 2026 } 2027 2028 return true; 2029 } 2030 2031 static void pc_machine_class_init(ObjectClass *oc, void *data) 2032 { 2033 MachineClass *mc = MACHINE_CLASS(oc); 2034 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2035 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2036 2037 pcmc->pci_enabled = true; 2038 pcmc->has_acpi_build = true; 2039 pcmc->rsdp_in_ram = true; 2040 pcmc->smbios_defaults = true; 2041 pcmc->smbios_uuid_encoded = true; 2042 pcmc->gigabyte_align = true; 2043 pcmc->has_reserved_memory = true; 2044 pcmc->kvmclock_enabled = true; 2045 pcmc->enforce_aligned_dimm = true; 2046 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2047 * to be used at the moment, 32K should be enough for a while. */ 2048 pcmc->acpi_data_size = 0x20000 + 0x8000; 2049 pcmc->linuxboot_dma_enabled = true; 2050 pcmc->pvh_enabled = true; 2051 assert(!mc->get_hotplug_handler); 2052 mc->get_hotplug_handler = pc_get_hotplug_handler; 2053 mc->hotplug_allowed = pc_hotplug_allowed; 2054 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 2055 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 2056 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 2057 mc->auto_enable_numa_with_memhp = true; 2058 mc->has_hotpluggable_cpus = true; 2059 mc->default_boot_order = "cad"; 2060 mc->hot_add_cpu = pc_hot_add_cpu; 2061 mc->smp_parse = pc_smp_parse; 2062 mc->block_default_type = IF_IDE; 2063 mc->max_cpus = 255; 2064 mc->reset = pc_machine_reset; 2065 mc->wakeup = pc_machine_wakeup; 2066 hc->pre_plug = pc_machine_device_pre_plug_cb; 2067 hc->plug = pc_machine_device_plug_cb; 2068 hc->unplug_request = pc_machine_device_unplug_request_cb; 2069 hc->unplug = pc_machine_device_unplug_cb; 2070 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2071 mc->nvdimm_supported = true; 2072 mc->numa_mem_supported = true; 2073 2074 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2075 pc_machine_get_device_memory_region_size, NULL, 2076 NULL, NULL, &error_abort); 2077 2078 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2079 pc_machine_get_vmport, pc_machine_set_vmport, 2080 NULL, NULL, &error_abort); 2081 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2082 "Enable vmport (pc & q35)", &error_abort); 2083 2084 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2085 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2086 2087 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2088 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2089 2090 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2091 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2092 } 2093 2094 static const TypeInfo pc_machine_info = { 2095 .name = TYPE_PC_MACHINE, 2096 .parent = TYPE_X86_MACHINE, 2097 .abstract = true, 2098 .instance_size = sizeof(PCMachineState), 2099 .instance_init = pc_machine_initfn, 2100 .class_size = sizeof(PCMachineClass), 2101 .class_init = pc_machine_class_init, 2102 .interfaces = (InterfaceInfo[]) { 2103 { TYPE_HOTPLUG_HANDLER }, 2104 { } 2105 }, 2106 }; 2107 2108 static void pc_machine_register_types(void) 2109 { 2110 type_register_static(&pc_machine_info); 2111 } 2112 2113 type_init(pc_machine_register_types) 2114