1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide/internal.h" 37 #include "hw/ide/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/intc/ioapic.h" 51 #include "hw/timer/i8254.h" 52 #include "hw/input/i8042.h" 53 #include "hw/irq.h" 54 #include "hw/audio/pcspk.h" 55 #include "hw/pci/msi.h" 56 #include "hw/sysbus.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/tcg.h" 59 #include "sysemu/numa.h" 60 #include "sysemu/kvm.h" 61 #include "sysemu/xen.h" 62 #include "sysemu/reset.h" 63 #include "sysemu/runstate.h" 64 #include "kvm/kvm_i386.h" 65 #include "hw/xen/xen.h" 66 #include "hw/xen/start_info.h" 67 #include "ui/qemu-spice.h" 68 #include "exec/memory.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/cxl/cxl.h" 80 #include "hw/cxl/cxl_host.h" 81 #include "qapi/error.h" 82 #include "qapi/qapi-visit-common.h" 83 #include "qapi/qapi-visit-machine.h" 84 #include "qapi/visitor.h" 85 #include "hw/core/cpu.h" 86 #include "hw/usb.h" 87 #include "hw/i386/intel_iommu.h" 88 #include "hw/net/ne2000-isa.h" 89 #include "standard-headers/asm-x86/bootparam.h" 90 #include "hw/virtio/virtio-iommu.h" 91 #include "hw/virtio/virtio-pmem-pci.h" 92 #include "hw/virtio/virtio-mem-pci.h" 93 #include "hw/i386/kvm/xen_overlay.h" 94 #include "hw/i386/kvm/xen_evtchn.h" 95 #include "hw/i386/kvm/xen_gnttab.h" 96 #include "hw/i386/kvm/xen_xenstore.h" 97 #include "hw/mem/memory-device.h" 98 #include "sysemu/replay.h" 99 #include "target/i386/cpu.h" 100 #include "e820_memory_layout.h" 101 #include "fw_cfg.h" 102 #include "trace.h" 103 #include CONFIG_DEVICES 104 105 /* 106 * Helper for setting model-id for CPU models that changed model-id 107 * depending on QEMU versions up to QEMU 2.4. 108 */ 109 #define PC_CPU_MODEL_IDS(v) \ 110 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 111 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 112 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 113 114 GlobalProperty pc_compat_7_2[] = { 115 { "ICH9-LPC", "noreboot", "true" }, 116 }; 117 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 118 119 GlobalProperty pc_compat_7_1[] = {}; 120 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 121 122 GlobalProperty pc_compat_7_0[] = {}; 123 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 124 125 GlobalProperty pc_compat_6_2[] = { 126 { "virtio-mem", "unplugged-inaccessible", "off" }, 127 }; 128 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 129 130 GlobalProperty pc_compat_6_1[] = { 131 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 132 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 133 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 134 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 135 }; 136 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 137 138 GlobalProperty pc_compat_6_0[] = { 139 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 140 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 141 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 142 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 143 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 144 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 145 }; 146 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 147 148 GlobalProperty pc_compat_5_2[] = { 149 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 150 }; 151 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 152 153 GlobalProperty pc_compat_5_1[] = { 154 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 155 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 156 }; 157 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 158 159 GlobalProperty pc_compat_5_0[] = { 160 }; 161 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 162 163 GlobalProperty pc_compat_4_2[] = { 164 { "mch", "smbase-smram", "off" }, 165 }; 166 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 167 168 GlobalProperty pc_compat_4_1[] = {}; 169 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 170 171 GlobalProperty pc_compat_4_0[] = {}; 172 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 173 174 GlobalProperty pc_compat_3_1[] = { 175 { "intel-iommu", "dma-drain", "off" }, 176 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 177 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 178 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 179 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 180 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 181 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 182 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 183 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 184 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 185 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 186 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 187 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 190 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 191 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 194 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 195 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 196 }; 197 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 198 199 GlobalProperty pc_compat_3_0[] = { 200 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 201 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 202 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 203 }; 204 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 205 206 GlobalProperty pc_compat_2_12[] = { 207 { TYPE_X86_CPU, "legacy-cache", "on" }, 208 { TYPE_X86_CPU, "topoext", "off" }, 209 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 210 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 211 }; 212 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 213 214 GlobalProperty pc_compat_2_11[] = { 215 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 216 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 217 }; 218 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 219 220 GlobalProperty pc_compat_2_10[] = { 221 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 222 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 223 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 224 }; 225 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 226 227 GlobalProperty pc_compat_2_9[] = { 228 { "mch", "extended-tseg-mbytes", "0" }, 229 }; 230 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 231 232 GlobalProperty pc_compat_2_8[] = { 233 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 234 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 235 { "ICH9-LPC", "x-smi-broadcast", "off" }, 236 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 237 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 238 }; 239 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 240 241 GlobalProperty pc_compat_2_7[] = { 242 { TYPE_X86_CPU, "l3-cache", "off" }, 243 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 244 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 245 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 246 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 247 { "isa-pcspk", "migrate", "off" }, 248 }; 249 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 250 251 GlobalProperty pc_compat_2_6[] = { 252 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 253 { "vmxnet3", "romfile", "" }, 254 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 255 { "apic-common", "legacy-instance-id", "on", } 256 }; 257 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 258 259 GlobalProperty pc_compat_2_5[] = {}; 260 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 261 262 GlobalProperty pc_compat_2_4[] = { 263 PC_CPU_MODEL_IDS("2.4.0") 264 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 265 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 266 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 267 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 268 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 269 { TYPE_X86_CPU, "check", "off" }, 270 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 271 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 272 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 273 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 274 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 275 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 276 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 277 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 278 }; 279 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 280 281 GlobalProperty pc_compat_2_3[] = { 282 PC_CPU_MODEL_IDS("2.3.0") 283 { TYPE_X86_CPU, "arat", "off" }, 284 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 285 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 286 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 287 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 288 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 289 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 291 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 292 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 293 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 294 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 295 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 296 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 297 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 298 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 299 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 300 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 301 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 302 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 303 }; 304 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 305 306 GlobalProperty pc_compat_2_2[] = { 307 PC_CPU_MODEL_IDS("2.2.0") 308 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 309 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 310 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 311 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 312 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 313 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 314 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 315 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 316 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 317 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 318 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 319 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 320 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 321 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 322 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 323 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 324 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 325 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 326 }; 327 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 328 329 GlobalProperty pc_compat_2_1[] = { 330 PC_CPU_MODEL_IDS("2.1.0") 331 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 332 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 333 }; 334 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 335 336 GlobalProperty pc_compat_2_0[] = { 337 PC_CPU_MODEL_IDS("2.0.0") 338 { "virtio-scsi-pci", "any_layout", "off" }, 339 { "PIIX4_PM", "memory-hotplug-support", "off" }, 340 { "apic", "version", "0x11" }, 341 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 342 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 343 { "pci-serial", "prog_if", "0" }, 344 { "pci-serial-2x", "prog_if", "0" }, 345 { "pci-serial-4x", "prog_if", "0" }, 346 { "virtio-net-pci", "guest_announce", "off" }, 347 { "ICH9-LPC", "memory-hotplug-support", "off" }, 348 }; 349 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 350 351 GlobalProperty pc_compat_1_7[] = { 352 PC_CPU_MODEL_IDS("1.7.0") 353 { TYPE_USB_DEVICE, "msos-desc", "no" }, 354 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 355 { "hpet", HPET_INTCAP, "4" }, 356 }; 357 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 358 359 GlobalProperty pc_compat_1_6[] = { 360 PC_CPU_MODEL_IDS("1.6.0") 361 { "e1000", "mitigation", "off" }, 362 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 363 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 364 { "i440FX-pcihost", "short_root_bus", "1" }, 365 { "q35-pcihost", "short_root_bus", "1" }, 366 }; 367 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 368 369 GlobalProperty pc_compat_1_5[] = { 370 PC_CPU_MODEL_IDS("1.5.0") 371 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 372 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 373 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 374 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 375 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 376 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 377 { "virtio-net-pci", "any_layout", "off" }, 378 { TYPE_X86_CPU, "pmu", "on" }, 379 { "i440FX-pcihost", "short_root_bus", "0" }, 380 { "q35-pcihost", "short_root_bus", "0" }, 381 }; 382 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 383 384 GlobalProperty pc_compat_1_4[] = { 385 PC_CPU_MODEL_IDS("1.4.0") 386 { "scsi-hd", "discard_granularity", "0" }, 387 { "scsi-cd", "discard_granularity", "0" }, 388 { "ide-hd", "discard_granularity", "0" }, 389 { "ide-cd", "discard_granularity", "0" }, 390 { "virtio-blk-pci", "discard_granularity", "0" }, 391 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 392 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 393 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 394 { "e1000", "romfile", "pxe-e1000.rom" }, 395 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 396 { "pcnet", "romfile", "pxe-pcnet.rom" }, 397 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 398 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 399 { "486-" TYPE_X86_CPU, "model", "0" }, 400 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 401 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 402 }; 403 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 404 405 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 406 { 407 GSIState *s; 408 409 s = g_new0(GSIState, 1); 410 if (kvm_ioapic_in_kernel()) { 411 kvm_pc_setup_irq_routing(pci_enabled); 412 } 413 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 414 415 return s; 416 } 417 418 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 419 unsigned size) 420 { 421 } 422 423 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 424 { 425 return 0xffffffffffffffffULL; 426 } 427 428 /* MSDOS compatibility mode FPU exception support */ 429 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 430 unsigned size) 431 { 432 if (tcg_enabled()) { 433 cpu_set_ignne(); 434 } 435 } 436 437 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 438 { 439 return 0xffffffffffffffffULL; 440 } 441 442 /* PC cmos mappings */ 443 444 #define REG_EQUIPMENT_BYTE 0x14 445 446 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 447 int16_t cylinders, int8_t heads, int8_t sectors) 448 { 449 mc146818rtc_set_cmos_data(s, type_ofs, 47); 450 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 451 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 452 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 453 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 454 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 455 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 456 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 457 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 458 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 459 } 460 461 /* convert boot_device letter to something recognizable by the bios */ 462 static int boot_device2nibble(char boot_device) 463 { 464 switch(boot_device) { 465 case 'a': 466 case 'b': 467 return 0x01; /* floppy boot */ 468 case 'c': 469 return 0x02; /* hard drive boot */ 470 case 'd': 471 return 0x03; /* CD-ROM boot */ 472 case 'n': 473 return 0x04; /* Network boot */ 474 } 475 return 0; 476 } 477 478 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 479 Error **errp) 480 { 481 #define PC_MAX_BOOT_DEVICES 3 482 int nbds, bds[3] = { 0, }; 483 int i; 484 485 nbds = strlen(boot_device); 486 if (nbds > PC_MAX_BOOT_DEVICES) { 487 error_setg(errp, "Too many boot devices for PC"); 488 return; 489 } 490 for (i = 0; i < nbds; i++) { 491 bds[i] = boot_device2nibble(boot_device[i]); 492 if (bds[i] == 0) { 493 error_setg(errp, "Invalid boot device for PC: '%c'", 494 boot_device[i]); 495 return; 496 } 497 } 498 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 499 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 500 } 501 502 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 503 { 504 set_boot_dev(opaque, boot_device, errp); 505 } 506 507 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 508 { 509 int val, nb, i; 510 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 511 FLOPPY_DRIVE_TYPE_NONE }; 512 513 /* floppy type */ 514 if (floppy) { 515 for (i = 0; i < 2; i++) { 516 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 517 } 518 } 519 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 520 cmos_get_fd_drive_type(fd_type[1]); 521 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 522 523 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 524 nb = 0; 525 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 526 nb++; 527 } 528 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 529 nb++; 530 } 531 switch (nb) { 532 case 0: 533 break; 534 case 1: 535 val |= 0x01; /* 1 drive, ready for boot */ 536 break; 537 case 2: 538 val |= 0x41; /* 2 drives, ready for boot */ 539 break; 540 } 541 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 542 } 543 544 typedef struct pc_cmos_init_late_arg { 545 MC146818RtcState *rtc_state; 546 BusState *idebus[2]; 547 } pc_cmos_init_late_arg; 548 549 typedef struct check_fdc_state { 550 ISADevice *floppy; 551 bool multiple; 552 } CheckFdcState; 553 554 static int check_fdc(Object *obj, void *opaque) 555 { 556 CheckFdcState *state = opaque; 557 Object *fdc; 558 uint32_t iobase; 559 Error *local_err = NULL; 560 561 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 562 if (!fdc) { 563 return 0; 564 } 565 566 iobase = object_property_get_uint(obj, "iobase", &local_err); 567 if (local_err || iobase != 0x3f0) { 568 error_free(local_err); 569 return 0; 570 } 571 572 if (state->floppy) { 573 state->multiple = true; 574 } else { 575 state->floppy = ISA_DEVICE(obj); 576 } 577 return 0; 578 } 579 580 static const char * const fdc_container_path[] = { 581 "/unattached", "/peripheral", "/peripheral-anon" 582 }; 583 584 /* 585 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 586 * and ACPI objects. 587 */ 588 static ISADevice *pc_find_fdc0(void) 589 { 590 int i; 591 Object *container; 592 CheckFdcState state = { 0 }; 593 594 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 595 container = container_get(qdev_get_machine(), fdc_container_path[i]); 596 object_child_foreach(container, check_fdc, &state); 597 } 598 599 if (state.multiple) { 600 warn_report("multiple floppy disk controllers with " 601 "iobase=0x3f0 have been found"); 602 error_printf("the one being picked for CMOS setup might not reflect " 603 "your intent"); 604 } 605 606 return state.floppy; 607 } 608 609 static void pc_cmos_init_late(void *opaque) 610 { 611 pc_cmos_init_late_arg *arg = opaque; 612 MC146818RtcState *s = arg->rtc_state; 613 int16_t cylinders; 614 int8_t heads, sectors; 615 int val; 616 int i, trans; 617 618 val = 0; 619 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 620 &cylinders, &heads, §ors) >= 0) { 621 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 622 val |= 0xf0; 623 } 624 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 625 &cylinders, &heads, §ors) >= 0) { 626 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 627 val |= 0x0f; 628 } 629 mc146818rtc_set_cmos_data(s, 0x12, val); 630 631 val = 0; 632 for (i = 0; i < 4; i++) { 633 /* NOTE: ide_get_geometry() returns the physical 634 geometry. It is always such that: 1 <= sects <= 63, 1 635 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 636 geometry can be different if a translation is done. */ 637 if (arg->idebus[i / 2] && 638 ide_get_geometry(arg->idebus[i / 2], i % 2, 639 &cylinders, &heads, §ors) >= 0) { 640 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 641 assert((trans & ~3) == 0); 642 val |= trans << (i * 2); 643 } 644 } 645 mc146818rtc_set_cmos_data(s, 0x39, val); 646 647 pc_cmos_init_floppy(s, pc_find_fdc0()); 648 649 qemu_unregister_reset(pc_cmos_init_late, opaque); 650 } 651 652 void pc_cmos_init(PCMachineState *pcms, 653 BusState *idebus0, BusState *idebus1, 654 ISADevice *rtc) 655 { 656 int val; 657 static pc_cmos_init_late_arg arg; 658 X86MachineState *x86ms = X86_MACHINE(pcms); 659 MC146818RtcState *s = MC146818_RTC(rtc); 660 661 /* various important CMOS locations needed by PC/Bochs bios */ 662 663 /* memory size */ 664 /* base memory (first MiB) */ 665 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 666 mc146818rtc_set_cmos_data(s, 0x15, val); 667 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 668 /* extended memory (next 64MiB) */ 669 if (x86ms->below_4g_mem_size > 1 * MiB) { 670 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 671 } else { 672 val = 0; 673 } 674 if (val > 65535) 675 val = 65535; 676 mc146818rtc_set_cmos_data(s, 0x17, val); 677 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 678 mc146818rtc_set_cmos_data(s, 0x30, val); 679 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 680 /* memory between 16MiB and 4GiB */ 681 if (x86ms->below_4g_mem_size > 16 * MiB) { 682 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 683 } else { 684 val = 0; 685 } 686 if (val > 65535) 687 val = 65535; 688 mc146818rtc_set_cmos_data(s, 0x34, val); 689 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 690 /* memory above 4GiB */ 691 val = x86ms->above_4g_mem_size / 65536; 692 mc146818rtc_set_cmos_data(s, 0x5b, val); 693 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 694 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 695 696 object_property_add_link(OBJECT(pcms), "rtc_state", 697 TYPE_ISA_DEVICE, 698 (Object **)&x86ms->rtc, 699 object_property_allow_set_link, 700 OBJ_PROP_LINK_STRONG); 701 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 702 &error_abort); 703 704 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 705 706 val = 0; 707 val |= 0x02; /* FPU is there */ 708 val |= 0x04; /* PS/2 mouse installed */ 709 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 710 711 /* hard drives and FDC */ 712 arg.rtc_state = s; 713 arg.idebus[0] = idebus0; 714 arg.idebus[1] = idebus1; 715 qemu_register_reset(pc_cmos_init_late, &arg); 716 } 717 718 static void handle_a20_line_change(void *opaque, int irq, int level) 719 { 720 X86CPU *cpu = opaque; 721 722 /* XXX: send to all CPUs ? */ 723 /* XXX: add logic to handle multiple A20 line sources */ 724 x86_cpu_set_a20(cpu, level); 725 } 726 727 #define NE2000_NB_MAX 6 728 729 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 730 0x280, 0x380 }; 731 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 732 733 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 734 { 735 static int nb_ne2k = 0; 736 737 if (nb_ne2k == NE2000_NB_MAX) 738 return; 739 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 740 ne2000_irq[nb_ne2k], nd); 741 nb_ne2k++; 742 } 743 744 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 745 { 746 X86CPU *cpu = opaque; 747 748 if (level) { 749 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 750 } 751 } 752 753 static 754 void pc_machine_done(Notifier *notifier, void *data) 755 { 756 PCMachineState *pcms = container_of(notifier, 757 PCMachineState, machine_done); 758 X86MachineState *x86ms = X86_MACHINE(pcms); 759 760 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 761 &error_fatal); 762 763 if (pcms->cxl_devices_state.is_enabled) { 764 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 765 } 766 767 /* set the number of CPUs */ 768 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 769 770 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 771 772 acpi_setup(); 773 if (x86ms->fw_cfg) { 774 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 775 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 776 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 777 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 778 } 779 } 780 781 void pc_guest_info_init(PCMachineState *pcms) 782 { 783 X86MachineState *x86ms = X86_MACHINE(pcms); 784 785 x86ms->apic_xrupt_override = true; 786 pcms->machine_done.notify = pc_machine_done; 787 qemu_add_machine_init_done_notifier(&pcms->machine_done); 788 } 789 790 /* setup pci memory address space mapping into system address space */ 791 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 792 MemoryRegion *pci_address_space) 793 { 794 /* Set to lower priority than RAM */ 795 memory_region_add_subregion_overlap(system_memory, 0x0, 796 pci_address_space, -1); 797 } 798 799 void xen_load_linux(PCMachineState *pcms) 800 { 801 int i; 802 FWCfgState *fw_cfg; 803 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 804 X86MachineState *x86ms = X86_MACHINE(pcms); 805 806 assert(MACHINE(pcms)->kernel_filename != NULL); 807 808 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 809 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 810 rom_set_fw(fw_cfg); 811 812 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 813 pcmc->pvh_enabled); 814 for (i = 0; i < nb_option_roms; i++) { 815 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 816 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 817 !strcmp(option_rom[i].name, "pvh.bin") || 818 !strcmp(option_rom[i].name, "multiboot.bin") || 819 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 820 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 821 } 822 x86ms->fw_cfg = fw_cfg; 823 } 824 825 #define PC_ROM_MIN_VGA 0xc0000 826 #define PC_ROM_MIN_OPTION 0xc8000 827 #define PC_ROM_MAX 0xe0000 828 #define PC_ROM_ALIGN 0x800 829 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 830 831 static hwaddr pc_above_4g_end(PCMachineState *pcms) 832 { 833 X86MachineState *x86ms = X86_MACHINE(pcms); 834 835 if (pcms->sgx_epc.size != 0) { 836 return sgx_epc_above_4g_end(&pcms->sgx_epc); 837 } 838 839 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 840 } 841 842 static void pc_get_device_memory_range(PCMachineState *pcms, 843 hwaddr *base, 844 ram_addr_t *device_mem_size) 845 { 846 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 847 MachineState *machine = MACHINE(pcms); 848 ram_addr_t size; 849 hwaddr addr; 850 851 size = machine->maxram_size - machine->ram_size; 852 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 853 854 if (pcmc->enforce_aligned_dimm) { 855 /* size device region assuming 1G page max alignment per slot */ 856 size += (1 * GiB) * machine->ram_slots; 857 } 858 859 *base = addr; 860 *device_mem_size = size; 861 } 862 863 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 864 { 865 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 866 hwaddr cxl_base; 867 ram_addr_t size; 868 869 if (pcmc->has_reserved_memory) { 870 pc_get_device_memory_range(pcms, &cxl_base, &size); 871 cxl_base += size; 872 } else { 873 cxl_base = pc_above_4g_end(pcms); 874 } 875 876 return cxl_base; 877 } 878 879 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 880 { 881 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 882 883 if (pcms->cxl_devices_state.fixed_windows) { 884 GList *it; 885 886 start = ROUND_UP(start, 256 * MiB); 887 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 888 CXLFixedWindow *fw = it->data; 889 start += fw->size; 890 } 891 } 892 893 return start; 894 } 895 896 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 897 { 898 X86CPU *cpu = X86_CPU(first_cpu); 899 900 /* 32-bit systems don't have hole64 thus return max CPU address */ 901 if (cpu->phys_bits <= 32) { 902 return ((hwaddr)1 << cpu->phys_bits) - 1; 903 } 904 905 return pc_pci_hole64_start() + pci_hole64_size - 1; 906 } 907 908 /* 909 * AMD systems with an IOMMU have an additional hole close to the 910 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 911 * on kernel version, VFIO may or may not let you DMA map those ranges. 912 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 913 * with certain memory sizes. It's also wrong to use those IOVA ranges 914 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 915 * The ranges reserved for Hyper-Transport are: 916 * 917 * FD_0000_0000h - FF_FFFF_FFFFh 918 * 919 * The ranges represent the following: 920 * 921 * Base Address Top Address Use 922 * 923 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 924 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 925 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 926 * FD_F910_0000h FD_F91F_FFFFh System Management 927 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 928 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 929 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 930 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 931 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 932 * FE_2000_0000h FF_FFFF_FFFFh Reserved 933 * 934 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 935 * Table 3: Special Address Controls (GPA) for more information. 936 */ 937 #define AMD_HT_START 0xfd00000000UL 938 #define AMD_HT_END 0xffffffffffUL 939 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 940 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 941 942 void pc_memory_init(PCMachineState *pcms, 943 MemoryRegion *system_memory, 944 MemoryRegion *rom_memory, 945 MemoryRegion **ram_memory, 946 uint64_t pci_hole64_size) 947 { 948 int linux_boot, i; 949 MemoryRegion *option_rom_mr; 950 MemoryRegion *ram_below_4g, *ram_above_4g; 951 FWCfgState *fw_cfg; 952 MachineState *machine = MACHINE(pcms); 953 MachineClass *mc = MACHINE_GET_CLASS(machine); 954 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 955 X86MachineState *x86ms = X86_MACHINE(pcms); 956 hwaddr maxphysaddr, maxusedaddr; 957 hwaddr cxl_base, cxl_resv_end = 0; 958 X86CPU *cpu = X86_CPU(first_cpu); 959 960 assert(machine->ram_size == x86ms->below_4g_mem_size + 961 x86ms->above_4g_mem_size); 962 963 linux_boot = (machine->kernel_filename != NULL); 964 965 /* 966 * The HyperTransport range close to the 1T boundary is unique to AMD 967 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 968 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 969 * older machine types (<= 7.0) for compatibility purposes. 970 */ 971 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 972 /* Bail out if max possible address does not cross HT range */ 973 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 974 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 975 } 976 977 /* 978 * Advertise the HT region if address space covers the reserved 979 * region or if we relocate. 980 */ 981 if (cpu->phys_bits >= 40) { 982 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 983 } 984 } 985 986 /* 987 * phys-bits is required to be appropriately configured 988 * to make sure max used GPA is reachable. 989 */ 990 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 991 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 992 if (maxphysaddr < maxusedaddr) { 993 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 994 " phys-bits too low (%u)", 995 maxphysaddr, maxusedaddr, cpu->phys_bits); 996 exit(EXIT_FAILURE); 997 } 998 999 /* 1000 * Split single memory region and use aliases to address portions of it, 1001 * done for backwards compatibility with older qemus. 1002 */ 1003 *ram_memory = machine->ram; 1004 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1005 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 1006 0, x86ms->below_4g_mem_size); 1007 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1008 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1009 if (x86ms->above_4g_mem_size > 0) { 1010 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1011 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1012 machine->ram, 1013 x86ms->below_4g_mem_size, 1014 x86ms->above_4g_mem_size); 1015 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1016 ram_above_4g); 1017 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1018 E820_RAM); 1019 } 1020 1021 if (pcms->sgx_epc.size != 0) { 1022 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1023 } 1024 1025 if (!pcmc->has_reserved_memory && 1026 (machine->ram_slots || 1027 (machine->maxram_size > machine->ram_size))) { 1028 1029 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1030 mc->name); 1031 exit(EXIT_FAILURE); 1032 } 1033 1034 /* always allocate the device memory information */ 1035 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1036 1037 /* initialize device memory address space */ 1038 if (pcmc->has_reserved_memory && 1039 (machine->ram_size < machine->maxram_size)) { 1040 ram_addr_t device_mem_size; 1041 1042 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1043 error_report("unsupported amount of memory slots: %"PRIu64, 1044 machine->ram_slots); 1045 exit(EXIT_FAILURE); 1046 } 1047 1048 if (QEMU_ALIGN_UP(machine->maxram_size, 1049 TARGET_PAGE_SIZE) != machine->maxram_size) { 1050 error_report("maximum memory size must by aligned to multiple of " 1051 "%d bytes", TARGET_PAGE_SIZE); 1052 exit(EXIT_FAILURE); 1053 } 1054 1055 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1056 1057 if ((machine->device_memory->base + device_mem_size) < 1058 device_mem_size) { 1059 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1060 machine->maxram_size); 1061 exit(EXIT_FAILURE); 1062 } 1063 1064 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1065 "device-memory", device_mem_size); 1066 memory_region_add_subregion(system_memory, machine->device_memory->base, 1067 &machine->device_memory->mr); 1068 } 1069 1070 if (pcms->cxl_devices_state.is_enabled) { 1071 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1072 hwaddr cxl_size = MiB; 1073 1074 cxl_base = pc_get_cxl_range_start(pcms); 1075 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1076 memory_region_add_subregion(system_memory, cxl_base, mr); 1077 cxl_resv_end = cxl_base + cxl_size; 1078 if (pcms->cxl_devices_state.fixed_windows) { 1079 hwaddr cxl_fmw_base; 1080 GList *it; 1081 1082 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1083 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1084 CXLFixedWindow *fw = it->data; 1085 1086 fw->base = cxl_fmw_base; 1087 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1088 "cxl-fixed-memory-region", fw->size); 1089 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1090 cxl_fmw_base += fw->size; 1091 cxl_resv_end = cxl_fmw_base; 1092 } 1093 } 1094 } 1095 1096 /* Initialize PC system firmware */ 1097 pc_system_firmware_init(pcms, rom_memory); 1098 1099 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1100 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1101 &error_fatal); 1102 if (pcmc->pci_enabled) { 1103 memory_region_set_readonly(option_rom_mr, true); 1104 } 1105 memory_region_add_subregion_overlap(rom_memory, 1106 PC_ROM_MIN_VGA, 1107 option_rom_mr, 1108 1); 1109 1110 fw_cfg = fw_cfg_arch_create(machine, 1111 x86ms->boot_cpus, x86ms->apic_id_limit); 1112 1113 rom_set_fw(fw_cfg); 1114 1115 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1116 uint64_t *val = g_malloc(sizeof(*val)); 1117 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1118 uint64_t res_mem_end = machine->device_memory->base; 1119 1120 if (!pcmc->broken_reserved_end) { 1121 res_mem_end += memory_region_size(&machine->device_memory->mr); 1122 } 1123 1124 if (pcms->cxl_devices_state.is_enabled) { 1125 res_mem_end = cxl_resv_end; 1126 } 1127 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1128 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1129 } 1130 1131 if (linux_boot) { 1132 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1133 pcmc->pvh_enabled); 1134 } 1135 1136 for (i = 0; i < nb_option_roms; i++) { 1137 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1138 } 1139 x86ms->fw_cfg = fw_cfg; 1140 1141 /* Init default IOAPIC address space */ 1142 x86ms->ioapic_as = &address_space_memory; 1143 1144 /* Init ACPI memory hotplug IO base address */ 1145 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1146 } 1147 1148 /* 1149 * The 64bit pci hole starts after "above 4G RAM" and 1150 * potentially the space reserved for memory hotplug. 1151 */ 1152 uint64_t pc_pci_hole64_start(void) 1153 { 1154 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1155 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1156 MachineState *ms = MACHINE(pcms); 1157 uint64_t hole64_start = 0; 1158 ram_addr_t size = 0; 1159 1160 if (pcms->cxl_devices_state.is_enabled) { 1161 hole64_start = pc_get_cxl_range_end(pcms); 1162 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1163 pc_get_device_memory_range(pcms, &hole64_start, &size); 1164 if (!pcmc->broken_reserved_end) { 1165 hole64_start += size; 1166 } 1167 } else { 1168 hole64_start = pc_above_4g_end(pcms); 1169 } 1170 1171 return ROUND_UP(hole64_start, 1 * GiB); 1172 } 1173 1174 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1175 { 1176 DeviceState *dev = NULL; 1177 1178 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1179 if (pci_bus) { 1180 PCIDevice *pcidev = pci_vga_init(pci_bus); 1181 dev = pcidev ? &pcidev->qdev : NULL; 1182 } else if (isa_bus) { 1183 ISADevice *isadev = isa_vga_init(isa_bus); 1184 dev = isadev ? DEVICE(isadev) : NULL; 1185 } 1186 rom_reset_order_override(); 1187 return dev; 1188 } 1189 1190 static const MemoryRegionOps ioport80_io_ops = { 1191 .write = ioport80_write, 1192 .read = ioport80_read, 1193 .endianness = DEVICE_NATIVE_ENDIAN, 1194 .impl = { 1195 .min_access_size = 1, 1196 .max_access_size = 1, 1197 }, 1198 }; 1199 1200 static const MemoryRegionOps ioportF0_io_ops = { 1201 .write = ioportF0_write, 1202 .read = ioportF0_read, 1203 .endianness = DEVICE_NATIVE_ENDIAN, 1204 .impl = { 1205 .min_access_size = 1, 1206 .max_access_size = 1, 1207 }, 1208 }; 1209 1210 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1211 bool create_i8042, bool no_vmport) 1212 { 1213 int i; 1214 DriveInfo *fd[MAX_FD]; 1215 qemu_irq *a20_line; 1216 ISADevice *fdc, *i8042, *port92, *vmmouse; 1217 1218 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1219 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1220 1221 for (i = 0; i < MAX_FD; i++) { 1222 fd[i] = drive_get(IF_FLOPPY, 0, i); 1223 create_fdctrl |= !!fd[i]; 1224 } 1225 if (create_fdctrl) { 1226 fdc = isa_new(TYPE_ISA_FDC); 1227 if (fdc) { 1228 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1229 isa_fdc_init_drives(fdc, fd); 1230 } 1231 } 1232 1233 if (!create_i8042) { 1234 return; 1235 } 1236 1237 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1238 if (!no_vmport) { 1239 isa_create_simple(isa_bus, TYPE_VMPORT); 1240 vmmouse = isa_try_new("vmmouse"); 1241 } else { 1242 vmmouse = NULL; 1243 } 1244 if (vmmouse) { 1245 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1246 &error_abort); 1247 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1248 } 1249 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1250 1251 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1252 i8042_setup_a20_line(i8042, a20_line[0]); 1253 qdev_connect_gpio_out_named(DEVICE(port92), 1254 PORT92_A20_LINE, 0, a20_line[1]); 1255 g_free(a20_line); 1256 } 1257 1258 void pc_basic_device_init(struct PCMachineState *pcms, 1259 ISABus *isa_bus, qemu_irq *gsi, 1260 ISADevice **rtc_state, 1261 bool create_fdctrl, 1262 uint32_t hpet_irqs) 1263 { 1264 int i; 1265 DeviceState *hpet = NULL; 1266 int pit_isa_irq = 0; 1267 qemu_irq pit_alt_irq = NULL; 1268 qemu_irq rtc_irq = NULL; 1269 ISADevice *pit = NULL; 1270 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1271 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1272 X86MachineState *x86ms = X86_MACHINE(pcms); 1273 1274 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1275 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1276 1277 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1278 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1279 1280 /* 1281 * Check if an HPET shall be created. 1282 * 1283 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1284 * when the HPET wants to take over. Thus we have to disable the latter. 1285 */ 1286 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1287 kvm_has_pit_state2())) { 1288 hpet = qdev_try_new(TYPE_HPET); 1289 if (!hpet) { 1290 error_report("couldn't create HPET device"); 1291 exit(1); 1292 } 1293 /* 1294 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1295 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1296 * IRQ2. 1297 */ 1298 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1299 HPET_INTCAP, NULL); 1300 if (!compat) { 1301 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1302 } 1303 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1304 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1305 1306 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1307 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1308 } 1309 pit_isa_irq = -1; 1310 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1311 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1312 } 1313 *rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq)); 1314 1315 #ifdef CONFIG_XEN_EMU 1316 if (xen_mode == XEN_EMULATE) { 1317 xen_evtchn_connect_gsis(gsi); 1318 if (pcms->bus) { 1319 pci_create_simple(pcms->bus, -1, "xen-platform"); 1320 } 1321 } 1322 #endif 1323 1324 qemu_register_boot_set(pc_boot_set, *rtc_state); 1325 1326 if (!xen_enabled() && 1327 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1328 if (kvm_pit_in_kernel()) { 1329 pit = kvm_pit_init(isa_bus, 0x40); 1330 } else { 1331 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1332 } 1333 if (hpet) { 1334 /* connect PIT to output control line of the HPET */ 1335 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1336 } 1337 pcspk_init(pcms->pcspk, isa_bus, pit); 1338 } 1339 1340 /* Super I/O */ 1341 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1342 pcms->vmport != ON_OFF_AUTO_ON); 1343 } 1344 1345 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1346 { 1347 int i; 1348 1349 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1350 for (i = 0; i < nb_nics; i++) { 1351 NICInfo *nd = &nd_table[i]; 1352 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1353 1354 if (g_str_equal(model, "ne2k_isa")) { 1355 pc_init_ne2k_isa(isa_bus, nd); 1356 } else { 1357 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1358 } 1359 } 1360 rom_reset_order_override(); 1361 } 1362 1363 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1364 { 1365 qemu_irq *i8259; 1366 1367 if (kvm_pic_in_kernel()) { 1368 i8259 = kvm_i8259_init(isa_bus); 1369 } else if (xen_enabled()) { 1370 i8259 = xen_interrupt_controller_init(); 1371 } else { 1372 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1373 } 1374 1375 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1376 i8259_irqs[i] = i8259[i]; 1377 } 1378 1379 g_free(i8259); 1380 } 1381 1382 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1383 Error **errp) 1384 { 1385 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1386 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1387 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1388 const MachineState *ms = MACHINE(hotplug_dev); 1389 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1390 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1391 Error *local_err = NULL; 1392 1393 /* 1394 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1395 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1396 * addition to cover this case. 1397 */ 1398 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1399 error_setg(errp, 1400 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1401 return; 1402 } 1403 1404 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1405 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1406 return; 1407 } 1408 1409 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1410 if (local_err) { 1411 error_propagate(errp, local_err); 1412 return; 1413 } 1414 1415 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1416 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1417 } 1418 1419 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1420 DeviceState *dev, Error **errp) 1421 { 1422 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1423 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1424 MachineState *ms = MACHINE(hotplug_dev); 1425 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1426 1427 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1428 1429 if (is_nvdimm) { 1430 nvdimm_plug(ms->nvdimms_state); 1431 } 1432 1433 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1434 } 1435 1436 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1437 DeviceState *dev, Error **errp) 1438 { 1439 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1440 1441 /* 1442 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1443 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1444 * addition to cover this case. 1445 */ 1446 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1447 error_setg(errp, 1448 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1449 return; 1450 } 1451 1452 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1453 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1454 return; 1455 } 1456 1457 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1458 errp); 1459 } 1460 1461 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1462 DeviceState *dev, Error **errp) 1463 { 1464 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1465 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1466 Error *local_err = NULL; 1467 1468 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1469 if (local_err) { 1470 goto out; 1471 } 1472 1473 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1474 qdev_unrealize(dev); 1475 out: 1476 error_propagate(errp, local_err); 1477 } 1478 1479 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1480 DeviceState *dev, Error **errp) 1481 { 1482 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1483 Error *local_err = NULL; 1484 1485 if (!hotplug_dev2 && dev->hotplugged) { 1486 /* 1487 * Without a bus hotplug handler, we cannot control the plug/unplug 1488 * order. We should never reach this point when hotplugging on x86, 1489 * however, better add a safety net. 1490 */ 1491 error_setg(errp, "hotplug of virtio based memory devices not supported" 1492 " on this bus."); 1493 return; 1494 } 1495 /* 1496 * First, see if we can plug this memory device at all. If that 1497 * succeeds, branch of to the actual hotplug handler. 1498 */ 1499 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1500 &local_err); 1501 if (!local_err && hotplug_dev2) { 1502 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1503 } 1504 error_propagate(errp, local_err); 1505 } 1506 1507 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1508 DeviceState *dev, Error **errp) 1509 { 1510 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1511 Error *local_err = NULL; 1512 1513 /* 1514 * Plug the memory device first and then branch off to the actual 1515 * hotplug handler. If that one fails, we can easily undo the memory 1516 * device bits. 1517 */ 1518 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1519 if (hotplug_dev2) { 1520 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1521 if (local_err) { 1522 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1523 } 1524 } 1525 error_propagate(errp, local_err); 1526 } 1527 1528 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1529 DeviceState *dev, Error **errp) 1530 { 1531 /* We don't support hot unplug of virtio based memory devices */ 1532 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1533 } 1534 1535 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1536 DeviceState *dev, Error **errp) 1537 { 1538 /* We don't support hot unplug of virtio based memory devices */ 1539 } 1540 1541 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1542 DeviceState *dev, Error **errp) 1543 { 1544 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1545 pc_memory_pre_plug(hotplug_dev, dev, errp); 1546 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1547 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1548 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1549 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1550 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1551 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1552 /* Declare the APIC range as the reserved MSI region */ 1553 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1554 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1555 1556 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1557 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1558 resv_prop_str, errp); 1559 g_free(resv_prop_str); 1560 } 1561 1562 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1563 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1564 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1565 1566 if (pcms->iommu) { 1567 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1568 "for x86 yet."); 1569 return; 1570 } 1571 pcms->iommu = dev; 1572 } 1573 } 1574 1575 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1576 DeviceState *dev, Error **errp) 1577 { 1578 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1579 pc_memory_plug(hotplug_dev, dev, errp); 1580 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1581 x86_cpu_plug(hotplug_dev, dev, errp); 1582 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1583 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1584 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1585 } 1586 } 1587 1588 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1589 DeviceState *dev, Error **errp) 1590 { 1591 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1592 pc_memory_unplug_request(hotplug_dev, dev, errp); 1593 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1594 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1595 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1596 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1597 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1598 } else { 1599 error_setg(errp, "acpi: device unplug request for not supported device" 1600 " type: %s", object_get_typename(OBJECT(dev))); 1601 } 1602 } 1603 1604 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1605 DeviceState *dev, Error **errp) 1606 { 1607 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1608 pc_memory_unplug(hotplug_dev, dev, errp); 1609 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1610 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1611 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1612 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1613 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1614 } else { 1615 error_setg(errp, "acpi: device unplug for not supported device" 1616 " type: %s", object_get_typename(OBJECT(dev))); 1617 } 1618 } 1619 1620 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1621 DeviceState *dev) 1622 { 1623 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1624 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1625 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1626 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1627 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1628 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1629 return HOTPLUG_HANDLER(machine); 1630 } 1631 1632 return NULL; 1633 } 1634 1635 static void 1636 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1637 const char *name, void *opaque, 1638 Error **errp) 1639 { 1640 MachineState *ms = MACHINE(obj); 1641 int64_t value = 0; 1642 1643 if (ms->device_memory) { 1644 value = memory_region_size(&ms->device_memory->mr); 1645 } 1646 1647 visit_type_int(v, name, &value, errp); 1648 } 1649 1650 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1651 void *opaque, Error **errp) 1652 { 1653 PCMachineState *pcms = PC_MACHINE(obj); 1654 OnOffAuto vmport = pcms->vmport; 1655 1656 visit_type_OnOffAuto(v, name, &vmport, errp); 1657 } 1658 1659 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1660 void *opaque, Error **errp) 1661 { 1662 PCMachineState *pcms = PC_MACHINE(obj); 1663 1664 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1665 } 1666 1667 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1668 { 1669 PCMachineState *pcms = PC_MACHINE(obj); 1670 1671 return pcms->smbus_enabled; 1672 } 1673 1674 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1675 { 1676 PCMachineState *pcms = PC_MACHINE(obj); 1677 1678 pcms->smbus_enabled = value; 1679 } 1680 1681 static bool pc_machine_get_sata(Object *obj, Error **errp) 1682 { 1683 PCMachineState *pcms = PC_MACHINE(obj); 1684 1685 return pcms->sata_enabled; 1686 } 1687 1688 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1689 { 1690 PCMachineState *pcms = PC_MACHINE(obj); 1691 1692 pcms->sata_enabled = value; 1693 } 1694 1695 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1696 { 1697 PCMachineState *pcms = PC_MACHINE(obj); 1698 1699 return pcms->hpet_enabled; 1700 } 1701 1702 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1703 { 1704 PCMachineState *pcms = PC_MACHINE(obj); 1705 1706 pcms->hpet_enabled = value; 1707 } 1708 1709 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1710 { 1711 PCMachineState *pcms = PC_MACHINE(obj); 1712 1713 return pcms->i8042_enabled; 1714 } 1715 1716 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1717 { 1718 PCMachineState *pcms = PC_MACHINE(obj); 1719 1720 pcms->i8042_enabled = value; 1721 } 1722 1723 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1724 { 1725 PCMachineState *pcms = PC_MACHINE(obj); 1726 1727 return pcms->default_bus_bypass_iommu; 1728 } 1729 1730 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1731 Error **errp) 1732 { 1733 PCMachineState *pcms = PC_MACHINE(obj); 1734 1735 pcms->default_bus_bypass_iommu = value; 1736 } 1737 1738 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1739 void *opaque, Error **errp) 1740 { 1741 PCMachineState *pcms = PC_MACHINE(obj); 1742 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1743 1744 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1745 } 1746 1747 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1748 void *opaque, Error **errp) 1749 { 1750 PCMachineState *pcms = PC_MACHINE(obj); 1751 1752 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1753 } 1754 1755 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1756 const char *name, void *opaque, 1757 Error **errp) 1758 { 1759 PCMachineState *pcms = PC_MACHINE(obj); 1760 uint64_t value = pcms->max_ram_below_4g; 1761 1762 visit_type_size(v, name, &value, errp); 1763 } 1764 1765 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1766 const char *name, void *opaque, 1767 Error **errp) 1768 { 1769 PCMachineState *pcms = PC_MACHINE(obj); 1770 uint64_t value; 1771 1772 if (!visit_type_size(v, name, &value, errp)) { 1773 return; 1774 } 1775 if (value > 4 * GiB) { 1776 error_setg(errp, 1777 "Machine option 'max-ram-below-4g=%"PRIu64 1778 "' expects size less than or equal to 4G", value); 1779 return; 1780 } 1781 1782 if (value < 1 * MiB) { 1783 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1784 "BIOS may not work with less than 1MiB", value); 1785 } 1786 1787 pcms->max_ram_below_4g = value; 1788 } 1789 1790 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1791 const char *name, void *opaque, 1792 Error **errp) 1793 { 1794 PCMachineState *pcms = PC_MACHINE(obj); 1795 uint64_t value = pcms->max_fw_size; 1796 1797 visit_type_size(v, name, &value, errp); 1798 } 1799 1800 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1801 const char *name, void *opaque, 1802 Error **errp) 1803 { 1804 PCMachineState *pcms = PC_MACHINE(obj); 1805 uint64_t value; 1806 1807 if (!visit_type_size(v, name, &value, errp)) { 1808 return; 1809 } 1810 1811 /* 1812 * We don't have a theoretically justifiable exact lower bound on the base 1813 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1814 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1815 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1816 * size. 1817 */ 1818 if (value > 16 * MiB) { 1819 error_setg(errp, 1820 "User specified max allowed firmware size %" PRIu64 " is " 1821 "greater than 16MiB. If combined firwmare size exceeds " 1822 "16MiB the system may not boot, or experience intermittent" 1823 "stability issues.", 1824 value); 1825 return; 1826 } 1827 1828 pcms->max_fw_size = value; 1829 } 1830 1831 1832 static void pc_machine_initfn(Object *obj) 1833 { 1834 PCMachineState *pcms = PC_MACHINE(obj); 1835 1836 #ifdef CONFIG_VMPORT 1837 pcms->vmport = ON_OFF_AUTO_AUTO; 1838 #else 1839 pcms->vmport = ON_OFF_AUTO_OFF; 1840 #endif /* CONFIG_VMPORT */ 1841 pcms->max_ram_below_4g = 0; /* use default */ 1842 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1843 1844 /* acpi build is enabled by default if machine supports it */ 1845 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1846 pcms->smbus_enabled = true; 1847 pcms->sata_enabled = true; 1848 pcms->i8042_enabled = true; 1849 pcms->max_fw_size = 8 * MiB; 1850 #ifdef CONFIG_HPET 1851 pcms->hpet_enabled = true; 1852 #endif 1853 pcms->default_bus_bypass_iommu = false; 1854 1855 pc_system_flash_create(pcms); 1856 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1857 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1858 OBJECT(pcms->pcspk), "audiodev"); 1859 cxl_machine_init(obj, &pcms->cxl_devices_state); 1860 } 1861 1862 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) 1863 { 1864 #ifdef CONFIG_XEN_EMU 1865 if (xen_mode == XEN_EMULATE) { 1866 xen_overlay_create(); 1867 xen_evtchn_create(); 1868 xen_gnttab_create(); 1869 xen_xenstore_create(); 1870 } 1871 #endif 1872 return 0; 1873 } 1874 1875 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1876 { 1877 CPUState *cs; 1878 X86CPU *cpu; 1879 1880 qemu_devices_reset(reason); 1881 1882 /* Reset APIC after devices have been reset to cancel 1883 * any changes that qemu_devices_reset() might have done. 1884 */ 1885 CPU_FOREACH(cs) { 1886 cpu = X86_CPU(cs); 1887 1888 x86_cpu_after_reset(cpu); 1889 } 1890 } 1891 1892 static void pc_machine_wakeup(MachineState *machine) 1893 { 1894 cpu_synchronize_all_states(); 1895 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1896 cpu_synchronize_all_post_reset(); 1897 } 1898 1899 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1900 { 1901 X86IOMMUState *iommu = x86_iommu_get_default(); 1902 IntelIOMMUState *intel_iommu; 1903 1904 if (iommu && 1905 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1906 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1907 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1908 if (!intel_iommu->caching_mode) { 1909 error_setg(errp, "Device assignment is not allowed without " 1910 "enabling caching-mode=on for Intel IOMMU."); 1911 return false; 1912 } 1913 } 1914 1915 return true; 1916 } 1917 1918 static void pc_machine_class_init(ObjectClass *oc, void *data) 1919 { 1920 MachineClass *mc = MACHINE_CLASS(oc); 1921 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1922 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1923 1924 pcmc->pci_enabled = true; 1925 pcmc->has_acpi_build = true; 1926 pcmc->rsdp_in_ram = true; 1927 pcmc->smbios_defaults = true; 1928 pcmc->smbios_uuid_encoded = true; 1929 pcmc->gigabyte_align = true; 1930 pcmc->has_reserved_memory = true; 1931 pcmc->kvmclock_enabled = true; 1932 pcmc->enforce_aligned_dimm = true; 1933 pcmc->enforce_amd_1tb_hole = true; 1934 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1935 * to be used at the moment, 32K should be enough for a while. */ 1936 pcmc->acpi_data_size = 0x20000 + 0x8000; 1937 pcmc->pvh_enabled = true; 1938 pcmc->kvmclock_create_always = true; 1939 assert(!mc->get_hotplug_handler); 1940 mc->get_hotplug_handler = pc_get_hotplug_handler; 1941 mc->hotplug_allowed = pc_hotplug_allowed; 1942 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1943 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1944 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1945 mc->auto_enable_numa_with_memhp = true; 1946 mc->auto_enable_numa_with_memdev = true; 1947 mc->has_hotpluggable_cpus = true; 1948 mc->default_boot_order = "cad"; 1949 mc->block_default_type = IF_IDE; 1950 mc->max_cpus = 255; 1951 mc->reset = pc_machine_reset; 1952 mc->wakeup = pc_machine_wakeup; 1953 hc->pre_plug = pc_machine_device_pre_plug_cb; 1954 hc->plug = pc_machine_device_plug_cb; 1955 hc->unplug_request = pc_machine_device_unplug_request_cb; 1956 hc->unplug = pc_machine_device_unplug_cb; 1957 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1958 mc->nvdimm_supported = true; 1959 mc->smp_props.dies_supported = true; 1960 mc->default_ram_id = "pc.ram"; 1961 1962 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1963 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1964 NULL, NULL); 1965 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1966 "Maximum ram below the 4G boundary (32bit boundary)"); 1967 1968 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1969 pc_machine_get_device_memory_region_size, NULL, 1970 NULL, NULL); 1971 1972 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1973 pc_machine_get_vmport, pc_machine_set_vmport, 1974 NULL, NULL); 1975 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1976 "Enable vmport (pc & q35)"); 1977 1978 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1979 pc_machine_get_smbus, pc_machine_set_smbus); 1980 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1981 "Enable/disable system management bus"); 1982 1983 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1984 pc_machine_get_sata, pc_machine_set_sata); 1985 object_class_property_set_description(oc, PC_MACHINE_SATA, 1986 "Enable/disable Serial ATA bus"); 1987 1988 object_class_property_add_bool(oc, "hpet", 1989 pc_machine_get_hpet, pc_machine_set_hpet); 1990 object_class_property_set_description(oc, "hpet", 1991 "Enable/disable high precision event timer emulation"); 1992 1993 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1994 pc_machine_get_i8042, pc_machine_set_i8042); 1995 1996 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1997 pc_machine_get_default_bus_bypass_iommu, 1998 pc_machine_set_default_bus_bypass_iommu); 1999 2000 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 2001 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 2002 NULL, NULL); 2003 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 2004 "Maximum combined firmware size"); 2005 2006 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 2007 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 2008 NULL, NULL); 2009 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 2010 "SMBIOS Entry Point type [32, 64]"); 2011 } 2012 2013 static const TypeInfo pc_machine_info = { 2014 .name = TYPE_PC_MACHINE, 2015 .parent = TYPE_X86_MACHINE, 2016 .abstract = true, 2017 .instance_size = sizeof(PCMachineState), 2018 .instance_init = pc_machine_initfn, 2019 .class_size = sizeof(PCMachineClass), 2020 .class_init = pc_machine_class_init, 2021 .interfaces = (InterfaceInfo[]) { 2022 { TYPE_HOTPLUG_HANDLER }, 2023 { } 2024 }, 2025 }; 2026 2027 static void pc_machine_register_types(void) 2028 { 2029 type_register_static(&pc_machine_info); 2030 } 2031 2032 type_init(pc_machine_register_types) 2033