1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/block-backend.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/acpi/cpu_hotplug.h" 57 #include "hw/cpu/icc_bus.h" 58 #include "hw/boards.h" 59 #include "hw/pci/pci_host.h" 60 #include "acpi-build.h" 61 #include "hw/mem/pc-dimm.h" 62 #include "trace.h" 63 #include "qapi/visitor.h" 64 #include "qapi-visit.h" 65 66 /* debug PC/ISA interrupts */ 67 //#define DEBUG_IRQ 68 69 #ifdef DEBUG_IRQ 70 #define DPRINTF(fmt, ...) \ 71 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 72 #else 73 #define DPRINTF(fmt, ...) 74 #endif 75 76 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 77 * (128K) and other BIOS datastructures (less than 4K reported to be used at 78 * the moment, 32K should be enough for a while). */ 79 static unsigned acpi_data_size = 0x20000 + 0x8000; 80 void pc_set_legacy_acpi_data_size(void) 81 { 82 acpi_data_size = 0x10000; 83 } 84 85 #define BIOS_CFG_IOPORT 0x510 86 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 87 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 88 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 89 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 90 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 91 92 #define E820_NR_ENTRIES 16 93 94 struct e820_entry { 95 uint64_t address; 96 uint64_t length; 97 uint32_t type; 98 } QEMU_PACKED __attribute((__aligned__(4))); 99 100 struct e820_table { 101 uint32_t count; 102 struct e820_entry entry[E820_NR_ENTRIES]; 103 } QEMU_PACKED __attribute((__aligned__(4))); 104 105 static struct e820_table e820_reserve; 106 static struct e820_entry *e820_table; 107 static unsigned e820_entries; 108 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 109 110 void gsi_handler(void *opaque, int n, int level) 111 { 112 GSIState *s = opaque; 113 114 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 115 if (n < ISA_NUM_IRQS) { 116 qemu_set_irq(s->i8259_irq[n], level); 117 } 118 qemu_set_irq(s->ioapic_irq[n], level); 119 } 120 121 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 122 unsigned size) 123 { 124 } 125 126 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 127 { 128 return 0xffffffffffffffffULL; 129 } 130 131 /* MSDOS compatibility mode FPU exception support */ 132 static qemu_irq ferr_irq; 133 134 void pc_register_ferr_irq(qemu_irq irq) 135 { 136 ferr_irq = irq; 137 } 138 139 /* XXX: add IGNNE support */ 140 void cpu_set_ferr(CPUX86State *s) 141 { 142 qemu_irq_raise(ferr_irq); 143 } 144 145 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 146 unsigned size) 147 { 148 qemu_irq_lower(ferr_irq); 149 } 150 151 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 152 { 153 return 0xffffffffffffffffULL; 154 } 155 156 /* TSC handling */ 157 uint64_t cpu_get_tsc(CPUX86State *env) 158 { 159 return cpu_get_ticks(); 160 } 161 162 /* SMM support */ 163 164 static cpu_set_smm_t smm_set; 165 static void *smm_arg; 166 167 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 168 { 169 assert(smm_set == NULL); 170 assert(smm_arg == NULL); 171 smm_set = callback; 172 smm_arg = arg; 173 } 174 175 void cpu_smm_update(CPUX86State *env) 176 { 177 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 178 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 179 } 180 } 181 182 183 /* IRQ handling */ 184 int cpu_get_pic_interrupt(CPUX86State *env) 185 { 186 X86CPU *cpu = x86_env_get_cpu(env); 187 int intno; 188 189 intno = apic_get_interrupt(cpu->apic_state); 190 if (intno >= 0) { 191 return intno; 192 } 193 /* read the irq from the PIC */ 194 if (!apic_accept_pic_intr(cpu->apic_state)) { 195 return -1; 196 } 197 198 intno = pic_read_irq(isa_pic); 199 return intno; 200 } 201 202 static void pic_irq_request(void *opaque, int irq, int level) 203 { 204 CPUState *cs = first_cpu; 205 X86CPU *cpu = X86_CPU(cs); 206 207 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 208 if (cpu->apic_state) { 209 CPU_FOREACH(cs) { 210 cpu = X86_CPU(cs); 211 if (apic_accept_pic_intr(cpu->apic_state)) { 212 apic_deliver_pic_intr(cpu->apic_state, level); 213 } 214 } 215 } else { 216 if (level) { 217 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 218 } else { 219 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 220 } 221 } 222 } 223 224 /* PC cmos mappings */ 225 226 #define REG_EQUIPMENT_BYTE 0x14 227 228 static int cmos_get_fd_drive_type(FDriveType fd0) 229 { 230 int val; 231 232 switch (fd0) { 233 case FDRIVE_DRV_144: 234 /* 1.44 Mb 3"5 drive */ 235 val = 4; 236 break; 237 case FDRIVE_DRV_288: 238 /* 2.88 Mb 3"5 drive */ 239 val = 5; 240 break; 241 case FDRIVE_DRV_120: 242 /* 1.2 Mb 5"5 drive */ 243 val = 2; 244 break; 245 case FDRIVE_DRV_NONE: 246 default: 247 val = 0; 248 break; 249 } 250 return val; 251 } 252 253 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 254 int16_t cylinders, int8_t heads, int8_t sectors) 255 { 256 rtc_set_memory(s, type_ofs, 47); 257 rtc_set_memory(s, info_ofs, cylinders); 258 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 259 rtc_set_memory(s, info_ofs + 2, heads); 260 rtc_set_memory(s, info_ofs + 3, 0xff); 261 rtc_set_memory(s, info_ofs + 4, 0xff); 262 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 263 rtc_set_memory(s, info_ofs + 6, cylinders); 264 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 265 rtc_set_memory(s, info_ofs + 8, sectors); 266 } 267 268 /* convert boot_device letter to something recognizable by the bios */ 269 static int boot_device2nibble(char boot_device) 270 { 271 switch(boot_device) { 272 case 'a': 273 case 'b': 274 return 0x01; /* floppy boot */ 275 case 'c': 276 return 0x02; /* hard drive boot */ 277 case 'd': 278 return 0x03; /* CD-ROM boot */ 279 case 'n': 280 return 0x04; /* Network boot */ 281 } 282 return 0; 283 } 284 285 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 286 { 287 #define PC_MAX_BOOT_DEVICES 3 288 int nbds, bds[3] = { 0, }; 289 int i; 290 291 nbds = strlen(boot_device); 292 if (nbds > PC_MAX_BOOT_DEVICES) { 293 error_setg(errp, "Too many boot devices for PC"); 294 return; 295 } 296 for (i = 0; i < nbds; i++) { 297 bds[i] = boot_device2nibble(boot_device[i]); 298 if (bds[i] == 0) { 299 error_setg(errp, "Invalid boot device for PC: '%c'", 300 boot_device[i]); 301 return; 302 } 303 } 304 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 305 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 306 } 307 308 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 309 { 310 set_boot_dev(opaque, boot_device, errp); 311 } 312 313 typedef struct pc_cmos_init_late_arg { 314 ISADevice *rtc_state; 315 BusState *idebus[2]; 316 } pc_cmos_init_late_arg; 317 318 static void pc_cmos_init_late(void *opaque) 319 { 320 pc_cmos_init_late_arg *arg = opaque; 321 ISADevice *s = arg->rtc_state; 322 int16_t cylinders; 323 int8_t heads, sectors; 324 int val; 325 int i, trans; 326 327 val = 0; 328 if (ide_get_geometry(arg->idebus[0], 0, 329 &cylinders, &heads, §ors) >= 0) { 330 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 331 val |= 0xf0; 332 } 333 if (ide_get_geometry(arg->idebus[0], 1, 334 &cylinders, &heads, §ors) >= 0) { 335 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 336 val |= 0x0f; 337 } 338 rtc_set_memory(s, 0x12, val); 339 340 val = 0; 341 for (i = 0; i < 4; i++) { 342 /* NOTE: ide_get_geometry() returns the physical 343 geometry. It is always such that: 1 <= sects <= 63, 1 344 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 345 geometry can be different if a translation is done. */ 346 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 347 &cylinders, &heads, §ors) >= 0) { 348 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 349 assert((trans & ~3) == 0); 350 val |= trans << (i * 2); 351 } 352 } 353 rtc_set_memory(s, 0x39, val); 354 355 qemu_unregister_reset(pc_cmos_init_late, opaque); 356 } 357 358 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 359 const char *boot_device, MachineState *machine, 360 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 361 ISADevice *s) 362 { 363 int val, nb, i; 364 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 365 static pc_cmos_init_late_arg arg; 366 PCMachineState *pc_machine = PC_MACHINE(machine); 367 Error *local_err = NULL; 368 369 /* various important CMOS locations needed by PC/Bochs bios */ 370 371 /* memory size */ 372 /* base memory (first MiB) */ 373 val = MIN(ram_size / 1024, 640); 374 rtc_set_memory(s, 0x15, val); 375 rtc_set_memory(s, 0x16, val >> 8); 376 /* extended memory (next 64MiB) */ 377 if (ram_size > 1024 * 1024) { 378 val = (ram_size - 1024 * 1024) / 1024; 379 } else { 380 val = 0; 381 } 382 if (val > 65535) 383 val = 65535; 384 rtc_set_memory(s, 0x17, val); 385 rtc_set_memory(s, 0x18, val >> 8); 386 rtc_set_memory(s, 0x30, val); 387 rtc_set_memory(s, 0x31, val >> 8); 388 /* memory between 16MiB and 4GiB */ 389 if (ram_size > 16 * 1024 * 1024) { 390 val = (ram_size - 16 * 1024 * 1024) / 65536; 391 } else { 392 val = 0; 393 } 394 if (val > 65535) 395 val = 65535; 396 rtc_set_memory(s, 0x34, val); 397 rtc_set_memory(s, 0x35, val >> 8); 398 /* memory above 4GiB */ 399 val = above_4g_mem_size / 65536; 400 rtc_set_memory(s, 0x5b, val); 401 rtc_set_memory(s, 0x5c, val >> 8); 402 rtc_set_memory(s, 0x5d, val >> 16); 403 404 /* set the number of CPU */ 405 rtc_set_memory(s, 0x5f, smp_cpus - 1); 406 407 object_property_add_link(OBJECT(machine), "rtc_state", 408 TYPE_ISA_DEVICE, 409 (Object **)&pc_machine->rtc, 410 object_property_allow_set_link, 411 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 412 object_property_set_link(OBJECT(machine), OBJECT(s), 413 "rtc_state", &error_abort); 414 415 set_boot_dev(s, boot_device, &local_err); 416 if (local_err) { 417 error_report("%s", error_get_pretty(local_err)); 418 exit(1); 419 } 420 421 /* floppy type */ 422 if (floppy) { 423 for (i = 0; i < 2; i++) { 424 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 425 } 426 } 427 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 428 cmos_get_fd_drive_type(fd_type[1]); 429 rtc_set_memory(s, 0x10, val); 430 431 val = 0; 432 nb = 0; 433 if (fd_type[0] < FDRIVE_DRV_NONE) { 434 nb++; 435 } 436 if (fd_type[1] < FDRIVE_DRV_NONE) { 437 nb++; 438 } 439 switch (nb) { 440 case 0: 441 break; 442 case 1: 443 val |= 0x01; /* 1 drive, ready for boot */ 444 break; 445 case 2: 446 val |= 0x41; /* 2 drives, ready for boot */ 447 break; 448 } 449 val |= 0x02; /* FPU is there */ 450 val |= 0x04; /* PS/2 mouse installed */ 451 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 452 453 /* hard drives */ 454 arg.rtc_state = s; 455 arg.idebus[0] = idebus0; 456 arg.idebus[1] = idebus1; 457 qemu_register_reset(pc_cmos_init_late, &arg); 458 } 459 460 #define TYPE_PORT92 "port92" 461 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 462 463 /* port 92 stuff: could be split off */ 464 typedef struct Port92State { 465 ISADevice parent_obj; 466 467 MemoryRegion io; 468 uint8_t outport; 469 qemu_irq *a20_out; 470 } Port92State; 471 472 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 473 unsigned size) 474 { 475 Port92State *s = opaque; 476 int oldval = s->outport; 477 478 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 479 s->outport = val; 480 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 481 if ((val & 1) && !(oldval & 1)) { 482 qemu_system_reset_request(); 483 } 484 } 485 486 static uint64_t port92_read(void *opaque, hwaddr addr, 487 unsigned size) 488 { 489 Port92State *s = opaque; 490 uint32_t ret; 491 492 ret = s->outport; 493 DPRINTF("port92: read 0x%02x\n", ret); 494 return ret; 495 } 496 497 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 498 { 499 Port92State *s = PORT92(dev); 500 501 s->a20_out = a20_out; 502 } 503 504 static const VMStateDescription vmstate_port92_isa = { 505 .name = "port92", 506 .version_id = 1, 507 .minimum_version_id = 1, 508 .fields = (VMStateField[]) { 509 VMSTATE_UINT8(outport, Port92State), 510 VMSTATE_END_OF_LIST() 511 } 512 }; 513 514 static void port92_reset(DeviceState *d) 515 { 516 Port92State *s = PORT92(d); 517 518 s->outport &= ~1; 519 } 520 521 static const MemoryRegionOps port92_ops = { 522 .read = port92_read, 523 .write = port92_write, 524 .impl = { 525 .min_access_size = 1, 526 .max_access_size = 1, 527 }, 528 .endianness = DEVICE_LITTLE_ENDIAN, 529 }; 530 531 static void port92_initfn(Object *obj) 532 { 533 Port92State *s = PORT92(obj); 534 535 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 536 537 s->outport = 0; 538 } 539 540 static void port92_realizefn(DeviceState *dev, Error **errp) 541 { 542 ISADevice *isadev = ISA_DEVICE(dev); 543 Port92State *s = PORT92(dev); 544 545 isa_register_ioport(isadev, &s->io, 0x92); 546 } 547 548 static void port92_class_initfn(ObjectClass *klass, void *data) 549 { 550 DeviceClass *dc = DEVICE_CLASS(klass); 551 552 dc->realize = port92_realizefn; 553 dc->reset = port92_reset; 554 dc->vmsd = &vmstate_port92_isa; 555 /* 556 * Reason: unlike ordinary ISA devices, this one needs additional 557 * wiring: its A20 output line needs to be wired up by 558 * port92_init(). 559 */ 560 dc->cannot_instantiate_with_device_add_yet = true; 561 } 562 563 static const TypeInfo port92_info = { 564 .name = TYPE_PORT92, 565 .parent = TYPE_ISA_DEVICE, 566 .instance_size = sizeof(Port92State), 567 .instance_init = port92_initfn, 568 .class_init = port92_class_initfn, 569 }; 570 571 static void port92_register_types(void) 572 { 573 type_register_static(&port92_info); 574 } 575 576 type_init(port92_register_types) 577 578 static void handle_a20_line_change(void *opaque, int irq, int level) 579 { 580 X86CPU *cpu = opaque; 581 582 /* XXX: send to all CPUs ? */ 583 /* XXX: add logic to handle multiple A20 line sources */ 584 x86_cpu_set_a20(cpu, level); 585 } 586 587 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 588 { 589 int index = le32_to_cpu(e820_reserve.count); 590 struct e820_entry *entry; 591 592 if (type != E820_RAM) { 593 /* old FW_CFG_E820_TABLE entry -- reservations only */ 594 if (index >= E820_NR_ENTRIES) { 595 return -EBUSY; 596 } 597 entry = &e820_reserve.entry[index++]; 598 599 entry->address = cpu_to_le64(address); 600 entry->length = cpu_to_le64(length); 601 entry->type = cpu_to_le32(type); 602 603 e820_reserve.count = cpu_to_le32(index); 604 } 605 606 /* new "etc/e820" file -- include ram too */ 607 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 608 e820_table[e820_entries].address = cpu_to_le64(address); 609 e820_table[e820_entries].length = cpu_to_le64(length); 610 e820_table[e820_entries].type = cpu_to_le32(type); 611 e820_entries++; 612 613 return e820_entries; 614 } 615 616 int e820_get_num_entries(void) 617 { 618 return e820_entries; 619 } 620 621 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 622 { 623 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 624 *address = le64_to_cpu(e820_table[idx].address); 625 *length = le64_to_cpu(e820_table[idx].length); 626 return true; 627 } 628 return false; 629 } 630 631 /* Calculates the limit to CPU APIC ID values 632 * 633 * This function returns the limit for the APIC ID value, so that all 634 * CPU APIC IDs are < pc_apic_id_limit(). 635 * 636 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 637 */ 638 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 639 { 640 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 641 } 642 643 static FWCfgState *bochs_bios_init(void) 644 { 645 FWCfgState *fw_cfg; 646 uint8_t *smbios_tables, *smbios_anchor; 647 size_t smbios_tables_len, smbios_anchor_len; 648 uint64_t *numa_fw_cfg; 649 int i, j; 650 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 651 652 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 653 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 654 * 655 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 656 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 657 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 658 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 659 * may see". 660 * 661 * So, this means we must not use max_cpus, here, but the maximum possible 662 * APIC ID value, plus one. 663 * 664 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 665 * the APIC ID, not the "CPU index" 666 */ 667 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 668 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 669 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 670 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 671 acpi_tables, acpi_tables_len); 672 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 673 674 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 675 if (smbios_tables) { 676 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 677 smbios_tables, smbios_tables_len); 678 } 679 680 smbios_get_tables(&smbios_tables, &smbios_tables_len, 681 &smbios_anchor, &smbios_anchor_len); 682 if (smbios_anchor) { 683 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 684 smbios_tables, smbios_tables_len); 685 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 686 smbios_anchor, smbios_anchor_len); 687 } 688 689 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 690 &e820_reserve, sizeof(e820_reserve)); 691 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 692 sizeof(struct e820_entry) * e820_entries); 693 694 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 695 /* allocate memory for the NUMA channel: one (64bit) word for the number 696 * of nodes, one word for each VCPU->node and one word for each node to 697 * hold the amount of memory. 698 */ 699 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 700 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 701 for (i = 0; i < max_cpus; i++) { 702 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 703 assert(apic_id < apic_id_limit); 704 for (j = 0; j < nb_numa_nodes; j++) { 705 if (test_bit(i, numa_info[j].node_cpu)) { 706 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 707 break; 708 } 709 } 710 } 711 for (i = 0; i < nb_numa_nodes; i++) { 712 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 713 } 714 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 715 (1 + apic_id_limit + nb_numa_nodes) * 716 sizeof(*numa_fw_cfg)); 717 718 return fw_cfg; 719 } 720 721 static long get_file_size(FILE *f) 722 { 723 long where, size; 724 725 /* XXX: on Unix systems, using fstat() probably makes more sense */ 726 727 where = ftell(f); 728 fseek(f, 0, SEEK_END); 729 size = ftell(f); 730 fseek(f, where, SEEK_SET); 731 732 return size; 733 } 734 735 static void load_linux(FWCfgState *fw_cfg, 736 const char *kernel_filename, 737 const char *initrd_filename, 738 const char *kernel_cmdline, 739 hwaddr max_ram_size) 740 { 741 uint16_t protocol; 742 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 743 uint32_t initrd_max; 744 uint8_t header[8192], *setup, *kernel, *initrd_data; 745 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 746 FILE *f; 747 char *vmode; 748 749 /* Align to 16 bytes as a paranoia measure */ 750 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 751 752 /* load the kernel header */ 753 f = fopen(kernel_filename, "rb"); 754 if (!f || !(kernel_size = get_file_size(f)) || 755 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 756 MIN(ARRAY_SIZE(header), kernel_size)) { 757 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 758 kernel_filename, strerror(errno)); 759 exit(1); 760 } 761 762 /* kernel protocol version */ 763 #if 0 764 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 765 #endif 766 if (ldl_p(header+0x202) == 0x53726448) { 767 protocol = lduw_p(header+0x206); 768 } else { 769 /* This looks like a multiboot kernel. If it is, let's stop 770 treating it like a Linux kernel. */ 771 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 772 kernel_cmdline, kernel_size, header)) { 773 return; 774 } 775 protocol = 0; 776 } 777 778 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 779 /* Low kernel */ 780 real_addr = 0x90000; 781 cmdline_addr = 0x9a000 - cmdline_size; 782 prot_addr = 0x10000; 783 } else if (protocol < 0x202) { 784 /* High but ancient kernel */ 785 real_addr = 0x90000; 786 cmdline_addr = 0x9a000 - cmdline_size; 787 prot_addr = 0x100000; 788 } else { 789 /* High and recent kernel */ 790 real_addr = 0x10000; 791 cmdline_addr = 0x20000; 792 prot_addr = 0x100000; 793 } 794 795 #if 0 796 fprintf(stderr, 797 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 798 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 799 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 800 real_addr, 801 cmdline_addr, 802 prot_addr); 803 #endif 804 805 /* highest address for loading the initrd */ 806 if (protocol >= 0x203) { 807 initrd_max = ldl_p(header+0x22c); 808 } else { 809 initrd_max = 0x37ffffff; 810 } 811 812 if (initrd_max >= max_ram_size - acpi_data_size) { 813 initrd_max = max_ram_size - acpi_data_size - 1; 814 } 815 816 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 817 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 818 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 819 820 if (protocol >= 0x202) { 821 stl_p(header+0x228, cmdline_addr); 822 } else { 823 stw_p(header+0x20, 0xA33F); 824 stw_p(header+0x22, cmdline_addr-real_addr); 825 } 826 827 /* handle vga= parameter */ 828 vmode = strstr(kernel_cmdline, "vga="); 829 if (vmode) { 830 unsigned int video_mode; 831 /* skip "vga=" */ 832 vmode += 4; 833 if (!strncmp(vmode, "normal", 6)) { 834 video_mode = 0xffff; 835 } else if (!strncmp(vmode, "ext", 3)) { 836 video_mode = 0xfffe; 837 } else if (!strncmp(vmode, "ask", 3)) { 838 video_mode = 0xfffd; 839 } else { 840 video_mode = strtol(vmode, NULL, 0); 841 } 842 stw_p(header+0x1fa, video_mode); 843 } 844 845 /* loader type */ 846 /* High nybble = B reserved for QEMU; low nybble is revision number. 847 If this code is substantially changed, you may want to consider 848 incrementing the revision. */ 849 if (protocol >= 0x200) { 850 header[0x210] = 0xB0; 851 } 852 /* heap */ 853 if (protocol >= 0x201) { 854 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 855 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 856 } 857 858 /* load initrd */ 859 if (initrd_filename) { 860 if (protocol < 0x200) { 861 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 862 exit(1); 863 } 864 865 initrd_size = get_image_size(initrd_filename); 866 if (initrd_size < 0) { 867 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 868 initrd_filename, strerror(errno)); 869 exit(1); 870 } 871 872 initrd_addr = (initrd_max-initrd_size) & ~4095; 873 874 initrd_data = g_malloc(initrd_size); 875 load_image(initrd_filename, initrd_data); 876 877 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 878 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 879 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 880 881 stl_p(header+0x218, initrd_addr); 882 stl_p(header+0x21c, initrd_size); 883 } 884 885 /* load kernel and setup */ 886 setup_size = header[0x1f1]; 887 if (setup_size == 0) { 888 setup_size = 4; 889 } 890 setup_size = (setup_size+1)*512; 891 kernel_size -= setup_size; 892 893 setup = g_malloc(setup_size); 894 kernel = g_malloc(kernel_size); 895 fseek(f, 0, SEEK_SET); 896 if (fread(setup, 1, setup_size, f) != setup_size) { 897 fprintf(stderr, "fread() failed\n"); 898 exit(1); 899 } 900 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 901 fprintf(stderr, "fread() failed\n"); 902 exit(1); 903 } 904 fclose(f); 905 memcpy(setup, header, MIN(sizeof(header), setup_size)); 906 907 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 908 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 909 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 910 911 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 912 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 913 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 914 915 option_rom[nb_option_roms].name = "linuxboot.bin"; 916 option_rom[nb_option_roms].bootindex = 0; 917 nb_option_roms++; 918 } 919 920 #define NE2000_NB_MAX 6 921 922 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 923 0x280, 0x380 }; 924 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 925 926 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 927 { 928 static int nb_ne2k = 0; 929 930 if (nb_ne2k == NE2000_NB_MAX) 931 return; 932 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 933 ne2000_irq[nb_ne2k], nd); 934 nb_ne2k++; 935 } 936 937 DeviceState *cpu_get_current_apic(void) 938 { 939 if (current_cpu) { 940 X86CPU *cpu = X86_CPU(current_cpu); 941 return cpu->apic_state; 942 } else { 943 return NULL; 944 } 945 } 946 947 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 948 { 949 X86CPU *cpu = opaque; 950 951 if (level) { 952 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 953 } 954 } 955 956 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 957 DeviceState *icc_bridge, Error **errp) 958 { 959 X86CPU *cpu; 960 Error *local_err = NULL; 961 962 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 963 if (local_err != NULL) { 964 error_propagate(errp, local_err); 965 return NULL; 966 } 967 968 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 969 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 970 971 if (local_err) { 972 error_propagate(errp, local_err); 973 object_unref(OBJECT(cpu)); 974 cpu = NULL; 975 } 976 return cpu; 977 } 978 979 static const char *current_cpu_model; 980 981 void pc_hot_add_cpu(const int64_t id, Error **errp) 982 { 983 DeviceState *icc_bridge; 984 int64_t apic_id = x86_cpu_apic_id_from_index(id); 985 986 if (id < 0) { 987 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 988 return; 989 } 990 991 if (cpu_exists(apic_id)) { 992 error_setg(errp, "Unable to add CPU: %" PRIi64 993 ", it already exists", id); 994 return; 995 } 996 997 if (id >= max_cpus) { 998 error_setg(errp, "Unable to add CPU: %" PRIi64 999 ", max allowed: %d", id, max_cpus - 1); 1000 return; 1001 } 1002 1003 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1004 error_setg(errp, "Unable to add CPU: %" PRIi64 1005 ", resulting APIC ID (%" PRIi64 ") is too large", 1006 id, apic_id); 1007 return; 1008 } 1009 1010 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1011 TYPE_ICC_BRIDGE, NULL)); 1012 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1013 } 1014 1015 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1016 { 1017 int i; 1018 X86CPU *cpu = NULL; 1019 Error *error = NULL; 1020 unsigned long apic_id_limit; 1021 1022 /* init CPUs */ 1023 if (cpu_model == NULL) { 1024 #ifdef TARGET_X86_64 1025 cpu_model = "qemu64"; 1026 #else 1027 cpu_model = "qemu32"; 1028 #endif 1029 } 1030 current_cpu_model = cpu_model; 1031 1032 apic_id_limit = pc_apic_id_limit(max_cpus); 1033 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1034 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1035 apic_id_limit - 1); 1036 exit(1); 1037 } 1038 1039 for (i = 0; i < smp_cpus; i++) { 1040 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1041 icc_bridge, &error); 1042 if (error) { 1043 error_report("%s", error_get_pretty(error)); 1044 error_free(error); 1045 exit(1); 1046 } 1047 } 1048 1049 /* map APIC MMIO area if CPU has APIC */ 1050 if (cpu && cpu->apic_state) { 1051 /* XXX: what if the base changes? */ 1052 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1053 APIC_DEFAULT_ADDRESS, 0x1000); 1054 } 1055 1056 /* tell smbios about cpuid version and features */ 1057 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1058 } 1059 1060 /* pci-info ROM file. Little endian format */ 1061 typedef struct PcRomPciInfo { 1062 uint64_t w32_min; 1063 uint64_t w32_max; 1064 uint64_t w64_min; 1065 uint64_t w64_max; 1066 } PcRomPciInfo; 1067 1068 typedef struct PcGuestInfoState { 1069 PcGuestInfo info; 1070 Notifier machine_done; 1071 } PcGuestInfoState; 1072 1073 static 1074 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1075 { 1076 PcGuestInfoState *guest_info_state = container_of(notifier, 1077 PcGuestInfoState, 1078 machine_done); 1079 acpi_setup(&guest_info_state->info); 1080 } 1081 1082 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1083 ram_addr_t above_4g_mem_size) 1084 { 1085 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1086 PcGuestInfo *guest_info = &guest_info_state->info; 1087 int i, j; 1088 1089 guest_info->ram_size_below_4g = below_4g_mem_size; 1090 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1091 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1092 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1093 guest_info->numa_nodes = nb_numa_nodes; 1094 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1095 sizeof *guest_info->node_mem); 1096 for (i = 0; i < nb_numa_nodes; i++) { 1097 guest_info->node_mem[i] = numa_info[i].node_mem; 1098 } 1099 1100 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1101 sizeof *guest_info->node_cpu); 1102 1103 for (i = 0; i < max_cpus; i++) { 1104 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1105 assert(apic_id < guest_info->apic_id_limit); 1106 for (j = 0; j < nb_numa_nodes; j++) { 1107 if (test_bit(i, numa_info[j].node_cpu)) { 1108 guest_info->node_cpu[apic_id] = j; 1109 break; 1110 } 1111 } 1112 } 1113 1114 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1115 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1116 return guest_info; 1117 } 1118 1119 /* setup pci memory address space mapping into system address space */ 1120 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1121 MemoryRegion *pci_address_space) 1122 { 1123 /* Set to lower priority than RAM */ 1124 memory_region_add_subregion_overlap(system_memory, 0x0, 1125 pci_address_space, -1); 1126 } 1127 1128 void pc_acpi_init(const char *default_dsdt) 1129 { 1130 char *filename; 1131 1132 if (acpi_tables != NULL) { 1133 /* manually set via -acpitable, leave it alone */ 1134 return; 1135 } 1136 1137 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1138 if (filename == NULL) { 1139 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1140 } else { 1141 char *arg; 1142 QemuOpts *opts; 1143 Error *err = NULL; 1144 1145 arg = g_strdup_printf("file=%s", filename); 1146 1147 /* creates a deep copy of "arg" */ 1148 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1149 g_assert(opts != NULL); 1150 1151 acpi_table_add_builtin(opts, &err); 1152 if (err) { 1153 error_report("WARNING: failed to load %s: %s", filename, 1154 error_get_pretty(err)); 1155 error_free(err); 1156 } 1157 g_free(arg); 1158 g_free(filename); 1159 } 1160 } 1161 1162 FWCfgState *xen_load_linux(const char *kernel_filename, 1163 const char *kernel_cmdline, 1164 const char *initrd_filename, 1165 ram_addr_t below_4g_mem_size, 1166 PcGuestInfo *guest_info) 1167 { 1168 int i; 1169 FWCfgState *fw_cfg; 1170 1171 assert(kernel_filename != NULL); 1172 1173 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1174 rom_set_fw(fw_cfg); 1175 1176 load_linux(fw_cfg, kernel_filename, initrd_filename, 1177 kernel_cmdline, below_4g_mem_size); 1178 for (i = 0; i < nb_option_roms; i++) { 1179 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1180 !strcmp(option_rom[i].name, "multiboot.bin")); 1181 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1182 } 1183 guest_info->fw_cfg = fw_cfg; 1184 return fw_cfg; 1185 } 1186 1187 FWCfgState *pc_memory_init(MachineState *machine, 1188 MemoryRegion *system_memory, 1189 ram_addr_t below_4g_mem_size, 1190 ram_addr_t above_4g_mem_size, 1191 MemoryRegion *rom_memory, 1192 MemoryRegion **ram_memory, 1193 PcGuestInfo *guest_info) 1194 { 1195 int linux_boot, i; 1196 MemoryRegion *ram, *option_rom_mr; 1197 MemoryRegion *ram_below_4g, *ram_above_4g; 1198 FWCfgState *fw_cfg; 1199 PCMachineState *pcms = PC_MACHINE(machine); 1200 1201 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1202 1203 linux_boot = (machine->kernel_filename != NULL); 1204 1205 /* Allocate RAM. We allocate it as a single memory region and use 1206 * aliases to address portions of it, mostly for backwards compatibility 1207 * with older qemus that used qemu_ram_alloc(). 1208 */ 1209 ram = g_malloc(sizeof(*ram)); 1210 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1211 machine->ram_size); 1212 *ram_memory = ram; 1213 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1214 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1215 0, below_4g_mem_size); 1216 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1217 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1218 if (above_4g_mem_size > 0) { 1219 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1220 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1221 below_4g_mem_size, above_4g_mem_size); 1222 memory_region_add_subregion(system_memory, 0x100000000ULL, 1223 ram_above_4g); 1224 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1225 } 1226 1227 if (!guest_info->has_reserved_memory && 1228 (machine->ram_slots || 1229 (machine->maxram_size > machine->ram_size))) { 1230 MachineClass *mc = MACHINE_GET_CLASS(machine); 1231 1232 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1233 mc->name); 1234 exit(EXIT_FAILURE); 1235 } 1236 1237 /* initialize hotplug memory address space */ 1238 if (guest_info->has_reserved_memory && 1239 (machine->ram_size < machine->maxram_size)) { 1240 ram_addr_t hotplug_mem_size = 1241 machine->maxram_size - machine->ram_size; 1242 1243 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1244 error_report("unsupported amount of memory slots: %"PRIu64, 1245 machine->ram_slots); 1246 exit(EXIT_FAILURE); 1247 } 1248 1249 pcms->hotplug_memory_base = 1250 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1251 1252 if (pcms->enforce_aligned_dimm) { 1253 /* size hotplug region assuming 1G page max alignment per slot */ 1254 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1255 } 1256 1257 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1258 hotplug_mem_size) { 1259 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1260 machine->maxram_size); 1261 exit(EXIT_FAILURE); 1262 } 1263 1264 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1265 "hotplug-memory", hotplug_mem_size); 1266 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1267 &pcms->hotplug_memory); 1268 } 1269 1270 /* Initialize PC system firmware */ 1271 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1272 1273 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1274 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1275 &error_abort); 1276 vmstate_register_ram_global(option_rom_mr); 1277 memory_region_add_subregion_overlap(rom_memory, 1278 PC_ROM_MIN_VGA, 1279 option_rom_mr, 1280 1); 1281 1282 fw_cfg = bochs_bios_init(); 1283 rom_set_fw(fw_cfg); 1284 1285 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1286 uint64_t *val = g_malloc(sizeof(*val)); 1287 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1288 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1289 } 1290 1291 if (linux_boot) { 1292 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1293 machine->kernel_cmdline, below_4g_mem_size); 1294 } 1295 1296 for (i = 0; i < nb_option_roms; i++) { 1297 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1298 } 1299 guest_info->fw_cfg = fw_cfg; 1300 return fw_cfg; 1301 } 1302 1303 qemu_irq *pc_allocate_cpu_irq(void) 1304 { 1305 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1306 } 1307 1308 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1309 { 1310 DeviceState *dev = NULL; 1311 1312 if (pci_bus) { 1313 PCIDevice *pcidev = pci_vga_init(pci_bus); 1314 dev = pcidev ? &pcidev->qdev : NULL; 1315 } else if (isa_bus) { 1316 ISADevice *isadev = isa_vga_init(isa_bus); 1317 dev = isadev ? DEVICE(isadev) : NULL; 1318 } 1319 return dev; 1320 } 1321 1322 static void cpu_request_exit(void *opaque, int irq, int level) 1323 { 1324 CPUState *cpu = current_cpu; 1325 1326 if (cpu && level) { 1327 cpu_exit(cpu); 1328 } 1329 } 1330 1331 static const MemoryRegionOps ioport80_io_ops = { 1332 .write = ioport80_write, 1333 .read = ioport80_read, 1334 .endianness = DEVICE_NATIVE_ENDIAN, 1335 .impl = { 1336 .min_access_size = 1, 1337 .max_access_size = 1, 1338 }, 1339 }; 1340 1341 static const MemoryRegionOps ioportF0_io_ops = { 1342 .write = ioportF0_write, 1343 .read = ioportF0_read, 1344 .endianness = DEVICE_NATIVE_ENDIAN, 1345 .impl = { 1346 .min_access_size = 1, 1347 .max_access_size = 1, 1348 }, 1349 }; 1350 1351 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1352 ISADevice **rtc_state, 1353 ISADevice **floppy, 1354 bool no_vmport, 1355 uint32 hpet_irqs) 1356 { 1357 int i; 1358 DriveInfo *fd[MAX_FD]; 1359 DeviceState *hpet = NULL; 1360 int pit_isa_irq = 0; 1361 qemu_irq pit_alt_irq = NULL; 1362 qemu_irq rtc_irq = NULL; 1363 qemu_irq *a20_line; 1364 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1365 qemu_irq *cpu_exit_irq; 1366 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1367 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1368 1369 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1370 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1371 1372 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1373 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1374 1375 /* 1376 * Check if an HPET shall be created. 1377 * 1378 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1379 * when the HPET wants to take over. Thus we have to disable the latter. 1380 */ 1381 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1382 /* In order to set property, here not using sysbus_try_create_simple */ 1383 hpet = qdev_try_create(NULL, TYPE_HPET); 1384 if (hpet) { 1385 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1386 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1387 * IRQ8 and IRQ2. 1388 */ 1389 uint8_t compat = object_property_get_int(OBJECT(hpet), 1390 HPET_INTCAP, NULL); 1391 if (!compat) { 1392 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1393 } 1394 qdev_init_nofail(hpet); 1395 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1396 1397 for (i = 0; i < GSI_NUM_PINS; i++) { 1398 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1399 } 1400 pit_isa_irq = -1; 1401 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1402 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1403 } 1404 } 1405 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1406 1407 qemu_register_boot_set(pc_boot_set, *rtc_state); 1408 1409 if (!xen_enabled()) { 1410 if (kvm_irqchip_in_kernel()) { 1411 pit = kvm_pit_init(isa_bus, 0x40); 1412 } else { 1413 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1414 } 1415 if (hpet) { 1416 /* connect PIT to output control line of the HPET */ 1417 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1418 } 1419 pcspk_init(isa_bus, pit); 1420 } 1421 1422 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1423 if (serial_hds[i]) { 1424 serial_isa_init(isa_bus, i, serial_hds[i]); 1425 } 1426 } 1427 1428 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1429 if (parallel_hds[i]) { 1430 parallel_init(isa_bus, i, parallel_hds[i]); 1431 } 1432 } 1433 1434 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1435 i8042 = isa_create_simple(isa_bus, "i8042"); 1436 i8042_setup_a20_line(i8042, &a20_line[0]); 1437 if (!no_vmport) { 1438 vmport_init(isa_bus); 1439 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1440 } else { 1441 vmmouse = NULL; 1442 } 1443 if (vmmouse) { 1444 DeviceState *dev = DEVICE(vmmouse); 1445 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1446 qdev_init_nofail(dev); 1447 } 1448 port92 = isa_create_simple(isa_bus, "port92"); 1449 port92_init(port92, &a20_line[1]); 1450 1451 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1452 DMA_init(0, cpu_exit_irq); 1453 1454 for(i = 0; i < MAX_FD; i++) { 1455 fd[i] = drive_get(IF_FLOPPY, 0, i); 1456 } 1457 *floppy = fdctrl_init_isa(isa_bus, fd); 1458 } 1459 1460 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1461 { 1462 int i; 1463 1464 for (i = 0; i < nb_nics; i++) { 1465 NICInfo *nd = &nd_table[i]; 1466 1467 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1468 pc_init_ne2k_isa(isa_bus, nd); 1469 } else { 1470 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1471 } 1472 } 1473 } 1474 1475 void pc_pci_device_init(PCIBus *pci_bus) 1476 { 1477 int max_bus; 1478 int bus; 1479 1480 max_bus = drive_get_max_bus(IF_SCSI); 1481 for (bus = 0; bus <= max_bus; bus++) { 1482 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1483 } 1484 } 1485 1486 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1487 { 1488 DeviceState *dev; 1489 SysBusDevice *d; 1490 unsigned int i; 1491 1492 if (kvm_irqchip_in_kernel()) { 1493 dev = qdev_create(NULL, "kvm-ioapic"); 1494 } else { 1495 dev = qdev_create(NULL, "ioapic"); 1496 } 1497 if (parent_name) { 1498 object_property_add_child(object_resolve_path(parent_name, NULL), 1499 "ioapic", OBJECT(dev), NULL); 1500 } 1501 qdev_init_nofail(dev); 1502 d = SYS_BUS_DEVICE(dev); 1503 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1504 1505 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1506 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1507 } 1508 } 1509 1510 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1511 { 1512 MachineClass *mc = MACHINE_CLASS(oc); 1513 QEMUMachine *qm = data; 1514 1515 mc->family = qm->family; 1516 mc->name = qm->name; 1517 mc->alias = qm->alias; 1518 mc->desc = qm->desc; 1519 mc->init = qm->init; 1520 mc->reset = qm->reset; 1521 mc->hot_add_cpu = qm->hot_add_cpu; 1522 mc->kvm_type = qm->kvm_type; 1523 mc->block_default_type = qm->block_default_type; 1524 mc->units_per_default_bus = qm->units_per_default_bus; 1525 mc->max_cpus = qm->max_cpus; 1526 mc->no_serial = qm->no_serial; 1527 mc->no_parallel = qm->no_parallel; 1528 mc->use_virtcon = qm->use_virtcon; 1529 mc->use_sclp = qm->use_sclp; 1530 mc->no_floppy = qm->no_floppy; 1531 mc->no_cdrom = qm->no_cdrom; 1532 mc->no_sdcard = qm->no_sdcard; 1533 mc->is_default = qm->is_default; 1534 mc->default_machine_opts = qm->default_machine_opts; 1535 mc->default_boot_order = qm->default_boot_order; 1536 mc->default_display = qm->default_display; 1537 mc->compat_props = qm->compat_props; 1538 mc->hw_version = qm->hw_version; 1539 } 1540 1541 void qemu_register_pc_machine(QEMUMachine *m) 1542 { 1543 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1544 TypeInfo ti = { 1545 .name = name, 1546 .parent = TYPE_PC_MACHINE, 1547 .class_init = pc_generic_machine_class_init, 1548 .class_data = (void *)m, 1549 }; 1550 1551 type_register(&ti); 1552 g_free(name); 1553 } 1554 1555 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1556 DeviceState *dev, Error **errp) 1557 { 1558 int slot; 1559 HotplugHandlerClass *hhc; 1560 Error *local_err = NULL; 1561 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1562 MachineState *machine = MACHINE(hotplug_dev); 1563 PCDIMMDevice *dimm = PC_DIMM(dev); 1564 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1565 MemoryRegion *mr = ddc->get_memory_region(dimm); 1566 uint64_t existing_dimms_capacity = 0; 1567 uint64_t align = TARGET_PAGE_SIZE; 1568 uint64_t addr; 1569 1570 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 1571 if (local_err) { 1572 goto out; 1573 } 1574 1575 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1576 align = memory_region_get_alignment(mr); 1577 } 1578 1579 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1580 memory_region_size(&pcms->hotplug_memory), 1581 !addr ? NULL : &addr, align, 1582 memory_region_size(mr), &local_err); 1583 if (local_err) { 1584 goto out; 1585 } 1586 1587 existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); 1588 if (local_err) { 1589 goto out; 1590 } 1591 1592 if (existing_dimms_capacity + memory_region_size(mr) > 1593 machine->maxram_size - machine->ram_size) { 1594 error_setg(&local_err, "not enough space, currently 0x%" PRIx64 1595 " in use of total hot pluggable 0x" RAM_ADDR_FMT, 1596 existing_dimms_capacity, 1597 machine->maxram_size - machine->ram_size); 1598 goto out; 1599 } 1600 1601 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1602 if (local_err) { 1603 goto out; 1604 } 1605 trace_mhp_pc_dimm_assigned_address(addr); 1606 1607 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1608 if (local_err) { 1609 goto out; 1610 } 1611 1612 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1613 machine->ram_slots, &local_err); 1614 if (local_err) { 1615 goto out; 1616 } 1617 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1618 if (local_err) { 1619 goto out; 1620 } 1621 trace_mhp_pc_dimm_assigned_slot(slot); 1622 1623 if (!pcms->acpi_dev) { 1624 error_setg(&local_err, 1625 "memory hotplug is not enabled: missing acpi device"); 1626 goto out; 1627 } 1628 1629 if (kvm_enabled() && !kvm_has_free_slot(machine)) { 1630 error_setg(&local_err, "hypervisor has no free memory slots left"); 1631 goto out; 1632 } 1633 1634 memory_region_add_subregion(&pcms->hotplug_memory, 1635 addr - pcms->hotplug_memory_base, mr); 1636 vmstate_register_ram(mr, dev); 1637 1638 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1639 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1640 out: 1641 error_propagate(errp, local_err); 1642 } 1643 1644 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1645 DeviceState *dev, Error **errp) 1646 { 1647 HotplugHandlerClass *hhc; 1648 Error *local_err = NULL; 1649 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1650 1651 if (!dev->hotplugged) { 1652 goto out; 1653 } 1654 1655 if (!pcms->acpi_dev) { 1656 error_setg(&local_err, 1657 "cpu hotplug is not enabled: missing acpi device"); 1658 goto out; 1659 } 1660 1661 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1662 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1663 if (local_err) { 1664 goto out; 1665 } 1666 1667 /* increment the number of CPUs */ 1668 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1669 out: 1670 error_propagate(errp, local_err); 1671 } 1672 1673 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1674 DeviceState *dev, Error **errp) 1675 { 1676 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1677 pc_dimm_plug(hotplug_dev, dev, errp); 1678 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1679 pc_cpu_plug(hotplug_dev, dev, errp); 1680 } 1681 } 1682 1683 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1684 DeviceState *dev) 1685 { 1686 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1687 1688 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1689 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1690 return HOTPLUG_HANDLER(machine); 1691 } 1692 1693 return pcmc->get_hotplug_handler ? 1694 pcmc->get_hotplug_handler(machine, dev) : NULL; 1695 } 1696 1697 static void 1698 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1699 const char *name, Error **errp) 1700 { 1701 PCMachineState *pcms = PC_MACHINE(obj); 1702 int64_t value = memory_region_size(&pcms->hotplug_memory); 1703 1704 visit_type_int(v, &value, name, errp); 1705 } 1706 1707 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1708 void *opaque, const char *name, 1709 Error **errp) 1710 { 1711 PCMachineState *pcms = PC_MACHINE(obj); 1712 uint64_t value = pcms->max_ram_below_4g; 1713 1714 visit_type_size(v, &value, name, errp); 1715 } 1716 1717 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1718 void *opaque, const char *name, 1719 Error **errp) 1720 { 1721 PCMachineState *pcms = PC_MACHINE(obj); 1722 Error *error = NULL; 1723 uint64_t value; 1724 1725 visit_type_size(v, &value, name, &error); 1726 if (error) { 1727 error_propagate(errp, error); 1728 return; 1729 } 1730 if (value > (1ULL << 32)) { 1731 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1732 "Machine option 'max-ram-below-4g=%"PRIu64 1733 "' expects size less than or equal to 4G", value); 1734 error_propagate(errp, error); 1735 return; 1736 } 1737 1738 if (value < (1ULL << 20)) { 1739 error_report("Warning: small max_ram_below_4g(%"PRIu64 1740 ") less than 1M. BIOS may not work..", 1741 value); 1742 } 1743 1744 pcms->max_ram_below_4g = value; 1745 } 1746 1747 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1748 const char *name, Error **errp) 1749 { 1750 PCMachineState *pcms = PC_MACHINE(obj); 1751 OnOffAuto vmport = pcms->vmport; 1752 1753 visit_type_OnOffAuto(v, &vmport, name, errp); 1754 } 1755 1756 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1757 const char *name, Error **errp) 1758 { 1759 PCMachineState *pcms = PC_MACHINE(obj); 1760 1761 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1762 } 1763 1764 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1765 { 1766 PCMachineState *pcms = PC_MACHINE(obj); 1767 1768 return pcms->enforce_aligned_dimm; 1769 } 1770 1771 static void pc_machine_initfn(Object *obj) 1772 { 1773 PCMachineState *pcms = PC_MACHINE(obj); 1774 1775 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1776 pc_machine_get_hotplug_memory_region_size, 1777 NULL, NULL, NULL, NULL); 1778 1779 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1780 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1781 pc_machine_get_max_ram_below_4g, 1782 pc_machine_set_max_ram_below_4g, 1783 NULL, NULL, NULL); 1784 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1785 "Maximum ram below the 4G boundary (32bit boundary)", 1786 NULL); 1787 1788 pcms->vmport = ON_OFF_AUTO_AUTO; 1789 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1790 pc_machine_get_vmport, 1791 pc_machine_set_vmport, 1792 NULL, NULL, NULL); 1793 object_property_set_description(obj, PC_MACHINE_VMPORT, 1794 "Enable vmport (pc & q35)", 1795 NULL); 1796 1797 pcms->enforce_aligned_dimm = true; 1798 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1799 pc_machine_get_aligned_dimm, 1800 NULL, NULL); 1801 } 1802 1803 static void pc_machine_class_init(ObjectClass *oc, void *data) 1804 { 1805 MachineClass *mc = MACHINE_CLASS(oc); 1806 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1807 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1808 1809 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1810 mc->get_hotplug_handler = pc_get_hotpug_handler; 1811 hc->plug = pc_machine_device_plug_cb; 1812 } 1813 1814 static const TypeInfo pc_machine_info = { 1815 .name = TYPE_PC_MACHINE, 1816 .parent = TYPE_MACHINE, 1817 .abstract = true, 1818 .instance_size = sizeof(PCMachineState), 1819 .instance_init = pc_machine_initfn, 1820 .class_size = sizeof(PCMachineClass), 1821 .class_init = pc_machine_class_init, 1822 .interfaces = (InterfaceInfo[]) { 1823 { TYPE_HOTPLUG_HANDLER }, 1824 { } 1825 }, 1826 }; 1827 1828 static void pc_machine_register_types(void) 1829 { 1830 type_register_static(&pc_machine_info); 1831 } 1832 1833 type_init(pc_machine_register_types) 1834