1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_9_0[] = { 82 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 83 { "sev-guest", "legacy-vm-type", "true" }, 84 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 85 }; 86 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 87 88 GlobalProperty pc_compat_8_2[] = {}; 89 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 90 91 GlobalProperty pc_compat_8_1[] = {}; 92 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 93 94 GlobalProperty pc_compat_8_0[] = { 95 { "virtio-mem", "unplugged-inaccessible", "auto" }, 96 }; 97 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 98 99 GlobalProperty pc_compat_7_2[] = { 100 { "ICH9-LPC", "noreboot", "true" }, 101 }; 102 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 103 104 GlobalProperty pc_compat_7_1[] = {}; 105 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 106 107 GlobalProperty pc_compat_7_0[] = {}; 108 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 109 110 GlobalProperty pc_compat_6_2[] = { 111 { "virtio-mem", "unplugged-inaccessible", "off" }, 112 }; 113 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 114 115 GlobalProperty pc_compat_6_1[] = { 116 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 117 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 118 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 119 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 120 }; 121 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 122 123 GlobalProperty pc_compat_6_0[] = { 124 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 125 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 126 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 127 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 128 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 129 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 130 }; 131 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 132 133 GlobalProperty pc_compat_5_2[] = { 134 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 135 }; 136 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 137 138 GlobalProperty pc_compat_5_1[] = { 139 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 140 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 141 }; 142 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 143 144 GlobalProperty pc_compat_5_0[] = { 145 }; 146 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 147 148 GlobalProperty pc_compat_4_2[] = { 149 { "mch", "smbase-smram", "off" }, 150 }; 151 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 152 153 GlobalProperty pc_compat_4_1[] = {}; 154 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 155 156 GlobalProperty pc_compat_4_0[] = {}; 157 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 158 159 GlobalProperty pc_compat_3_1[] = { 160 { "intel-iommu", "dma-drain", "off" }, 161 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 162 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 163 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 166 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 167 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 168 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 169 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 170 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 171 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 172 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 173 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 174 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 175 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 176 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 177 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 178 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 179 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 180 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 181 }; 182 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 183 184 GlobalProperty pc_compat_3_0[] = { 185 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 186 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 187 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 188 }; 189 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 190 191 GlobalProperty pc_compat_2_12[] = { 192 { TYPE_X86_CPU, "legacy-cache", "on" }, 193 { TYPE_X86_CPU, "topoext", "off" }, 194 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 195 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 196 }; 197 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 198 199 GlobalProperty pc_compat_2_11[] = { 200 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 201 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 202 }; 203 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 204 205 GlobalProperty pc_compat_2_10[] = { 206 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 207 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 208 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 209 }; 210 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 211 212 GlobalProperty pc_compat_2_9[] = { 213 { "mch", "extended-tseg-mbytes", "0" }, 214 }; 215 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 216 217 GlobalProperty pc_compat_2_8[] = { 218 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 219 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 220 { "ICH9-LPC", "x-smi-broadcast", "off" }, 221 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 222 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 223 }; 224 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 225 226 GlobalProperty pc_compat_2_7[] = { 227 { TYPE_X86_CPU, "l3-cache", "off" }, 228 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 229 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 230 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 231 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 232 { "isa-pcspk", "migrate", "off" }, 233 }; 234 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 235 236 GlobalProperty pc_compat_2_6[] = { 237 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 238 { "vmxnet3", "romfile", "" }, 239 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 240 { "apic-common", "legacy-instance-id", "on", } 241 }; 242 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 243 244 GlobalProperty pc_compat_2_5[] = {}; 245 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 246 247 GlobalProperty pc_compat_2_4[] = { 248 PC_CPU_MODEL_IDS("2.4.0") 249 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 250 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 251 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 252 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 253 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 254 { TYPE_X86_CPU, "check", "off" }, 255 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 256 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 257 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 258 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 259 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 260 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 261 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 262 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 263 }; 264 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 265 266 GlobalProperty pc_compat_2_3[] = { 267 PC_CPU_MODEL_IDS("2.3.0") 268 { TYPE_X86_CPU, "arat", "off" }, 269 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 270 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 271 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 272 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 273 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 274 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 275 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 276 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 281 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 282 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 283 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 284 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 285 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 286 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 287 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 288 }; 289 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 290 291 GlobalProperty pc_compat_2_2[] = { 292 PC_CPU_MODEL_IDS("2.2.0") 293 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 301 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 302 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 303 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 307 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 308 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 309 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 310 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 311 }; 312 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 313 314 GlobalProperty pc_compat_2_1[] = { 315 PC_CPU_MODEL_IDS("2.1.0") 316 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 317 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 318 }; 319 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 320 321 GlobalProperty pc_compat_2_0[] = { 322 PC_CPU_MODEL_IDS("2.0.0") 323 { "virtio-scsi-pci", "any_layout", "off" }, 324 { "PIIX4_PM", "memory-hotplug-support", "off" }, 325 { "apic", "version", "0x11" }, 326 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 327 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 328 { "pci-serial", "prog_if", "0" }, 329 { "pci-serial-2x", "prog_if", "0" }, 330 { "pci-serial-4x", "prog_if", "0" }, 331 { "virtio-net-pci", "guest_announce", "off" }, 332 { "ICH9-LPC", "memory-hotplug-support", "off" }, 333 }; 334 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 335 336 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 337 { 338 GSIState *s; 339 340 s = g_new0(GSIState, 1); 341 if (kvm_ioapic_in_kernel()) { 342 kvm_pc_setup_irq_routing(pci_enabled); 343 } 344 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 345 346 return s; 347 } 348 349 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 350 unsigned size) 351 { 352 } 353 354 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 355 { 356 return 0xffffffffffffffffULL; 357 } 358 359 /* MS-DOS compatibility mode FPU exception support */ 360 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 361 unsigned size) 362 { 363 if (tcg_enabled()) { 364 cpu_set_ignne(); 365 } 366 } 367 368 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 369 { 370 return 0xffffffffffffffffULL; 371 } 372 373 /* PC cmos mappings */ 374 375 #define REG_EQUIPMENT_BYTE 0x14 376 377 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 378 int16_t cylinders, int8_t heads, int8_t sectors) 379 { 380 mc146818rtc_set_cmos_data(s, type_ofs, 47); 381 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 382 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 383 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 384 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 385 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 386 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 387 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 388 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 389 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 390 } 391 392 /* convert boot_device letter to something recognizable by the bios */ 393 static int boot_device2nibble(char boot_device) 394 { 395 switch(boot_device) { 396 case 'a': 397 case 'b': 398 return 0x01; /* floppy boot */ 399 case 'c': 400 return 0x02; /* hard drive boot */ 401 case 'd': 402 return 0x03; /* CD-ROM boot */ 403 case 'n': 404 return 0x04; /* Network boot */ 405 } 406 return 0; 407 } 408 409 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 410 const char *boot_device, Error **errp) 411 { 412 #define PC_MAX_BOOT_DEVICES 3 413 int nbds, bds[3] = { 0, }; 414 int i; 415 416 nbds = strlen(boot_device); 417 if (nbds > PC_MAX_BOOT_DEVICES) { 418 error_setg(errp, "Too many boot devices for PC"); 419 return; 420 } 421 for (i = 0; i < nbds; i++) { 422 bds[i] = boot_device2nibble(boot_device[i]); 423 if (bds[i] == 0) { 424 error_setg(errp, "Invalid boot device for PC: '%c'", 425 boot_device[i]); 426 return; 427 } 428 } 429 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 430 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 431 } 432 433 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 434 { 435 PCMachineState *pcms = opaque; 436 X86MachineState *x86ms = X86_MACHINE(pcms); 437 438 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 439 } 440 441 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 442 { 443 int val, nb, i; 444 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 445 FLOPPY_DRIVE_TYPE_NONE }; 446 447 /* floppy type */ 448 if (floppy) { 449 for (i = 0; i < 2; i++) { 450 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 451 } 452 } 453 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 454 cmos_get_fd_drive_type(fd_type[1]); 455 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 456 457 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 458 nb = 0; 459 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 460 nb++; 461 } 462 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 463 nb++; 464 } 465 switch (nb) { 466 case 0: 467 break; 468 case 1: 469 val |= 0x01; /* 1 drive, ready for boot */ 470 break; 471 case 2: 472 val |= 0x41; /* 2 drives, ready for boot */ 473 break; 474 } 475 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 476 } 477 478 typedef struct check_fdc_state { 479 ISADevice *floppy; 480 bool multiple; 481 } CheckFdcState; 482 483 static int check_fdc(Object *obj, void *opaque) 484 { 485 CheckFdcState *state = opaque; 486 Object *fdc; 487 uint32_t iobase; 488 Error *local_err = NULL; 489 490 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 491 if (!fdc) { 492 return 0; 493 } 494 495 iobase = object_property_get_uint(obj, "iobase", &local_err); 496 if (local_err || iobase != 0x3f0) { 497 error_free(local_err); 498 return 0; 499 } 500 501 if (state->floppy) { 502 state->multiple = true; 503 } else { 504 state->floppy = ISA_DEVICE(obj); 505 } 506 return 0; 507 } 508 509 static const char * const fdc_container_path[] = { 510 "/unattached", "/peripheral", "/peripheral-anon" 511 }; 512 513 /* 514 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 515 * and ACPI objects. 516 */ 517 static ISADevice *pc_find_fdc0(void) 518 { 519 int i; 520 Object *container; 521 CheckFdcState state = { 0 }; 522 523 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 524 container = container_get(qdev_get_machine(), fdc_container_path[i]); 525 object_child_foreach(container, check_fdc, &state); 526 } 527 528 if (state.multiple) { 529 warn_report("multiple floppy disk controllers with " 530 "iobase=0x3f0 have been found"); 531 error_printf("the one being picked for CMOS setup might not reflect " 532 "your intent"); 533 } 534 535 return state.floppy; 536 } 537 538 static void pc_cmos_init_late(PCMachineState *pcms) 539 { 540 X86MachineState *x86ms = X86_MACHINE(pcms); 541 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 542 int16_t cylinders; 543 int8_t heads, sectors; 544 int val; 545 int i, trans; 546 547 val = 0; 548 if (pcms->idebus[0] && 549 ide_get_geometry(pcms->idebus[0], 0, 550 &cylinders, &heads, §ors) >= 0) { 551 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 552 val |= 0xf0; 553 } 554 if (pcms->idebus[0] && 555 ide_get_geometry(pcms->idebus[0], 1, 556 &cylinders, &heads, §ors) >= 0) { 557 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 558 val |= 0x0f; 559 } 560 mc146818rtc_set_cmos_data(s, 0x12, val); 561 562 val = 0; 563 for (i = 0; i < 4; i++) { 564 /* NOTE: ide_get_geometry() returns the physical 565 geometry. It is always such that: 1 <= sects <= 63, 1 566 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 567 geometry can be different if a translation is done. */ 568 BusState *idebus = pcms->idebus[i / 2]; 569 if (idebus && 570 ide_get_geometry(idebus, i % 2, 571 &cylinders, &heads, §ors) >= 0) { 572 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 573 assert((trans & ~3) == 0); 574 val |= trans << (i * 2); 575 } 576 } 577 mc146818rtc_set_cmos_data(s, 0x39, val); 578 579 pc_cmos_init_floppy(s, pc_find_fdc0()); 580 581 /* various important CMOS locations needed by PC/Bochs bios */ 582 583 /* memory size */ 584 /* base memory (first MiB) */ 585 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 586 mc146818rtc_set_cmos_data(s, 0x15, val); 587 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 588 /* extended memory (next 64MiB) */ 589 if (x86ms->below_4g_mem_size > 1 * MiB) { 590 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 591 } else { 592 val = 0; 593 } 594 if (val > 65535) 595 val = 65535; 596 mc146818rtc_set_cmos_data(s, 0x17, val); 597 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 598 mc146818rtc_set_cmos_data(s, 0x30, val); 599 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 600 /* memory between 16MiB and 4GiB */ 601 if (x86ms->below_4g_mem_size > 16 * MiB) { 602 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 603 } else { 604 val = 0; 605 } 606 if (val > 65535) 607 val = 65535; 608 mc146818rtc_set_cmos_data(s, 0x34, val); 609 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 610 /* memory above 4GiB */ 611 val = x86ms->above_4g_mem_size / 65536; 612 mc146818rtc_set_cmos_data(s, 0x5b, val); 613 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 614 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 615 616 val = 0; 617 val |= 0x02; /* FPU is there */ 618 val |= 0x04; /* PS/2 mouse installed */ 619 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 620 } 621 622 static void handle_a20_line_change(void *opaque, int irq, int level) 623 { 624 X86CPU *cpu = opaque; 625 626 /* XXX: send to all CPUs ? */ 627 /* XXX: add logic to handle multiple A20 line sources */ 628 x86_cpu_set_a20(cpu, level); 629 } 630 631 #define NE2000_NB_MAX 6 632 633 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 634 0x280, 0x380 }; 635 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 636 637 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 638 { 639 static int nb_ne2k = 0; 640 641 if (nb_ne2k == NE2000_NB_MAX) { 642 error_setg(errp, 643 "maximum number of ISA NE2000 devices exceeded"); 644 return false; 645 } 646 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 647 ne2000_irq[nb_ne2k], nd); 648 nb_ne2k++; 649 return true; 650 } 651 652 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 653 { 654 X86CPU *cpu = opaque; 655 656 if (level) { 657 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 658 } 659 } 660 661 static 662 void pc_machine_done(Notifier *notifier, void *data) 663 { 664 PCMachineState *pcms = container_of(notifier, 665 PCMachineState, machine_done); 666 X86MachineState *x86ms = X86_MACHINE(pcms); 667 668 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 669 &error_fatal); 670 671 if (pcms->cxl_devices_state.is_enabled) { 672 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 673 } 674 675 /* set the number of CPUs */ 676 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 677 678 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 679 680 acpi_setup(); 681 if (x86ms->fw_cfg) { 682 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 683 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 684 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 685 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 686 } 687 688 pc_cmos_init_late(pcms); 689 } 690 691 /* setup pci memory address space mapping into system address space */ 692 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 693 MemoryRegion *pci_address_space) 694 { 695 /* Set to lower priority than RAM */ 696 memory_region_add_subregion_overlap(system_memory, 0x0, 697 pci_address_space, -1); 698 } 699 700 void xen_load_linux(PCMachineState *pcms) 701 { 702 int i; 703 FWCfgState *fw_cfg; 704 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 705 X86MachineState *x86ms = X86_MACHINE(pcms); 706 707 assert(MACHINE(pcms)->kernel_filename != NULL); 708 709 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 710 &address_space_memory); 711 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 712 rom_set_fw(fw_cfg); 713 714 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 715 pcmc->pvh_enabled); 716 for (i = 0; i < nb_option_roms; i++) { 717 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 718 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 719 !strcmp(option_rom[i].name, "pvh.bin") || 720 !strcmp(option_rom[i].name, "multiboot.bin") || 721 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 722 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 723 } 724 x86ms->fw_cfg = fw_cfg; 725 } 726 727 #define PC_ROM_MIN_VGA 0xc0000 728 #define PC_ROM_MIN_OPTION 0xc8000 729 #define PC_ROM_MAX 0xe0000 730 #define PC_ROM_ALIGN 0x800 731 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 732 733 static hwaddr pc_above_4g_end(PCMachineState *pcms) 734 { 735 X86MachineState *x86ms = X86_MACHINE(pcms); 736 737 if (pcms->sgx_epc.size != 0) { 738 return sgx_epc_above_4g_end(&pcms->sgx_epc); 739 } 740 741 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 742 } 743 744 static void pc_get_device_memory_range(PCMachineState *pcms, 745 hwaddr *base, 746 ram_addr_t *device_mem_size) 747 { 748 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 749 MachineState *machine = MACHINE(pcms); 750 ram_addr_t size; 751 hwaddr addr; 752 753 size = machine->maxram_size - machine->ram_size; 754 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 755 756 if (pcmc->enforce_aligned_dimm) { 757 /* size device region assuming 1G page max alignment per slot */ 758 size += (1 * GiB) * machine->ram_slots; 759 } 760 761 *base = addr; 762 *device_mem_size = size; 763 } 764 765 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 766 { 767 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 768 MachineState *ms = MACHINE(pcms); 769 hwaddr cxl_base; 770 ram_addr_t size; 771 772 if (pcmc->has_reserved_memory && 773 (ms->ram_size < ms->maxram_size)) { 774 pc_get_device_memory_range(pcms, &cxl_base, &size); 775 cxl_base += size; 776 } else { 777 cxl_base = pc_above_4g_end(pcms); 778 } 779 780 return cxl_base; 781 } 782 783 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 784 { 785 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 786 787 if (pcms->cxl_devices_state.fixed_windows) { 788 GList *it; 789 790 start = ROUND_UP(start, 256 * MiB); 791 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 792 CXLFixedWindow *fw = it->data; 793 start += fw->size; 794 } 795 } 796 797 return start; 798 } 799 800 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 801 { 802 X86CPU *cpu = X86_CPU(first_cpu); 803 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 804 MachineState *ms = MACHINE(pcms); 805 806 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 807 /* 64-bit systems */ 808 return pc_pci_hole64_start() + pci_hole64_size - 1; 809 } 810 811 /* 32-bit systems */ 812 if (pcmc->broken_32bit_mem_addr_check) { 813 /* old value for compatibility reasons */ 814 return ((hwaddr)1 << cpu->phys_bits) - 1; 815 } 816 817 /* 818 * 32-bit systems don't have hole64 but they might have a region for 819 * memory devices. Even if additional hotplugged memory devices might 820 * not be usable by most guest OSes, we need to still consider them for 821 * calculating the highest possible GPA so that we can properly report 822 * if someone configures them on a CPU that cannot possibly address them. 823 */ 824 if (pcmc->has_reserved_memory && 825 (ms->ram_size < ms->maxram_size)) { 826 hwaddr devmem_start; 827 ram_addr_t devmem_size; 828 829 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 830 devmem_start += devmem_size; 831 return devmem_start - 1; 832 } 833 834 /* configuration without any memory hotplug */ 835 return pc_above_4g_end(pcms) - 1; 836 } 837 838 /* 839 * AMD systems with an IOMMU have an additional hole close to the 840 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 841 * on kernel version, VFIO may or may not let you DMA map those ranges. 842 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 843 * with certain memory sizes. It's also wrong to use those IOVA ranges 844 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 845 * The ranges reserved for Hyper-Transport are: 846 * 847 * FD_0000_0000h - FF_FFFF_FFFFh 848 * 849 * The ranges represent the following: 850 * 851 * Base Address Top Address Use 852 * 853 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 854 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 855 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 856 * FD_F910_0000h FD_F91F_FFFFh System Management 857 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 858 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 859 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 860 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 861 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 862 * FE_2000_0000h FF_FFFF_FFFFh Reserved 863 * 864 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 865 * Table 3: Special Address Controls (GPA) for more information. 866 */ 867 #define AMD_HT_START 0xfd00000000UL 868 #define AMD_HT_END 0xffffffffffUL 869 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 870 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 871 872 void pc_memory_init(PCMachineState *pcms, 873 MemoryRegion *system_memory, 874 MemoryRegion *rom_memory, 875 uint64_t pci_hole64_size) 876 { 877 int linux_boot, i; 878 MemoryRegion *option_rom_mr; 879 MemoryRegion *ram_below_4g, *ram_above_4g; 880 FWCfgState *fw_cfg; 881 MachineState *machine = MACHINE(pcms); 882 MachineClass *mc = MACHINE_GET_CLASS(machine); 883 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 884 X86MachineState *x86ms = X86_MACHINE(pcms); 885 hwaddr maxphysaddr, maxusedaddr; 886 hwaddr cxl_base, cxl_resv_end = 0; 887 X86CPU *cpu = X86_CPU(first_cpu); 888 889 assert(machine->ram_size == x86ms->below_4g_mem_size + 890 x86ms->above_4g_mem_size); 891 892 linux_boot = (machine->kernel_filename != NULL); 893 894 /* 895 * The HyperTransport range close to the 1T boundary is unique to AMD 896 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 897 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 898 * older machine types (<= 7.0) for compatibility purposes. 899 */ 900 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 901 /* Bail out if max possible address does not cross HT range */ 902 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 903 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 904 } 905 906 /* 907 * Advertise the HT region if address space covers the reserved 908 * region or if we relocate. 909 */ 910 if (cpu->phys_bits >= 40) { 911 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 912 } 913 } 914 915 /* 916 * phys-bits is required to be appropriately configured 917 * to make sure max used GPA is reachable. 918 */ 919 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 920 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 921 if (maxphysaddr < maxusedaddr) { 922 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 923 " phys-bits too low (%u)", 924 maxphysaddr, maxusedaddr, cpu->phys_bits); 925 exit(EXIT_FAILURE); 926 } 927 928 /* 929 * Split single memory region and use aliases to address portions of it, 930 * done for backwards compatibility with older qemus. 931 */ 932 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 933 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 934 0, x86ms->below_4g_mem_size); 935 memory_region_add_subregion(system_memory, 0, ram_below_4g); 936 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 937 if (x86ms->above_4g_mem_size > 0) { 938 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 939 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 940 machine->ram, 941 x86ms->below_4g_mem_size, 942 x86ms->above_4g_mem_size); 943 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 944 ram_above_4g); 945 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 946 E820_RAM); 947 } 948 949 if (pcms->sgx_epc.size != 0) { 950 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 951 } 952 953 if (!pcmc->has_reserved_memory && 954 (machine->ram_slots || 955 (machine->maxram_size > machine->ram_size))) { 956 957 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 958 mc->name); 959 exit(EXIT_FAILURE); 960 } 961 962 /* initialize device memory address space */ 963 if (pcmc->has_reserved_memory && 964 (machine->ram_size < machine->maxram_size)) { 965 ram_addr_t device_mem_size; 966 hwaddr device_mem_base; 967 968 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 969 error_report("unsupported amount of memory slots: %"PRIu64, 970 machine->ram_slots); 971 exit(EXIT_FAILURE); 972 } 973 974 if (QEMU_ALIGN_UP(machine->maxram_size, 975 TARGET_PAGE_SIZE) != machine->maxram_size) { 976 error_report("maximum memory size must by aligned to multiple of " 977 "%d bytes", TARGET_PAGE_SIZE); 978 exit(EXIT_FAILURE); 979 } 980 981 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 982 983 if (device_mem_base + device_mem_size < device_mem_size) { 984 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 985 machine->maxram_size); 986 exit(EXIT_FAILURE); 987 } 988 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 989 } 990 991 if (pcms->cxl_devices_state.is_enabled) { 992 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 993 hwaddr cxl_size = MiB; 994 995 cxl_base = pc_get_cxl_range_start(pcms); 996 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 997 memory_region_add_subregion(system_memory, cxl_base, mr); 998 cxl_resv_end = cxl_base + cxl_size; 999 if (pcms->cxl_devices_state.fixed_windows) { 1000 hwaddr cxl_fmw_base; 1001 GList *it; 1002 1003 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1004 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1005 CXLFixedWindow *fw = it->data; 1006 1007 fw->base = cxl_fmw_base; 1008 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1009 "cxl-fixed-memory-region", fw->size); 1010 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1011 cxl_fmw_base += fw->size; 1012 cxl_resv_end = cxl_fmw_base; 1013 } 1014 } 1015 } 1016 1017 /* Initialize PC system firmware */ 1018 pc_system_firmware_init(pcms, rom_memory); 1019 1020 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1021 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1022 &error_fatal); 1023 if (pcmc->pci_enabled) { 1024 memory_region_set_readonly(option_rom_mr, true); 1025 } 1026 memory_region_add_subregion_overlap(rom_memory, 1027 PC_ROM_MIN_VGA, 1028 option_rom_mr, 1029 1); 1030 1031 fw_cfg = fw_cfg_arch_create(machine, 1032 x86ms->boot_cpus, x86ms->apic_id_limit); 1033 1034 rom_set_fw(fw_cfg); 1035 1036 if (machine->device_memory) { 1037 uint64_t *val = g_malloc(sizeof(*val)); 1038 uint64_t res_mem_end = machine->device_memory->base; 1039 1040 if (!pcmc->broken_reserved_end) { 1041 res_mem_end += memory_region_size(&machine->device_memory->mr); 1042 } 1043 1044 if (pcms->cxl_devices_state.is_enabled) { 1045 res_mem_end = cxl_resv_end; 1046 } 1047 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1048 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1049 } 1050 1051 if (linux_boot) { 1052 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1053 pcmc->pvh_enabled); 1054 } 1055 1056 for (i = 0; i < nb_option_roms; i++) { 1057 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1058 } 1059 x86ms->fw_cfg = fw_cfg; 1060 1061 /* Init default IOAPIC address space */ 1062 x86ms->ioapic_as = &address_space_memory; 1063 1064 /* Init ACPI memory hotplug IO base address */ 1065 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1066 } 1067 1068 /* 1069 * The 64bit pci hole starts after "above 4G RAM" and 1070 * potentially the space reserved for memory hotplug. 1071 */ 1072 uint64_t pc_pci_hole64_start(void) 1073 { 1074 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1075 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1076 MachineState *ms = MACHINE(pcms); 1077 uint64_t hole64_start = 0; 1078 ram_addr_t size = 0; 1079 1080 if (pcms->cxl_devices_state.is_enabled) { 1081 hole64_start = pc_get_cxl_range_end(pcms); 1082 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1083 pc_get_device_memory_range(pcms, &hole64_start, &size); 1084 if (!pcmc->broken_reserved_end) { 1085 hole64_start += size; 1086 } 1087 } else { 1088 hole64_start = pc_above_4g_end(pcms); 1089 } 1090 1091 return ROUND_UP(hole64_start, 1 * GiB); 1092 } 1093 1094 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1095 { 1096 DeviceState *dev = NULL; 1097 1098 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1099 if (pci_bus) { 1100 PCIDevice *pcidev = pci_vga_init(pci_bus); 1101 dev = pcidev ? &pcidev->qdev : NULL; 1102 } else if (isa_bus) { 1103 ISADevice *isadev = isa_vga_init(isa_bus); 1104 dev = isadev ? DEVICE(isadev) : NULL; 1105 } 1106 rom_reset_order_override(); 1107 return dev; 1108 } 1109 1110 static const MemoryRegionOps ioport80_io_ops = { 1111 .write = ioport80_write, 1112 .read = ioport80_read, 1113 .endianness = DEVICE_NATIVE_ENDIAN, 1114 .impl = { 1115 .min_access_size = 1, 1116 .max_access_size = 1, 1117 }, 1118 }; 1119 1120 static const MemoryRegionOps ioportF0_io_ops = { 1121 .write = ioportF0_write, 1122 .read = ioportF0_read, 1123 .endianness = DEVICE_NATIVE_ENDIAN, 1124 .impl = { 1125 .min_access_size = 1, 1126 .max_access_size = 1, 1127 }, 1128 }; 1129 1130 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1131 bool create_i8042, bool no_vmport) 1132 { 1133 int i; 1134 DriveInfo *fd[MAX_FD]; 1135 qemu_irq *a20_line; 1136 ISADevice *fdc, *i8042, *port92, *vmmouse; 1137 1138 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1139 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1140 1141 for (i = 0; i < MAX_FD; i++) { 1142 fd[i] = drive_get(IF_FLOPPY, 0, i); 1143 create_fdctrl |= !!fd[i]; 1144 } 1145 if (create_fdctrl) { 1146 fdc = isa_new(TYPE_ISA_FDC); 1147 if (fdc) { 1148 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1149 isa_fdc_init_drives(fdc, fd); 1150 } 1151 } 1152 1153 if (!create_i8042) { 1154 return; 1155 } 1156 1157 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1158 if (!no_vmport) { 1159 isa_create_simple(isa_bus, TYPE_VMPORT); 1160 vmmouse = isa_try_new("vmmouse"); 1161 } else { 1162 vmmouse = NULL; 1163 } 1164 if (vmmouse) { 1165 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1166 &error_abort); 1167 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1168 } 1169 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1170 1171 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1172 qdev_connect_gpio_out_named(DEVICE(i8042), 1173 I8042_A20_LINE, 0, a20_line[0]); 1174 qdev_connect_gpio_out_named(DEVICE(port92), 1175 PORT92_A20_LINE, 0, a20_line[1]); 1176 g_free(a20_line); 1177 } 1178 1179 void pc_basic_device_init(struct PCMachineState *pcms, 1180 ISABus *isa_bus, qemu_irq *gsi, 1181 ISADevice *rtc_state, 1182 bool create_fdctrl, 1183 uint32_t hpet_irqs) 1184 { 1185 int i; 1186 DeviceState *hpet = NULL; 1187 int pit_isa_irq = 0; 1188 qemu_irq pit_alt_irq = NULL; 1189 ISADevice *pit = NULL; 1190 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1191 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1192 X86MachineState *x86ms = X86_MACHINE(pcms); 1193 1194 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1195 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1196 1197 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1198 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1199 1200 /* 1201 * Check if an HPET shall be created. 1202 */ 1203 if (pcms->hpet_enabled) { 1204 qemu_irq rtc_irq; 1205 1206 hpet = qdev_try_new(TYPE_HPET); 1207 if (!hpet) { 1208 error_report("couldn't create HPET device"); 1209 exit(1); 1210 } 1211 /* 1212 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1213 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1214 * the property, use whatever mask they specified. 1215 */ 1216 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1217 HPET_INTCAP, NULL); 1218 if (!compat) { 1219 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1220 } 1221 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1222 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1223 1224 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1225 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1226 } 1227 pit_isa_irq = -1; 1228 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1229 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1230 1231 /* overwrite connection created by south bridge */ 1232 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1233 } 1234 1235 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1236 "date"); 1237 1238 #ifdef CONFIG_XEN_EMU 1239 if (xen_mode == XEN_EMULATE) { 1240 xen_overlay_create(); 1241 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1242 xen_gnttab_create(); 1243 xen_xenstore_create(); 1244 if (pcms->pcibus) { 1245 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1246 } 1247 xen_bus_init(); 1248 xen_be_init(); 1249 } 1250 #endif 1251 1252 qemu_register_boot_set(pc_boot_set, pcms); 1253 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1254 MACHINE(pcms)->boot_config.order, &error_fatal); 1255 1256 if (!xen_enabled() && 1257 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1258 if (kvm_pit_in_kernel()) { 1259 pit = kvm_pit_init(isa_bus, 0x40); 1260 } else { 1261 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1262 } 1263 if (hpet) { 1264 /* connect PIT to output control line of the HPET */ 1265 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1266 } 1267 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1268 OBJECT(pit), &error_fatal); 1269 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1270 } 1271 1272 /* Super I/O */ 1273 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1274 pcms->vmport != ON_OFF_AUTO_ON); 1275 } 1276 1277 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1278 { 1279 MachineClass *mc = MACHINE_CLASS(pcmc); 1280 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1281 NICInfo *nd; 1282 1283 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1284 1285 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1286 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1287 } 1288 1289 /* Anything remaining should be a PCI NIC */ 1290 pci_init_nic_devices(pci_bus, mc->default_nic); 1291 1292 rom_reset_order_override(); 1293 } 1294 1295 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1296 { 1297 qemu_irq *i8259; 1298 1299 if (kvm_pic_in_kernel()) { 1300 i8259 = kvm_i8259_init(isa_bus); 1301 } else if (xen_enabled()) { 1302 i8259 = xen_interrupt_controller_init(); 1303 } else { 1304 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1305 } 1306 1307 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1308 i8259_irqs[i] = i8259[i]; 1309 } 1310 1311 g_free(i8259); 1312 } 1313 1314 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1315 Error **errp) 1316 { 1317 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1318 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1319 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1320 const MachineState *ms = MACHINE(hotplug_dev); 1321 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1322 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1323 Error *local_err = NULL; 1324 1325 /* 1326 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1327 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1328 * addition to cover this case. 1329 */ 1330 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1331 error_setg(errp, 1332 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1333 return; 1334 } 1335 1336 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1337 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1338 return; 1339 } 1340 1341 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1342 if (local_err) { 1343 error_propagate(errp, local_err); 1344 return; 1345 } 1346 1347 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1348 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1349 } 1350 1351 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1352 DeviceState *dev, Error **errp) 1353 { 1354 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1355 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1356 MachineState *ms = MACHINE(hotplug_dev); 1357 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1358 1359 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1360 1361 if (is_nvdimm) { 1362 nvdimm_plug(ms->nvdimms_state); 1363 } 1364 1365 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1366 } 1367 1368 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1369 DeviceState *dev, Error **errp) 1370 { 1371 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1372 1373 /* 1374 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1375 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1376 * addition to cover this case. 1377 */ 1378 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1379 error_setg(errp, 1380 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1381 return; 1382 } 1383 1384 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1385 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1386 return; 1387 } 1388 1389 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1390 errp); 1391 } 1392 1393 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1394 DeviceState *dev, Error **errp) 1395 { 1396 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1397 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1398 Error *local_err = NULL; 1399 1400 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1401 if (local_err) { 1402 goto out; 1403 } 1404 1405 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1406 qdev_unrealize(dev); 1407 out: 1408 error_propagate(errp, local_err); 1409 } 1410 1411 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1412 DeviceState *dev, Error **errp) 1413 { 1414 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1415 g_assert(!dev->hotplugged); 1416 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1417 errp); 1418 } 1419 1420 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1421 DeviceState *dev, Error **errp) 1422 { 1423 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1424 } 1425 1426 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1427 DeviceState *dev, Error **errp) 1428 { 1429 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1430 pc_memory_pre_plug(hotplug_dev, dev, errp); 1431 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1432 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1433 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1434 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1435 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1436 /* Declare the APIC range as the reserved MSI region */ 1437 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1438 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1439 QList *reserved_regions = qlist_new(); 1440 1441 qlist_append_str(reserved_regions, resv_prop_str); 1442 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1443 1444 g_free(resv_prop_str); 1445 } 1446 1447 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1448 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1449 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1450 1451 if (pcms->iommu) { 1452 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1453 "for x86 yet."); 1454 return; 1455 } 1456 pcms->iommu = dev; 1457 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1458 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1459 } 1460 } 1461 1462 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1463 DeviceState *dev, Error **errp) 1464 { 1465 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1466 pc_memory_plug(hotplug_dev, dev, errp); 1467 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1468 x86_cpu_plug(hotplug_dev, dev, errp); 1469 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1470 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1471 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1472 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1473 } 1474 } 1475 1476 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1477 DeviceState *dev, Error **errp) 1478 { 1479 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1480 pc_memory_unplug_request(hotplug_dev, dev, errp); 1481 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1482 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1483 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1484 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1485 errp); 1486 } else { 1487 error_setg(errp, "acpi: device unplug request for not supported device" 1488 " type: %s", object_get_typename(OBJECT(dev))); 1489 } 1490 } 1491 1492 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1493 DeviceState *dev, Error **errp) 1494 { 1495 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1496 pc_memory_unplug(hotplug_dev, dev, errp); 1497 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1498 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1499 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1500 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1501 } else { 1502 error_setg(errp, "acpi: device unplug for not supported device" 1503 " type: %s", object_get_typename(OBJECT(dev))); 1504 } 1505 } 1506 1507 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1508 DeviceState *dev) 1509 { 1510 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1511 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1512 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1513 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1514 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1515 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1516 return HOTPLUG_HANDLER(machine); 1517 } 1518 1519 return NULL; 1520 } 1521 1522 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1523 void *opaque, Error **errp) 1524 { 1525 PCMachineState *pcms = PC_MACHINE(obj); 1526 OnOffAuto vmport = pcms->vmport; 1527 1528 visit_type_OnOffAuto(v, name, &vmport, errp); 1529 } 1530 1531 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1532 void *opaque, Error **errp) 1533 { 1534 PCMachineState *pcms = PC_MACHINE(obj); 1535 1536 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1537 } 1538 1539 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1540 { 1541 PCMachineState *pcms = PC_MACHINE(obj); 1542 1543 return pcms->fd_bootchk; 1544 } 1545 1546 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1547 { 1548 PCMachineState *pcms = PC_MACHINE(obj); 1549 1550 pcms->fd_bootchk = value; 1551 } 1552 1553 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1554 { 1555 PCMachineState *pcms = PC_MACHINE(obj); 1556 1557 return pcms->smbus_enabled; 1558 } 1559 1560 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1561 { 1562 PCMachineState *pcms = PC_MACHINE(obj); 1563 1564 pcms->smbus_enabled = value; 1565 } 1566 1567 static bool pc_machine_get_sata(Object *obj, Error **errp) 1568 { 1569 PCMachineState *pcms = PC_MACHINE(obj); 1570 1571 return pcms->sata_enabled; 1572 } 1573 1574 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1575 { 1576 PCMachineState *pcms = PC_MACHINE(obj); 1577 1578 pcms->sata_enabled = value; 1579 } 1580 1581 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1582 { 1583 PCMachineState *pcms = PC_MACHINE(obj); 1584 1585 return pcms->hpet_enabled; 1586 } 1587 1588 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1589 { 1590 PCMachineState *pcms = PC_MACHINE(obj); 1591 1592 pcms->hpet_enabled = value; 1593 } 1594 1595 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1596 { 1597 PCMachineState *pcms = PC_MACHINE(obj); 1598 1599 return pcms->i8042_enabled; 1600 } 1601 1602 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1603 { 1604 PCMachineState *pcms = PC_MACHINE(obj); 1605 1606 pcms->i8042_enabled = value; 1607 } 1608 1609 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1610 { 1611 PCMachineState *pcms = PC_MACHINE(obj); 1612 1613 return pcms->default_bus_bypass_iommu; 1614 } 1615 1616 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1617 Error **errp) 1618 { 1619 PCMachineState *pcms = PC_MACHINE(obj); 1620 1621 pcms->default_bus_bypass_iommu = value; 1622 } 1623 1624 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1625 void *opaque, Error **errp) 1626 { 1627 PCMachineState *pcms = PC_MACHINE(obj); 1628 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1629 1630 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1631 } 1632 1633 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1634 void *opaque, Error **errp) 1635 { 1636 PCMachineState *pcms = PC_MACHINE(obj); 1637 1638 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1639 } 1640 1641 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1642 const char *name, void *opaque, 1643 Error **errp) 1644 { 1645 PCMachineState *pcms = PC_MACHINE(obj); 1646 uint64_t value = pcms->max_ram_below_4g; 1647 1648 visit_type_size(v, name, &value, errp); 1649 } 1650 1651 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1652 const char *name, void *opaque, 1653 Error **errp) 1654 { 1655 PCMachineState *pcms = PC_MACHINE(obj); 1656 uint64_t value; 1657 1658 if (!visit_type_size(v, name, &value, errp)) { 1659 return; 1660 } 1661 if (value > 4 * GiB) { 1662 error_setg(errp, 1663 "Machine option 'max-ram-below-4g=%"PRIu64 1664 "' expects size less than or equal to 4G", value); 1665 return; 1666 } 1667 1668 if (value < 1 * MiB) { 1669 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1670 "BIOS may not work with less than 1MiB", value); 1671 } 1672 1673 pcms->max_ram_below_4g = value; 1674 } 1675 1676 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1677 const char *name, void *opaque, 1678 Error **errp) 1679 { 1680 PCMachineState *pcms = PC_MACHINE(obj); 1681 uint64_t value = pcms->max_fw_size; 1682 1683 visit_type_size(v, name, &value, errp); 1684 } 1685 1686 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1687 const char *name, void *opaque, 1688 Error **errp) 1689 { 1690 PCMachineState *pcms = PC_MACHINE(obj); 1691 uint64_t value; 1692 1693 if (!visit_type_size(v, name, &value, errp)) { 1694 return; 1695 } 1696 1697 /* 1698 * We don't have a theoretically justifiable exact lower bound on the base 1699 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1700 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1701 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1702 * 16MiB in size. 1703 */ 1704 if (value > 16 * MiB) { 1705 error_setg(errp, 1706 "User specified max allowed firmware size %" PRIu64 " is " 1707 "greater than 16MiB. If combined firmware size exceeds " 1708 "16MiB the system may not boot, or experience intermittent" 1709 "stability issues.", 1710 value); 1711 return; 1712 } 1713 1714 pcms->max_fw_size = value; 1715 } 1716 1717 1718 static void pc_machine_initfn(Object *obj) 1719 { 1720 PCMachineState *pcms = PC_MACHINE(obj); 1721 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1722 1723 #ifdef CONFIG_VMPORT 1724 pcms->vmport = ON_OFF_AUTO_AUTO; 1725 #else 1726 pcms->vmport = ON_OFF_AUTO_OFF; 1727 #endif /* CONFIG_VMPORT */ 1728 pcms->max_ram_below_4g = 0; /* use default */ 1729 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1730 pcms->south_bridge = pcmc->default_south_bridge; 1731 1732 /* acpi build is enabled by default if machine supports it */ 1733 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1734 pcms->smbus_enabled = true; 1735 pcms->sata_enabled = true; 1736 pcms->i8042_enabled = true; 1737 pcms->max_fw_size = 8 * MiB; 1738 #ifdef CONFIG_HPET 1739 pcms->hpet_enabled = true; 1740 #endif 1741 pcms->fd_bootchk = true; 1742 pcms->default_bus_bypass_iommu = false; 1743 1744 pc_system_flash_create(pcms); 1745 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1746 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1747 OBJECT(pcms->pcspk), "audiodev"); 1748 if (pcmc->pci_enabled) { 1749 cxl_machine_init(obj, &pcms->cxl_devices_state); 1750 } 1751 1752 pcms->machine_done.notify = pc_machine_done; 1753 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1754 } 1755 1756 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1757 { 1758 CPUState *cs; 1759 X86CPU *cpu; 1760 1761 qemu_devices_reset(reason); 1762 1763 /* Reset APIC after devices have been reset to cancel 1764 * any changes that qemu_devices_reset() might have done. 1765 */ 1766 CPU_FOREACH(cs) { 1767 cpu = X86_CPU(cs); 1768 1769 x86_cpu_after_reset(cpu); 1770 } 1771 } 1772 1773 static void pc_machine_wakeup(MachineState *machine) 1774 { 1775 cpu_synchronize_all_states(); 1776 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1777 cpu_synchronize_all_post_reset(); 1778 } 1779 1780 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1781 { 1782 X86IOMMUState *iommu = x86_iommu_get_default(); 1783 IntelIOMMUState *intel_iommu; 1784 1785 if (iommu && 1786 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1787 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1788 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1789 if (!intel_iommu->caching_mode) { 1790 error_setg(errp, "Device assignment is not allowed without " 1791 "enabling caching-mode=on for Intel IOMMU."); 1792 return false; 1793 } 1794 } 1795 1796 return true; 1797 } 1798 1799 static void pc_machine_class_init(ObjectClass *oc, void *data) 1800 { 1801 MachineClass *mc = MACHINE_CLASS(oc); 1802 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1803 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1804 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1805 1806 pcmc->pci_enabled = true; 1807 pcmc->has_acpi_build = true; 1808 pcmc->rsdp_in_ram = true; 1809 pcmc->smbios_defaults = true; 1810 pcmc->smbios_uuid_encoded = true; 1811 pcmc->gigabyte_align = true; 1812 pcmc->has_reserved_memory = true; 1813 pcmc->enforce_aligned_dimm = true; 1814 pcmc->enforce_amd_1tb_hole = true; 1815 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1816 * to be used at the moment, 32K should be enough for a while. */ 1817 pcmc->acpi_data_size = 0x20000 + 0x8000; 1818 pcmc->pvh_enabled = true; 1819 pcmc->kvmclock_create_always = true; 1820 pcmc->resizable_acpi_blob = true; 1821 x86mc->apic_xrupt_override = true; 1822 assert(!mc->get_hotplug_handler); 1823 mc->get_hotplug_handler = pc_get_hotplug_handler; 1824 mc->hotplug_allowed = pc_hotplug_allowed; 1825 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1826 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1827 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1828 mc->auto_enable_numa_with_memhp = true; 1829 mc->auto_enable_numa_with_memdev = true; 1830 mc->has_hotpluggable_cpus = true; 1831 mc->default_boot_order = "cad"; 1832 mc->block_default_type = IF_IDE; 1833 mc->max_cpus = 255; 1834 mc->reset = pc_machine_reset; 1835 mc->wakeup = pc_machine_wakeup; 1836 hc->pre_plug = pc_machine_device_pre_plug_cb; 1837 hc->plug = pc_machine_device_plug_cb; 1838 hc->unplug_request = pc_machine_device_unplug_request_cb; 1839 hc->unplug = pc_machine_device_unplug_cb; 1840 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1841 mc->nvdimm_supported = true; 1842 mc->smp_props.dies_supported = true; 1843 mc->default_ram_id = "pc.ram"; 1844 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1845 1846 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1847 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1848 NULL, NULL); 1849 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1850 "Maximum ram below the 4G boundary (32bit boundary)"); 1851 1852 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1853 pc_machine_get_vmport, pc_machine_set_vmport, 1854 NULL, NULL); 1855 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1856 "Enable vmport (pc & q35)"); 1857 1858 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1859 pc_machine_get_smbus, pc_machine_set_smbus); 1860 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1861 "Enable/disable system management bus"); 1862 1863 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1864 pc_machine_get_sata, pc_machine_set_sata); 1865 object_class_property_set_description(oc, PC_MACHINE_SATA, 1866 "Enable/disable Serial ATA bus"); 1867 1868 object_class_property_add_bool(oc, "hpet", 1869 pc_machine_get_hpet, pc_machine_set_hpet); 1870 object_class_property_set_description(oc, "hpet", 1871 "Enable/disable high precision event timer emulation"); 1872 1873 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1874 pc_machine_get_i8042, pc_machine_set_i8042); 1875 1876 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1877 pc_machine_get_default_bus_bypass_iommu, 1878 pc_machine_set_default_bus_bypass_iommu); 1879 1880 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1881 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1882 NULL, NULL); 1883 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1884 "Maximum combined firmware size"); 1885 1886 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1887 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1888 NULL, NULL); 1889 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1890 "SMBIOS Entry Point type [32, 64]"); 1891 1892 object_class_property_add_bool(oc, "fd-bootchk", 1893 pc_machine_get_fd_bootchk, 1894 pc_machine_set_fd_bootchk); 1895 } 1896 1897 static const TypeInfo pc_machine_info = { 1898 .name = TYPE_PC_MACHINE, 1899 .parent = TYPE_X86_MACHINE, 1900 .abstract = true, 1901 .instance_size = sizeof(PCMachineState), 1902 .instance_init = pc_machine_initfn, 1903 .class_size = sizeof(PCMachineClass), 1904 .class_init = pc_machine_class_init, 1905 .interfaces = (InterfaceInfo[]) { 1906 { TYPE_HOTPLUG_HANDLER }, 1907 { } 1908 }, 1909 }; 1910 1911 static void pc_machine_register_types(void) 1912 { 1913 type_register_static(&pc_machine_info); 1914 } 1915 1916 type_init(pc_machine_register_types) 1917