1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide/internal.h" 37 #include "hw/ide/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/intc/ioapic.h" 51 #include "hw/timer/i8254.h" 52 #include "hw/input/i8042.h" 53 #include "hw/irq.h" 54 #include "hw/audio/pcspk.h" 55 #include "hw/pci/msi.h" 56 #include "hw/sysbus.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/tcg.h" 59 #include "sysemu/numa.h" 60 #include "sysemu/kvm.h" 61 #include "sysemu/xen.h" 62 #include "sysemu/reset.h" 63 #include "sysemu/runstate.h" 64 #include "kvm/kvm_i386.h" 65 #include "hw/xen/xen.h" 66 #include "hw/xen/start_info.h" 67 #include "ui/qemu-spice.h" 68 #include "exec/memory.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/cxl/cxl.h" 80 #include "hw/cxl/cxl_host.h" 81 #include "qapi/error.h" 82 #include "qapi/qapi-visit-common.h" 83 #include "qapi/qapi-visit-machine.h" 84 #include "qapi/visitor.h" 85 #include "hw/core/cpu.h" 86 #include "hw/usb.h" 87 #include "hw/i386/intel_iommu.h" 88 #include "hw/net/ne2000-isa.h" 89 #include "standard-headers/asm-x86/bootparam.h" 90 #include "hw/virtio/virtio-iommu.h" 91 #include "hw/virtio/virtio-pmem-pci.h" 92 #include "hw/virtio/virtio-mem-pci.h" 93 #include "hw/mem/memory-device.h" 94 #include "sysemu/replay.h" 95 #include "target/i386/cpu.h" 96 #include "e820_memory_layout.h" 97 #include "fw_cfg.h" 98 #include "trace.h" 99 #include CONFIG_DEVICES 100 101 /* 102 * Helper for setting model-id for CPU models that changed model-id 103 * depending on QEMU versions up to QEMU 2.4. 104 */ 105 #define PC_CPU_MODEL_IDS(v) \ 106 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 107 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 108 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 109 110 GlobalProperty pc_compat_7_2[] = { 111 { "ICH9-LPC", "noreboot", "true" }, 112 }; 113 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 114 115 GlobalProperty pc_compat_7_1[] = {}; 116 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 117 118 GlobalProperty pc_compat_7_0[] = {}; 119 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 120 121 GlobalProperty pc_compat_6_2[] = { 122 { "virtio-mem", "unplugged-inaccessible", "off" }, 123 }; 124 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 125 126 GlobalProperty pc_compat_6_1[] = { 127 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 128 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 129 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 130 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 131 }; 132 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 133 134 GlobalProperty pc_compat_6_0[] = { 135 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 136 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 137 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 138 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 139 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 140 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 141 }; 142 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 143 144 GlobalProperty pc_compat_5_2[] = { 145 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 146 }; 147 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 148 149 GlobalProperty pc_compat_5_1[] = { 150 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 151 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 152 }; 153 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 154 155 GlobalProperty pc_compat_5_0[] = { 156 }; 157 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 158 159 GlobalProperty pc_compat_4_2[] = { 160 { "mch", "smbase-smram", "off" }, 161 }; 162 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 163 164 GlobalProperty pc_compat_4_1[] = {}; 165 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 166 167 GlobalProperty pc_compat_4_0[] = {}; 168 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 169 170 GlobalProperty pc_compat_3_1[] = { 171 { "intel-iommu", "dma-drain", "off" }, 172 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 173 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 174 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 175 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 176 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 177 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 178 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 179 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 180 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 181 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 182 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 183 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 184 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 185 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 186 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 187 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 188 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 189 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 190 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 191 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 192 }; 193 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 194 195 GlobalProperty pc_compat_3_0[] = { 196 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 197 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 198 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 199 }; 200 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 201 202 GlobalProperty pc_compat_2_12[] = { 203 { TYPE_X86_CPU, "legacy-cache", "on" }, 204 { TYPE_X86_CPU, "topoext", "off" }, 205 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 206 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 207 }; 208 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 209 210 GlobalProperty pc_compat_2_11[] = { 211 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 212 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 213 }; 214 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 215 216 GlobalProperty pc_compat_2_10[] = { 217 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 218 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 219 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 220 }; 221 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 222 223 GlobalProperty pc_compat_2_9[] = { 224 { "mch", "extended-tseg-mbytes", "0" }, 225 }; 226 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 227 228 GlobalProperty pc_compat_2_8[] = { 229 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 230 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 231 { "ICH9-LPC", "x-smi-broadcast", "off" }, 232 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 233 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 234 }; 235 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 236 237 GlobalProperty pc_compat_2_7[] = { 238 { TYPE_X86_CPU, "l3-cache", "off" }, 239 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 240 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 241 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 242 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 243 { "isa-pcspk", "migrate", "off" }, 244 }; 245 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 246 247 GlobalProperty pc_compat_2_6[] = { 248 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 249 { "vmxnet3", "romfile", "" }, 250 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 251 { "apic-common", "legacy-instance-id", "on", } 252 }; 253 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 254 255 GlobalProperty pc_compat_2_5[] = {}; 256 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 257 258 GlobalProperty pc_compat_2_4[] = { 259 PC_CPU_MODEL_IDS("2.4.0") 260 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 261 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 262 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 263 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 264 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 265 { TYPE_X86_CPU, "check", "off" }, 266 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 267 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 268 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 269 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 270 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 271 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 272 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 273 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 274 }; 275 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 276 277 GlobalProperty pc_compat_2_3[] = { 278 PC_CPU_MODEL_IDS("2.3.0") 279 { TYPE_X86_CPU, "arat", "off" }, 280 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 281 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 282 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 283 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 284 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 285 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 286 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 287 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 288 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 289 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 291 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 293 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 294 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 295 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 296 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 297 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 298 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 299 }; 300 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 301 302 GlobalProperty pc_compat_2_2[] = { 303 PC_CPU_MODEL_IDS("2.2.0") 304 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 307 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 308 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 309 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 310 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 311 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 312 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 313 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 314 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 315 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 316 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 317 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 318 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 319 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 320 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 321 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 322 }; 323 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 324 325 GlobalProperty pc_compat_2_1[] = { 326 PC_CPU_MODEL_IDS("2.1.0") 327 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 328 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 329 }; 330 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 331 332 GlobalProperty pc_compat_2_0[] = { 333 PC_CPU_MODEL_IDS("2.0.0") 334 { "virtio-scsi-pci", "any_layout", "off" }, 335 { "PIIX4_PM", "memory-hotplug-support", "off" }, 336 { "apic", "version", "0x11" }, 337 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 338 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 339 { "pci-serial", "prog_if", "0" }, 340 { "pci-serial-2x", "prog_if", "0" }, 341 { "pci-serial-4x", "prog_if", "0" }, 342 { "virtio-net-pci", "guest_announce", "off" }, 343 { "ICH9-LPC", "memory-hotplug-support", "off" }, 344 }; 345 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 346 347 GlobalProperty pc_compat_1_7[] = { 348 PC_CPU_MODEL_IDS("1.7.0") 349 { TYPE_USB_DEVICE, "msos-desc", "no" }, 350 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 351 { "hpet", HPET_INTCAP, "4" }, 352 }; 353 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 354 355 GlobalProperty pc_compat_1_6[] = { 356 PC_CPU_MODEL_IDS("1.6.0") 357 { "e1000", "mitigation", "off" }, 358 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 359 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 360 { "i440FX-pcihost", "short_root_bus", "1" }, 361 { "q35-pcihost", "short_root_bus", "1" }, 362 }; 363 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 364 365 GlobalProperty pc_compat_1_5[] = { 366 PC_CPU_MODEL_IDS("1.5.0") 367 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 368 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 369 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 370 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 371 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 372 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 373 { "virtio-net-pci", "any_layout", "off" }, 374 { TYPE_X86_CPU, "pmu", "on" }, 375 { "i440FX-pcihost", "short_root_bus", "0" }, 376 { "q35-pcihost", "short_root_bus", "0" }, 377 }; 378 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 379 380 GlobalProperty pc_compat_1_4[] = { 381 PC_CPU_MODEL_IDS("1.4.0") 382 { "scsi-hd", "discard_granularity", "0" }, 383 { "scsi-cd", "discard_granularity", "0" }, 384 { "ide-hd", "discard_granularity", "0" }, 385 { "ide-cd", "discard_granularity", "0" }, 386 { "virtio-blk-pci", "discard_granularity", "0" }, 387 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 388 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 389 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 390 { "e1000", "romfile", "pxe-e1000.rom" }, 391 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 392 { "pcnet", "romfile", "pxe-pcnet.rom" }, 393 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 394 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 395 { "486-" TYPE_X86_CPU, "model", "0" }, 396 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 397 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 398 }; 399 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 400 401 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 402 { 403 GSIState *s; 404 405 s = g_new0(GSIState, 1); 406 if (kvm_ioapic_in_kernel()) { 407 kvm_pc_setup_irq_routing(pci_enabled); 408 } 409 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 410 411 return s; 412 } 413 414 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 415 unsigned size) 416 { 417 } 418 419 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 420 { 421 return 0xffffffffffffffffULL; 422 } 423 424 /* MSDOS compatibility mode FPU exception support */ 425 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 426 unsigned size) 427 { 428 if (tcg_enabled()) { 429 cpu_set_ignne(); 430 } 431 } 432 433 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 434 { 435 return 0xffffffffffffffffULL; 436 } 437 438 /* PC cmos mappings */ 439 440 #define REG_EQUIPMENT_BYTE 0x14 441 442 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 443 int16_t cylinders, int8_t heads, int8_t sectors) 444 { 445 mc146818rtc_set_cmos_data(s, type_ofs, 47); 446 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 447 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 448 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 449 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 450 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 451 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 452 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 453 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 454 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 455 } 456 457 /* convert boot_device letter to something recognizable by the bios */ 458 static int boot_device2nibble(char boot_device) 459 { 460 switch(boot_device) { 461 case 'a': 462 case 'b': 463 return 0x01; /* floppy boot */ 464 case 'c': 465 return 0x02; /* hard drive boot */ 466 case 'd': 467 return 0x03; /* CD-ROM boot */ 468 case 'n': 469 return 0x04; /* Network boot */ 470 } 471 return 0; 472 } 473 474 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 475 Error **errp) 476 { 477 #define PC_MAX_BOOT_DEVICES 3 478 int nbds, bds[3] = { 0, }; 479 int i; 480 481 nbds = strlen(boot_device); 482 if (nbds > PC_MAX_BOOT_DEVICES) { 483 error_setg(errp, "Too many boot devices for PC"); 484 return; 485 } 486 for (i = 0; i < nbds; i++) { 487 bds[i] = boot_device2nibble(boot_device[i]); 488 if (bds[i] == 0) { 489 error_setg(errp, "Invalid boot device for PC: '%c'", 490 boot_device[i]); 491 return; 492 } 493 } 494 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 495 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 496 } 497 498 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 499 { 500 set_boot_dev(opaque, boot_device, errp); 501 } 502 503 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 504 { 505 int val, nb, i; 506 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 507 FLOPPY_DRIVE_TYPE_NONE }; 508 509 /* floppy type */ 510 if (floppy) { 511 for (i = 0; i < 2; i++) { 512 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 513 } 514 } 515 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 516 cmos_get_fd_drive_type(fd_type[1]); 517 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 518 519 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 520 nb = 0; 521 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 522 nb++; 523 } 524 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 525 nb++; 526 } 527 switch (nb) { 528 case 0: 529 break; 530 case 1: 531 val |= 0x01; /* 1 drive, ready for boot */ 532 break; 533 case 2: 534 val |= 0x41; /* 2 drives, ready for boot */ 535 break; 536 } 537 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 538 } 539 540 typedef struct pc_cmos_init_late_arg { 541 MC146818RtcState *rtc_state; 542 BusState *idebus[2]; 543 } pc_cmos_init_late_arg; 544 545 typedef struct check_fdc_state { 546 ISADevice *floppy; 547 bool multiple; 548 } CheckFdcState; 549 550 static int check_fdc(Object *obj, void *opaque) 551 { 552 CheckFdcState *state = opaque; 553 Object *fdc; 554 uint32_t iobase; 555 Error *local_err = NULL; 556 557 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 558 if (!fdc) { 559 return 0; 560 } 561 562 iobase = object_property_get_uint(obj, "iobase", &local_err); 563 if (local_err || iobase != 0x3f0) { 564 error_free(local_err); 565 return 0; 566 } 567 568 if (state->floppy) { 569 state->multiple = true; 570 } else { 571 state->floppy = ISA_DEVICE(obj); 572 } 573 return 0; 574 } 575 576 static const char * const fdc_container_path[] = { 577 "/unattached", "/peripheral", "/peripheral-anon" 578 }; 579 580 /* 581 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 582 * and ACPI objects. 583 */ 584 static ISADevice *pc_find_fdc0(void) 585 { 586 int i; 587 Object *container; 588 CheckFdcState state = { 0 }; 589 590 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 591 container = container_get(qdev_get_machine(), fdc_container_path[i]); 592 object_child_foreach(container, check_fdc, &state); 593 } 594 595 if (state.multiple) { 596 warn_report("multiple floppy disk controllers with " 597 "iobase=0x3f0 have been found"); 598 error_printf("the one being picked for CMOS setup might not reflect " 599 "your intent"); 600 } 601 602 return state.floppy; 603 } 604 605 static void pc_cmos_init_late(void *opaque) 606 { 607 pc_cmos_init_late_arg *arg = opaque; 608 MC146818RtcState *s = arg->rtc_state; 609 int16_t cylinders; 610 int8_t heads, sectors; 611 int val; 612 int i, trans; 613 614 val = 0; 615 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 616 &cylinders, &heads, §ors) >= 0) { 617 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 618 val |= 0xf0; 619 } 620 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 621 &cylinders, &heads, §ors) >= 0) { 622 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 623 val |= 0x0f; 624 } 625 mc146818rtc_set_cmos_data(s, 0x12, val); 626 627 val = 0; 628 for (i = 0; i < 4; i++) { 629 /* NOTE: ide_get_geometry() returns the physical 630 geometry. It is always such that: 1 <= sects <= 63, 1 631 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 632 geometry can be different if a translation is done. */ 633 if (arg->idebus[i / 2] && 634 ide_get_geometry(arg->idebus[i / 2], i % 2, 635 &cylinders, &heads, §ors) >= 0) { 636 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 637 assert((trans & ~3) == 0); 638 val |= trans << (i * 2); 639 } 640 } 641 mc146818rtc_set_cmos_data(s, 0x39, val); 642 643 pc_cmos_init_floppy(s, pc_find_fdc0()); 644 645 qemu_unregister_reset(pc_cmos_init_late, opaque); 646 } 647 648 void pc_cmos_init(PCMachineState *pcms, 649 BusState *idebus0, BusState *idebus1, 650 ISADevice *rtc) 651 { 652 int val; 653 static pc_cmos_init_late_arg arg; 654 X86MachineState *x86ms = X86_MACHINE(pcms); 655 MC146818RtcState *s = MC146818_RTC(rtc); 656 657 /* various important CMOS locations needed by PC/Bochs bios */ 658 659 /* memory size */ 660 /* base memory (first MiB) */ 661 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 662 mc146818rtc_set_cmos_data(s, 0x15, val); 663 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 664 /* extended memory (next 64MiB) */ 665 if (x86ms->below_4g_mem_size > 1 * MiB) { 666 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 667 } else { 668 val = 0; 669 } 670 if (val > 65535) 671 val = 65535; 672 mc146818rtc_set_cmos_data(s, 0x17, val); 673 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 674 mc146818rtc_set_cmos_data(s, 0x30, val); 675 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 676 /* memory between 16MiB and 4GiB */ 677 if (x86ms->below_4g_mem_size > 16 * MiB) { 678 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 679 } else { 680 val = 0; 681 } 682 if (val > 65535) 683 val = 65535; 684 mc146818rtc_set_cmos_data(s, 0x34, val); 685 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 686 /* memory above 4GiB */ 687 val = x86ms->above_4g_mem_size / 65536; 688 mc146818rtc_set_cmos_data(s, 0x5b, val); 689 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 690 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 691 692 object_property_add_link(OBJECT(pcms), "rtc_state", 693 TYPE_ISA_DEVICE, 694 (Object **)&x86ms->rtc, 695 object_property_allow_set_link, 696 OBJ_PROP_LINK_STRONG); 697 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 698 &error_abort); 699 700 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 701 702 val = 0; 703 val |= 0x02; /* FPU is there */ 704 val |= 0x04; /* PS/2 mouse installed */ 705 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 706 707 /* hard drives and FDC */ 708 arg.rtc_state = s; 709 arg.idebus[0] = idebus0; 710 arg.idebus[1] = idebus1; 711 qemu_register_reset(pc_cmos_init_late, &arg); 712 } 713 714 static void handle_a20_line_change(void *opaque, int irq, int level) 715 { 716 X86CPU *cpu = opaque; 717 718 /* XXX: send to all CPUs ? */ 719 /* XXX: add logic to handle multiple A20 line sources */ 720 x86_cpu_set_a20(cpu, level); 721 } 722 723 #define NE2000_NB_MAX 6 724 725 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 726 0x280, 0x380 }; 727 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 728 729 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 730 { 731 static int nb_ne2k = 0; 732 733 if (nb_ne2k == NE2000_NB_MAX) 734 return; 735 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 736 ne2000_irq[nb_ne2k], nd); 737 nb_ne2k++; 738 } 739 740 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 741 { 742 X86CPU *cpu = opaque; 743 744 if (level) { 745 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 746 } 747 } 748 749 static 750 void pc_machine_done(Notifier *notifier, void *data) 751 { 752 PCMachineState *pcms = container_of(notifier, 753 PCMachineState, machine_done); 754 X86MachineState *x86ms = X86_MACHINE(pcms); 755 756 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 757 &error_fatal); 758 759 if (pcms->cxl_devices_state.is_enabled) { 760 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 761 } 762 763 /* set the number of CPUs */ 764 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 765 766 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 767 768 acpi_setup(); 769 if (x86ms->fw_cfg) { 770 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 771 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 772 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 773 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 774 } 775 } 776 777 void pc_guest_info_init(PCMachineState *pcms) 778 { 779 X86MachineState *x86ms = X86_MACHINE(pcms); 780 781 x86ms->apic_xrupt_override = true; 782 pcms->machine_done.notify = pc_machine_done; 783 qemu_add_machine_init_done_notifier(&pcms->machine_done); 784 } 785 786 /* setup pci memory address space mapping into system address space */ 787 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 788 MemoryRegion *pci_address_space) 789 { 790 /* Set to lower priority than RAM */ 791 memory_region_add_subregion_overlap(system_memory, 0x0, 792 pci_address_space, -1); 793 } 794 795 void xen_load_linux(PCMachineState *pcms) 796 { 797 int i; 798 FWCfgState *fw_cfg; 799 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 800 X86MachineState *x86ms = X86_MACHINE(pcms); 801 802 assert(MACHINE(pcms)->kernel_filename != NULL); 803 804 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 805 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 806 rom_set_fw(fw_cfg); 807 808 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 809 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 810 for (i = 0; i < nb_option_roms; i++) { 811 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 812 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 813 !strcmp(option_rom[i].name, "pvh.bin") || 814 !strcmp(option_rom[i].name, "multiboot.bin") || 815 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 816 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 817 } 818 x86ms->fw_cfg = fw_cfg; 819 } 820 821 #define PC_ROM_MIN_VGA 0xc0000 822 #define PC_ROM_MIN_OPTION 0xc8000 823 #define PC_ROM_MAX 0xe0000 824 #define PC_ROM_ALIGN 0x800 825 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 826 827 static hwaddr pc_above_4g_end(PCMachineState *pcms) 828 { 829 X86MachineState *x86ms = X86_MACHINE(pcms); 830 831 if (pcms->sgx_epc.size != 0) { 832 return sgx_epc_above_4g_end(&pcms->sgx_epc); 833 } 834 835 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 836 } 837 838 static void pc_get_device_memory_range(PCMachineState *pcms, 839 hwaddr *base, 840 ram_addr_t *device_mem_size) 841 { 842 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 843 MachineState *machine = MACHINE(pcms); 844 ram_addr_t size; 845 hwaddr addr; 846 847 size = machine->maxram_size - machine->ram_size; 848 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 849 850 if (pcmc->enforce_aligned_dimm) { 851 /* size device region assuming 1G page max alignment per slot */ 852 size += (1 * GiB) * machine->ram_slots; 853 } 854 855 *base = addr; 856 *device_mem_size = size; 857 } 858 859 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 860 { 861 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 862 hwaddr cxl_base; 863 ram_addr_t size; 864 865 if (pcmc->has_reserved_memory) { 866 pc_get_device_memory_range(pcms, &cxl_base, &size); 867 cxl_base += size; 868 } else { 869 cxl_base = pc_above_4g_end(pcms); 870 } 871 872 return cxl_base; 873 } 874 875 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 876 { 877 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 878 879 if (pcms->cxl_devices_state.fixed_windows) { 880 GList *it; 881 882 start = ROUND_UP(start, 256 * MiB); 883 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 884 CXLFixedWindow *fw = it->data; 885 start += fw->size; 886 } 887 } 888 889 return start; 890 } 891 892 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 893 { 894 X86CPU *cpu = X86_CPU(first_cpu); 895 896 /* 32-bit systems don't have hole64 thus return max CPU address */ 897 if (cpu->phys_bits <= 32) { 898 return ((hwaddr)1 << cpu->phys_bits) - 1; 899 } 900 901 return pc_pci_hole64_start() + pci_hole64_size - 1; 902 } 903 904 /* 905 * AMD systems with an IOMMU have an additional hole close to the 906 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 907 * on kernel version, VFIO may or may not let you DMA map those ranges. 908 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 909 * with certain memory sizes. It's also wrong to use those IOVA ranges 910 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 911 * The ranges reserved for Hyper-Transport are: 912 * 913 * FD_0000_0000h - FF_FFFF_FFFFh 914 * 915 * The ranges represent the following: 916 * 917 * Base Address Top Address Use 918 * 919 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 920 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 921 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 922 * FD_F910_0000h FD_F91F_FFFFh System Management 923 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 924 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 925 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 926 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 927 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 928 * FE_2000_0000h FF_FFFF_FFFFh Reserved 929 * 930 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 931 * Table 3: Special Address Controls (GPA) for more information. 932 */ 933 #define AMD_HT_START 0xfd00000000UL 934 #define AMD_HT_END 0xffffffffffUL 935 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 936 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 937 938 void pc_memory_init(PCMachineState *pcms, 939 MemoryRegion *system_memory, 940 MemoryRegion *rom_memory, 941 MemoryRegion **ram_memory, 942 uint64_t pci_hole64_size) 943 { 944 int linux_boot, i; 945 MemoryRegion *option_rom_mr; 946 MemoryRegion *ram_below_4g, *ram_above_4g; 947 FWCfgState *fw_cfg; 948 MachineState *machine = MACHINE(pcms); 949 MachineClass *mc = MACHINE_GET_CLASS(machine); 950 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 951 X86MachineState *x86ms = X86_MACHINE(pcms); 952 hwaddr maxphysaddr, maxusedaddr; 953 hwaddr cxl_base, cxl_resv_end = 0; 954 X86CPU *cpu = X86_CPU(first_cpu); 955 956 assert(machine->ram_size == x86ms->below_4g_mem_size + 957 x86ms->above_4g_mem_size); 958 959 linux_boot = (machine->kernel_filename != NULL); 960 961 /* 962 * The HyperTransport range close to the 1T boundary is unique to AMD 963 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 964 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 965 * older machine types (<= 7.0) for compatibility purposes. 966 */ 967 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 968 /* Bail out if max possible address does not cross HT range */ 969 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 970 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 971 } 972 973 /* 974 * Advertise the HT region if address space covers the reserved 975 * region or if we relocate. 976 */ 977 if (cpu->phys_bits >= 40) { 978 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 979 } 980 } 981 982 /* 983 * phys-bits is required to be appropriately configured 984 * to make sure max used GPA is reachable. 985 */ 986 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 987 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 988 if (maxphysaddr < maxusedaddr) { 989 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 990 " phys-bits too low (%u)", 991 maxphysaddr, maxusedaddr, cpu->phys_bits); 992 exit(EXIT_FAILURE); 993 } 994 995 /* 996 * Split single memory region and use aliases to address portions of it, 997 * done for backwards compatibility with older qemus. 998 */ 999 *ram_memory = machine->ram; 1000 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1001 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 1002 0, x86ms->below_4g_mem_size); 1003 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1004 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1005 if (x86ms->above_4g_mem_size > 0) { 1006 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1007 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1008 machine->ram, 1009 x86ms->below_4g_mem_size, 1010 x86ms->above_4g_mem_size); 1011 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1012 ram_above_4g); 1013 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1014 E820_RAM); 1015 } 1016 1017 if (pcms->sgx_epc.size != 0) { 1018 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1019 } 1020 1021 if (!pcmc->has_reserved_memory && 1022 (machine->ram_slots || 1023 (machine->maxram_size > machine->ram_size))) { 1024 1025 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1026 mc->name); 1027 exit(EXIT_FAILURE); 1028 } 1029 1030 /* always allocate the device memory information */ 1031 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1032 1033 /* initialize device memory address space */ 1034 if (pcmc->has_reserved_memory && 1035 (machine->ram_size < machine->maxram_size)) { 1036 ram_addr_t device_mem_size; 1037 1038 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1039 error_report("unsupported amount of memory slots: %"PRIu64, 1040 machine->ram_slots); 1041 exit(EXIT_FAILURE); 1042 } 1043 1044 if (QEMU_ALIGN_UP(machine->maxram_size, 1045 TARGET_PAGE_SIZE) != machine->maxram_size) { 1046 error_report("maximum memory size must by aligned to multiple of " 1047 "%d bytes", TARGET_PAGE_SIZE); 1048 exit(EXIT_FAILURE); 1049 } 1050 1051 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1052 1053 if ((machine->device_memory->base + device_mem_size) < 1054 device_mem_size) { 1055 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1056 machine->maxram_size); 1057 exit(EXIT_FAILURE); 1058 } 1059 1060 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1061 "device-memory", device_mem_size); 1062 memory_region_add_subregion(system_memory, machine->device_memory->base, 1063 &machine->device_memory->mr); 1064 } 1065 1066 if (pcms->cxl_devices_state.is_enabled) { 1067 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1068 hwaddr cxl_size = MiB; 1069 1070 cxl_base = pc_get_cxl_range_start(pcms); 1071 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1072 memory_region_add_subregion(system_memory, cxl_base, mr); 1073 cxl_resv_end = cxl_base + cxl_size; 1074 if (pcms->cxl_devices_state.fixed_windows) { 1075 hwaddr cxl_fmw_base; 1076 GList *it; 1077 1078 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1079 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1080 CXLFixedWindow *fw = it->data; 1081 1082 fw->base = cxl_fmw_base; 1083 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1084 "cxl-fixed-memory-region", fw->size); 1085 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1086 cxl_fmw_base += fw->size; 1087 cxl_resv_end = cxl_fmw_base; 1088 } 1089 } 1090 } 1091 1092 /* Initialize PC system firmware */ 1093 pc_system_firmware_init(pcms, rom_memory); 1094 1095 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1096 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1097 &error_fatal); 1098 if (pcmc->pci_enabled) { 1099 memory_region_set_readonly(option_rom_mr, true); 1100 } 1101 memory_region_add_subregion_overlap(rom_memory, 1102 PC_ROM_MIN_VGA, 1103 option_rom_mr, 1104 1); 1105 1106 fw_cfg = fw_cfg_arch_create(machine, 1107 x86ms->boot_cpus, x86ms->apic_id_limit); 1108 1109 rom_set_fw(fw_cfg); 1110 1111 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1112 uint64_t *val = g_malloc(sizeof(*val)); 1113 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1114 uint64_t res_mem_end = machine->device_memory->base; 1115 1116 if (!pcmc->broken_reserved_end) { 1117 res_mem_end += memory_region_size(&machine->device_memory->mr); 1118 } 1119 1120 if (pcms->cxl_devices_state.is_enabled) { 1121 res_mem_end = cxl_resv_end; 1122 } 1123 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1124 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1125 } 1126 1127 if (linux_boot) { 1128 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1129 pcmc->pvh_enabled, pcmc->legacy_no_rng_seed); 1130 } 1131 1132 for (i = 0; i < nb_option_roms; i++) { 1133 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1134 } 1135 x86ms->fw_cfg = fw_cfg; 1136 1137 /* Init default IOAPIC address space */ 1138 x86ms->ioapic_as = &address_space_memory; 1139 1140 /* Init ACPI memory hotplug IO base address */ 1141 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1142 } 1143 1144 /* 1145 * The 64bit pci hole starts after "above 4G RAM" and 1146 * potentially the space reserved for memory hotplug. 1147 */ 1148 uint64_t pc_pci_hole64_start(void) 1149 { 1150 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1151 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1152 MachineState *ms = MACHINE(pcms); 1153 uint64_t hole64_start = 0; 1154 ram_addr_t size = 0; 1155 1156 if (pcms->cxl_devices_state.is_enabled) { 1157 hole64_start = pc_get_cxl_range_end(pcms); 1158 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1159 pc_get_device_memory_range(pcms, &hole64_start, &size); 1160 if (!pcmc->broken_reserved_end) { 1161 hole64_start += size; 1162 } 1163 } else { 1164 hole64_start = pc_above_4g_end(pcms); 1165 } 1166 1167 return ROUND_UP(hole64_start, 1 * GiB); 1168 } 1169 1170 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1171 { 1172 DeviceState *dev = NULL; 1173 1174 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1175 if (pci_bus) { 1176 PCIDevice *pcidev = pci_vga_init(pci_bus); 1177 dev = pcidev ? &pcidev->qdev : NULL; 1178 } else if (isa_bus) { 1179 ISADevice *isadev = isa_vga_init(isa_bus); 1180 dev = isadev ? DEVICE(isadev) : NULL; 1181 } 1182 rom_reset_order_override(); 1183 return dev; 1184 } 1185 1186 static const MemoryRegionOps ioport80_io_ops = { 1187 .write = ioport80_write, 1188 .read = ioport80_read, 1189 .endianness = DEVICE_NATIVE_ENDIAN, 1190 .impl = { 1191 .min_access_size = 1, 1192 .max_access_size = 1, 1193 }, 1194 }; 1195 1196 static const MemoryRegionOps ioportF0_io_ops = { 1197 .write = ioportF0_write, 1198 .read = ioportF0_read, 1199 .endianness = DEVICE_NATIVE_ENDIAN, 1200 .impl = { 1201 .min_access_size = 1, 1202 .max_access_size = 1, 1203 }, 1204 }; 1205 1206 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1207 bool create_i8042, bool no_vmport) 1208 { 1209 int i; 1210 DriveInfo *fd[MAX_FD]; 1211 qemu_irq *a20_line; 1212 ISADevice *fdc, *i8042, *port92, *vmmouse; 1213 1214 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1215 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1216 1217 for (i = 0; i < MAX_FD; i++) { 1218 fd[i] = drive_get(IF_FLOPPY, 0, i); 1219 create_fdctrl |= !!fd[i]; 1220 } 1221 if (create_fdctrl) { 1222 fdc = isa_new(TYPE_ISA_FDC); 1223 if (fdc) { 1224 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1225 isa_fdc_init_drives(fdc, fd); 1226 } 1227 } 1228 1229 if (!create_i8042) { 1230 return; 1231 } 1232 1233 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1234 if (!no_vmport) { 1235 isa_create_simple(isa_bus, TYPE_VMPORT); 1236 vmmouse = isa_try_new("vmmouse"); 1237 } else { 1238 vmmouse = NULL; 1239 } 1240 if (vmmouse) { 1241 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1242 &error_abort); 1243 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1244 } 1245 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1246 1247 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1248 i8042_setup_a20_line(i8042, a20_line[0]); 1249 qdev_connect_gpio_out_named(DEVICE(port92), 1250 PORT92_A20_LINE, 0, a20_line[1]); 1251 g_free(a20_line); 1252 } 1253 1254 void pc_basic_device_init(struct PCMachineState *pcms, 1255 ISABus *isa_bus, qemu_irq *gsi, 1256 ISADevice **rtc_state, 1257 bool create_fdctrl, 1258 uint32_t hpet_irqs) 1259 { 1260 int i; 1261 DeviceState *hpet = NULL; 1262 int pit_isa_irq = 0; 1263 qemu_irq pit_alt_irq = NULL; 1264 qemu_irq rtc_irq = NULL; 1265 ISADevice *pit = NULL; 1266 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1267 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1268 X86MachineState *x86ms = X86_MACHINE(pcms); 1269 1270 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1271 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1272 1273 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1274 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1275 1276 /* 1277 * Check if an HPET shall be created. 1278 * 1279 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1280 * when the HPET wants to take over. Thus we have to disable the latter. 1281 */ 1282 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1283 kvm_has_pit_state2())) { 1284 hpet = qdev_try_new(TYPE_HPET); 1285 if (!hpet) { 1286 error_report("couldn't create HPET device"); 1287 exit(1); 1288 } 1289 /* 1290 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1291 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1292 * IRQ2. 1293 */ 1294 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1295 HPET_INTCAP, NULL); 1296 if (!compat) { 1297 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1298 } 1299 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1300 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1301 1302 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1303 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1304 } 1305 pit_isa_irq = -1; 1306 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1307 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1308 } 1309 *rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq)); 1310 1311 qemu_register_boot_set(pc_boot_set, *rtc_state); 1312 1313 if (!xen_enabled() && 1314 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1315 if (kvm_pit_in_kernel()) { 1316 pit = kvm_pit_init(isa_bus, 0x40); 1317 } else { 1318 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1319 } 1320 if (hpet) { 1321 /* connect PIT to output control line of the HPET */ 1322 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1323 } 1324 pcspk_init(pcms->pcspk, isa_bus, pit); 1325 } 1326 1327 /* Super I/O */ 1328 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1329 pcms->vmport != ON_OFF_AUTO_ON); 1330 } 1331 1332 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1333 { 1334 int i; 1335 1336 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1337 for (i = 0; i < nb_nics; i++) { 1338 NICInfo *nd = &nd_table[i]; 1339 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1340 1341 if (g_str_equal(model, "ne2k_isa")) { 1342 pc_init_ne2k_isa(isa_bus, nd); 1343 } else { 1344 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1345 } 1346 } 1347 rom_reset_order_override(); 1348 } 1349 1350 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1351 { 1352 qemu_irq *i8259; 1353 1354 if (kvm_pic_in_kernel()) { 1355 i8259 = kvm_i8259_init(isa_bus); 1356 } else if (xen_enabled()) { 1357 i8259 = xen_interrupt_controller_init(); 1358 } else { 1359 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1360 } 1361 1362 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1363 i8259_irqs[i] = i8259[i]; 1364 } 1365 1366 g_free(i8259); 1367 } 1368 1369 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1370 Error **errp) 1371 { 1372 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1373 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1374 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1375 const MachineState *ms = MACHINE(hotplug_dev); 1376 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1377 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1378 Error *local_err = NULL; 1379 1380 /* 1381 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1382 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1383 * addition to cover this case. 1384 */ 1385 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1386 error_setg(errp, 1387 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1388 return; 1389 } 1390 1391 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1392 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1393 return; 1394 } 1395 1396 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1397 if (local_err) { 1398 error_propagate(errp, local_err); 1399 return; 1400 } 1401 1402 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1403 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1404 } 1405 1406 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1407 DeviceState *dev, Error **errp) 1408 { 1409 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1410 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1411 MachineState *ms = MACHINE(hotplug_dev); 1412 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1413 1414 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1415 1416 if (is_nvdimm) { 1417 nvdimm_plug(ms->nvdimms_state); 1418 } 1419 1420 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1421 } 1422 1423 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1424 DeviceState *dev, Error **errp) 1425 { 1426 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1427 1428 /* 1429 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1430 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1431 * addition to cover this case. 1432 */ 1433 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1434 error_setg(errp, 1435 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1436 return; 1437 } 1438 1439 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1440 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1441 return; 1442 } 1443 1444 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1445 errp); 1446 } 1447 1448 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1449 DeviceState *dev, Error **errp) 1450 { 1451 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1452 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1453 Error *local_err = NULL; 1454 1455 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1456 if (local_err) { 1457 goto out; 1458 } 1459 1460 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1461 qdev_unrealize(dev); 1462 out: 1463 error_propagate(errp, local_err); 1464 } 1465 1466 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1467 DeviceState *dev, Error **errp) 1468 { 1469 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1470 Error *local_err = NULL; 1471 1472 if (!hotplug_dev2 && dev->hotplugged) { 1473 /* 1474 * Without a bus hotplug handler, we cannot control the plug/unplug 1475 * order. We should never reach this point when hotplugging on x86, 1476 * however, better add a safety net. 1477 */ 1478 error_setg(errp, "hotplug of virtio based memory devices not supported" 1479 " on this bus."); 1480 return; 1481 } 1482 /* 1483 * First, see if we can plug this memory device at all. If that 1484 * succeeds, branch of to the actual hotplug handler. 1485 */ 1486 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1487 &local_err); 1488 if (!local_err && hotplug_dev2) { 1489 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1490 } 1491 error_propagate(errp, local_err); 1492 } 1493 1494 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1495 DeviceState *dev, Error **errp) 1496 { 1497 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1498 Error *local_err = NULL; 1499 1500 /* 1501 * Plug the memory device first and then branch off to the actual 1502 * hotplug handler. If that one fails, we can easily undo the memory 1503 * device bits. 1504 */ 1505 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1506 if (hotplug_dev2) { 1507 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1508 if (local_err) { 1509 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1510 } 1511 } 1512 error_propagate(errp, local_err); 1513 } 1514 1515 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1516 DeviceState *dev, Error **errp) 1517 { 1518 /* We don't support hot unplug of virtio based memory devices */ 1519 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1520 } 1521 1522 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1523 DeviceState *dev, Error **errp) 1524 { 1525 /* We don't support hot unplug of virtio based memory devices */ 1526 } 1527 1528 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1529 DeviceState *dev, Error **errp) 1530 { 1531 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1532 pc_memory_pre_plug(hotplug_dev, dev, errp); 1533 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1534 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1535 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1536 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1537 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1538 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1539 /* Declare the APIC range as the reserved MSI region */ 1540 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1541 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1542 1543 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1544 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1545 resv_prop_str, errp); 1546 g_free(resv_prop_str); 1547 } 1548 1549 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1550 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1551 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1552 1553 if (pcms->iommu) { 1554 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1555 "for x86 yet."); 1556 return; 1557 } 1558 pcms->iommu = dev; 1559 } 1560 } 1561 1562 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1563 DeviceState *dev, Error **errp) 1564 { 1565 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1566 pc_memory_plug(hotplug_dev, dev, errp); 1567 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1568 x86_cpu_plug(hotplug_dev, dev, errp); 1569 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1570 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1571 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1572 } 1573 } 1574 1575 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1576 DeviceState *dev, Error **errp) 1577 { 1578 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1579 pc_memory_unplug_request(hotplug_dev, dev, errp); 1580 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1581 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1582 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1583 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1584 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1585 } else { 1586 error_setg(errp, "acpi: device unplug request for not supported device" 1587 " type: %s", object_get_typename(OBJECT(dev))); 1588 } 1589 } 1590 1591 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1592 DeviceState *dev, Error **errp) 1593 { 1594 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1595 pc_memory_unplug(hotplug_dev, dev, errp); 1596 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1597 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1598 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1599 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1600 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1601 } else { 1602 error_setg(errp, "acpi: device unplug for not supported device" 1603 " type: %s", object_get_typename(OBJECT(dev))); 1604 } 1605 } 1606 1607 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1608 DeviceState *dev) 1609 { 1610 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1611 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1612 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1613 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1614 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1615 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1616 return HOTPLUG_HANDLER(machine); 1617 } 1618 1619 return NULL; 1620 } 1621 1622 static void 1623 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1624 const char *name, void *opaque, 1625 Error **errp) 1626 { 1627 MachineState *ms = MACHINE(obj); 1628 int64_t value = 0; 1629 1630 if (ms->device_memory) { 1631 value = memory_region_size(&ms->device_memory->mr); 1632 } 1633 1634 visit_type_int(v, name, &value, errp); 1635 } 1636 1637 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1638 void *opaque, Error **errp) 1639 { 1640 PCMachineState *pcms = PC_MACHINE(obj); 1641 OnOffAuto vmport = pcms->vmport; 1642 1643 visit_type_OnOffAuto(v, name, &vmport, errp); 1644 } 1645 1646 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1647 void *opaque, Error **errp) 1648 { 1649 PCMachineState *pcms = PC_MACHINE(obj); 1650 1651 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1652 } 1653 1654 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1655 { 1656 PCMachineState *pcms = PC_MACHINE(obj); 1657 1658 return pcms->smbus_enabled; 1659 } 1660 1661 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(obj); 1664 1665 pcms->smbus_enabled = value; 1666 } 1667 1668 static bool pc_machine_get_sata(Object *obj, Error **errp) 1669 { 1670 PCMachineState *pcms = PC_MACHINE(obj); 1671 1672 return pcms->sata_enabled; 1673 } 1674 1675 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1676 { 1677 PCMachineState *pcms = PC_MACHINE(obj); 1678 1679 pcms->sata_enabled = value; 1680 } 1681 1682 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1683 { 1684 PCMachineState *pcms = PC_MACHINE(obj); 1685 1686 return pcms->hpet_enabled; 1687 } 1688 1689 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1690 { 1691 PCMachineState *pcms = PC_MACHINE(obj); 1692 1693 pcms->hpet_enabled = value; 1694 } 1695 1696 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1697 { 1698 PCMachineState *pcms = PC_MACHINE(obj); 1699 1700 return pcms->i8042_enabled; 1701 } 1702 1703 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1704 { 1705 PCMachineState *pcms = PC_MACHINE(obj); 1706 1707 pcms->i8042_enabled = value; 1708 } 1709 1710 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1711 { 1712 PCMachineState *pcms = PC_MACHINE(obj); 1713 1714 return pcms->default_bus_bypass_iommu; 1715 } 1716 1717 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1718 Error **errp) 1719 { 1720 PCMachineState *pcms = PC_MACHINE(obj); 1721 1722 pcms->default_bus_bypass_iommu = value; 1723 } 1724 1725 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1726 void *opaque, Error **errp) 1727 { 1728 PCMachineState *pcms = PC_MACHINE(obj); 1729 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1730 1731 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1732 } 1733 1734 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1735 void *opaque, Error **errp) 1736 { 1737 PCMachineState *pcms = PC_MACHINE(obj); 1738 1739 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1740 } 1741 1742 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1743 const char *name, void *opaque, 1744 Error **errp) 1745 { 1746 PCMachineState *pcms = PC_MACHINE(obj); 1747 uint64_t value = pcms->max_ram_below_4g; 1748 1749 visit_type_size(v, name, &value, errp); 1750 } 1751 1752 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1753 const char *name, void *opaque, 1754 Error **errp) 1755 { 1756 PCMachineState *pcms = PC_MACHINE(obj); 1757 uint64_t value; 1758 1759 if (!visit_type_size(v, name, &value, errp)) { 1760 return; 1761 } 1762 if (value > 4 * GiB) { 1763 error_setg(errp, 1764 "Machine option 'max-ram-below-4g=%"PRIu64 1765 "' expects size less than or equal to 4G", value); 1766 return; 1767 } 1768 1769 if (value < 1 * MiB) { 1770 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1771 "BIOS may not work with less than 1MiB", value); 1772 } 1773 1774 pcms->max_ram_below_4g = value; 1775 } 1776 1777 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1778 const char *name, void *opaque, 1779 Error **errp) 1780 { 1781 PCMachineState *pcms = PC_MACHINE(obj); 1782 uint64_t value = pcms->max_fw_size; 1783 1784 visit_type_size(v, name, &value, errp); 1785 } 1786 1787 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1788 const char *name, void *opaque, 1789 Error **errp) 1790 { 1791 PCMachineState *pcms = PC_MACHINE(obj); 1792 uint64_t value; 1793 1794 if (!visit_type_size(v, name, &value, errp)) { 1795 return; 1796 } 1797 1798 /* 1799 * We don't have a theoretically justifiable exact lower bound on the base 1800 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1801 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1802 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1803 * size. 1804 */ 1805 if (value > 16 * MiB) { 1806 error_setg(errp, 1807 "User specified max allowed firmware size %" PRIu64 " is " 1808 "greater than 16MiB. If combined firwmare size exceeds " 1809 "16MiB the system may not boot, or experience intermittent" 1810 "stability issues.", 1811 value); 1812 return; 1813 } 1814 1815 pcms->max_fw_size = value; 1816 } 1817 1818 1819 static void pc_machine_initfn(Object *obj) 1820 { 1821 PCMachineState *pcms = PC_MACHINE(obj); 1822 1823 #ifdef CONFIG_VMPORT 1824 pcms->vmport = ON_OFF_AUTO_AUTO; 1825 #else 1826 pcms->vmport = ON_OFF_AUTO_OFF; 1827 #endif /* CONFIG_VMPORT */ 1828 pcms->max_ram_below_4g = 0; /* use default */ 1829 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1830 1831 /* acpi build is enabled by default if machine supports it */ 1832 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1833 pcms->smbus_enabled = true; 1834 pcms->sata_enabled = true; 1835 pcms->i8042_enabled = true; 1836 pcms->max_fw_size = 8 * MiB; 1837 #ifdef CONFIG_HPET 1838 pcms->hpet_enabled = true; 1839 #endif 1840 pcms->default_bus_bypass_iommu = false; 1841 1842 pc_system_flash_create(pcms); 1843 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1844 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1845 OBJECT(pcms->pcspk), "audiodev"); 1846 cxl_machine_init(obj, &pcms->cxl_devices_state); 1847 } 1848 1849 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1850 { 1851 CPUState *cs; 1852 X86CPU *cpu; 1853 1854 qemu_devices_reset(reason); 1855 1856 /* Reset APIC after devices have been reset to cancel 1857 * any changes that qemu_devices_reset() might have done. 1858 */ 1859 CPU_FOREACH(cs) { 1860 cpu = X86_CPU(cs); 1861 1862 x86_cpu_after_reset(cpu); 1863 } 1864 } 1865 1866 static void pc_machine_wakeup(MachineState *machine) 1867 { 1868 cpu_synchronize_all_states(); 1869 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1870 cpu_synchronize_all_post_reset(); 1871 } 1872 1873 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1874 { 1875 X86IOMMUState *iommu = x86_iommu_get_default(); 1876 IntelIOMMUState *intel_iommu; 1877 1878 if (iommu && 1879 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1880 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1881 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1882 if (!intel_iommu->caching_mode) { 1883 error_setg(errp, "Device assignment is not allowed without " 1884 "enabling caching-mode=on for Intel IOMMU."); 1885 return false; 1886 } 1887 } 1888 1889 return true; 1890 } 1891 1892 static void pc_machine_class_init(ObjectClass *oc, void *data) 1893 { 1894 MachineClass *mc = MACHINE_CLASS(oc); 1895 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1896 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1897 1898 pcmc->pci_enabled = true; 1899 pcmc->has_acpi_build = true; 1900 pcmc->rsdp_in_ram = true; 1901 pcmc->smbios_defaults = true; 1902 pcmc->smbios_uuid_encoded = true; 1903 pcmc->gigabyte_align = true; 1904 pcmc->has_reserved_memory = true; 1905 pcmc->kvmclock_enabled = true; 1906 pcmc->enforce_aligned_dimm = true; 1907 pcmc->enforce_amd_1tb_hole = true; 1908 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1909 * to be used at the moment, 32K should be enough for a while. */ 1910 pcmc->acpi_data_size = 0x20000 + 0x8000; 1911 pcmc->pvh_enabled = true; 1912 pcmc->kvmclock_create_always = true; 1913 assert(!mc->get_hotplug_handler); 1914 mc->get_hotplug_handler = pc_get_hotplug_handler; 1915 mc->hotplug_allowed = pc_hotplug_allowed; 1916 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1917 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1918 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1919 mc->auto_enable_numa_with_memhp = true; 1920 mc->auto_enable_numa_with_memdev = true; 1921 mc->has_hotpluggable_cpus = true; 1922 mc->default_boot_order = "cad"; 1923 mc->block_default_type = IF_IDE; 1924 mc->max_cpus = 255; 1925 mc->reset = pc_machine_reset; 1926 mc->wakeup = pc_machine_wakeup; 1927 hc->pre_plug = pc_machine_device_pre_plug_cb; 1928 hc->plug = pc_machine_device_plug_cb; 1929 hc->unplug_request = pc_machine_device_unplug_request_cb; 1930 hc->unplug = pc_machine_device_unplug_cb; 1931 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1932 mc->nvdimm_supported = true; 1933 mc->smp_props.dies_supported = true; 1934 mc->default_ram_id = "pc.ram"; 1935 1936 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1937 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1938 NULL, NULL); 1939 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1940 "Maximum ram below the 4G boundary (32bit boundary)"); 1941 1942 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1943 pc_machine_get_device_memory_region_size, NULL, 1944 NULL, NULL); 1945 1946 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1947 pc_machine_get_vmport, pc_machine_set_vmport, 1948 NULL, NULL); 1949 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1950 "Enable vmport (pc & q35)"); 1951 1952 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1953 pc_machine_get_smbus, pc_machine_set_smbus); 1954 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1955 "Enable/disable system management bus"); 1956 1957 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1958 pc_machine_get_sata, pc_machine_set_sata); 1959 object_class_property_set_description(oc, PC_MACHINE_SATA, 1960 "Enable/disable Serial ATA bus"); 1961 1962 object_class_property_add_bool(oc, "hpet", 1963 pc_machine_get_hpet, pc_machine_set_hpet); 1964 object_class_property_set_description(oc, "hpet", 1965 "Enable/disable high precision event timer emulation"); 1966 1967 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1968 pc_machine_get_i8042, pc_machine_set_i8042); 1969 1970 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1971 pc_machine_get_default_bus_bypass_iommu, 1972 pc_machine_set_default_bus_bypass_iommu); 1973 1974 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1975 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1976 NULL, NULL); 1977 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1978 "Maximum combined firmware size"); 1979 1980 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1981 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1982 NULL, NULL); 1983 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1984 "SMBIOS Entry Point type [32, 64]"); 1985 } 1986 1987 static const TypeInfo pc_machine_info = { 1988 .name = TYPE_PC_MACHINE, 1989 .parent = TYPE_X86_MACHINE, 1990 .abstract = true, 1991 .instance_size = sizeof(PCMachineState), 1992 .instance_init = pc_machine_initfn, 1993 .class_size = sizeof(PCMachineClass), 1994 .class_init = pc_machine_class_init, 1995 .interfaces = (InterfaceInfo[]) { 1996 { TYPE_HOTPLUG_HANDLER }, 1997 { } 1998 }, 1999 }; 2000 2001 static void pc_machine_register_types(void) 2002 { 2003 type_register_static(&pc_machine_info); 2004 } 2005 2006 type_init(pc_machine_register_types) 2007