1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "exec/address-spaces.h" 69 #include "sysemu/arch_init.h" 70 #include "qemu/bitmap.h" 71 #include "qemu/config-file.h" 72 #include "qemu/error-report.h" 73 #include "qemu/option.h" 74 #include "qemu/cutils.h" 75 #include "hw/acpi/acpi.h" 76 #include "hw/acpi/cpu_hotplug.h" 77 #include "hw/boards.h" 78 #include "acpi-build.h" 79 #include "hw/mem/pc-dimm.h" 80 #include "hw/mem/nvdimm.h" 81 #include "qapi/error.h" 82 #include "qapi/qapi-visit-common.h" 83 #include "qapi/visitor.h" 84 #include "hw/core/cpu.h" 85 #include "hw/usb.h" 86 #include "hw/i386/intel_iommu.h" 87 #include "hw/net/ne2000-isa.h" 88 #include "standard-headers/asm-x86/bootparam.h" 89 #include "hw/virtio/virtio-pmem-pci.h" 90 #include "hw/virtio/virtio-mem-pci.h" 91 #include "hw/mem/memory-device.h" 92 #include "sysemu/replay.h" 93 #include "qapi/qmp/qerror.h" 94 #include "e820_memory_layout.h" 95 #include "fw_cfg.h" 96 #include "trace.h" 97 #include CONFIG_DEVICES 98 99 GlobalProperty pc_compat_5_2[] = { 100 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 101 }; 102 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 103 104 GlobalProperty pc_compat_5_1[] = { 105 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 106 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 107 }; 108 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 109 110 GlobalProperty pc_compat_5_0[] = { 111 }; 112 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 113 114 GlobalProperty pc_compat_4_2[] = { 115 { "mch", "smbase-smram", "off" }, 116 }; 117 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 118 119 GlobalProperty pc_compat_4_1[] = {}; 120 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 121 122 GlobalProperty pc_compat_4_0[] = {}; 123 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 124 125 GlobalProperty pc_compat_3_1[] = { 126 { "intel-iommu", "dma-drain", "off" }, 127 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 128 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 129 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 130 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 131 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 132 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 133 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 134 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 135 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 136 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 137 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 138 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 139 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 140 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 142 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 143 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 144 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 145 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 146 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 147 }; 148 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 149 150 GlobalProperty pc_compat_3_0[] = { 151 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 152 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 153 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 154 }; 155 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 156 157 GlobalProperty pc_compat_2_12[] = { 158 { TYPE_X86_CPU, "legacy-cache", "on" }, 159 { TYPE_X86_CPU, "topoext", "off" }, 160 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 161 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 162 }; 163 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 164 165 GlobalProperty pc_compat_2_11[] = { 166 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 168 }; 169 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 170 171 GlobalProperty pc_compat_2_10[] = { 172 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 173 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 174 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 175 }; 176 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 177 178 GlobalProperty pc_compat_2_9[] = { 179 { "mch", "extended-tseg-mbytes", "0" }, 180 }; 181 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 182 183 GlobalProperty pc_compat_2_8[] = { 184 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 185 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 186 { "ICH9-LPC", "x-smi-broadcast", "off" }, 187 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 188 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 189 }; 190 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 191 192 GlobalProperty pc_compat_2_7[] = { 193 { TYPE_X86_CPU, "l3-cache", "off" }, 194 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 195 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 196 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 197 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 198 { "isa-pcspk", "migrate", "off" }, 199 }; 200 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 201 202 GlobalProperty pc_compat_2_6[] = { 203 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 204 { "vmxnet3", "romfile", "" }, 205 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 206 { "apic-common", "legacy-instance-id", "on", } 207 }; 208 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 209 210 GlobalProperty pc_compat_2_5[] = {}; 211 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 212 213 GlobalProperty pc_compat_2_4[] = { 214 PC_CPU_MODEL_IDS("2.4.0") 215 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 216 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 217 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 218 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 219 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 220 { TYPE_X86_CPU, "check", "off" }, 221 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 222 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 223 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 224 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 225 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 226 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 227 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 228 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 229 }; 230 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 231 232 GlobalProperty pc_compat_2_3[] = { 233 PC_CPU_MODEL_IDS("2.3.0") 234 { TYPE_X86_CPU, "arat", "off" }, 235 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 236 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 237 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 238 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 239 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 240 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 241 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 242 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 254 }; 255 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 256 257 GlobalProperty pc_compat_2_2[] = { 258 PC_CPU_MODEL_IDS("2.2.0") 259 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 274 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 275 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 276 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 277 }; 278 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 279 280 GlobalProperty pc_compat_2_1[] = { 281 PC_CPU_MODEL_IDS("2.1.0") 282 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 283 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 284 }; 285 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 286 287 GlobalProperty pc_compat_2_0[] = { 288 PC_CPU_MODEL_IDS("2.0.0") 289 { "virtio-scsi-pci", "any_layout", "off" }, 290 { "PIIX4_PM", "memory-hotplug-support", "off" }, 291 { "apic", "version", "0x11" }, 292 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 293 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 294 { "pci-serial", "prog_if", "0" }, 295 { "pci-serial-2x", "prog_if", "0" }, 296 { "pci-serial-4x", "prog_if", "0" }, 297 { "virtio-net-pci", "guest_announce", "off" }, 298 { "ICH9-LPC", "memory-hotplug-support", "off" }, 299 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 300 { "ioh3420", COMPAT_PROP_PCP, "off" }, 301 }; 302 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 303 304 GlobalProperty pc_compat_1_7[] = { 305 PC_CPU_MODEL_IDS("1.7.0") 306 { TYPE_USB_DEVICE, "msos-desc", "no" }, 307 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 308 { "hpet", HPET_INTCAP, "4" }, 309 }; 310 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 311 312 GlobalProperty pc_compat_1_6[] = { 313 PC_CPU_MODEL_IDS("1.6.0") 314 { "e1000", "mitigation", "off" }, 315 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 316 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 317 { "i440FX-pcihost", "short_root_bus", "1" }, 318 { "q35-pcihost", "short_root_bus", "1" }, 319 }; 320 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 321 322 GlobalProperty pc_compat_1_5[] = { 323 PC_CPU_MODEL_IDS("1.5.0") 324 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 325 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 326 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 327 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 328 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 329 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 330 { "virtio-net-pci", "any_layout", "off" }, 331 { TYPE_X86_CPU, "pmu", "on" }, 332 { "i440FX-pcihost", "short_root_bus", "0" }, 333 { "q35-pcihost", "short_root_bus", "0" }, 334 }; 335 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 336 337 GlobalProperty pc_compat_1_4[] = { 338 PC_CPU_MODEL_IDS("1.4.0") 339 { "scsi-hd", "discard_granularity", "0" }, 340 { "scsi-cd", "discard_granularity", "0" }, 341 { "ide-hd", "discard_granularity", "0" }, 342 { "ide-cd", "discard_granularity", "0" }, 343 { "virtio-blk-pci", "discard_granularity", "0" }, 344 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 345 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 346 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 347 { "e1000", "romfile", "pxe-e1000.rom" }, 348 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 349 { "pcnet", "romfile", "pxe-pcnet.rom" }, 350 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 351 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 352 { "486-" TYPE_X86_CPU, "model", "0" }, 353 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 354 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 355 }; 356 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 357 358 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 359 { 360 GSIState *s; 361 362 s = g_new0(GSIState, 1); 363 if (kvm_ioapic_in_kernel()) { 364 kvm_pc_setup_irq_routing(pci_enabled); 365 } 366 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 367 368 return s; 369 } 370 371 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 372 unsigned size) 373 { 374 } 375 376 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 377 { 378 return 0xffffffffffffffffULL; 379 } 380 381 /* MSDOS compatibility mode FPU exception support */ 382 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 383 unsigned size) 384 { 385 if (tcg_enabled()) { 386 cpu_set_ignne(); 387 } 388 } 389 390 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 391 { 392 return 0xffffffffffffffffULL; 393 } 394 395 /* PC cmos mappings */ 396 397 #define REG_EQUIPMENT_BYTE 0x14 398 399 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 400 int16_t cylinders, int8_t heads, int8_t sectors) 401 { 402 rtc_set_memory(s, type_ofs, 47); 403 rtc_set_memory(s, info_ofs, cylinders); 404 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 405 rtc_set_memory(s, info_ofs + 2, heads); 406 rtc_set_memory(s, info_ofs + 3, 0xff); 407 rtc_set_memory(s, info_ofs + 4, 0xff); 408 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 409 rtc_set_memory(s, info_ofs + 6, cylinders); 410 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 411 rtc_set_memory(s, info_ofs + 8, sectors); 412 } 413 414 /* convert boot_device letter to something recognizable by the bios */ 415 static int boot_device2nibble(char boot_device) 416 { 417 switch(boot_device) { 418 case 'a': 419 case 'b': 420 return 0x01; /* floppy boot */ 421 case 'c': 422 return 0x02; /* hard drive boot */ 423 case 'd': 424 return 0x03; /* CD-ROM boot */ 425 case 'n': 426 return 0x04; /* Network boot */ 427 } 428 return 0; 429 } 430 431 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 432 { 433 #define PC_MAX_BOOT_DEVICES 3 434 int nbds, bds[3] = { 0, }; 435 int i; 436 437 nbds = strlen(boot_device); 438 if (nbds > PC_MAX_BOOT_DEVICES) { 439 error_setg(errp, "Too many boot devices for PC"); 440 return; 441 } 442 for (i = 0; i < nbds; i++) { 443 bds[i] = boot_device2nibble(boot_device[i]); 444 if (bds[i] == 0) { 445 error_setg(errp, "Invalid boot device for PC: '%c'", 446 boot_device[i]); 447 return; 448 } 449 } 450 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 451 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 452 } 453 454 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 455 { 456 set_boot_dev(opaque, boot_device, errp); 457 } 458 459 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 460 { 461 int val, nb, i; 462 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 463 FLOPPY_DRIVE_TYPE_NONE }; 464 465 /* floppy type */ 466 if (floppy) { 467 for (i = 0; i < 2; i++) { 468 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 469 } 470 } 471 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 472 cmos_get_fd_drive_type(fd_type[1]); 473 rtc_set_memory(rtc_state, 0x10, val); 474 475 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 476 nb = 0; 477 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 478 nb++; 479 } 480 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 481 nb++; 482 } 483 switch (nb) { 484 case 0: 485 break; 486 case 1: 487 val |= 0x01; /* 1 drive, ready for boot */ 488 break; 489 case 2: 490 val |= 0x41; /* 2 drives, ready for boot */ 491 break; 492 } 493 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 494 } 495 496 typedef struct pc_cmos_init_late_arg { 497 ISADevice *rtc_state; 498 BusState *idebus[2]; 499 } pc_cmos_init_late_arg; 500 501 typedef struct check_fdc_state { 502 ISADevice *floppy; 503 bool multiple; 504 } CheckFdcState; 505 506 static int check_fdc(Object *obj, void *opaque) 507 { 508 CheckFdcState *state = opaque; 509 Object *fdc; 510 uint32_t iobase; 511 Error *local_err = NULL; 512 513 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 514 if (!fdc) { 515 return 0; 516 } 517 518 iobase = object_property_get_uint(obj, "iobase", &local_err); 519 if (local_err || iobase != 0x3f0) { 520 error_free(local_err); 521 return 0; 522 } 523 524 if (state->floppy) { 525 state->multiple = true; 526 } else { 527 state->floppy = ISA_DEVICE(obj); 528 } 529 return 0; 530 } 531 532 static const char * const fdc_container_path[] = { 533 "/unattached", "/peripheral", "/peripheral-anon" 534 }; 535 536 /* 537 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 538 * and ACPI objects. 539 */ 540 ISADevice *pc_find_fdc0(void) 541 { 542 int i; 543 Object *container; 544 CheckFdcState state = { 0 }; 545 546 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 547 container = container_get(qdev_get_machine(), fdc_container_path[i]); 548 object_child_foreach(container, check_fdc, &state); 549 } 550 551 if (state.multiple) { 552 warn_report("multiple floppy disk controllers with " 553 "iobase=0x3f0 have been found"); 554 error_printf("the one being picked for CMOS setup might not reflect " 555 "your intent"); 556 } 557 558 return state.floppy; 559 } 560 561 static void pc_cmos_init_late(void *opaque) 562 { 563 pc_cmos_init_late_arg *arg = opaque; 564 ISADevice *s = arg->rtc_state; 565 int16_t cylinders; 566 int8_t heads, sectors; 567 int val; 568 int i, trans; 569 570 val = 0; 571 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 572 &cylinders, &heads, §ors) >= 0) { 573 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 574 val |= 0xf0; 575 } 576 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 577 &cylinders, &heads, §ors) >= 0) { 578 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 579 val |= 0x0f; 580 } 581 rtc_set_memory(s, 0x12, val); 582 583 val = 0; 584 for (i = 0; i < 4; i++) { 585 /* NOTE: ide_get_geometry() returns the physical 586 geometry. It is always such that: 1 <= sects <= 63, 1 587 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 588 geometry can be different if a translation is done. */ 589 if (arg->idebus[i / 2] && 590 ide_get_geometry(arg->idebus[i / 2], i % 2, 591 &cylinders, &heads, §ors) >= 0) { 592 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 593 assert((trans & ~3) == 0); 594 val |= trans << (i * 2); 595 } 596 } 597 rtc_set_memory(s, 0x39, val); 598 599 pc_cmos_init_floppy(s, pc_find_fdc0()); 600 601 qemu_unregister_reset(pc_cmos_init_late, opaque); 602 } 603 604 void pc_cmos_init(PCMachineState *pcms, 605 BusState *idebus0, BusState *idebus1, 606 ISADevice *s) 607 { 608 int val; 609 static pc_cmos_init_late_arg arg; 610 X86MachineState *x86ms = X86_MACHINE(pcms); 611 612 /* various important CMOS locations needed by PC/Bochs bios */ 613 614 /* memory size */ 615 /* base memory (first MiB) */ 616 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 617 rtc_set_memory(s, 0x15, val); 618 rtc_set_memory(s, 0x16, val >> 8); 619 /* extended memory (next 64MiB) */ 620 if (x86ms->below_4g_mem_size > 1 * MiB) { 621 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 622 } else { 623 val = 0; 624 } 625 if (val > 65535) 626 val = 65535; 627 rtc_set_memory(s, 0x17, val); 628 rtc_set_memory(s, 0x18, val >> 8); 629 rtc_set_memory(s, 0x30, val); 630 rtc_set_memory(s, 0x31, val >> 8); 631 /* memory between 16MiB and 4GiB */ 632 if (x86ms->below_4g_mem_size > 16 * MiB) { 633 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 634 } else { 635 val = 0; 636 } 637 if (val > 65535) 638 val = 65535; 639 rtc_set_memory(s, 0x34, val); 640 rtc_set_memory(s, 0x35, val >> 8); 641 /* memory above 4GiB */ 642 val = x86ms->above_4g_mem_size / 65536; 643 rtc_set_memory(s, 0x5b, val); 644 rtc_set_memory(s, 0x5c, val >> 8); 645 rtc_set_memory(s, 0x5d, val >> 16); 646 647 object_property_add_link(OBJECT(pcms), "rtc_state", 648 TYPE_ISA_DEVICE, 649 (Object **)&x86ms->rtc, 650 object_property_allow_set_link, 651 OBJ_PROP_LINK_STRONG); 652 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 653 &error_abort); 654 655 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 656 657 val = 0; 658 val |= 0x02; /* FPU is there */ 659 val |= 0x04; /* PS/2 mouse installed */ 660 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 661 662 /* hard drives and FDC */ 663 arg.rtc_state = s; 664 arg.idebus[0] = idebus0; 665 arg.idebus[1] = idebus1; 666 qemu_register_reset(pc_cmos_init_late, &arg); 667 } 668 669 static void handle_a20_line_change(void *opaque, int irq, int level) 670 { 671 X86CPU *cpu = opaque; 672 673 /* XXX: send to all CPUs ? */ 674 /* XXX: add logic to handle multiple A20 line sources */ 675 x86_cpu_set_a20(cpu, level); 676 } 677 678 #define NE2000_NB_MAX 6 679 680 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 681 0x280, 0x380 }; 682 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 683 684 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 685 { 686 static int nb_ne2k = 0; 687 688 if (nb_ne2k == NE2000_NB_MAX) 689 return; 690 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 691 ne2000_irq[nb_ne2k], nd); 692 nb_ne2k++; 693 } 694 695 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 696 { 697 X86CPU *cpu = opaque; 698 699 if (level) { 700 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 701 } 702 } 703 704 /* 705 * This function is very similar to smp_parse() 706 * in hw/core/machine.c but includes CPU die support. 707 */ 708 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 709 { 710 X86MachineState *x86ms = X86_MACHINE(ms); 711 712 if (opts) { 713 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 714 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 715 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 716 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 717 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 718 719 /* compute missing values, prefer sockets over cores over threads */ 720 if (cpus == 0 || sockets == 0) { 721 cores = cores > 0 ? cores : 1; 722 threads = threads > 0 ? threads : 1; 723 if (cpus == 0) { 724 sockets = sockets > 0 ? sockets : 1; 725 cpus = cores * threads * dies * sockets; 726 } else { 727 ms->smp.max_cpus = 728 qemu_opt_get_number(opts, "maxcpus", cpus); 729 sockets = ms->smp.max_cpus / (cores * threads * dies); 730 } 731 } else if (cores == 0) { 732 threads = threads > 0 ? threads : 1; 733 cores = cpus / (sockets * dies * threads); 734 cores = cores > 0 ? cores : 1; 735 } else if (threads == 0) { 736 threads = cpus / (cores * dies * sockets); 737 threads = threads > 0 ? threads : 1; 738 } else if (sockets * dies * cores * threads < cpus) { 739 error_report("cpu topology: " 740 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 741 "smp_cpus (%u)", 742 sockets, dies, cores, threads, cpus); 743 exit(1); 744 } 745 746 ms->smp.max_cpus = 747 qemu_opt_get_number(opts, "maxcpus", cpus); 748 749 if (ms->smp.max_cpus < cpus) { 750 error_report("maxcpus must be equal to or greater than smp"); 751 exit(1); 752 } 753 754 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 755 error_report("Invalid CPU topology deprecated: " 756 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 757 "!= maxcpus (%u)", 758 sockets, dies, cores, threads, 759 ms->smp.max_cpus); 760 exit(1); 761 } 762 763 ms->smp.cpus = cpus; 764 ms->smp.cores = cores; 765 ms->smp.threads = threads; 766 ms->smp.sockets = sockets; 767 x86ms->smp_dies = dies; 768 } 769 770 if (ms->smp.cpus > 1) { 771 Error *blocker = NULL; 772 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 773 replay_add_blocker(blocker); 774 } 775 } 776 777 static 778 void pc_machine_done(Notifier *notifier, void *data) 779 { 780 PCMachineState *pcms = container_of(notifier, 781 PCMachineState, machine_done); 782 X86MachineState *x86ms = X86_MACHINE(pcms); 783 784 /* set the number of CPUs */ 785 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 786 787 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 788 789 acpi_setup(); 790 if (x86ms->fw_cfg) { 791 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 792 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 793 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 794 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 795 } 796 797 798 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 799 !kvm_irqchip_in_kernel()) { 800 error_report("current -smp configuration requires kernel " 801 "irqchip support."); 802 exit(EXIT_FAILURE); 803 } 804 } 805 806 void pc_guest_info_init(PCMachineState *pcms) 807 { 808 int i; 809 MachineState *ms = MACHINE(pcms); 810 X86MachineState *x86ms = X86_MACHINE(pcms); 811 812 x86ms->apic_xrupt_override = true; 813 pcms->numa_nodes = ms->numa_state->num_nodes; 814 pcms->node_mem = g_malloc0(pcms->numa_nodes * 815 sizeof *pcms->node_mem); 816 for (i = 0; i < ms->numa_state->num_nodes; i++) { 817 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 818 } 819 820 pcms->machine_done.notify = pc_machine_done; 821 qemu_add_machine_init_done_notifier(&pcms->machine_done); 822 } 823 824 /* setup pci memory address space mapping into system address space */ 825 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 826 MemoryRegion *pci_address_space) 827 { 828 /* Set to lower priority than RAM */ 829 memory_region_add_subregion_overlap(system_memory, 0x0, 830 pci_address_space, -1); 831 } 832 833 void xen_load_linux(PCMachineState *pcms) 834 { 835 int i; 836 FWCfgState *fw_cfg; 837 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 838 X86MachineState *x86ms = X86_MACHINE(pcms); 839 840 assert(MACHINE(pcms)->kernel_filename != NULL); 841 842 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 843 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 844 rom_set_fw(fw_cfg); 845 846 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 847 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 848 for (i = 0; i < nb_option_roms; i++) { 849 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 850 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 851 !strcmp(option_rom[i].name, "pvh.bin") || 852 !strcmp(option_rom[i].name, "multiboot.bin")); 853 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 854 } 855 x86ms->fw_cfg = fw_cfg; 856 } 857 858 void pc_memory_init(PCMachineState *pcms, 859 MemoryRegion *system_memory, 860 MemoryRegion *rom_memory, 861 MemoryRegion **ram_memory) 862 { 863 int linux_boot, i; 864 MemoryRegion *option_rom_mr; 865 MemoryRegion *ram_below_4g, *ram_above_4g; 866 FWCfgState *fw_cfg; 867 MachineState *machine = MACHINE(pcms); 868 MachineClass *mc = MACHINE_GET_CLASS(machine); 869 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 870 X86MachineState *x86ms = X86_MACHINE(pcms); 871 872 assert(machine->ram_size == x86ms->below_4g_mem_size + 873 x86ms->above_4g_mem_size); 874 875 linux_boot = (machine->kernel_filename != NULL); 876 877 /* 878 * Split single memory region and use aliases to address portions of it, 879 * done for backwards compatibility with older qemus. 880 */ 881 *ram_memory = machine->ram; 882 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 883 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 884 0, x86ms->below_4g_mem_size); 885 memory_region_add_subregion(system_memory, 0, ram_below_4g); 886 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 887 if (x86ms->above_4g_mem_size > 0) { 888 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 889 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 890 machine->ram, 891 x86ms->below_4g_mem_size, 892 x86ms->above_4g_mem_size); 893 memory_region_add_subregion(system_memory, 0x100000000ULL, 894 ram_above_4g); 895 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 896 } 897 898 if (!pcmc->has_reserved_memory && 899 (machine->ram_slots || 900 (machine->maxram_size > machine->ram_size))) { 901 902 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 903 mc->name); 904 exit(EXIT_FAILURE); 905 } 906 907 /* always allocate the device memory information */ 908 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 909 910 /* initialize device memory address space */ 911 if (pcmc->has_reserved_memory && 912 (machine->ram_size < machine->maxram_size)) { 913 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 914 915 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 916 error_report("unsupported amount of memory slots: %"PRIu64, 917 machine->ram_slots); 918 exit(EXIT_FAILURE); 919 } 920 921 if (QEMU_ALIGN_UP(machine->maxram_size, 922 TARGET_PAGE_SIZE) != machine->maxram_size) { 923 error_report("maximum memory size must by aligned to multiple of " 924 "%d bytes", TARGET_PAGE_SIZE); 925 exit(EXIT_FAILURE); 926 } 927 928 machine->device_memory->base = 929 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 930 931 if (pcmc->enforce_aligned_dimm) { 932 /* size device region assuming 1G page max alignment per slot */ 933 device_mem_size += (1 * GiB) * machine->ram_slots; 934 } 935 936 if ((machine->device_memory->base + device_mem_size) < 937 device_mem_size) { 938 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 939 machine->maxram_size); 940 exit(EXIT_FAILURE); 941 } 942 943 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 944 "device-memory", device_mem_size); 945 memory_region_add_subregion(system_memory, machine->device_memory->base, 946 &machine->device_memory->mr); 947 } 948 949 /* Initialize PC system firmware */ 950 pc_system_firmware_init(pcms, rom_memory); 951 952 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 953 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 954 &error_fatal); 955 if (pcmc->pci_enabled) { 956 memory_region_set_readonly(option_rom_mr, true); 957 } 958 memory_region_add_subregion_overlap(rom_memory, 959 PC_ROM_MIN_VGA, 960 option_rom_mr, 961 1); 962 963 fw_cfg = fw_cfg_arch_create(machine, 964 x86ms->boot_cpus, x86ms->apic_id_limit); 965 966 rom_set_fw(fw_cfg); 967 968 if (pcmc->has_reserved_memory && machine->device_memory->base) { 969 uint64_t *val = g_malloc(sizeof(*val)); 970 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 971 uint64_t res_mem_end = machine->device_memory->base; 972 973 if (!pcmc->broken_reserved_end) { 974 res_mem_end += memory_region_size(&machine->device_memory->mr); 975 } 976 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 977 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 978 } 979 980 if (linux_boot) { 981 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 982 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 983 } 984 985 for (i = 0; i < nb_option_roms; i++) { 986 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 987 } 988 x86ms->fw_cfg = fw_cfg; 989 990 /* Init default IOAPIC address space */ 991 x86ms->ioapic_as = &address_space_memory; 992 993 /* Init ACPI memory hotplug IO base address */ 994 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 995 } 996 997 /* 998 * The 64bit pci hole starts after "above 4G RAM" and 999 * potentially the space reserved for memory hotplug. 1000 */ 1001 uint64_t pc_pci_hole64_start(void) 1002 { 1003 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1004 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1005 MachineState *ms = MACHINE(pcms); 1006 X86MachineState *x86ms = X86_MACHINE(pcms); 1007 uint64_t hole64_start = 0; 1008 1009 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1010 hole64_start = ms->device_memory->base; 1011 if (!pcmc->broken_reserved_end) { 1012 hole64_start += memory_region_size(&ms->device_memory->mr); 1013 } 1014 } else { 1015 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1016 } 1017 1018 return ROUND_UP(hole64_start, 1 * GiB); 1019 } 1020 1021 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1022 { 1023 DeviceState *dev = NULL; 1024 1025 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1026 if (pci_bus) { 1027 PCIDevice *pcidev = pci_vga_init(pci_bus); 1028 dev = pcidev ? &pcidev->qdev : NULL; 1029 } else if (isa_bus) { 1030 ISADevice *isadev = isa_vga_init(isa_bus); 1031 dev = isadev ? DEVICE(isadev) : NULL; 1032 } 1033 rom_reset_order_override(); 1034 return dev; 1035 } 1036 1037 static const MemoryRegionOps ioport80_io_ops = { 1038 .write = ioport80_write, 1039 .read = ioport80_read, 1040 .endianness = DEVICE_NATIVE_ENDIAN, 1041 .impl = { 1042 .min_access_size = 1, 1043 .max_access_size = 1, 1044 }, 1045 }; 1046 1047 static const MemoryRegionOps ioportF0_io_ops = { 1048 .write = ioportF0_write, 1049 .read = ioportF0_read, 1050 .endianness = DEVICE_NATIVE_ENDIAN, 1051 .impl = { 1052 .min_access_size = 1, 1053 .max_access_size = 1, 1054 }, 1055 }; 1056 1057 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1058 { 1059 int i; 1060 DriveInfo *fd[MAX_FD]; 1061 qemu_irq *a20_line; 1062 ISADevice *fdc, *i8042, *port92, *vmmouse; 1063 1064 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1065 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1066 1067 for (i = 0; i < MAX_FD; i++) { 1068 fd[i] = drive_get(IF_FLOPPY, 0, i); 1069 create_fdctrl |= !!fd[i]; 1070 } 1071 if (create_fdctrl) { 1072 fdc = isa_new(TYPE_ISA_FDC); 1073 if (fdc) { 1074 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1075 isa_fdc_init_drives(fdc, fd); 1076 } 1077 } 1078 1079 i8042 = isa_create_simple(isa_bus, "i8042"); 1080 if (!no_vmport) { 1081 isa_create_simple(isa_bus, TYPE_VMPORT); 1082 vmmouse = isa_try_new("vmmouse"); 1083 } else { 1084 vmmouse = NULL; 1085 } 1086 if (vmmouse) { 1087 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1088 &error_abort); 1089 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1090 } 1091 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1092 1093 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1094 i8042_setup_a20_line(i8042, a20_line[0]); 1095 qdev_connect_gpio_out_named(DEVICE(port92), 1096 PORT92_A20_LINE, 0, a20_line[1]); 1097 g_free(a20_line); 1098 } 1099 1100 void pc_basic_device_init(struct PCMachineState *pcms, 1101 ISABus *isa_bus, qemu_irq *gsi, 1102 ISADevice **rtc_state, 1103 bool create_fdctrl, 1104 uint32_t hpet_irqs) 1105 { 1106 int i; 1107 DeviceState *hpet = NULL; 1108 int pit_isa_irq = 0; 1109 qemu_irq pit_alt_irq = NULL; 1110 qemu_irq rtc_irq = NULL; 1111 ISADevice *pit = NULL; 1112 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1113 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1114 1115 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1116 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1117 1118 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1119 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1120 1121 /* 1122 * Check if an HPET shall be created. 1123 * 1124 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1125 * when the HPET wants to take over. Thus we have to disable the latter. 1126 */ 1127 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1128 kvm_has_pit_state2())) { 1129 hpet = qdev_try_new(TYPE_HPET); 1130 if (!hpet) { 1131 error_report("couldn't create HPET device"); 1132 exit(1); 1133 } 1134 /* 1135 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1136 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1137 * IRQ2. 1138 */ 1139 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1140 HPET_INTCAP, NULL); 1141 if (!compat) { 1142 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1143 } 1144 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1145 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1146 1147 for (i = 0; i < GSI_NUM_PINS; i++) { 1148 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1149 } 1150 pit_isa_irq = -1; 1151 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1152 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1153 } 1154 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1155 1156 qemu_register_boot_set(pc_boot_set, *rtc_state); 1157 1158 if (!xen_enabled() && pcms->pit_enabled) { 1159 if (kvm_pit_in_kernel()) { 1160 pit = kvm_pit_init(isa_bus, 0x40); 1161 } else { 1162 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1163 } 1164 if (hpet) { 1165 /* connect PIT to output control line of the HPET */ 1166 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1167 } 1168 pcspk_init(pcms->pcspk, isa_bus, pit); 1169 } 1170 1171 i8257_dma_init(isa_bus, 0); 1172 1173 /* Super I/O */ 1174 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1175 } 1176 1177 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1178 { 1179 int i; 1180 1181 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1182 for (i = 0; i < nb_nics; i++) { 1183 NICInfo *nd = &nd_table[i]; 1184 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1185 1186 if (g_str_equal(model, "ne2k_isa")) { 1187 pc_init_ne2k_isa(isa_bus, nd); 1188 } else { 1189 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1190 } 1191 } 1192 rom_reset_order_override(); 1193 } 1194 1195 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1196 { 1197 qemu_irq *i8259; 1198 1199 if (kvm_pic_in_kernel()) { 1200 i8259 = kvm_i8259_init(isa_bus); 1201 } else if (xen_enabled()) { 1202 i8259 = xen_interrupt_controller_init(); 1203 } else { 1204 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1205 } 1206 1207 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1208 i8259_irqs[i] = i8259[i]; 1209 } 1210 1211 g_free(i8259); 1212 } 1213 1214 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1215 Error **errp) 1216 { 1217 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1218 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1219 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1220 const MachineState *ms = MACHINE(hotplug_dev); 1221 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1222 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1223 Error *local_err = NULL; 1224 1225 /* 1226 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1227 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1228 * addition to cover this case. 1229 */ 1230 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1231 error_setg(errp, 1232 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1233 return; 1234 } 1235 1236 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1237 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1238 return; 1239 } 1240 1241 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1242 if (local_err) { 1243 error_propagate(errp, local_err); 1244 return; 1245 } 1246 1247 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1248 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1249 } 1250 1251 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1252 DeviceState *dev, Error **errp) 1253 { 1254 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1255 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1256 MachineState *ms = MACHINE(hotplug_dev); 1257 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1258 1259 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1260 1261 if (is_nvdimm) { 1262 nvdimm_plug(ms->nvdimms_state); 1263 } 1264 1265 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1266 } 1267 1268 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1269 DeviceState *dev, Error **errp) 1270 { 1271 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1272 1273 /* 1274 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1275 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1276 * addition to cover this case. 1277 */ 1278 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1279 error_setg(errp, 1280 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1281 return; 1282 } 1283 1284 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1285 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1286 return; 1287 } 1288 1289 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1290 errp); 1291 } 1292 1293 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1294 DeviceState *dev, Error **errp) 1295 { 1296 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1297 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1298 Error *local_err = NULL; 1299 1300 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1301 if (local_err) { 1302 goto out; 1303 } 1304 1305 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1306 qdev_unrealize(dev); 1307 out: 1308 error_propagate(errp, local_err); 1309 } 1310 1311 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1312 DeviceState *dev, Error **errp) 1313 { 1314 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1315 Error *local_err = NULL; 1316 1317 if (!hotplug_dev2 && dev->hotplugged) { 1318 /* 1319 * Without a bus hotplug handler, we cannot control the plug/unplug 1320 * order. We should never reach this point when hotplugging on x86, 1321 * however, better add a safety net. 1322 */ 1323 error_setg(errp, "hotplug of virtio based memory devices not supported" 1324 " on this bus."); 1325 return; 1326 } 1327 /* 1328 * First, see if we can plug this memory device at all. If that 1329 * succeeds, branch of to the actual hotplug handler. 1330 */ 1331 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1332 &local_err); 1333 if (!local_err && hotplug_dev2) { 1334 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1335 } 1336 error_propagate(errp, local_err); 1337 } 1338 1339 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1340 DeviceState *dev, Error **errp) 1341 { 1342 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1343 Error *local_err = NULL; 1344 1345 /* 1346 * Plug the memory device first and then branch off to the actual 1347 * hotplug handler. If that one fails, we can easily undo the memory 1348 * device bits. 1349 */ 1350 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1351 if (hotplug_dev2) { 1352 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1353 if (local_err) { 1354 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1355 } 1356 } 1357 error_propagate(errp, local_err); 1358 } 1359 1360 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1361 DeviceState *dev, Error **errp) 1362 { 1363 /* We don't support hot unplug of virtio based memory devices */ 1364 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1365 } 1366 1367 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 /* We don't support hot unplug of virtio based memory devices */ 1371 } 1372 1373 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1374 DeviceState *dev, Error **errp) 1375 { 1376 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1377 pc_memory_pre_plug(hotplug_dev, dev, errp); 1378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1379 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1380 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1381 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1382 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1383 } 1384 } 1385 1386 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1387 DeviceState *dev, Error **errp) 1388 { 1389 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1390 pc_memory_plug(hotplug_dev, dev, errp); 1391 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1392 x86_cpu_plug(hotplug_dev, dev, errp); 1393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1394 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1395 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1396 } 1397 } 1398 1399 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1400 DeviceState *dev, Error **errp) 1401 { 1402 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1403 pc_memory_unplug_request(hotplug_dev, dev, errp); 1404 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1405 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1406 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1407 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1408 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1409 } else { 1410 error_setg(errp, "acpi: device unplug request for not supported device" 1411 " type: %s", object_get_typename(OBJECT(dev))); 1412 } 1413 } 1414 1415 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1416 DeviceState *dev, Error **errp) 1417 { 1418 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1419 pc_memory_unplug(hotplug_dev, dev, errp); 1420 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1421 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1422 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1423 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1424 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1425 } else { 1426 error_setg(errp, "acpi: device unplug for not supported device" 1427 " type: %s", object_get_typename(OBJECT(dev))); 1428 } 1429 } 1430 1431 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1432 DeviceState *dev) 1433 { 1434 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1435 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1436 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1437 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1438 return HOTPLUG_HANDLER(machine); 1439 } 1440 1441 return NULL; 1442 } 1443 1444 static void 1445 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1446 const char *name, void *opaque, 1447 Error **errp) 1448 { 1449 MachineState *ms = MACHINE(obj); 1450 int64_t value = 0; 1451 1452 if (ms->device_memory) { 1453 value = memory_region_size(&ms->device_memory->mr); 1454 } 1455 1456 visit_type_int(v, name, &value, errp); 1457 } 1458 1459 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1460 void *opaque, Error **errp) 1461 { 1462 PCMachineState *pcms = PC_MACHINE(obj); 1463 OnOffAuto vmport = pcms->vmport; 1464 1465 visit_type_OnOffAuto(v, name, &vmport, errp); 1466 } 1467 1468 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1469 void *opaque, Error **errp) 1470 { 1471 PCMachineState *pcms = PC_MACHINE(obj); 1472 1473 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1474 } 1475 1476 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1477 { 1478 PCMachineState *pcms = PC_MACHINE(obj); 1479 1480 return pcms->smbus_enabled; 1481 } 1482 1483 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1484 { 1485 PCMachineState *pcms = PC_MACHINE(obj); 1486 1487 pcms->smbus_enabled = value; 1488 } 1489 1490 static bool pc_machine_get_sata(Object *obj, Error **errp) 1491 { 1492 PCMachineState *pcms = PC_MACHINE(obj); 1493 1494 return pcms->sata_enabled; 1495 } 1496 1497 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1498 { 1499 PCMachineState *pcms = PC_MACHINE(obj); 1500 1501 pcms->sata_enabled = value; 1502 } 1503 1504 static bool pc_machine_get_pit(Object *obj, Error **errp) 1505 { 1506 PCMachineState *pcms = PC_MACHINE(obj); 1507 1508 return pcms->pit_enabled; 1509 } 1510 1511 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1512 { 1513 PCMachineState *pcms = PC_MACHINE(obj); 1514 1515 pcms->pit_enabled = value; 1516 } 1517 1518 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1519 { 1520 PCMachineState *pcms = PC_MACHINE(obj); 1521 1522 return pcms->hpet_enabled; 1523 } 1524 1525 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1526 { 1527 PCMachineState *pcms = PC_MACHINE(obj); 1528 1529 pcms->hpet_enabled = value; 1530 } 1531 1532 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1533 const char *name, void *opaque, 1534 Error **errp) 1535 { 1536 PCMachineState *pcms = PC_MACHINE(obj); 1537 uint64_t value = pcms->max_ram_below_4g; 1538 1539 visit_type_size(v, name, &value, errp); 1540 } 1541 1542 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1543 const char *name, void *opaque, 1544 Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 uint64_t value; 1548 1549 if (!visit_type_size(v, name, &value, errp)) { 1550 return; 1551 } 1552 if (value > 4 * GiB) { 1553 error_setg(errp, 1554 "Machine option 'max-ram-below-4g=%"PRIu64 1555 "' expects size less than or equal to 4G", value); 1556 return; 1557 } 1558 1559 if (value < 1 * MiB) { 1560 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1561 "BIOS may not work with less than 1MiB", value); 1562 } 1563 1564 pcms->max_ram_below_4g = value; 1565 } 1566 1567 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1568 const char *name, void *opaque, 1569 Error **errp) 1570 { 1571 PCMachineState *pcms = PC_MACHINE(obj); 1572 uint64_t value = pcms->max_fw_size; 1573 1574 visit_type_size(v, name, &value, errp); 1575 } 1576 1577 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1578 const char *name, void *opaque, 1579 Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 Error *error = NULL; 1583 uint64_t value; 1584 1585 visit_type_size(v, name, &value, &error); 1586 if (error) { 1587 error_propagate(errp, error); 1588 return; 1589 } 1590 1591 /* 1592 * We don't have a theoretically justifiable exact lower bound on the base 1593 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1594 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1595 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1596 * size. 1597 */ 1598 if (value > 16 * MiB) { 1599 error_setg(errp, 1600 "User specified max allowed firmware size %" PRIu64 " is " 1601 "greater than 16MiB. If combined firwmare size exceeds " 1602 "16MiB the system may not boot, or experience intermittent" 1603 "stability issues.", 1604 value); 1605 return; 1606 } 1607 1608 pcms->max_fw_size = value; 1609 } 1610 1611 1612 static void pc_machine_initfn(Object *obj) 1613 { 1614 PCMachineState *pcms = PC_MACHINE(obj); 1615 1616 #ifdef CONFIG_VMPORT 1617 pcms->vmport = ON_OFF_AUTO_AUTO; 1618 #else 1619 pcms->vmport = ON_OFF_AUTO_OFF; 1620 #endif /* CONFIG_VMPORT */ 1621 pcms->max_ram_below_4g = 0; /* use default */ 1622 /* acpi build is enabled by default if machine supports it */ 1623 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1624 pcms->smbus_enabled = true; 1625 pcms->sata_enabled = true; 1626 pcms->pit_enabled = true; 1627 pcms->max_fw_size = 8 * MiB; 1628 #ifdef CONFIG_HPET 1629 pcms->hpet_enabled = true; 1630 #endif 1631 1632 pc_system_flash_create(pcms); 1633 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1634 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1635 OBJECT(pcms->pcspk), "audiodev"); 1636 } 1637 1638 static void pc_machine_reset(MachineState *machine) 1639 { 1640 CPUState *cs; 1641 X86CPU *cpu; 1642 1643 qemu_devices_reset(); 1644 1645 /* Reset APIC after devices have been reset to cancel 1646 * any changes that qemu_devices_reset() might have done. 1647 */ 1648 CPU_FOREACH(cs) { 1649 cpu = X86_CPU(cs); 1650 1651 if (cpu->apic_state) { 1652 device_legacy_reset(cpu->apic_state); 1653 } 1654 } 1655 } 1656 1657 static void pc_machine_wakeup(MachineState *machine) 1658 { 1659 cpu_synchronize_all_states(); 1660 pc_machine_reset(machine); 1661 cpu_synchronize_all_post_reset(); 1662 } 1663 1664 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1665 { 1666 X86IOMMUState *iommu = x86_iommu_get_default(); 1667 IntelIOMMUState *intel_iommu; 1668 1669 if (iommu && 1670 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1671 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1672 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1673 if (!intel_iommu->caching_mode) { 1674 error_setg(errp, "Device assignment is not allowed without " 1675 "enabling caching-mode=on for Intel IOMMU."); 1676 return false; 1677 } 1678 } 1679 1680 return true; 1681 } 1682 1683 static void pc_machine_class_init(ObjectClass *oc, void *data) 1684 { 1685 MachineClass *mc = MACHINE_CLASS(oc); 1686 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1687 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1688 1689 pcmc->pci_enabled = true; 1690 pcmc->has_acpi_build = true; 1691 pcmc->rsdp_in_ram = true; 1692 pcmc->smbios_defaults = true; 1693 pcmc->smbios_uuid_encoded = true; 1694 pcmc->gigabyte_align = true; 1695 pcmc->has_reserved_memory = true; 1696 pcmc->kvmclock_enabled = true; 1697 pcmc->enforce_aligned_dimm = true; 1698 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1699 * to be used at the moment, 32K should be enough for a while. */ 1700 pcmc->acpi_data_size = 0x20000 + 0x8000; 1701 pcmc->linuxboot_dma_enabled = true; 1702 pcmc->pvh_enabled = true; 1703 pcmc->kvmclock_create_always = true; 1704 assert(!mc->get_hotplug_handler); 1705 mc->get_hotplug_handler = pc_get_hotplug_handler; 1706 mc->hotplug_allowed = pc_hotplug_allowed; 1707 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1708 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1709 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1710 mc->auto_enable_numa_with_memhp = true; 1711 mc->auto_enable_numa_with_memdev = true; 1712 mc->has_hotpluggable_cpus = true; 1713 mc->default_boot_order = "cad"; 1714 mc->smp_parse = pc_smp_parse; 1715 mc->block_default_type = IF_IDE; 1716 mc->max_cpus = 255; 1717 mc->reset = pc_machine_reset; 1718 mc->wakeup = pc_machine_wakeup; 1719 hc->pre_plug = pc_machine_device_pre_plug_cb; 1720 hc->plug = pc_machine_device_plug_cb; 1721 hc->unplug_request = pc_machine_device_unplug_request_cb; 1722 hc->unplug = pc_machine_device_unplug_cb; 1723 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1724 mc->nvdimm_supported = true; 1725 mc->default_ram_id = "pc.ram"; 1726 1727 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1728 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1729 NULL, NULL); 1730 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1731 "Maximum ram below the 4G boundary (32bit boundary)"); 1732 1733 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1734 pc_machine_get_device_memory_region_size, NULL, 1735 NULL, NULL); 1736 1737 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1738 pc_machine_get_vmport, pc_machine_set_vmport, 1739 NULL, NULL); 1740 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1741 "Enable vmport (pc & q35)"); 1742 1743 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1744 pc_machine_get_smbus, pc_machine_set_smbus); 1745 1746 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1747 pc_machine_get_sata, pc_machine_set_sata); 1748 1749 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1750 pc_machine_get_pit, pc_machine_set_pit); 1751 1752 object_class_property_add_bool(oc, "hpet", 1753 pc_machine_get_hpet, pc_machine_set_hpet); 1754 1755 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1756 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1757 NULL, NULL); 1758 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1759 "Maximum combined firmware size"); 1760 } 1761 1762 static const TypeInfo pc_machine_info = { 1763 .name = TYPE_PC_MACHINE, 1764 .parent = TYPE_X86_MACHINE, 1765 .abstract = true, 1766 .instance_size = sizeof(PCMachineState), 1767 .instance_init = pc_machine_initfn, 1768 .class_size = sizeof(PCMachineClass), 1769 .class_init = pc_machine_class_init, 1770 .interfaces = (InterfaceInfo[]) { 1771 { TYPE_HOTPLUG_HANDLER }, 1772 { } 1773 }, 1774 }; 1775 1776 static void pc_machine_register_types(void) 1777 { 1778 type_register_static(&pc_machine_info); 1779 } 1780 1781 type_init(pc_machine_register_types) 1782