1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide/internal.h" 37 #include "hw/ide/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/intc/ioapic.h" 51 #include "hw/timer/i8254.h" 52 #include "hw/input/i8042.h" 53 #include "hw/irq.h" 54 #include "hw/audio/pcspk.h" 55 #include "hw/pci/msi.h" 56 #include "hw/sysbus.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/tcg.h" 59 #include "sysemu/numa.h" 60 #include "sysemu/kvm.h" 61 #include "sysemu/xen.h" 62 #include "sysemu/reset.h" 63 #include "sysemu/runstate.h" 64 #include "kvm/kvm_i386.h" 65 #include "hw/xen/xen.h" 66 #include "hw/xen/start_info.h" 67 #include "ui/qemu-spice.h" 68 #include "exec/memory.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/cxl/cxl.h" 80 #include "hw/cxl/cxl_host.h" 81 #include "qapi/error.h" 82 #include "qapi/qapi-visit-common.h" 83 #include "qapi/qapi-visit-machine.h" 84 #include "qapi/visitor.h" 85 #include "hw/core/cpu.h" 86 #include "hw/usb.h" 87 #include "hw/i386/intel_iommu.h" 88 #include "hw/net/ne2000-isa.h" 89 #include "standard-headers/asm-x86/bootparam.h" 90 #include "hw/virtio/virtio-iommu.h" 91 #include "hw/virtio/virtio-pmem-pci.h" 92 #include "hw/virtio/virtio-mem-pci.h" 93 #include "hw/i386/kvm/xen_overlay.h" 94 #include "hw/i386/kvm/xen_evtchn.h" 95 #include "hw/i386/kvm/xen_gnttab.h" 96 #include "hw/i386/kvm/xen_xenstore.h" 97 #include "hw/mem/memory-device.h" 98 #include "sysemu/replay.h" 99 #include "target/i386/cpu.h" 100 #include "e820_memory_layout.h" 101 #include "fw_cfg.h" 102 #include "trace.h" 103 #include CONFIG_DEVICES 104 105 #ifdef CONFIG_XEN_EMU 106 #include "hw/xen/xen-legacy-backend.h" 107 #include "hw/xen/xen-bus.h" 108 #endif 109 110 /* 111 * Helper for setting model-id for CPU models that changed model-id 112 * depending on QEMU versions up to QEMU 2.4. 113 */ 114 #define PC_CPU_MODEL_IDS(v) \ 115 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 116 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 117 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 118 119 GlobalProperty pc_compat_8_0[] = { 120 { "virtio-mem", "unplugged-inaccessible", "auto" }, 121 }; 122 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 123 124 GlobalProperty pc_compat_7_2[] = { 125 { "ICH9-LPC", "noreboot", "true" }, 126 }; 127 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 128 129 GlobalProperty pc_compat_7_1[] = {}; 130 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 131 132 GlobalProperty pc_compat_7_0[] = {}; 133 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 134 135 GlobalProperty pc_compat_6_2[] = { 136 { "virtio-mem", "unplugged-inaccessible", "off" }, 137 }; 138 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 139 140 GlobalProperty pc_compat_6_1[] = { 141 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 142 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 143 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 144 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 145 }; 146 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 147 148 GlobalProperty pc_compat_6_0[] = { 149 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 150 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 151 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 152 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 153 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 154 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 155 }; 156 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 157 158 GlobalProperty pc_compat_5_2[] = { 159 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 160 }; 161 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 162 163 GlobalProperty pc_compat_5_1[] = { 164 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 165 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 166 }; 167 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 168 169 GlobalProperty pc_compat_5_0[] = { 170 }; 171 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 172 173 GlobalProperty pc_compat_4_2[] = { 174 { "mch", "smbase-smram", "off" }, 175 }; 176 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 177 178 GlobalProperty pc_compat_4_1[] = {}; 179 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 180 181 GlobalProperty pc_compat_4_0[] = {}; 182 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 183 184 GlobalProperty pc_compat_3_1[] = { 185 { "intel-iommu", "dma-drain", "off" }, 186 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 187 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 188 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 189 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 190 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 191 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 192 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 193 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 194 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 195 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 196 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 197 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 198 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 199 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 200 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 201 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 202 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 203 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 204 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 205 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 206 }; 207 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 208 209 GlobalProperty pc_compat_3_0[] = { 210 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 211 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 212 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 213 }; 214 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 215 216 GlobalProperty pc_compat_2_12[] = { 217 { TYPE_X86_CPU, "legacy-cache", "on" }, 218 { TYPE_X86_CPU, "topoext", "off" }, 219 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 220 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 221 }; 222 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 223 224 GlobalProperty pc_compat_2_11[] = { 225 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 226 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 227 }; 228 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 229 230 GlobalProperty pc_compat_2_10[] = { 231 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 232 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 233 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 234 }; 235 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 236 237 GlobalProperty pc_compat_2_9[] = { 238 { "mch", "extended-tseg-mbytes", "0" }, 239 }; 240 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 241 242 GlobalProperty pc_compat_2_8[] = { 243 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 244 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 245 { "ICH9-LPC", "x-smi-broadcast", "off" }, 246 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 247 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 248 }; 249 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 250 251 GlobalProperty pc_compat_2_7[] = { 252 { TYPE_X86_CPU, "l3-cache", "off" }, 253 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 254 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 255 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 256 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 257 { "isa-pcspk", "migrate", "off" }, 258 }; 259 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 260 261 GlobalProperty pc_compat_2_6[] = { 262 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 263 { "vmxnet3", "romfile", "" }, 264 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 265 { "apic-common", "legacy-instance-id", "on", } 266 }; 267 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 268 269 GlobalProperty pc_compat_2_5[] = {}; 270 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 271 272 GlobalProperty pc_compat_2_4[] = { 273 PC_CPU_MODEL_IDS("2.4.0") 274 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 275 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 276 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 277 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 278 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 279 { TYPE_X86_CPU, "check", "off" }, 280 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 281 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 282 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 283 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 284 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 285 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 286 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 287 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 288 }; 289 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 290 291 GlobalProperty pc_compat_2_3[] = { 292 PC_CPU_MODEL_IDS("2.3.0") 293 { TYPE_X86_CPU, "arat", "off" }, 294 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 295 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 296 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 297 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 298 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 299 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 300 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 301 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 302 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 303 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 304 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 305 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 306 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 307 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 308 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 309 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 310 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 311 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 312 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 313 }; 314 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 315 316 GlobalProperty pc_compat_2_2[] = { 317 PC_CPU_MODEL_IDS("2.2.0") 318 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 319 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 320 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 321 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 322 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 323 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 324 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 325 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 326 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 327 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 328 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 329 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 330 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 331 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 332 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 333 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 334 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 335 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 336 }; 337 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 338 339 GlobalProperty pc_compat_2_1[] = { 340 PC_CPU_MODEL_IDS("2.1.0") 341 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 342 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 343 }; 344 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 345 346 GlobalProperty pc_compat_2_0[] = { 347 PC_CPU_MODEL_IDS("2.0.0") 348 { "virtio-scsi-pci", "any_layout", "off" }, 349 { "PIIX4_PM", "memory-hotplug-support", "off" }, 350 { "apic", "version", "0x11" }, 351 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 352 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 353 { "pci-serial", "prog_if", "0" }, 354 { "pci-serial-2x", "prog_if", "0" }, 355 { "pci-serial-4x", "prog_if", "0" }, 356 { "virtio-net-pci", "guest_announce", "off" }, 357 { "ICH9-LPC", "memory-hotplug-support", "off" }, 358 }; 359 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 360 361 GlobalProperty pc_compat_1_7[] = { 362 PC_CPU_MODEL_IDS("1.7.0") 363 { TYPE_USB_DEVICE, "msos-desc", "no" }, 364 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 365 { "hpet", HPET_INTCAP, "4" }, 366 }; 367 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 368 369 GlobalProperty pc_compat_1_6[] = { 370 PC_CPU_MODEL_IDS("1.6.0") 371 { "e1000", "mitigation", "off" }, 372 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 373 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 374 { "i440FX-pcihost", "short_root_bus", "1" }, 375 { "q35-pcihost", "short_root_bus", "1" }, 376 }; 377 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 378 379 GlobalProperty pc_compat_1_5[] = { 380 PC_CPU_MODEL_IDS("1.5.0") 381 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 382 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 383 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 384 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 385 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 386 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 387 { "virtio-net-pci", "any_layout", "off" }, 388 { TYPE_X86_CPU, "pmu", "on" }, 389 { "i440FX-pcihost", "short_root_bus", "0" }, 390 { "q35-pcihost", "short_root_bus", "0" }, 391 }; 392 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 393 394 GlobalProperty pc_compat_1_4[] = { 395 PC_CPU_MODEL_IDS("1.4.0") 396 { "scsi-hd", "discard_granularity", "0" }, 397 { "scsi-cd", "discard_granularity", "0" }, 398 { "ide-hd", "discard_granularity", "0" }, 399 { "ide-cd", "discard_granularity", "0" }, 400 { "virtio-blk-pci", "discard_granularity", "0" }, 401 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 402 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 403 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 404 { "e1000", "romfile", "pxe-e1000.rom" }, 405 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 406 { "pcnet", "romfile", "pxe-pcnet.rom" }, 407 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 408 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 409 { "486-" TYPE_X86_CPU, "model", "0" }, 410 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 411 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 412 }; 413 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 414 415 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 416 { 417 GSIState *s; 418 419 s = g_new0(GSIState, 1); 420 if (kvm_ioapic_in_kernel()) { 421 kvm_pc_setup_irq_routing(pci_enabled); 422 } 423 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 424 425 return s; 426 } 427 428 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 429 unsigned size) 430 { 431 } 432 433 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 434 { 435 return 0xffffffffffffffffULL; 436 } 437 438 /* MSDOS compatibility mode FPU exception support */ 439 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 440 unsigned size) 441 { 442 if (tcg_enabled()) { 443 cpu_set_ignne(); 444 } 445 } 446 447 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 448 { 449 return 0xffffffffffffffffULL; 450 } 451 452 /* PC cmos mappings */ 453 454 #define REG_EQUIPMENT_BYTE 0x14 455 456 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 457 int16_t cylinders, int8_t heads, int8_t sectors) 458 { 459 mc146818rtc_set_cmos_data(s, type_ofs, 47); 460 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 461 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 462 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 463 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 464 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 465 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 466 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 467 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 468 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 469 } 470 471 /* convert boot_device letter to something recognizable by the bios */ 472 static int boot_device2nibble(char boot_device) 473 { 474 switch(boot_device) { 475 case 'a': 476 case 'b': 477 return 0x01; /* floppy boot */ 478 case 'c': 479 return 0x02; /* hard drive boot */ 480 case 'd': 481 return 0x03; /* CD-ROM boot */ 482 case 'n': 483 return 0x04; /* Network boot */ 484 } 485 return 0; 486 } 487 488 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 489 Error **errp) 490 { 491 #define PC_MAX_BOOT_DEVICES 3 492 int nbds, bds[3] = { 0, }; 493 int i; 494 495 nbds = strlen(boot_device); 496 if (nbds > PC_MAX_BOOT_DEVICES) { 497 error_setg(errp, "Too many boot devices for PC"); 498 return; 499 } 500 for (i = 0; i < nbds; i++) { 501 bds[i] = boot_device2nibble(boot_device[i]); 502 if (bds[i] == 0) { 503 error_setg(errp, "Invalid boot device for PC: '%c'", 504 boot_device[i]); 505 return; 506 } 507 } 508 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 509 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 510 } 511 512 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 513 { 514 set_boot_dev(opaque, boot_device, errp); 515 } 516 517 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 518 { 519 int val, nb, i; 520 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 521 FLOPPY_DRIVE_TYPE_NONE }; 522 523 /* floppy type */ 524 if (floppy) { 525 for (i = 0; i < 2; i++) { 526 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 527 } 528 } 529 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 530 cmos_get_fd_drive_type(fd_type[1]); 531 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 532 533 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 534 nb = 0; 535 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 536 nb++; 537 } 538 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 539 nb++; 540 } 541 switch (nb) { 542 case 0: 543 break; 544 case 1: 545 val |= 0x01; /* 1 drive, ready for boot */ 546 break; 547 case 2: 548 val |= 0x41; /* 2 drives, ready for boot */ 549 break; 550 } 551 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 552 } 553 554 typedef struct pc_cmos_init_late_arg { 555 MC146818RtcState *rtc_state; 556 BusState *idebus[2]; 557 } pc_cmos_init_late_arg; 558 559 typedef struct check_fdc_state { 560 ISADevice *floppy; 561 bool multiple; 562 } CheckFdcState; 563 564 static int check_fdc(Object *obj, void *opaque) 565 { 566 CheckFdcState *state = opaque; 567 Object *fdc; 568 uint32_t iobase; 569 Error *local_err = NULL; 570 571 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 572 if (!fdc) { 573 return 0; 574 } 575 576 iobase = object_property_get_uint(obj, "iobase", &local_err); 577 if (local_err || iobase != 0x3f0) { 578 error_free(local_err); 579 return 0; 580 } 581 582 if (state->floppy) { 583 state->multiple = true; 584 } else { 585 state->floppy = ISA_DEVICE(obj); 586 } 587 return 0; 588 } 589 590 static const char * const fdc_container_path[] = { 591 "/unattached", "/peripheral", "/peripheral-anon" 592 }; 593 594 /* 595 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 596 * and ACPI objects. 597 */ 598 static ISADevice *pc_find_fdc0(void) 599 { 600 int i; 601 Object *container; 602 CheckFdcState state = { 0 }; 603 604 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 605 container = container_get(qdev_get_machine(), fdc_container_path[i]); 606 object_child_foreach(container, check_fdc, &state); 607 } 608 609 if (state.multiple) { 610 warn_report("multiple floppy disk controllers with " 611 "iobase=0x3f0 have been found"); 612 error_printf("the one being picked for CMOS setup might not reflect " 613 "your intent"); 614 } 615 616 return state.floppy; 617 } 618 619 static void pc_cmos_init_late(void *opaque) 620 { 621 pc_cmos_init_late_arg *arg = opaque; 622 MC146818RtcState *s = arg->rtc_state; 623 int16_t cylinders; 624 int8_t heads, sectors; 625 int val; 626 int i, trans; 627 628 val = 0; 629 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 630 &cylinders, &heads, §ors) >= 0) { 631 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 632 val |= 0xf0; 633 } 634 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 635 &cylinders, &heads, §ors) >= 0) { 636 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 637 val |= 0x0f; 638 } 639 mc146818rtc_set_cmos_data(s, 0x12, val); 640 641 val = 0; 642 for (i = 0; i < 4; i++) { 643 /* NOTE: ide_get_geometry() returns the physical 644 geometry. It is always such that: 1 <= sects <= 63, 1 645 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 646 geometry can be different if a translation is done. */ 647 if (arg->idebus[i / 2] && 648 ide_get_geometry(arg->idebus[i / 2], i % 2, 649 &cylinders, &heads, §ors) >= 0) { 650 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 651 assert((trans & ~3) == 0); 652 val |= trans << (i * 2); 653 } 654 } 655 mc146818rtc_set_cmos_data(s, 0x39, val); 656 657 pc_cmos_init_floppy(s, pc_find_fdc0()); 658 659 qemu_unregister_reset(pc_cmos_init_late, opaque); 660 } 661 662 void pc_cmos_init(PCMachineState *pcms, 663 BusState *idebus0, BusState *idebus1, 664 ISADevice *rtc) 665 { 666 int val; 667 static pc_cmos_init_late_arg arg; 668 X86MachineState *x86ms = X86_MACHINE(pcms); 669 MC146818RtcState *s = MC146818_RTC(rtc); 670 671 /* various important CMOS locations needed by PC/Bochs bios */ 672 673 /* memory size */ 674 /* base memory (first MiB) */ 675 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 676 mc146818rtc_set_cmos_data(s, 0x15, val); 677 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 678 /* extended memory (next 64MiB) */ 679 if (x86ms->below_4g_mem_size > 1 * MiB) { 680 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 681 } else { 682 val = 0; 683 } 684 if (val > 65535) 685 val = 65535; 686 mc146818rtc_set_cmos_data(s, 0x17, val); 687 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 688 mc146818rtc_set_cmos_data(s, 0x30, val); 689 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 690 /* memory between 16MiB and 4GiB */ 691 if (x86ms->below_4g_mem_size > 16 * MiB) { 692 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 693 } else { 694 val = 0; 695 } 696 if (val > 65535) 697 val = 65535; 698 mc146818rtc_set_cmos_data(s, 0x34, val); 699 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 700 /* memory above 4GiB */ 701 val = x86ms->above_4g_mem_size / 65536; 702 mc146818rtc_set_cmos_data(s, 0x5b, val); 703 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 704 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 705 706 object_property_add_link(OBJECT(pcms), "rtc_state", 707 TYPE_ISA_DEVICE, 708 (Object **)&x86ms->rtc, 709 object_property_allow_set_link, 710 OBJ_PROP_LINK_STRONG); 711 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 712 &error_abort); 713 714 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 715 716 val = 0; 717 val |= 0x02; /* FPU is there */ 718 val |= 0x04; /* PS/2 mouse installed */ 719 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 720 721 /* hard drives and FDC */ 722 arg.rtc_state = s; 723 arg.idebus[0] = idebus0; 724 arg.idebus[1] = idebus1; 725 qemu_register_reset(pc_cmos_init_late, &arg); 726 } 727 728 static void handle_a20_line_change(void *opaque, int irq, int level) 729 { 730 X86CPU *cpu = opaque; 731 732 /* XXX: send to all CPUs ? */ 733 /* XXX: add logic to handle multiple A20 line sources */ 734 x86_cpu_set_a20(cpu, level); 735 } 736 737 #define NE2000_NB_MAX 6 738 739 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 740 0x280, 0x380 }; 741 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 742 743 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 744 { 745 static int nb_ne2k = 0; 746 747 if (nb_ne2k == NE2000_NB_MAX) 748 return; 749 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 750 ne2000_irq[nb_ne2k], nd); 751 nb_ne2k++; 752 } 753 754 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 755 { 756 X86CPU *cpu = opaque; 757 758 if (level) { 759 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 760 } 761 } 762 763 static 764 void pc_machine_done(Notifier *notifier, void *data) 765 { 766 PCMachineState *pcms = container_of(notifier, 767 PCMachineState, machine_done); 768 X86MachineState *x86ms = X86_MACHINE(pcms); 769 770 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 771 &error_fatal); 772 773 if (pcms->cxl_devices_state.is_enabled) { 774 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 775 } 776 777 /* set the number of CPUs */ 778 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 779 780 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 781 782 acpi_setup(); 783 if (x86ms->fw_cfg) { 784 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 785 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 786 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 787 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 788 } 789 } 790 791 void pc_guest_info_init(PCMachineState *pcms) 792 { 793 X86MachineState *x86ms = X86_MACHINE(pcms); 794 795 x86ms->apic_xrupt_override = true; 796 pcms->machine_done.notify = pc_machine_done; 797 qemu_add_machine_init_done_notifier(&pcms->machine_done); 798 } 799 800 /* setup pci memory address space mapping into system address space */ 801 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 802 MemoryRegion *pci_address_space) 803 { 804 /* Set to lower priority than RAM */ 805 memory_region_add_subregion_overlap(system_memory, 0x0, 806 pci_address_space, -1); 807 } 808 809 void xen_load_linux(PCMachineState *pcms) 810 { 811 int i; 812 FWCfgState *fw_cfg; 813 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 814 X86MachineState *x86ms = X86_MACHINE(pcms); 815 816 assert(MACHINE(pcms)->kernel_filename != NULL); 817 818 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 819 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 820 rom_set_fw(fw_cfg); 821 822 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 823 pcmc->pvh_enabled); 824 for (i = 0; i < nb_option_roms; i++) { 825 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 826 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 827 !strcmp(option_rom[i].name, "pvh.bin") || 828 !strcmp(option_rom[i].name, "multiboot.bin") || 829 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 830 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 831 } 832 x86ms->fw_cfg = fw_cfg; 833 } 834 835 #define PC_ROM_MIN_VGA 0xc0000 836 #define PC_ROM_MIN_OPTION 0xc8000 837 #define PC_ROM_MAX 0xe0000 838 #define PC_ROM_ALIGN 0x800 839 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 840 841 static hwaddr pc_above_4g_end(PCMachineState *pcms) 842 { 843 X86MachineState *x86ms = X86_MACHINE(pcms); 844 845 if (pcms->sgx_epc.size != 0) { 846 return sgx_epc_above_4g_end(&pcms->sgx_epc); 847 } 848 849 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 850 } 851 852 static void pc_get_device_memory_range(PCMachineState *pcms, 853 hwaddr *base, 854 ram_addr_t *device_mem_size) 855 { 856 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 857 MachineState *machine = MACHINE(pcms); 858 ram_addr_t size; 859 hwaddr addr; 860 861 size = machine->maxram_size - machine->ram_size; 862 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 863 864 if (pcmc->enforce_aligned_dimm) { 865 /* size device region assuming 1G page max alignment per slot */ 866 size += (1 * GiB) * machine->ram_slots; 867 } 868 869 *base = addr; 870 *device_mem_size = size; 871 } 872 873 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 874 { 875 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 876 hwaddr cxl_base; 877 ram_addr_t size; 878 879 if (pcmc->has_reserved_memory) { 880 pc_get_device_memory_range(pcms, &cxl_base, &size); 881 cxl_base += size; 882 } else { 883 cxl_base = pc_above_4g_end(pcms); 884 } 885 886 return cxl_base; 887 } 888 889 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 890 { 891 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 892 893 if (pcms->cxl_devices_state.fixed_windows) { 894 GList *it; 895 896 start = ROUND_UP(start, 256 * MiB); 897 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 898 CXLFixedWindow *fw = it->data; 899 start += fw->size; 900 } 901 } 902 903 return start; 904 } 905 906 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 907 { 908 X86CPU *cpu = X86_CPU(first_cpu); 909 910 /* 32-bit systems don't have hole64 thus return max CPU address */ 911 if (cpu->phys_bits <= 32) { 912 return ((hwaddr)1 << cpu->phys_bits) - 1; 913 } 914 915 return pc_pci_hole64_start() + pci_hole64_size - 1; 916 } 917 918 /* 919 * AMD systems with an IOMMU have an additional hole close to the 920 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 921 * on kernel version, VFIO may or may not let you DMA map those ranges. 922 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 923 * with certain memory sizes. It's also wrong to use those IOVA ranges 924 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 925 * The ranges reserved for Hyper-Transport are: 926 * 927 * FD_0000_0000h - FF_FFFF_FFFFh 928 * 929 * The ranges represent the following: 930 * 931 * Base Address Top Address Use 932 * 933 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 934 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 935 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 936 * FD_F910_0000h FD_F91F_FFFFh System Management 937 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 938 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 939 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 940 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 941 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 942 * FE_2000_0000h FF_FFFF_FFFFh Reserved 943 * 944 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 945 * Table 3: Special Address Controls (GPA) for more information. 946 */ 947 #define AMD_HT_START 0xfd00000000UL 948 #define AMD_HT_END 0xffffffffffUL 949 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 950 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 951 952 void pc_memory_init(PCMachineState *pcms, 953 MemoryRegion *system_memory, 954 MemoryRegion *rom_memory, 955 uint64_t pci_hole64_size) 956 { 957 int linux_boot, i; 958 MemoryRegion *option_rom_mr; 959 MemoryRegion *ram_below_4g, *ram_above_4g; 960 FWCfgState *fw_cfg; 961 MachineState *machine = MACHINE(pcms); 962 MachineClass *mc = MACHINE_GET_CLASS(machine); 963 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 964 X86MachineState *x86ms = X86_MACHINE(pcms); 965 hwaddr maxphysaddr, maxusedaddr; 966 hwaddr cxl_base, cxl_resv_end = 0; 967 X86CPU *cpu = X86_CPU(first_cpu); 968 969 assert(machine->ram_size == x86ms->below_4g_mem_size + 970 x86ms->above_4g_mem_size); 971 972 linux_boot = (machine->kernel_filename != NULL); 973 974 /* 975 * The HyperTransport range close to the 1T boundary is unique to AMD 976 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 977 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 978 * older machine types (<= 7.0) for compatibility purposes. 979 */ 980 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 981 /* Bail out if max possible address does not cross HT range */ 982 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 983 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 984 } 985 986 /* 987 * Advertise the HT region if address space covers the reserved 988 * region or if we relocate. 989 */ 990 if (cpu->phys_bits >= 40) { 991 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 992 } 993 } 994 995 /* 996 * phys-bits is required to be appropriately configured 997 * to make sure max used GPA is reachable. 998 */ 999 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 1000 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 1001 if (maxphysaddr < maxusedaddr) { 1002 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 1003 " phys-bits too low (%u)", 1004 maxphysaddr, maxusedaddr, cpu->phys_bits); 1005 exit(EXIT_FAILURE); 1006 } 1007 1008 /* 1009 * Split single memory region and use aliases to address portions of it, 1010 * done for backwards compatibility with older qemus. 1011 */ 1012 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1013 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 1014 0, x86ms->below_4g_mem_size); 1015 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1016 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1017 if (x86ms->above_4g_mem_size > 0) { 1018 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1019 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1020 machine->ram, 1021 x86ms->below_4g_mem_size, 1022 x86ms->above_4g_mem_size); 1023 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1024 ram_above_4g); 1025 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1026 E820_RAM); 1027 } 1028 1029 if (pcms->sgx_epc.size != 0) { 1030 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1031 } 1032 1033 if (!pcmc->has_reserved_memory && 1034 (machine->ram_slots || 1035 (machine->maxram_size > machine->ram_size))) { 1036 1037 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1038 mc->name); 1039 exit(EXIT_FAILURE); 1040 } 1041 1042 /* always allocate the device memory information */ 1043 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1044 1045 /* initialize device memory address space */ 1046 if (pcmc->has_reserved_memory && 1047 (machine->ram_size < machine->maxram_size)) { 1048 ram_addr_t device_mem_size; 1049 1050 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1051 error_report("unsupported amount of memory slots: %"PRIu64, 1052 machine->ram_slots); 1053 exit(EXIT_FAILURE); 1054 } 1055 1056 if (QEMU_ALIGN_UP(machine->maxram_size, 1057 TARGET_PAGE_SIZE) != machine->maxram_size) { 1058 error_report("maximum memory size must by aligned to multiple of " 1059 "%d bytes", TARGET_PAGE_SIZE); 1060 exit(EXIT_FAILURE); 1061 } 1062 1063 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1064 1065 if ((machine->device_memory->base + device_mem_size) < 1066 device_mem_size) { 1067 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1068 machine->maxram_size); 1069 exit(EXIT_FAILURE); 1070 } 1071 1072 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1073 "device-memory", device_mem_size); 1074 memory_region_add_subregion(system_memory, machine->device_memory->base, 1075 &machine->device_memory->mr); 1076 } 1077 1078 if (pcms->cxl_devices_state.is_enabled) { 1079 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1080 hwaddr cxl_size = MiB; 1081 1082 cxl_base = pc_get_cxl_range_start(pcms); 1083 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1084 memory_region_add_subregion(system_memory, cxl_base, mr); 1085 cxl_resv_end = cxl_base + cxl_size; 1086 if (pcms->cxl_devices_state.fixed_windows) { 1087 hwaddr cxl_fmw_base; 1088 GList *it; 1089 1090 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1091 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1092 CXLFixedWindow *fw = it->data; 1093 1094 fw->base = cxl_fmw_base; 1095 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1096 "cxl-fixed-memory-region", fw->size); 1097 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1098 cxl_fmw_base += fw->size; 1099 cxl_resv_end = cxl_fmw_base; 1100 } 1101 } 1102 } 1103 1104 /* Initialize PC system firmware */ 1105 pc_system_firmware_init(pcms, rom_memory); 1106 1107 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1108 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1109 &error_fatal); 1110 if (pcmc->pci_enabled) { 1111 memory_region_set_readonly(option_rom_mr, true); 1112 } 1113 memory_region_add_subregion_overlap(rom_memory, 1114 PC_ROM_MIN_VGA, 1115 option_rom_mr, 1116 1); 1117 1118 fw_cfg = fw_cfg_arch_create(machine, 1119 x86ms->boot_cpus, x86ms->apic_id_limit); 1120 1121 rom_set_fw(fw_cfg); 1122 1123 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1124 uint64_t *val = g_malloc(sizeof(*val)); 1125 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1126 uint64_t res_mem_end = machine->device_memory->base; 1127 1128 if (!pcmc->broken_reserved_end) { 1129 res_mem_end += memory_region_size(&machine->device_memory->mr); 1130 } 1131 1132 if (pcms->cxl_devices_state.is_enabled) { 1133 res_mem_end = cxl_resv_end; 1134 } 1135 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1136 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1137 } 1138 1139 if (linux_boot) { 1140 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1141 pcmc->pvh_enabled); 1142 } 1143 1144 for (i = 0; i < nb_option_roms; i++) { 1145 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1146 } 1147 x86ms->fw_cfg = fw_cfg; 1148 1149 /* Init default IOAPIC address space */ 1150 x86ms->ioapic_as = &address_space_memory; 1151 1152 /* Init ACPI memory hotplug IO base address */ 1153 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1154 } 1155 1156 /* 1157 * The 64bit pci hole starts after "above 4G RAM" and 1158 * potentially the space reserved for memory hotplug. 1159 */ 1160 uint64_t pc_pci_hole64_start(void) 1161 { 1162 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1163 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1164 MachineState *ms = MACHINE(pcms); 1165 uint64_t hole64_start = 0; 1166 ram_addr_t size = 0; 1167 1168 if (pcms->cxl_devices_state.is_enabled) { 1169 hole64_start = pc_get_cxl_range_end(pcms); 1170 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1171 pc_get_device_memory_range(pcms, &hole64_start, &size); 1172 if (!pcmc->broken_reserved_end) { 1173 hole64_start += size; 1174 } 1175 } else { 1176 hole64_start = pc_above_4g_end(pcms); 1177 } 1178 1179 return ROUND_UP(hole64_start, 1 * GiB); 1180 } 1181 1182 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1183 { 1184 DeviceState *dev = NULL; 1185 1186 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1187 if (pci_bus) { 1188 PCIDevice *pcidev = pci_vga_init(pci_bus); 1189 dev = pcidev ? &pcidev->qdev : NULL; 1190 } else if (isa_bus) { 1191 ISADevice *isadev = isa_vga_init(isa_bus); 1192 dev = isadev ? DEVICE(isadev) : NULL; 1193 } 1194 rom_reset_order_override(); 1195 return dev; 1196 } 1197 1198 static const MemoryRegionOps ioport80_io_ops = { 1199 .write = ioport80_write, 1200 .read = ioport80_read, 1201 .endianness = DEVICE_NATIVE_ENDIAN, 1202 .impl = { 1203 .min_access_size = 1, 1204 .max_access_size = 1, 1205 }, 1206 }; 1207 1208 static const MemoryRegionOps ioportF0_io_ops = { 1209 .write = ioportF0_write, 1210 .read = ioportF0_read, 1211 .endianness = DEVICE_NATIVE_ENDIAN, 1212 .impl = { 1213 .min_access_size = 1, 1214 .max_access_size = 1, 1215 }, 1216 }; 1217 1218 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1219 bool create_i8042, bool no_vmport) 1220 { 1221 int i; 1222 DriveInfo *fd[MAX_FD]; 1223 qemu_irq *a20_line; 1224 ISADevice *fdc, *i8042, *port92, *vmmouse; 1225 1226 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1227 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1228 1229 for (i = 0; i < MAX_FD; i++) { 1230 fd[i] = drive_get(IF_FLOPPY, 0, i); 1231 create_fdctrl |= !!fd[i]; 1232 } 1233 if (create_fdctrl) { 1234 fdc = isa_new(TYPE_ISA_FDC); 1235 if (fdc) { 1236 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1237 isa_fdc_init_drives(fdc, fd); 1238 } 1239 } 1240 1241 if (!create_i8042) { 1242 return; 1243 } 1244 1245 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1246 if (!no_vmport) { 1247 isa_create_simple(isa_bus, TYPE_VMPORT); 1248 vmmouse = isa_try_new("vmmouse"); 1249 } else { 1250 vmmouse = NULL; 1251 } 1252 if (vmmouse) { 1253 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1254 &error_abort); 1255 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1256 } 1257 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1258 1259 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1260 i8042_setup_a20_line(i8042, a20_line[0]); 1261 qdev_connect_gpio_out_named(DEVICE(port92), 1262 PORT92_A20_LINE, 0, a20_line[1]); 1263 g_free(a20_line); 1264 } 1265 1266 void pc_basic_device_init(struct PCMachineState *pcms, 1267 ISABus *isa_bus, qemu_irq *gsi, 1268 ISADevice *rtc_state, 1269 bool create_fdctrl, 1270 uint32_t hpet_irqs) 1271 { 1272 int i; 1273 DeviceState *hpet = NULL; 1274 int pit_isa_irq = 0; 1275 qemu_irq pit_alt_irq = NULL; 1276 qemu_irq rtc_irq = NULL; 1277 ISADevice *pit = NULL; 1278 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1279 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1280 X86MachineState *x86ms = X86_MACHINE(pcms); 1281 1282 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1283 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1284 1285 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1286 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1287 1288 /* 1289 * Check if an HPET shall be created. 1290 * 1291 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1292 * when the HPET wants to take over. Thus we have to disable the latter. 1293 */ 1294 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1295 kvm_has_pit_state2())) { 1296 hpet = qdev_try_new(TYPE_HPET); 1297 if (!hpet) { 1298 error_report("couldn't create HPET device"); 1299 exit(1); 1300 } 1301 /* 1302 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1303 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1304 * IRQ2. 1305 */ 1306 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1307 HPET_INTCAP, NULL); 1308 if (!compat) { 1309 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1310 } 1311 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1312 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1313 1314 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1315 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1316 } 1317 pit_isa_irq = -1; 1318 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1319 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1320 } 1321 1322 if (rtc_irq) { 1323 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1324 } else { 1325 uint32_t irq = object_property_get_uint(OBJECT(rtc_state), 1326 "irq", 1327 &error_fatal); 1328 isa_connect_gpio_out(rtc_state, 0, irq); 1329 } 1330 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1331 "date"); 1332 1333 #ifdef CONFIG_XEN_EMU 1334 if (xen_mode == XEN_EMULATE) { 1335 xen_evtchn_connect_gsis(gsi); 1336 if (pcms->bus) { 1337 pci_create_simple(pcms->bus, -1, "xen-platform"); 1338 } 1339 xen_bus_init(); 1340 xen_be_init(); 1341 } 1342 #endif 1343 1344 qemu_register_boot_set(pc_boot_set, rtc_state); 1345 1346 if (!xen_enabled() && 1347 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1348 if (kvm_pit_in_kernel()) { 1349 pit = kvm_pit_init(isa_bus, 0x40); 1350 } else { 1351 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1352 } 1353 if (hpet) { 1354 /* connect PIT to output control line of the HPET */ 1355 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1356 } 1357 pcspk_init(pcms->pcspk, isa_bus, pit); 1358 } 1359 1360 /* Super I/O */ 1361 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1362 pcms->vmport != ON_OFF_AUTO_ON); 1363 } 1364 1365 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1366 { 1367 MachineClass *mc = MACHINE_CLASS(pcmc); 1368 int i; 1369 1370 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1371 for (i = 0; i < nb_nics; i++) { 1372 NICInfo *nd = &nd_table[i]; 1373 const char *model = nd->model ? nd->model : mc->default_nic; 1374 1375 if (g_str_equal(model, "ne2k_isa")) { 1376 pc_init_ne2k_isa(isa_bus, nd); 1377 } else { 1378 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1379 } 1380 } 1381 rom_reset_order_override(); 1382 } 1383 1384 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1385 { 1386 qemu_irq *i8259; 1387 1388 if (kvm_pic_in_kernel()) { 1389 i8259 = kvm_i8259_init(isa_bus); 1390 } else if (xen_enabled()) { 1391 i8259 = xen_interrupt_controller_init(); 1392 } else { 1393 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1394 } 1395 1396 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1397 i8259_irqs[i] = i8259[i]; 1398 } 1399 1400 g_free(i8259); 1401 } 1402 1403 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1404 Error **errp) 1405 { 1406 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1407 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1408 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1409 const MachineState *ms = MACHINE(hotplug_dev); 1410 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1411 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1412 Error *local_err = NULL; 1413 1414 /* 1415 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1416 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1417 * addition to cover this case. 1418 */ 1419 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1420 error_setg(errp, 1421 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1422 return; 1423 } 1424 1425 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1426 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1427 return; 1428 } 1429 1430 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1431 if (local_err) { 1432 error_propagate(errp, local_err); 1433 return; 1434 } 1435 1436 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1437 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1438 } 1439 1440 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1441 DeviceState *dev, Error **errp) 1442 { 1443 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1444 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1445 MachineState *ms = MACHINE(hotplug_dev); 1446 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1447 1448 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1449 1450 if (is_nvdimm) { 1451 nvdimm_plug(ms->nvdimms_state); 1452 } 1453 1454 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1455 } 1456 1457 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1458 DeviceState *dev, Error **errp) 1459 { 1460 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1461 1462 /* 1463 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1464 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1465 * addition to cover this case. 1466 */ 1467 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1468 error_setg(errp, 1469 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1470 return; 1471 } 1472 1473 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1474 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1475 return; 1476 } 1477 1478 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1479 errp); 1480 } 1481 1482 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1483 DeviceState *dev, Error **errp) 1484 { 1485 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1486 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1487 Error *local_err = NULL; 1488 1489 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1490 if (local_err) { 1491 goto out; 1492 } 1493 1494 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1495 qdev_unrealize(dev); 1496 out: 1497 error_propagate(errp, local_err); 1498 } 1499 1500 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1501 DeviceState *dev, Error **errp) 1502 { 1503 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1504 Error *local_err = NULL; 1505 1506 if (!hotplug_dev2 && dev->hotplugged) { 1507 /* 1508 * Without a bus hotplug handler, we cannot control the plug/unplug 1509 * order. We should never reach this point when hotplugging on x86, 1510 * however, better add a safety net. 1511 */ 1512 error_setg(errp, "hotplug of virtio based memory devices not supported" 1513 " on this bus."); 1514 return; 1515 } 1516 /* 1517 * First, see if we can plug this memory device at all. If that 1518 * succeeds, branch of to the actual hotplug handler. 1519 */ 1520 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1521 &local_err); 1522 if (!local_err && hotplug_dev2) { 1523 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1524 } 1525 error_propagate(errp, local_err); 1526 } 1527 1528 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1529 DeviceState *dev, Error **errp) 1530 { 1531 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1532 Error *local_err = NULL; 1533 1534 /* 1535 * Plug the memory device first and then branch off to the actual 1536 * hotplug handler. If that one fails, we can easily undo the memory 1537 * device bits. 1538 */ 1539 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1540 if (hotplug_dev2) { 1541 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1542 if (local_err) { 1543 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1544 } 1545 } 1546 error_propagate(errp, local_err); 1547 } 1548 1549 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1550 DeviceState *dev, Error **errp) 1551 { 1552 /* We don't support hot unplug of virtio based memory devices */ 1553 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1554 } 1555 1556 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1557 DeviceState *dev, Error **errp) 1558 { 1559 /* We don't support hot unplug of virtio based memory devices */ 1560 } 1561 1562 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1563 DeviceState *dev, Error **errp) 1564 { 1565 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1566 pc_memory_pre_plug(hotplug_dev, dev, errp); 1567 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1568 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1569 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1570 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1571 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1572 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1573 /* Declare the APIC range as the reserved MSI region */ 1574 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1575 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1576 1577 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1578 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1579 resv_prop_str, errp); 1580 g_free(resv_prop_str); 1581 } 1582 1583 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1584 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1585 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1586 1587 if (pcms->iommu) { 1588 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1589 "for x86 yet."); 1590 return; 1591 } 1592 pcms->iommu = dev; 1593 } 1594 } 1595 1596 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1597 DeviceState *dev, Error **errp) 1598 { 1599 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1600 pc_memory_plug(hotplug_dev, dev, errp); 1601 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1602 x86_cpu_plug(hotplug_dev, dev, errp); 1603 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1604 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1605 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1606 } 1607 } 1608 1609 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1610 DeviceState *dev, Error **errp) 1611 { 1612 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1613 pc_memory_unplug_request(hotplug_dev, dev, errp); 1614 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1615 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1616 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1617 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1618 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1619 } else { 1620 error_setg(errp, "acpi: device unplug request for not supported device" 1621 " type: %s", object_get_typename(OBJECT(dev))); 1622 } 1623 } 1624 1625 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1626 DeviceState *dev, Error **errp) 1627 { 1628 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1629 pc_memory_unplug(hotplug_dev, dev, errp); 1630 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1631 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1632 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1633 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1634 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1635 } else { 1636 error_setg(errp, "acpi: device unplug for not supported device" 1637 " type: %s", object_get_typename(OBJECT(dev))); 1638 } 1639 } 1640 1641 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1642 DeviceState *dev) 1643 { 1644 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1645 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1646 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1647 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1648 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1649 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1650 return HOTPLUG_HANDLER(machine); 1651 } 1652 1653 return NULL; 1654 } 1655 1656 static void 1657 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1658 const char *name, void *opaque, 1659 Error **errp) 1660 { 1661 MachineState *ms = MACHINE(obj); 1662 int64_t value = 0; 1663 1664 if (ms->device_memory) { 1665 value = memory_region_size(&ms->device_memory->mr); 1666 } 1667 1668 visit_type_int(v, name, &value, errp); 1669 } 1670 1671 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1672 void *opaque, Error **errp) 1673 { 1674 PCMachineState *pcms = PC_MACHINE(obj); 1675 OnOffAuto vmport = pcms->vmport; 1676 1677 visit_type_OnOffAuto(v, name, &vmport, errp); 1678 } 1679 1680 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1681 void *opaque, Error **errp) 1682 { 1683 PCMachineState *pcms = PC_MACHINE(obj); 1684 1685 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1686 } 1687 1688 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1689 { 1690 PCMachineState *pcms = PC_MACHINE(obj); 1691 1692 return pcms->smbus_enabled; 1693 } 1694 1695 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1696 { 1697 PCMachineState *pcms = PC_MACHINE(obj); 1698 1699 pcms->smbus_enabled = value; 1700 } 1701 1702 static bool pc_machine_get_sata(Object *obj, Error **errp) 1703 { 1704 PCMachineState *pcms = PC_MACHINE(obj); 1705 1706 return pcms->sata_enabled; 1707 } 1708 1709 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1710 { 1711 PCMachineState *pcms = PC_MACHINE(obj); 1712 1713 pcms->sata_enabled = value; 1714 } 1715 1716 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1717 { 1718 PCMachineState *pcms = PC_MACHINE(obj); 1719 1720 return pcms->hpet_enabled; 1721 } 1722 1723 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1724 { 1725 PCMachineState *pcms = PC_MACHINE(obj); 1726 1727 pcms->hpet_enabled = value; 1728 } 1729 1730 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1731 { 1732 PCMachineState *pcms = PC_MACHINE(obj); 1733 1734 return pcms->i8042_enabled; 1735 } 1736 1737 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1738 { 1739 PCMachineState *pcms = PC_MACHINE(obj); 1740 1741 pcms->i8042_enabled = value; 1742 } 1743 1744 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1745 { 1746 PCMachineState *pcms = PC_MACHINE(obj); 1747 1748 return pcms->default_bus_bypass_iommu; 1749 } 1750 1751 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1752 Error **errp) 1753 { 1754 PCMachineState *pcms = PC_MACHINE(obj); 1755 1756 pcms->default_bus_bypass_iommu = value; 1757 } 1758 1759 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1760 void *opaque, Error **errp) 1761 { 1762 PCMachineState *pcms = PC_MACHINE(obj); 1763 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1764 1765 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1766 } 1767 1768 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1769 void *opaque, Error **errp) 1770 { 1771 PCMachineState *pcms = PC_MACHINE(obj); 1772 1773 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1774 } 1775 1776 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1777 const char *name, void *opaque, 1778 Error **errp) 1779 { 1780 PCMachineState *pcms = PC_MACHINE(obj); 1781 uint64_t value = pcms->max_ram_below_4g; 1782 1783 visit_type_size(v, name, &value, errp); 1784 } 1785 1786 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1787 const char *name, void *opaque, 1788 Error **errp) 1789 { 1790 PCMachineState *pcms = PC_MACHINE(obj); 1791 uint64_t value; 1792 1793 if (!visit_type_size(v, name, &value, errp)) { 1794 return; 1795 } 1796 if (value > 4 * GiB) { 1797 error_setg(errp, 1798 "Machine option 'max-ram-below-4g=%"PRIu64 1799 "' expects size less than or equal to 4G", value); 1800 return; 1801 } 1802 1803 if (value < 1 * MiB) { 1804 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1805 "BIOS may not work with less than 1MiB", value); 1806 } 1807 1808 pcms->max_ram_below_4g = value; 1809 } 1810 1811 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1812 const char *name, void *opaque, 1813 Error **errp) 1814 { 1815 PCMachineState *pcms = PC_MACHINE(obj); 1816 uint64_t value = pcms->max_fw_size; 1817 1818 visit_type_size(v, name, &value, errp); 1819 } 1820 1821 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1822 const char *name, void *opaque, 1823 Error **errp) 1824 { 1825 PCMachineState *pcms = PC_MACHINE(obj); 1826 uint64_t value; 1827 1828 if (!visit_type_size(v, name, &value, errp)) { 1829 return; 1830 } 1831 1832 /* 1833 * We don't have a theoretically justifiable exact lower bound on the base 1834 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1835 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1836 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1837 * size. 1838 */ 1839 if (value > 16 * MiB) { 1840 error_setg(errp, 1841 "User specified max allowed firmware size %" PRIu64 " is " 1842 "greater than 16MiB. If combined firwmare size exceeds " 1843 "16MiB the system may not boot, or experience intermittent" 1844 "stability issues.", 1845 value); 1846 return; 1847 } 1848 1849 pcms->max_fw_size = value; 1850 } 1851 1852 1853 static void pc_machine_initfn(Object *obj) 1854 { 1855 PCMachineState *pcms = PC_MACHINE(obj); 1856 1857 #ifdef CONFIG_VMPORT 1858 pcms->vmport = ON_OFF_AUTO_AUTO; 1859 #else 1860 pcms->vmport = ON_OFF_AUTO_OFF; 1861 #endif /* CONFIG_VMPORT */ 1862 pcms->max_ram_below_4g = 0; /* use default */ 1863 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1864 1865 /* acpi build is enabled by default if machine supports it */ 1866 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1867 pcms->smbus_enabled = true; 1868 pcms->sata_enabled = true; 1869 pcms->i8042_enabled = true; 1870 pcms->max_fw_size = 8 * MiB; 1871 #ifdef CONFIG_HPET 1872 pcms->hpet_enabled = true; 1873 #endif 1874 pcms->default_bus_bypass_iommu = false; 1875 1876 pc_system_flash_create(pcms); 1877 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1878 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1879 OBJECT(pcms->pcspk), "audiodev"); 1880 cxl_machine_init(obj, &pcms->cxl_devices_state); 1881 } 1882 1883 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) 1884 { 1885 #ifdef CONFIG_XEN_EMU 1886 if (xen_mode == XEN_EMULATE) { 1887 xen_overlay_create(); 1888 xen_evtchn_create(); 1889 xen_gnttab_create(); 1890 xen_xenstore_create(); 1891 } 1892 #endif 1893 return 0; 1894 } 1895 1896 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1897 { 1898 CPUState *cs; 1899 X86CPU *cpu; 1900 1901 qemu_devices_reset(reason); 1902 1903 /* Reset APIC after devices have been reset to cancel 1904 * any changes that qemu_devices_reset() might have done. 1905 */ 1906 CPU_FOREACH(cs) { 1907 cpu = X86_CPU(cs); 1908 1909 x86_cpu_after_reset(cpu); 1910 } 1911 } 1912 1913 static void pc_machine_wakeup(MachineState *machine) 1914 { 1915 cpu_synchronize_all_states(); 1916 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1917 cpu_synchronize_all_post_reset(); 1918 } 1919 1920 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1921 { 1922 X86IOMMUState *iommu = x86_iommu_get_default(); 1923 IntelIOMMUState *intel_iommu; 1924 1925 if (iommu && 1926 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1927 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1928 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1929 if (!intel_iommu->caching_mode) { 1930 error_setg(errp, "Device assignment is not allowed without " 1931 "enabling caching-mode=on for Intel IOMMU."); 1932 return false; 1933 } 1934 } 1935 1936 return true; 1937 } 1938 1939 static void pc_machine_class_init(ObjectClass *oc, void *data) 1940 { 1941 MachineClass *mc = MACHINE_CLASS(oc); 1942 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1943 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1944 1945 pcmc->pci_enabled = true; 1946 pcmc->has_acpi_build = true; 1947 pcmc->rsdp_in_ram = true; 1948 pcmc->smbios_defaults = true; 1949 pcmc->smbios_uuid_encoded = true; 1950 pcmc->gigabyte_align = true; 1951 pcmc->has_reserved_memory = true; 1952 pcmc->kvmclock_enabled = true; 1953 pcmc->enforce_aligned_dimm = true; 1954 pcmc->enforce_amd_1tb_hole = true; 1955 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1956 * to be used at the moment, 32K should be enough for a while. */ 1957 pcmc->acpi_data_size = 0x20000 + 0x8000; 1958 pcmc->pvh_enabled = true; 1959 pcmc->kvmclock_create_always = true; 1960 pcmc->resizable_acpi_blob = true; 1961 assert(!mc->get_hotplug_handler); 1962 mc->get_hotplug_handler = pc_get_hotplug_handler; 1963 mc->hotplug_allowed = pc_hotplug_allowed; 1964 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1965 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1966 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1967 mc->auto_enable_numa_with_memhp = true; 1968 mc->auto_enable_numa_with_memdev = true; 1969 mc->has_hotpluggable_cpus = true; 1970 mc->default_boot_order = "cad"; 1971 mc->block_default_type = IF_IDE; 1972 mc->max_cpus = 255; 1973 mc->reset = pc_machine_reset; 1974 mc->wakeup = pc_machine_wakeup; 1975 hc->pre_plug = pc_machine_device_pre_plug_cb; 1976 hc->plug = pc_machine_device_plug_cb; 1977 hc->unplug_request = pc_machine_device_unplug_request_cb; 1978 hc->unplug = pc_machine_device_unplug_cb; 1979 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1980 mc->nvdimm_supported = true; 1981 mc->smp_props.dies_supported = true; 1982 mc->default_ram_id = "pc.ram"; 1983 1984 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1985 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1986 NULL, NULL); 1987 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1988 "Maximum ram below the 4G boundary (32bit boundary)"); 1989 1990 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1991 pc_machine_get_device_memory_region_size, NULL, 1992 NULL, NULL); 1993 1994 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1995 pc_machine_get_vmport, pc_machine_set_vmport, 1996 NULL, NULL); 1997 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1998 "Enable vmport (pc & q35)"); 1999 2000 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2001 pc_machine_get_smbus, pc_machine_set_smbus); 2002 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 2003 "Enable/disable system management bus"); 2004 2005 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2006 pc_machine_get_sata, pc_machine_set_sata); 2007 object_class_property_set_description(oc, PC_MACHINE_SATA, 2008 "Enable/disable Serial ATA bus"); 2009 2010 object_class_property_add_bool(oc, "hpet", 2011 pc_machine_get_hpet, pc_machine_set_hpet); 2012 object_class_property_set_description(oc, "hpet", 2013 "Enable/disable high precision event timer emulation"); 2014 2015 object_class_property_add_bool(oc, PC_MACHINE_I8042, 2016 pc_machine_get_i8042, pc_machine_set_i8042); 2017 2018 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 2019 pc_machine_get_default_bus_bypass_iommu, 2020 pc_machine_set_default_bus_bypass_iommu); 2021 2022 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 2023 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 2024 NULL, NULL); 2025 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 2026 "Maximum combined firmware size"); 2027 2028 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 2029 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 2030 NULL, NULL); 2031 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 2032 "SMBIOS Entry Point type [32, 64]"); 2033 } 2034 2035 static const TypeInfo pc_machine_info = { 2036 .name = TYPE_PC_MACHINE, 2037 .parent = TYPE_X86_MACHINE, 2038 .abstract = true, 2039 .instance_size = sizeof(PCMachineState), 2040 .instance_init = pc_machine_initfn, 2041 .class_size = sizeof(PCMachineClass), 2042 .class_init = pc_machine_class_init, 2043 .interfaces = (InterfaceInfo[]) { 2044 { TYPE_HOTPLUG_HANDLER }, 2045 { } 2046 }, 2047 }; 2048 2049 static void pc_machine_register_types(void) 2050 { 2051 type_register_static(&pc_machine_info); 2052 } 2053 2054 type_init(pc_machine_register_types) 2055