1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "multiboot.h" 45 #include "hw/timer/mc146818rtc.h" 46 #include "hw/dma/i8257.h" 47 #include "hw/timer/i8254.h" 48 #include "hw/input/i8042.h" 49 #include "hw/audio/pcspk.h" 50 #include "hw/pci/msi.h" 51 #include "hw/sysbus.h" 52 #include "sysemu/sysemu.h" 53 #include "sysemu/tcg.h" 54 #include "sysemu/numa.h" 55 #include "sysemu/kvm.h" 56 #include "sysemu/qtest.h" 57 #include "kvm_i386.h" 58 #include "hw/xen/xen.h" 59 #include "hw/xen/start_info.h" 60 #include "ui/qemu-spice.h" 61 #include "exec/memory.h" 62 #include "exec/address-spaces.h" 63 #include "sysemu/arch_init.h" 64 #include "qemu/bitmap.h" 65 #include "qemu/config-file.h" 66 #include "qemu/error-report.h" 67 #include "qemu/option.h" 68 #include "hw/acpi/acpi.h" 69 #include "hw/acpi/cpu_hotplug.h" 70 #include "hw/boards.h" 71 #include "acpi-build.h" 72 #include "hw/mem/pc-dimm.h" 73 #include "qapi/error.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qapi/visitor.h" 76 #include "qom/cpu.h" 77 #include "hw/nmi.h" 78 #include "hw/usb.h" 79 #include "hw/i386/intel_iommu.h" 80 #include "hw/net/ne2000-isa.h" 81 #include "standard-headers/asm-x86/bootparam.h" 82 #include "hw/virtio/virtio-pmem-pci.h" 83 #include "hw/mem/memory-device.h" 84 85 /* debug PC/ISA interrupts */ 86 //#define DEBUG_IRQ 87 88 #ifdef DEBUG_IRQ 89 #define DPRINTF(fmt, ...) \ 90 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 91 #else 92 #define DPRINTF(fmt, ...) 93 #endif 94 95 #define E820_NR_ENTRIES 16 96 97 struct e820_entry { 98 uint64_t address; 99 uint64_t length; 100 uint32_t type; 101 } QEMU_PACKED __attribute((__aligned__(4))); 102 103 struct e820_table { 104 uint32_t count; 105 struct e820_entry entry[E820_NR_ENTRIES]; 106 } QEMU_PACKED __attribute((__aligned__(4))); 107 108 static struct e820_table e820_reserve; 109 static struct e820_entry *e820_table; 110 static unsigned e820_entries; 111 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 112 113 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 114 static size_t pvh_start_addr; 115 116 GlobalProperty pc_compat_4_0[] = {}; 117 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 118 119 GlobalProperty pc_compat_3_1[] = { 120 { "intel-iommu", "dma-drain", "off" }, 121 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 122 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 123 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 124 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 125 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 126 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 127 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 128 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 129 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 130 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 131 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 132 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 133 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 136 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 137 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 138 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 139 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 140 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 141 }; 142 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 143 144 GlobalProperty pc_compat_3_0[] = { 145 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 146 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 147 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 148 }; 149 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 150 151 GlobalProperty pc_compat_2_12[] = { 152 { TYPE_X86_CPU, "legacy-cache", "on" }, 153 { TYPE_X86_CPU, "topoext", "off" }, 154 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 155 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 156 }; 157 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 158 159 GlobalProperty pc_compat_2_11[] = { 160 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 161 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 162 }; 163 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 164 165 GlobalProperty pc_compat_2_10[] = { 166 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 167 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 168 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 169 }; 170 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 171 172 GlobalProperty pc_compat_2_9[] = { 173 { "mch", "extended-tseg-mbytes", "0" }, 174 }; 175 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 176 177 GlobalProperty pc_compat_2_8[] = { 178 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 179 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 180 { "ICH9-LPC", "x-smi-broadcast", "off" }, 181 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 182 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 183 }; 184 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 185 186 GlobalProperty pc_compat_2_7[] = { 187 { TYPE_X86_CPU, "l3-cache", "off" }, 188 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 189 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 190 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 191 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 192 { "isa-pcspk", "migrate", "off" }, 193 }; 194 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 195 196 GlobalProperty pc_compat_2_6[] = { 197 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 198 { "vmxnet3", "romfile", "" }, 199 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 200 { "apic-common", "legacy-instance-id", "on", } 201 }; 202 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 203 204 GlobalProperty pc_compat_2_5[] = {}; 205 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 206 207 GlobalProperty pc_compat_2_4[] = { 208 PC_CPU_MODEL_IDS("2.4.0") 209 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 210 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 211 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 212 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 213 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 214 { TYPE_X86_CPU, "check", "off" }, 215 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 216 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 217 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 218 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 219 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 220 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 221 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 222 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 223 }; 224 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 225 226 GlobalProperty pc_compat_2_3[] = { 227 PC_CPU_MODEL_IDS("2.3.0") 228 { TYPE_X86_CPU, "arat", "off" }, 229 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 230 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 231 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 232 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 233 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 234 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 235 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 236 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 248 }; 249 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 250 251 GlobalProperty pc_compat_2_2[] = { 252 PC_CPU_MODEL_IDS("2.2.0") 253 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 268 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 269 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 270 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 271 }; 272 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 273 274 GlobalProperty pc_compat_2_1[] = { 275 PC_CPU_MODEL_IDS("2.1.0") 276 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 277 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 278 }; 279 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 280 281 GlobalProperty pc_compat_2_0[] = { 282 PC_CPU_MODEL_IDS("2.0.0") 283 { "virtio-scsi-pci", "any_layout", "off" }, 284 { "PIIX4_PM", "memory-hotplug-support", "off" }, 285 { "apic", "version", "0x11" }, 286 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 287 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 288 { "pci-serial", "prog_if", "0" }, 289 { "pci-serial-2x", "prog_if", "0" }, 290 { "pci-serial-4x", "prog_if", "0" }, 291 { "virtio-net-pci", "guest_announce", "off" }, 292 { "ICH9-LPC", "memory-hotplug-support", "off" }, 293 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 294 { "ioh3420", COMPAT_PROP_PCP, "off" }, 295 }; 296 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 297 298 GlobalProperty pc_compat_1_7[] = { 299 PC_CPU_MODEL_IDS("1.7.0") 300 { TYPE_USB_DEVICE, "msos-desc", "no" }, 301 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 302 { "hpet", HPET_INTCAP, "4" }, 303 }; 304 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 305 306 GlobalProperty pc_compat_1_6[] = { 307 PC_CPU_MODEL_IDS("1.6.0") 308 { "e1000", "mitigation", "off" }, 309 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 310 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 311 { "i440FX-pcihost", "short_root_bus", "1" }, 312 { "q35-pcihost", "short_root_bus", "1" }, 313 }; 314 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 315 316 GlobalProperty pc_compat_1_5[] = { 317 PC_CPU_MODEL_IDS("1.5.0") 318 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 319 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 320 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 321 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 322 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 323 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 324 { "virtio-net-pci", "any_layout", "off" }, 325 { TYPE_X86_CPU, "pmu", "on" }, 326 { "i440FX-pcihost", "short_root_bus", "0" }, 327 { "q35-pcihost", "short_root_bus", "0" }, 328 }; 329 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 330 331 GlobalProperty pc_compat_1_4[] = { 332 PC_CPU_MODEL_IDS("1.4.0") 333 { "scsi-hd", "discard_granularity", "0" }, 334 { "scsi-cd", "discard_granularity", "0" }, 335 { "scsi-disk", "discard_granularity", "0" }, 336 { "ide-hd", "discard_granularity", "0" }, 337 { "ide-cd", "discard_granularity", "0" }, 338 { "ide-drive", "discard_granularity", "0" }, 339 { "virtio-blk-pci", "discard_granularity", "0" }, 340 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 341 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 342 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 343 { "e1000", "romfile", "pxe-e1000.rom" }, 344 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 345 { "pcnet", "romfile", "pxe-pcnet.rom" }, 346 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 347 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 348 { "486-" TYPE_X86_CPU, "model", "0" }, 349 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 350 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 351 }; 352 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 353 354 void gsi_handler(void *opaque, int n, int level) 355 { 356 GSIState *s = opaque; 357 358 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 359 if (n < ISA_NUM_IRQS) { 360 qemu_set_irq(s->i8259_irq[n], level); 361 } 362 qemu_set_irq(s->ioapic_irq[n], level); 363 } 364 365 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 366 unsigned size) 367 { 368 } 369 370 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 371 { 372 return 0xffffffffffffffffULL; 373 } 374 375 /* MSDOS compatibility mode FPU exception support */ 376 static qemu_irq ferr_irq; 377 378 void pc_register_ferr_irq(qemu_irq irq) 379 { 380 ferr_irq = irq; 381 } 382 383 /* XXX: add IGNNE support */ 384 void cpu_set_ferr(CPUX86State *s) 385 { 386 qemu_irq_raise(ferr_irq); 387 } 388 389 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 390 unsigned size) 391 { 392 qemu_irq_lower(ferr_irq); 393 } 394 395 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 396 { 397 return 0xffffffffffffffffULL; 398 } 399 400 /* TSC handling */ 401 uint64_t cpu_get_tsc(CPUX86State *env) 402 { 403 return cpu_get_ticks(); 404 } 405 406 /* IRQ handling */ 407 int cpu_get_pic_interrupt(CPUX86State *env) 408 { 409 X86CPU *cpu = env_archcpu(env); 410 int intno; 411 412 if (!kvm_irqchip_in_kernel()) { 413 intno = apic_get_interrupt(cpu->apic_state); 414 if (intno >= 0) { 415 return intno; 416 } 417 /* read the irq from the PIC */ 418 if (!apic_accept_pic_intr(cpu->apic_state)) { 419 return -1; 420 } 421 } 422 423 intno = pic_read_irq(isa_pic); 424 return intno; 425 } 426 427 static void pic_irq_request(void *opaque, int irq, int level) 428 { 429 CPUState *cs = first_cpu; 430 X86CPU *cpu = X86_CPU(cs); 431 432 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 433 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 434 CPU_FOREACH(cs) { 435 cpu = X86_CPU(cs); 436 if (apic_accept_pic_intr(cpu->apic_state)) { 437 apic_deliver_pic_intr(cpu->apic_state, level); 438 } 439 } 440 } else { 441 if (level) { 442 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 443 } else { 444 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 445 } 446 } 447 } 448 449 /* PC cmos mappings */ 450 451 #define REG_EQUIPMENT_BYTE 0x14 452 453 int cmos_get_fd_drive_type(FloppyDriveType fd0) 454 { 455 int val; 456 457 switch (fd0) { 458 case FLOPPY_DRIVE_TYPE_144: 459 /* 1.44 Mb 3"5 drive */ 460 val = 4; 461 break; 462 case FLOPPY_DRIVE_TYPE_288: 463 /* 2.88 Mb 3"5 drive */ 464 val = 5; 465 break; 466 case FLOPPY_DRIVE_TYPE_120: 467 /* 1.2 Mb 5"5 drive */ 468 val = 2; 469 break; 470 case FLOPPY_DRIVE_TYPE_NONE: 471 default: 472 val = 0; 473 break; 474 } 475 return val; 476 } 477 478 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 479 int16_t cylinders, int8_t heads, int8_t sectors) 480 { 481 rtc_set_memory(s, type_ofs, 47); 482 rtc_set_memory(s, info_ofs, cylinders); 483 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 484 rtc_set_memory(s, info_ofs + 2, heads); 485 rtc_set_memory(s, info_ofs + 3, 0xff); 486 rtc_set_memory(s, info_ofs + 4, 0xff); 487 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 488 rtc_set_memory(s, info_ofs + 6, cylinders); 489 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 490 rtc_set_memory(s, info_ofs + 8, sectors); 491 } 492 493 /* convert boot_device letter to something recognizable by the bios */ 494 static int boot_device2nibble(char boot_device) 495 { 496 switch(boot_device) { 497 case 'a': 498 case 'b': 499 return 0x01; /* floppy boot */ 500 case 'c': 501 return 0x02; /* hard drive boot */ 502 case 'd': 503 return 0x03; /* CD-ROM boot */ 504 case 'n': 505 return 0x04; /* Network boot */ 506 } 507 return 0; 508 } 509 510 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 511 { 512 #define PC_MAX_BOOT_DEVICES 3 513 int nbds, bds[3] = { 0, }; 514 int i; 515 516 nbds = strlen(boot_device); 517 if (nbds > PC_MAX_BOOT_DEVICES) { 518 error_setg(errp, "Too many boot devices for PC"); 519 return; 520 } 521 for (i = 0; i < nbds; i++) { 522 bds[i] = boot_device2nibble(boot_device[i]); 523 if (bds[i] == 0) { 524 error_setg(errp, "Invalid boot device for PC: '%c'", 525 boot_device[i]); 526 return; 527 } 528 } 529 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 530 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 531 } 532 533 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 534 { 535 set_boot_dev(opaque, boot_device, errp); 536 } 537 538 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 539 { 540 int val, nb, i; 541 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 542 FLOPPY_DRIVE_TYPE_NONE }; 543 544 /* floppy type */ 545 if (floppy) { 546 for (i = 0; i < 2; i++) { 547 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 548 } 549 } 550 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 551 cmos_get_fd_drive_type(fd_type[1]); 552 rtc_set_memory(rtc_state, 0x10, val); 553 554 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 555 nb = 0; 556 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 557 nb++; 558 } 559 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 560 nb++; 561 } 562 switch (nb) { 563 case 0: 564 break; 565 case 1: 566 val |= 0x01; /* 1 drive, ready for boot */ 567 break; 568 case 2: 569 val |= 0x41; /* 2 drives, ready for boot */ 570 break; 571 } 572 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 573 } 574 575 typedef struct pc_cmos_init_late_arg { 576 ISADevice *rtc_state; 577 BusState *idebus[2]; 578 } pc_cmos_init_late_arg; 579 580 typedef struct check_fdc_state { 581 ISADevice *floppy; 582 bool multiple; 583 } CheckFdcState; 584 585 static int check_fdc(Object *obj, void *opaque) 586 { 587 CheckFdcState *state = opaque; 588 Object *fdc; 589 uint32_t iobase; 590 Error *local_err = NULL; 591 592 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 593 if (!fdc) { 594 return 0; 595 } 596 597 iobase = object_property_get_uint(obj, "iobase", &local_err); 598 if (local_err || iobase != 0x3f0) { 599 error_free(local_err); 600 return 0; 601 } 602 603 if (state->floppy) { 604 state->multiple = true; 605 } else { 606 state->floppy = ISA_DEVICE(obj); 607 } 608 return 0; 609 } 610 611 static const char * const fdc_container_path[] = { 612 "/unattached", "/peripheral", "/peripheral-anon" 613 }; 614 615 /* 616 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 617 * and ACPI objects. 618 */ 619 ISADevice *pc_find_fdc0(void) 620 { 621 int i; 622 Object *container; 623 CheckFdcState state = { 0 }; 624 625 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 626 container = container_get(qdev_get_machine(), fdc_container_path[i]); 627 object_child_foreach(container, check_fdc, &state); 628 } 629 630 if (state.multiple) { 631 warn_report("multiple floppy disk controllers with " 632 "iobase=0x3f0 have been found"); 633 error_printf("the one being picked for CMOS setup might not reflect " 634 "your intent"); 635 } 636 637 return state.floppy; 638 } 639 640 static void pc_cmos_init_late(void *opaque) 641 { 642 pc_cmos_init_late_arg *arg = opaque; 643 ISADevice *s = arg->rtc_state; 644 int16_t cylinders; 645 int8_t heads, sectors; 646 int val; 647 int i, trans; 648 649 val = 0; 650 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 651 &cylinders, &heads, §ors) >= 0) { 652 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 653 val |= 0xf0; 654 } 655 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 656 &cylinders, &heads, §ors) >= 0) { 657 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 658 val |= 0x0f; 659 } 660 rtc_set_memory(s, 0x12, val); 661 662 val = 0; 663 for (i = 0; i < 4; i++) { 664 /* NOTE: ide_get_geometry() returns the physical 665 geometry. It is always such that: 1 <= sects <= 63, 1 666 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 667 geometry can be different if a translation is done. */ 668 if (arg->idebus[i / 2] && 669 ide_get_geometry(arg->idebus[i / 2], i % 2, 670 &cylinders, &heads, §ors) >= 0) { 671 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 672 assert((trans & ~3) == 0); 673 val |= trans << (i * 2); 674 } 675 } 676 rtc_set_memory(s, 0x39, val); 677 678 pc_cmos_init_floppy(s, pc_find_fdc0()); 679 680 qemu_unregister_reset(pc_cmos_init_late, opaque); 681 } 682 683 void pc_cmos_init(PCMachineState *pcms, 684 BusState *idebus0, BusState *idebus1, 685 ISADevice *s) 686 { 687 int val; 688 static pc_cmos_init_late_arg arg; 689 690 /* various important CMOS locations needed by PC/Bochs bios */ 691 692 /* memory size */ 693 /* base memory (first MiB) */ 694 val = MIN(pcms->below_4g_mem_size / KiB, 640); 695 rtc_set_memory(s, 0x15, val); 696 rtc_set_memory(s, 0x16, val >> 8); 697 /* extended memory (next 64MiB) */ 698 if (pcms->below_4g_mem_size > 1 * MiB) { 699 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 700 } else { 701 val = 0; 702 } 703 if (val > 65535) 704 val = 65535; 705 rtc_set_memory(s, 0x17, val); 706 rtc_set_memory(s, 0x18, val >> 8); 707 rtc_set_memory(s, 0x30, val); 708 rtc_set_memory(s, 0x31, val >> 8); 709 /* memory between 16MiB and 4GiB */ 710 if (pcms->below_4g_mem_size > 16 * MiB) { 711 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 712 } else { 713 val = 0; 714 } 715 if (val > 65535) 716 val = 65535; 717 rtc_set_memory(s, 0x34, val); 718 rtc_set_memory(s, 0x35, val >> 8); 719 /* memory above 4GiB */ 720 val = pcms->above_4g_mem_size / 65536; 721 rtc_set_memory(s, 0x5b, val); 722 rtc_set_memory(s, 0x5c, val >> 8); 723 rtc_set_memory(s, 0x5d, val >> 16); 724 725 object_property_add_link(OBJECT(pcms), "rtc_state", 726 TYPE_ISA_DEVICE, 727 (Object **)&pcms->rtc, 728 object_property_allow_set_link, 729 OBJ_PROP_LINK_STRONG, &error_abort); 730 object_property_set_link(OBJECT(pcms), OBJECT(s), 731 "rtc_state", &error_abort); 732 733 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 734 735 val = 0; 736 val |= 0x02; /* FPU is there */ 737 val |= 0x04; /* PS/2 mouse installed */ 738 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 739 740 /* hard drives and FDC */ 741 arg.rtc_state = s; 742 arg.idebus[0] = idebus0; 743 arg.idebus[1] = idebus1; 744 qemu_register_reset(pc_cmos_init_late, &arg); 745 } 746 747 #define TYPE_PORT92 "port92" 748 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 749 750 /* port 92 stuff: could be split off */ 751 typedef struct Port92State { 752 ISADevice parent_obj; 753 754 MemoryRegion io; 755 uint8_t outport; 756 qemu_irq a20_out; 757 } Port92State; 758 759 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 760 unsigned size) 761 { 762 Port92State *s = opaque; 763 int oldval = s->outport; 764 765 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 766 s->outport = val; 767 qemu_set_irq(s->a20_out, (val >> 1) & 1); 768 if ((val & 1) && !(oldval & 1)) { 769 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 770 } 771 } 772 773 static uint64_t port92_read(void *opaque, hwaddr addr, 774 unsigned size) 775 { 776 Port92State *s = opaque; 777 uint32_t ret; 778 779 ret = s->outport; 780 DPRINTF("port92: read 0x%02x\n", ret); 781 return ret; 782 } 783 784 static void port92_init(ISADevice *dev, qemu_irq a20_out) 785 { 786 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 787 } 788 789 static const VMStateDescription vmstate_port92_isa = { 790 .name = "port92", 791 .version_id = 1, 792 .minimum_version_id = 1, 793 .fields = (VMStateField[]) { 794 VMSTATE_UINT8(outport, Port92State), 795 VMSTATE_END_OF_LIST() 796 } 797 }; 798 799 static void port92_reset(DeviceState *d) 800 { 801 Port92State *s = PORT92(d); 802 803 s->outport &= ~1; 804 } 805 806 static const MemoryRegionOps port92_ops = { 807 .read = port92_read, 808 .write = port92_write, 809 .impl = { 810 .min_access_size = 1, 811 .max_access_size = 1, 812 }, 813 .endianness = DEVICE_LITTLE_ENDIAN, 814 }; 815 816 static void port92_initfn(Object *obj) 817 { 818 Port92State *s = PORT92(obj); 819 820 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 821 822 s->outport = 0; 823 824 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 825 } 826 827 static void port92_realizefn(DeviceState *dev, Error **errp) 828 { 829 ISADevice *isadev = ISA_DEVICE(dev); 830 Port92State *s = PORT92(dev); 831 832 isa_register_ioport(isadev, &s->io, 0x92); 833 } 834 835 static void port92_class_initfn(ObjectClass *klass, void *data) 836 { 837 DeviceClass *dc = DEVICE_CLASS(klass); 838 839 dc->realize = port92_realizefn; 840 dc->reset = port92_reset; 841 dc->vmsd = &vmstate_port92_isa; 842 /* 843 * Reason: unlike ordinary ISA devices, this one needs additional 844 * wiring: its A20 output line needs to be wired up by 845 * port92_init(). 846 */ 847 dc->user_creatable = false; 848 } 849 850 static const TypeInfo port92_info = { 851 .name = TYPE_PORT92, 852 .parent = TYPE_ISA_DEVICE, 853 .instance_size = sizeof(Port92State), 854 .instance_init = port92_initfn, 855 .class_init = port92_class_initfn, 856 }; 857 858 static void port92_register_types(void) 859 { 860 type_register_static(&port92_info); 861 } 862 863 type_init(port92_register_types) 864 865 static void handle_a20_line_change(void *opaque, int irq, int level) 866 { 867 X86CPU *cpu = opaque; 868 869 /* XXX: send to all CPUs ? */ 870 /* XXX: add logic to handle multiple A20 line sources */ 871 x86_cpu_set_a20(cpu, level); 872 } 873 874 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 875 { 876 int index = le32_to_cpu(e820_reserve.count); 877 struct e820_entry *entry; 878 879 if (type != E820_RAM) { 880 /* old FW_CFG_E820_TABLE entry -- reservations only */ 881 if (index >= E820_NR_ENTRIES) { 882 return -EBUSY; 883 } 884 entry = &e820_reserve.entry[index++]; 885 886 entry->address = cpu_to_le64(address); 887 entry->length = cpu_to_le64(length); 888 entry->type = cpu_to_le32(type); 889 890 e820_reserve.count = cpu_to_le32(index); 891 } 892 893 /* new "etc/e820" file -- include ram too */ 894 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 895 e820_table[e820_entries].address = cpu_to_le64(address); 896 e820_table[e820_entries].length = cpu_to_le64(length); 897 e820_table[e820_entries].type = cpu_to_le32(type); 898 e820_entries++; 899 900 return e820_entries; 901 } 902 903 int e820_get_num_entries(void) 904 { 905 return e820_entries; 906 } 907 908 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 909 { 910 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 911 *address = le64_to_cpu(e820_table[idx].address); 912 *length = le64_to_cpu(e820_table[idx].length); 913 return true; 914 } 915 return false; 916 } 917 918 /* Calculates initial APIC ID for a specific CPU index 919 * 920 * Currently we need to be able to calculate the APIC ID from the CPU index 921 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 922 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 923 * all CPUs up to max_cpus. 924 */ 925 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, 926 unsigned int cpu_index) 927 { 928 MachineState *ms = MACHINE(pcms); 929 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 930 uint32_t correct_id; 931 static bool warned; 932 933 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, 934 ms->smp.threads, cpu_index); 935 if (pcmc->compat_apic_id_mode) { 936 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 937 error_report("APIC IDs set in compatibility mode, " 938 "CPU topology won't match the configuration"); 939 warned = true; 940 } 941 return cpu_index; 942 } else { 943 return correct_id; 944 } 945 } 946 947 static void pc_build_smbios(PCMachineState *pcms) 948 { 949 uint8_t *smbios_tables, *smbios_anchor; 950 size_t smbios_tables_len, smbios_anchor_len; 951 struct smbios_phys_mem_area *mem_array; 952 unsigned i, array_count; 953 MachineState *ms = MACHINE(pcms); 954 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 955 956 /* tell smbios about cpuid version and features */ 957 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 958 959 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); 960 if (smbios_tables) { 961 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 962 smbios_tables, smbios_tables_len); 963 } 964 965 /* build the array of physical mem area from e820 table */ 966 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 967 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 968 uint64_t addr, len; 969 970 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 971 mem_array[array_count].address = addr; 972 mem_array[array_count].length = len; 973 array_count++; 974 } 975 } 976 smbios_get_tables(ms, mem_array, array_count, 977 &smbios_tables, &smbios_tables_len, 978 &smbios_anchor, &smbios_anchor_len); 979 g_free(mem_array); 980 981 if (smbios_anchor) { 982 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 983 smbios_tables, smbios_tables_len); 984 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 985 smbios_anchor, smbios_anchor_len); 986 } 987 } 988 989 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 990 { 991 FWCfgState *fw_cfg; 992 uint64_t *numa_fw_cfg; 993 int i; 994 const CPUArchIdList *cpus; 995 MachineClass *mc = MACHINE_GET_CLASS(pcms); 996 997 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 998 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 999 1000 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1001 * 1002 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1003 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1004 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1005 * for CPU hotplug also uses APIC ID and not "CPU index". 1006 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1007 * but the "limit to the APIC ID values SeaBIOS may see". 1008 * 1009 * So for compatibility reasons with old BIOSes we are stuck with 1010 * "etc/max-cpus" actually being apic_id_limit 1011 */ 1012 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1013 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1014 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1015 acpi_tables, acpi_tables_len); 1016 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1017 1018 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1019 &e820_reserve, sizeof(e820_reserve)); 1020 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1021 sizeof(struct e820_entry) * e820_entries); 1022 1023 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1024 /* allocate memory for the NUMA channel: one (64bit) word for the number 1025 * of nodes, one word for each VCPU->node and one word for each node to 1026 * hold the amount of memory. 1027 */ 1028 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1029 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1030 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1031 for (i = 0; i < cpus->len; i++) { 1032 unsigned int apic_id = cpus->cpus[i].arch_id; 1033 assert(apic_id < pcms->apic_id_limit); 1034 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1035 } 1036 for (i = 0; i < nb_numa_nodes; i++) { 1037 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1038 cpu_to_le64(numa_info[i].node_mem); 1039 } 1040 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1041 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1042 sizeof(*numa_fw_cfg)); 1043 1044 return fw_cfg; 1045 } 1046 1047 static long get_file_size(FILE *f) 1048 { 1049 long where, size; 1050 1051 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1052 1053 where = ftell(f); 1054 fseek(f, 0, SEEK_END); 1055 size = ftell(f); 1056 fseek(f, where, SEEK_SET); 1057 1058 return size; 1059 } 1060 1061 struct setup_data { 1062 uint64_t next; 1063 uint32_t type; 1064 uint32_t len; 1065 uint8_t data[0]; 1066 } __attribute__((packed)); 1067 1068 1069 /* 1070 * The entry point into the kernel for PVH boot is different from 1071 * the native entry point. The PVH entry is defined by the x86/HVM 1072 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 1073 * 1074 * This function is passed to load_elf() when it is called from 1075 * load_elfboot() which then additionally checks for an ELF Note of 1076 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 1077 * parse the PVH entry address from the ELF Note. 1078 * 1079 * Due to trickery in elf_opts.h, load_elf() is actually available as 1080 * load_elf32() or load_elf64() and this routine needs to be able 1081 * to deal with being called as 32 or 64 bit. 1082 * 1083 * The address of the PVH entry point is saved to the 'pvh_start_addr' 1084 * global variable. (although the entry point is 32-bit, the kernel 1085 * binary can be either 32-bit or 64-bit). 1086 */ 1087 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 1088 { 1089 size_t *elf_note_data_addr; 1090 1091 /* Check if ELF Note header passed in is valid */ 1092 if (arg1 == NULL) { 1093 return 0; 1094 } 1095 1096 if (is64) { 1097 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 1098 uint64_t nhdr_size64 = sizeof(struct elf64_note); 1099 uint64_t phdr_align = *(uint64_t *)arg2; 1100 uint64_t nhdr_namesz = nhdr64->n_namesz; 1101 1102 elf_note_data_addr = 1103 ((void *)nhdr64) + nhdr_size64 + 1104 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1105 } else { 1106 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 1107 uint32_t nhdr_size32 = sizeof(struct elf32_note); 1108 uint32_t phdr_align = *(uint32_t *)arg2; 1109 uint32_t nhdr_namesz = nhdr32->n_namesz; 1110 1111 elf_note_data_addr = 1112 ((void *)nhdr32) + nhdr_size32 + 1113 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1114 } 1115 1116 pvh_start_addr = *elf_note_data_addr; 1117 1118 return pvh_start_addr; 1119 } 1120 1121 static bool load_elfboot(const char *kernel_filename, 1122 int kernel_file_size, 1123 uint8_t *header, 1124 size_t pvh_xen_start_addr, 1125 FWCfgState *fw_cfg) 1126 { 1127 uint32_t flags = 0; 1128 uint32_t mh_load_addr = 0; 1129 uint32_t elf_kernel_size = 0; 1130 uint64_t elf_entry; 1131 uint64_t elf_low, elf_high; 1132 int kernel_size; 1133 1134 if (ldl_p(header) != 0x464c457f) { 1135 return false; /* no elfboot */ 1136 } 1137 1138 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 1139 flags = elf_is64 ? 1140 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 1141 1142 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 1143 error_report("elfboot unsupported flags = %x", flags); 1144 exit(1); 1145 } 1146 1147 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 1148 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1149 NULL, &elf_note_type, &elf_entry, 1150 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1151 0, 0); 1152 1153 if (kernel_size < 0) { 1154 error_report("Error while loading elf kernel"); 1155 exit(1); 1156 } 1157 mh_load_addr = elf_low; 1158 elf_kernel_size = elf_high - elf_low; 1159 1160 if (pvh_start_addr == 0) { 1161 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1162 exit(1); 1163 } 1164 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1165 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1166 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1167 1168 return true; 1169 } 1170 1171 static void load_linux(PCMachineState *pcms, 1172 FWCfgState *fw_cfg) 1173 { 1174 uint16_t protocol; 1175 int setup_size, kernel_size, cmdline_size; 1176 int dtb_size, setup_data_offset; 1177 uint32_t initrd_max; 1178 uint8_t header[8192], *setup, *kernel; 1179 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1180 FILE *f; 1181 char *vmode; 1182 MachineState *machine = MACHINE(pcms); 1183 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1184 struct setup_data *setup_data; 1185 const char *kernel_filename = machine->kernel_filename; 1186 const char *initrd_filename = machine->initrd_filename; 1187 const char *dtb_filename = machine->dtb; 1188 const char *kernel_cmdline = machine->kernel_cmdline; 1189 1190 /* Align to 16 bytes as a paranoia measure */ 1191 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1192 1193 /* load the kernel header */ 1194 f = fopen(kernel_filename, "rb"); 1195 if (!f || !(kernel_size = get_file_size(f)) || 1196 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1197 MIN(ARRAY_SIZE(header), kernel_size)) { 1198 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1199 kernel_filename, strerror(errno)); 1200 exit(1); 1201 } 1202 1203 /* kernel protocol version */ 1204 #if 0 1205 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1206 #endif 1207 if (ldl_p(header+0x202) == 0x53726448) { 1208 protocol = lduw_p(header+0x206); 1209 } else { 1210 /* 1211 * This could be a multiboot kernel. If it is, let's stop treating it 1212 * like a Linux kernel. 1213 * Note: some multiboot images could be in the ELF format (the same of 1214 * PVH), so we try multiboot first since we check the multiboot magic 1215 * header before to load it. 1216 */ 1217 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1218 kernel_cmdline, kernel_size, header)) { 1219 return; 1220 } 1221 /* 1222 * Check if the file is an uncompressed kernel file (ELF) and load it, 1223 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1224 * If load_elfboot() is successful, populate the fw_cfg info. 1225 */ 1226 if (pcmc->pvh_enabled && 1227 load_elfboot(kernel_filename, kernel_size, 1228 header, pvh_start_addr, fw_cfg)) { 1229 fclose(f); 1230 1231 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1232 strlen(kernel_cmdline) + 1); 1233 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1234 1235 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1236 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1237 header, sizeof(header)); 1238 1239 /* load initrd */ 1240 if (initrd_filename) { 1241 gsize initrd_size; 1242 gchar *initrd_data; 1243 GError *gerr = NULL; 1244 1245 if (!g_file_get_contents(initrd_filename, &initrd_data, 1246 &initrd_size, &gerr)) { 1247 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1248 initrd_filename, gerr->message); 1249 exit(1); 1250 } 1251 1252 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1253 if (initrd_size >= initrd_max) { 1254 fprintf(stderr, "qemu: initrd is too large, cannot support." 1255 "(max: %"PRIu32", need %"PRId64")\n", 1256 initrd_max, (uint64_t)initrd_size); 1257 exit(1); 1258 } 1259 1260 initrd_addr = (initrd_max - initrd_size) & ~4095; 1261 1262 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1263 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1264 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1265 initrd_size); 1266 } 1267 1268 option_rom[nb_option_roms].bootindex = 0; 1269 option_rom[nb_option_roms].name = "pvh.bin"; 1270 nb_option_roms++; 1271 1272 return; 1273 } 1274 protocol = 0; 1275 } 1276 1277 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1278 /* Low kernel */ 1279 real_addr = 0x90000; 1280 cmdline_addr = 0x9a000 - cmdline_size; 1281 prot_addr = 0x10000; 1282 } else if (protocol < 0x202) { 1283 /* High but ancient kernel */ 1284 real_addr = 0x90000; 1285 cmdline_addr = 0x9a000 - cmdline_size; 1286 prot_addr = 0x100000; 1287 } else { 1288 /* High and recent kernel */ 1289 real_addr = 0x10000; 1290 cmdline_addr = 0x20000; 1291 prot_addr = 0x100000; 1292 } 1293 1294 #if 0 1295 fprintf(stderr, 1296 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1297 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1298 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1299 real_addr, 1300 cmdline_addr, 1301 prot_addr); 1302 #endif 1303 1304 /* highest address for loading the initrd */ 1305 if (protocol >= 0x20c && 1306 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1307 /* 1308 * Linux has supported initrd up to 4 GB for a very long time (2007, 1309 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1310 * though it only sets initrd_max to 2 GB to "work around bootloader 1311 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1312 * has supported this. 1313 * 1314 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1315 * be loaded into any address. 1316 * 1317 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1318 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1319 * field). 1320 * 1321 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1322 */ 1323 initrd_max = UINT32_MAX; 1324 } else if (protocol >= 0x203) { 1325 initrd_max = ldl_p(header+0x22c); 1326 } else { 1327 initrd_max = 0x37ffffff; 1328 } 1329 1330 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1331 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1332 } 1333 1334 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1335 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1336 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1337 1338 if (protocol >= 0x202) { 1339 stl_p(header+0x228, cmdline_addr); 1340 } else { 1341 stw_p(header+0x20, 0xA33F); 1342 stw_p(header+0x22, cmdline_addr-real_addr); 1343 } 1344 1345 /* handle vga= parameter */ 1346 vmode = strstr(kernel_cmdline, "vga="); 1347 if (vmode) { 1348 unsigned int video_mode; 1349 /* skip "vga=" */ 1350 vmode += 4; 1351 if (!strncmp(vmode, "normal", 6)) { 1352 video_mode = 0xffff; 1353 } else if (!strncmp(vmode, "ext", 3)) { 1354 video_mode = 0xfffe; 1355 } else if (!strncmp(vmode, "ask", 3)) { 1356 video_mode = 0xfffd; 1357 } else { 1358 video_mode = strtol(vmode, NULL, 0); 1359 } 1360 stw_p(header+0x1fa, video_mode); 1361 } 1362 1363 /* loader type */ 1364 /* High nybble = B reserved for QEMU; low nybble is revision number. 1365 If this code is substantially changed, you may want to consider 1366 incrementing the revision. */ 1367 if (protocol >= 0x200) { 1368 header[0x210] = 0xB0; 1369 } 1370 /* heap */ 1371 if (protocol >= 0x201) { 1372 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1373 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1374 } 1375 1376 /* load initrd */ 1377 if (initrd_filename) { 1378 gsize initrd_size; 1379 gchar *initrd_data; 1380 GError *gerr = NULL; 1381 1382 if (protocol < 0x200) { 1383 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1384 exit(1); 1385 } 1386 1387 if (!g_file_get_contents(initrd_filename, &initrd_data, 1388 &initrd_size, &gerr)) { 1389 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1390 initrd_filename, gerr->message); 1391 exit(1); 1392 } 1393 if (initrd_size >= initrd_max) { 1394 fprintf(stderr, "qemu: initrd is too large, cannot support." 1395 "(max: %"PRIu32", need %"PRId64")\n", 1396 initrd_max, (uint64_t)initrd_size); 1397 exit(1); 1398 } 1399 1400 initrd_addr = (initrd_max-initrd_size) & ~4095; 1401 1402 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1403 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1404 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1405 1406 stl_p(header+0x218, initrd_addr); 1407 stl_p(header+0x21c, initrd_size); 1408 } 1409 1410 /* load kernel and setup */ 1411 setup_size = header[0x1f1]; 1412 if (setup_size == 0) { 1413 setup_size = 4; 1414 } 1415 setup_size = (setup_size+1)*512; 1416 if (setup_size > kernel_size) { 1417 fprintf(stderr, "qemu: invalid kernel header\n"); 1418 exit(1); 1419 } 1420 kernel_size -= setup_size; 1421 1422 setup = g_malloc(setup_size); 1423 kernel = g_malloc(kernel_size); 1424 fseek(f, 0, SEEK_SET); 1425 if (fread(setup, 1, setup_size, f) != setup_size) { 1426 fprintf(stderr, "fread() failed\n"); 1427 exit(1); 1428 } 1429 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1430 fprintf(stderr, "fread() failed\n"); 1431 exit(1); 1432 } 1433 fclose(f); 1434 1435 /* append dtb to kernel */ 1436 if (dtb_filename) { 1437 if (protocol < 0x209) { 1438 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1439 exit(1); 1440 } 1441 1442 dtb_size = get_image_size(dtb_filename); 1443 if (dtb_size <= 0) { 1444 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1445 dtb_filename, strerror(errno)); 1446 exit(1); 1447 } 1448 1449 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1450 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1451 kernel = g_realloc(kernel, kernel_size); 1452 1453 stq_p(header+0x250, prot_addr + setup_data_offset); 1454 1455 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1456 setup_data->next = 0; 1457 setup_data->type = cpu_to_le32(SETUP_DTB); 1458 setup_data->len = cpu_to_le32(dtb_size); 1459 1460 load_image_size(dtb_filename, setup_data->data, dtb_size); 1461 } 1462 1463 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1464 1465 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1466 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1467 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1468 1469 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1470 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1471 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1472 1473 option_rom[nb_option_roms].bootindex = 0; 1474 option_rom[nb_option_roms].name = "linuxboot.bin"; 1475 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1476 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1477 } 1478 nb_option_roms++; 1479 } 1480 1481 #define NE2000_NB_MAX 6 1482 1483 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1484 0x280, 0x380 }; 1485 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1486 1487 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1488 { 1489 static int nb_ne2k = 0; 1490 1491 if (nb_ne2k == NE2000_NB_MAX) 1492 return; 1493 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1494 ne2000_irq[nb_ne2k], nd); 1495 nb_ne2k++; 1496 } 1497 1498 DeviceState *cpu_get_current_apic(void) 1499 { 1500 if (current_cpu) { 1501 X86CPU *cpu = X86_CPU(current_cpu); 1502 return cpu->apic_state; 1503 } else { 1504 return NULL; 1505 } 1506 } 1507 1508 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1509 { 1510 X86CPU *cpu = opaque; 1511 1512 if (level) { 1513 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1514 } 1515 } 1516 1517 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) 1518 { 1519 Object *cpu = NULL; 1520 Error *local_err = NULL; 1521 CPUX86State *env = NULL; 1522 1523 cpu = object_new(MACHINE(pcms)->cpu_type); 1524 1525 env = &X86_CPU(cpu)->env; 1526 env->nr_dies = pcms->smp_dies; 1527 1528 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1529 object_property_set_bool(cpu, true, "realized", &local_err); 1530 1531 object_unref(cpu); 1532 error_propagate(errp, local_err); 1533 } 1534 1535 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 1536 { 1537 PCMachineState *pcms = PC_MACHINE(ms); 1538 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); 1539 Error *local_err = NULL; 1540 1541 if (id < 0) { 1542 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1543 return; 1544 } 1545 1546 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1547 error_setg(errp, "Unable to add CPU: %" PRIi64 1548 ", resulting APIC ID (%" PRIi64 ") is too large", 1549 id, apic_id); 1550 return; 1551 } 1552 1553 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err); 1554 if (local_err) { 1555 error_propagate(errp, local_err); 1556 return; 1557 } 1558 } 1559 1560 void pc_cpus_init(PCMachineState *pcms) 1561 { 1562 int i; 1563 const CPUArchIdList *possible_cpus; 1564 MachineState *ms = MACHINE(pcms); 1565 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1566 1567 /* Calculates the limit to CPU APIC ID values 1568 * 1569 * Limit for the APIC ID value, so that all 1570 * CPU APIC IDs are < pcms->apic_id_limit. 1571 * 1572 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1573 */ 1574 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, 1575 ms->smp.max_cpus - 1) + 1; 1576 possible_cpus = mc->possible_cpu_arch_ids(ms); 1577 for (i = 0; i < ms->smp.cpus; i++) { 1578 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal); 1579 } 1580 } 1581 1582 static void pc_build_feature_control_file(PCMachineState *pcms) 1583 { 1584 MachineState *ms = MACHINE(pcms); 1585 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1586 CPUX86State *env = &cpu->env; 1587 uint32_t unused, ecx, edx; 1588 uint64_t feature_control_bits = 0; 1589 uint64_t *val; 1590 1591 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1592 if (ecx & CPUID_EXT_VMX) { 1593 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1594 } 1595 1596 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1597 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1598 (env->mcg_cap & MCG_LMCE_P)) { 1599 feature_control_bits |= FEATURE_CONTROL_LMCE; 1600 } 1601 1602 if (!feature_control_bits) { 1603 return; 1604 } 1605 1606 val = g_malloc(sizeof(*val)); 1607 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1608 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1609 } 1610 1611 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1612 { 1613 if (cpus_count > 0xff) { 1614 /* If the number of CPUs can't be represented in 8 bits, the 1615 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1616 * to make old BIOSes fail more predictably. 1617 */ 1618 rtc_set_memory(rtc, 0x5f, 0); 1619 } else { 1620 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1621 } 1622 } 1623 1624 static 1625 void pc_machine_done(Notifier *notifier, void *data) 1626 { 1627 PCMachineState *pcms = container_of(notifier, 1628 PCMachineState, machine_done); 1629 PCIBus *bus = pcms->bus; 1630 1631 /* set the number of CPUs */ 1632 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1633 1634 if (bus) { 1635 int extra_hosts = 0; 1636 1637 QLIST_FOREACH(bus, &bus->child, sibling) { 1638 /* look for expander root buses */ 1639 if (pci_bus_is_root(bus)) { 1640 extra_hosts++; 1641 } 1642 } 1643 if (extra_hosts && pcms->fw_cfg) { 1644 uint64_t *val = g_malloc(sizeof(*val)); 1645 *val = cpu_to_le64(extra_hosts); 1646 fw_cfg_add_file(pcms->fw_cfg, 1647 "etc/extra-pci-roots", val, sizeof(*val)); 1648 } 1649 } 1650 1651 acpi_setup(); 1652 if (pcms->fw_cfg) { 1653 pc_build_smbios(pcms); 1654 pc_build_feature_control_file(pcms); 1655 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1656 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1657 } 1658 1659 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1660 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1661 1662 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1663 iommu->intr_eim != ON_OFF_AUTO_ON) { 1664 error_report("current -smp configuration requires " 1665 "Extended Interrupt Mode enabled. " 1666 "You can add an IOMMU using: " 1667 "-device intel-iommu,intremap=on,eim=on"); 1668 exit(EXIT_FAILURE); 1669 } 1670 } 1671 } 1672 1673 void pc_guest_info_init(PCMachineState *pcms) 1674 { 1675 int i; 1676 1677 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1678 pcms->numa_nodes = nb_numa_nodes; 1679 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1680 sizeof *pcms->node_mem); 1681 for (i = 0; i < nb_numa_nodes; i++) { 1682 pcms->node_mem[i] = numa_info[i].node_mem; 1683 } 1684 1685 pcms->machine_done.notify = pc_machine_done; 1686 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1687 } 1688 1689 /* setup pci memory address space mapping into system address space */ 1690 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1691 MemoryRegion *pci_address_space) 1692 { 1693 /* Set to lower priority than RAM */ 1694 memory_region_add_subregion_overlap(system_memory, 0x0, 1695 pci_address_space, -1); 1696 } 1697 1698 void xen_load_linux(PCMachineState *pcms) 1699 { 1700 int i; 1701 FWCfgState *fw_cfg; 1702 1703 assert(MACHINE(pcms)->kernel_filename != NULL); 1704 1705 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1706 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1707 rom_set_fw(fw_cfg); 1708 1709 load_linux(pcms, fw_cfg); 1710 for (i = 0; i < nb_option_roms; i++) { 1711 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1712 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1713 !strcmp(option_rom[i].name, "pvh.bin") || 1714 !strcmp(option_rom[i].name, "multiboot.bin")); 1715 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1716 } 1717 pcms->fw_cfg = fw_cfg; 1718 } 1719 1720 void pc_memory_init(PCMachineState *pcms, 1721 MemoryRegion *system_memory, 1722 MemoryRegion *rom_memory, 1723 MemoryRegion **ram_memory) 1724 { 1725 int linux_boot, i; 1726 MemoryRegion *ram, *option_rom_mr; 1727 MemoryRegion *ram_below_4g, *ram_above_4g; 1728 FWCfgState *fw_cfg; 1729 MachineState *machine = MACHINE(pcms); 1730 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1731 1732 assert(machine->ram_size == pcms->below_4g_mem_size + 1733 pcms->above_4g_mem_size); 1734 1735 linux_boot = (machine->kernel_filename != NULL); 1736 1737 /* Allocate RAM. We allocate it as a single memory region and use 1738 * aliases to address portions of it, mostly for backwards compatibility 1739 * with older qemus that used qemu_ram_alloc(). 1740 */ 1741 ram = g_malloc(sizeof(*ram)); 1742 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1743 machine->ram_size); 1744 *ram_memory = ram; 1745 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1746 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1747 0, pcms->below_4g_mem_size); 1748 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1749 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1750 if (pcms->above_4g_mem_size > 0) { 1751 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1752 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1753 pcms->below_4g_mem_size, 1754 pcms->above_4g_mem_size); 1755 memory_region_add_subregion(system_memory, 0x100000000ULL, 1756 ram_above_4g); 1757 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1758 } 1759 1760 if (!pcmc->has_reserved_memory && 1761 (machine->ram_slots || 1762 (machine->maxram_size > machine->ram_size))) { 1763 MachineClass *mc = MACHINE_GET_CLASS(machine); 1764 1765 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1766 mc->name); 1767 exit(EXIT_FAILURE); 1768 } 1769 1770 /* always allocate the device memory information */ 1771 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1772 1773 /* initialize device memory address space */ 1774 if (pcmc->has_reserved_memory && 1775 (machine->ram_size < machine->maxram_size)) { 1776 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1777 1778 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1779 error_report("unsupported amount of memory slots: %"PRIu64, 1780 machine->ram_slots); 1781 exit(EXIT_FAILURE); 1782 } 1783 1784 if (QEMU_ALIGN_UP(machine->maxram_size, 1785 TARGET_PAGE_SIZE) != machine->maxram_size) { 1786 error_report("maximum memory size must by aligned to multiple of " 1787 "%d bytes", TARGET_PAGE_SIZE); 1788 exit(EXIT_FAILURE); 1789 } 1790 1791 machine->device_memory->base = 1792 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1793 1794 if (pcmc->enforce_aligned_dimm) { 1795 /* size device region assuming 1G page max alignment per slot */ 1796 device_mem_size += (1 * GiB) * machine->ram_slots; 1797 } 1798 1799 if ((machine->device_memory->base + device_mem_size) < 1800 device_mem_size) { 1801 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1802 machine->maxram_size); 1803 exit(EXIT_FAILURE); 1804 } 1805 1806 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1807 "device-memory", device_mem_size); 1808 memory_region_add_subregion(system_memory, machine->device_memory->base, 1809 &machine->device_memory->mr); 1810 } 1811 1812 /* Initialize PC system firmware */ 1813 pc_system_firmware_init(pcms, rom_memory); 1814 1815 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1816 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1817 &error_fatal); 1818 if (pcmc->pci_enabled) { 1819 memory_region_set_readonly(option_rom_mr, true); 1820 } 1821 memory_region_add_subregion_overlap(rom_memory, 1822 PC_ROM_MIN_VGA, 1823 option_rom_mr, 1824 1); 1825 1826 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1827 1828 rom_set_fw(fw_cfg); 1829 1830 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1831 uint64_t *val = g_malloc(sizeof(*val)); 1832 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1833 uint64_t res_mem_end = machine->device_memory->base; 1834 1835 if (!pcmc->broken_reserved_end) { 1836 res_mem_end += memory_region_size(&machine->device_memory->mr); 1837 } 1838 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1839 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1840 } 1841 1842 if (linux_boot) { 1843 load_linux(pcms, fw_cfg); 1844 } 1845 1846 for (i = 0; i < nb_option_roms; i++) { 1847 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1848 } 1849 pcms->fw_cfg = fw_cfg; 1850 1851 /* Init default IOAPIC address space */ 1852 pcms->ioapic_as = &address_space_memory; 1853 } 1854 1855 /* 1856 * The 64bit pci hole starts after "above 4G RAM" and 1857 * potentially the space reserved for memory hotplug. 1858 */ 1859 uint64_t pc_pci_hole64_start(void) 1860 { 1861 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1862 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1863 MachineState *ms = MACHINE(pcms); 1864 uint64_t hole64_start = 0; 1865 1866 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1867 hole64_start = ms->device_memory->base; 1868 if (!pcmc->broken_reserved_end) { 1869 hole64_start += memory_region_size(&ms->device_memory->mr); 1870 } 1871 } else { 1872 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1873 } 1874 1875 return ROUND_UP(hole64_start, 1 * GiB); 1876 } 1877 1878 qemu_irq pc_allocate_cpu_irq(void) 1879 { 1880 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1881 } 1882 1883 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1884 { 1885 DeviceState *dev = NULL; 1886 1887 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1888 if (pci_bus) { 1889 PCIDevice *pcidev = pci_vga_init(pci_bus); 1890 dev = pcidev ? &pcidev->qdev : NULL; 1891 } else if (isa_bus) { 1892 ISADevice *isadev = isa_vga_init(isa_bus); 1893 dev = isadev ? DEVICE(isadev) : NULL; 1894 } 1895 rom_reset_order_override(); 1896 return dev; 1897 } 1898 1899 static const MemoryRegionOps ioport80_io_ops = { 1900 .write = ioport80_write, 1901 .read = ioport80_read, 1902 .endianness = DEVICE_NATIVE_ENDIAN, 1903 .impl = { 1904 .min_access_size = 1, 1905 .max_access_size = 1, 1906 }, 1907 }; 1908 1909 static const MemoryRegionOps ioportF0_io_ops = { 1910 .write = ioportF0_write, 1911 .read = ioportF0_read, 1912 .endianness = DEVICE_NATIVE_ENDIAN, 1913 .impl = { 1914 .min_access_size = 1, 1915 .max_access_size = 1, 1916 }, 1917 }; 1918 1919 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1920 { 1921 int i; 1922 DriveInfo *fd[MAX_FD]; 1923 qemu_irq *a20_line; 1924 ISADevice *i8042, *port92, *vmmouse; 1925 1926 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1927 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1928 1929 for (i = 0; i < MAX_FD; i++) { 1930 fd[i] = drive_get(IF_FLOPPY, 0, i); 1931 create_fdctrl |= !!fd[i]; 1932 } 1933 if (create_fdctrl) { 1934 fdctrl_init_isa(isa_bus, fd); 1935 } 1936 1937 i8042 = isa_create_simple(isa_bus, "i8042"); 1938 if (!no_vmport) { 1939 vmport_init(isa_bus); 1940 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1941 } else { 1942 vmmouse = NULL; 1943 } 1944 if (vmmouse) { 1945 DeviceState *dev = DEVICE(vmmouse); 1946 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1947 qdev_init_nofail(dev); 1948 } 1949 port92 = isa_create_simple(isa_bus, "port92"); 1950 1951 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1952 i8042_setup_a20_line(i8042, a20_line[0]); 1953 port92_init(port92, a20_line[1]); 1954 g_free(a20_line); 1955 } 1956 1957 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1958 ISADevice **rtc_state, 1959 bool create_fdctrl, 1960 bool no_vmport, 1961 bool has_pit, 1962 uint32_t hpet_irqs) 1963 { 1964 int i; 1965 DeviceState *hpet = NULL; 1966 int pit_isa_irq = 0; 1967 qemu_irq pit_alt_irq = NULL; 1968 qemu_irq rtc_irq = NULL; 1969 ISADevice *pit = NULL; 1970 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1971 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1972 1973 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1974 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1975 1976 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1977 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1978 1979 /* 1980 * Check if an HPET shall be created. 1981 * 1982 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1983 * when the HPET wants to take over. Thus we have to disable the latter. 1984 */ 1985 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1986 /* In order to set property, here not using sysbus_try_create_simple */ 1987 hpet = qdev_try_create(NULL, TYPE_HPET); 1988 if (hpet) { 1989 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1990 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1991 * IRQ8 and IRQ2. 1992 */ 1993 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1994 HPET_INTCAP, NULL); 1995 if (!compat) { 1996 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1997 } 1998 qdev_init_nofail(hpet); 1999 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 2000 2001 for (i = 0; i < GSI_NUM_PINS; i++) { 2002 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 2003 } 2004 pit_isa_irq = -1; 2005 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 2006 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 2007 } 2008 } 2009 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 2010 2011 qemu_register_boot_set(pc_boot_set, *rtc_state); 2012 2013 if (!xen_enabled() && has_pit) { 2014 if (kvm_pit_in_kernel()) { 2015 pit = kvm_pit_init(isa_bus, 0x40); 2016 } else { 2017 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 2018 } 2019 if (hpet) { 2020 /* connect PIT to output control line of the HPET */ 2021 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 2022 } 2023 pcspk_init(isa_bus, pit); 2024 } 2025 2026 i8257_dma_init(isa_bus, 0); 2027 2028 /* Super I/O */ 2029 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 2030 } 2031 2032 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 2033 { 2034 int i; 2035 2036 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 2037 for (i = 0; i < nb_nics; i++) { 2038 NICInfo *nd = &nd_table[i]; 2039 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 2040 2041 if (g_str_equal(model, "ne2k_isa")) { 2042 pc_init_ne2k_isa(isa_bus, nd); 2043 } else { 2044 pci_nic_init_nofail(nd, pci_bus, model, NULL); 2045 } 2046 } 2047 rom_reset_order_override(); 2048 } 2049 2050 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 2051 { 2052 DeviceState *dev; 2053 SysBusDevice *d; 2054 unsigned int i; 2055 2056 if (kvm_ioapic_in_kernel()) { 2057 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 2058 } else { 2059 dev = qdev_create(NULL, TYPE_IOAPIC); 2060 } 2061 if (parent_name) { 2062 object_property_add_child(object_resolve_path(parent_name, NULL), 2063 "ioapic", OBJECT(dev), NULL); 2064 } 2065 qdev_init_nofail(dev); 2066 d = SYS_BUS_DEVICE(dev); 2067 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2068 2069 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2070 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2071 } 2072 } 2073 2074 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2075 Error **errp) 2076 { 2077 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2078 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2079 const MachineState *ms = MACHINE(hotplug_dev); 2080 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2081 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2082 Error *local_err = NULL; 2083 2084 /* 2085 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2086 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2087 * addition to cover this case. 2088 */ 2089 if (!pcms->acpi_dev || !acpi_enabled) { 2090 error_setg(errp, 2091 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2092 return; 2093 } 2094 2095 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2096 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2097 return; 2098 } 2099 2100 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 2101 if (local_err) { 2102 error_propagate(errp, local_err); 2103 return; 2104 } 2105 2106 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2107 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2108 } 2109 2110 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2111 DeviceState *dev, Error **errp) 2112 { 2113 Error *local_err = NULL; 2114 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2115 MachineState *ms = MACHINE(hotplug_dev); 2116 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2117 2118 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2119 if (local_err) { 2120 goto out; 2121 } 2122 2123 if (is_nvdimm) { 2124 nvdimm_plug(ms->nvdimms_state); 2125 } 2126 2127 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2128 out: 2129 error_propagate(errp, local_err); 2130 } 2131 2132 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2133 DeviceState *dev, Error **errp) 2134 { 2135 Error *local_err = NULL; 2136 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2137 2138 /* 2139 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2140 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2141 * addition to cover this case. 2142 */ 2143 if (!pcms->acpi_dev || !acpi_enabled) { 2144 error_setg(&local_err, 2145 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2146 goto out; 2147 } 2148 2149 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2150 error_setg(&local_err, 2151 "nvdimm device hot unplug is not supported yet."); 2152 goto out; 2153 } 2154 2155 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2156 &local_err); 2157 out: 2158 error_propagate(errp, local_err); 2159 } 2160 2161 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2162 DeviceState *dev, Error **errp) 2163 { 2164 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2165 Error *local_err = NULL; 2166 2167 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2168 if (local_err) { 2169 goto out; 2170 } 2171 2172 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2173 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2174 out: 2175 error_propagate(errp, local_err); 2176 } 2177 2178 static int pc_apic_cmp(const void *a, const void *b) 2179 { 2180 CPUArchId *apic_a = (CPUArchId *)a; 2181 CPUArchId *apic_b = (CPUArchId *)b; 2182 2183 return apic_a->arch_id - apic_b->arch_id; 2184 } 2185 2186 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2187 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2188 * entry corresponding to CPU's apic_id returns NULL. 2189 */ 2190 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2191 { 2192 CPUArchId apic_id, *found_cpu; 2193 2194 apic_id.arch_id = id; 2195 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2196 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2197 pc_apic_cmp); 2198 if (found_cpu && idx) { 2199 *idx = found_cpu - ms->possible_cpus->cpus; 2200 } 2201 return found_cpu; 2202 } 2203 2204 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2205 DeviceState *dev, Error **errp) 2206 { 2207 CPUArchId *found_cpu; 2208 Error *local_err = NULL; 2209 X86CPU *cpu = X86_CPU(dev); 2210 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2211 2212 if (pcms->acpi_dev) { 2213 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2214 if (local_err) { 2215 goto out; 2216 } 2217 } 2218 2219 /* increment the number of CPUs */ 2220 pcms->boot_cpus++; 2221 if (pcms->rtc) { 2222 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2223 } 2224 if (pcms->fw_cfg) { 2225 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2226 } 2227 2228 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2229 found_cpu->cpu = OBJECT(dev); 2230 out: 2231 error_propagate(errp, local_err); 2232 } 2233 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2234 DeviceState *dev, Error **errp) 2235 { 2236 int idx = -1; 2237 Error *local_err = NULL; 2238 X86CPU *cpu = X86_CPU(dev); 2239 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2240 2241 if (!pcms->acpi_dev) { 2242 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2243 goto out; 2244 } 2245 2246 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2247 assert(idx != -1); 2248 if (idx == 0) { 2249 error_setg(&local_err, "Boot CPU is unpluggable"); 2250 goto out; 2251 } 2252 2253 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2254 &local_err); 2255 if (local_err) { 2256 goto out; 2257 } 2258 2259 out: 2260 error_propagate(errp, local_err); 2261 2262 } 2263 2264 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2265 DeviceState *dev, Error **errp) 2266 { 2267 CPUArchId *found_cpu; 2268 Error *local_err = NULL; 2269 X86CPU *cpu = X86_CPU(dev); 2270 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2271 2272 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2273 if (local_err) { 2274 goto out; 2275 } 2276 2277 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2278 found_cpu->cpu = NULL; 2279 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2280 2281 /* decrement the number of CPUs */ 2282 pcms->boot_cpus--; 2283 /* Update the number of CPUs in CMOS */ 2284 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2285 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2286 out: 2287 error_propagate(errp, local_err); 2288 } 2289 2290 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2291 DeviceState *dev, Error **errp) 2292 { 2293 int idx; 2294 CPUState *cs; 2295 CPUArchId *cpu_slot; 2296 X86CPUTopoInfo topo; 2297 X86CPU *cpu = X86_CPU(dev); 2298 CPUX86State *env = &cpu->env; 2299 MachineState *ms = MACHINE(hotplug_dev); 2300 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2301 unsigned int smp_cores = ms->smp.cores; 2302 unsigned int smp_threads = ms->smp.threads; 2303 2304 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2305 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2306 ms->cpu_type); 2307 return; 2308 } 2309 2310 env->nr_dies = pcms->smp_dies; 2311 2312 /* 2313 * If APIC ID is not set, 2314 * set it based on socket/die/core/thread properties. 2315 */ 2316 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2317 int max_socket = (ms->smp.max_cpus - 1) / 2318 smp_threads / smp_cores / pcms->smp_dies; 2319 2320 if (cpu->socket_id < 0) { 2321 error_setg(errp, "CPU socket-id is not set"); 2322 return; 2323 } else if (cpu->socket_id > max_socket) { 2324 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2325 cpu->socket_id, max_socket); 2326 return; 2327 } else if (cpu->die_id > pcms->smp_dies - 1) { 2328 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 2329 cpu->die_id, max_socket); 2330 return; 2331 } 2332 if (cpu->core_id < 0) { 2333 error_setg(errp, "CPU core-id is not set"); 2334 return; 2335 } else if (cpu->core_id > (smp_cores - 1)) { 2336 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2337 cpu->core_id, smp_cores - 1); 2338 return; 2339 } 2340 if (cpu->thread_id < 0) { 2341 error_setg(errp, "CPU thread-id is not set"); 2342 return; 2343 } else if (cpu->thread_id > (smp_threads - 1)) { 2344 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2345 cpu->thread_id, smp_threads - 1); 2346 return; 2347 } 2348 2349 topo.pkg_id = cpu->socket_id; 2350 topo.die_id = cpu->die_id; 2351 topo.core_id = cpu->core_id; 2352 topo.smt_id = cpu->thread_id; 2353 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, 2354 smp_threads, &topo); 2355 } 2356 2357 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2358 if (!cpu_slot) { 2359 MachineState *ms = MACHINE(pcms); 2360 2361 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2362 smp_cores, smp_threads, &topo); 2363 error_setg(errp, 2364 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 2365 " APIC ID %" PRIu32 ", valid index range 0:%d", 2366 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 2367 cpu->apic_id, ms->possible_cpus->len - 1); 2368 return; 2369 } 2370 2371 if (cpu_slot->cpu) { 2372 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2373 idx, cpu->apic_id); 2374 return; 2375 } 2376 2377 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2378 * so that machine_query_hotpluggable_cpus would show correct values 2379 */ 2380 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2381 * once -smp refactoring is complete and there will be CPU private 2382 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2383 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2384 smp_cores, smp_threads, &topo); 2385 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2386 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2387 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2388 return; 2389 } 2390 cpu->socket_id = topo.pkg_id; 2391 2392 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 2393 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 2394 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 2395 return; 2396 } 2397 cpu->die_id = topo.die_id; 2398 2399 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2400 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2401 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2402 return; 2403 } 2404 cpu->core_id = topo.core_id; 2405 2406 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2407 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2408 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2409 return; 2410 } 2411 cpu->thread_id = topo.smt_id; 2412 2413 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 2414 !kvm_hv_vpindex_settable()) { 2415 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2416 return; 2417 } 2418 2419 cs = CPU(cpu); 2420 cs->cpu_index = idx; 2421 2422 numa_cpu_pre_plug(cpu_slot, dev, errp); 2423 } 2424 2425 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 2426 DeviceState *dev, Error **errp) 2427 { 2428 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2429 Error *local_err = NULL; 2430 2431 if (!hotplug_dev2) { 2432 /* 2433 * Without a bus hotplug handler, we cannot control the plug/unplug 2434 * order. This should never be the case on x86, however better add 2435 * a safety net. 2436 */ 2437 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 2438 return; 2439 } 2440 /* 2441 * First, see if we can plug this memory device at all. If that 2442 * succeeds, branch of to the actual hotplug handler. 2443 */ 2444 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2445 &local_err); 2446 if (!local_err) { 2447 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2448 } 2449 error_propagate(errp, local_err); 2450 } 2451 2452 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 2453 DeviceState *dev, Error **errp) 2454 { 2455 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2456 Error *local_err = NULL; 2457 2458 /* 2459 * Plug the memory device first and then branch off to the actual 2460 * hotplug handler. If that one fails, we can easily undo the memory 2461 * device bits. 2462 */ 2463 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2464 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2465 if (local_err) { 2466 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2467 } 2468 error_propagate(errp, local_err); 2469 } 2470 2471 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 2472 DeviceState *dev, Error **errp) 2473 { 2474 /* We don't support virtio pmem hot unplug */ 2475 error_setg(errp, "virtio pmem device unplug not supported."); 2476 } 2477 2478 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 2479 DeviceState *dev, Error **errp) 2480 { 2481 /* We don't support virtio pmem hot unplug */ 2482 } 2483 2484 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2485 DeviceState *dev, Error **errp) 2486 { 2487 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2488 pc_memory_pre_plug(hotplug_dev, dev, errp); 2489 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2490 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2491 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2492 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 2493 } 2494 } 2495 2496 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2497 DeviceState *dev, Error **errp) 2498 { 2499 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2500 pc_memory_plug(hotplug_dev, dev, errp); 2501 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2502 pc_cpu_plug(hotplug_dev, dev, errp); 2503 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2504 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 2505 } 2506 } 2507 2508 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2509 DeviceState *dev, Error **errp) 2510 { 2511 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2512 pc_memory_unplug_request(hotplug_dev, dev, errp); 2513 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2514 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2515 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2516 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 2517 } else { 2518 error_setg(errp, "acpi: device unplug request for not supported device" 2519 " type: %s", object_get_typename(OBJECT(dev))); 2520 } 2521 } 2522 2523 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2524 DeviceState *dev, Error **errp) 2525 { 2526 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2527 pc_memory_unplug(hotplug_dev, dev, errp); 2528 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2529 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2530 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2531 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 2532 } else { 2533 error_setg(errp, "acpi: device unplug for not supported device" 2534 " type: %s", object_get_typename(OBJECT(dev))); 2535 } 2536 } 2537 2538 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2539 DeviceState *dev) 2540 { 2541 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2542 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 2543 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2544 return HOTPLUG_HANDLER(machine); 2545 } 2546 2547 return NULL; 2548 } 2549 2550 static void 2551 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2552 const char *name, void *opaque, 2553 Error **errp) 2554 { 2555 MachineState *ms = MACHINE(obj); 2556 int64_t value = 0; 2557 2558 if (ms->device_memory) { 2559 value = memory_region_size(&ms->device_memory->mr); 2560 } 2561 2562 visit_type_int(v, name, &value, errp); 2563 } 2564 2565 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2566 const char *name, void *opaque, 2567 Error **errp) 2568 { 2569 PCMachineState *pcms = PC_MACHINE(obj); 2570 uint64_t value = pcms->max_ram_below_4g; 2571 2572 visit_type_size(v, name, &value, errp); 2573 } 2574 2575 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2576 const char *name, void *opaque, 2577 Error **errp) 2578 { 2579 PCMachineState *pcms = PC_MACHINE(obj); 2580 Error *error = NULL; 2581 uint64_t value; 2582 2583 visit_type_size(v, name, &value, &error); 2584 if (error) { 2585 error_propagate(errp, error); 2586 return; 2587 } 2588 if (value > 4 * GiB) { 2589 error_setg(&error, 2590 "Machine option 'max-ram-below-4g=%"PRIu64 2591 "' expects size less than or equal to 4G", value); 2592 error_propagate(errp, error); 2593 return; 2594 } 2595 2596 if (value < 1 * MiB) { 2597 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2598 "BIOS may not work with less than 1MiB", value); 2599 } 2600 2601 pcms->max_ram_below_4g = value; 2602 } 2603 2604 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2605 void *opaque, Error **errp) 2606 { 2607 PCMachineState *pcms = PC_MACHINE(obj); 2608 OnOffAuto vmport = pcms->vmport; 2609 2610 visit_type_OnOffAuto(v, name, &vmport, errp); 2611 } 2612 2613 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2614 void *opaque, Error **errp) 2615 { 2616 PCMachineState *pcms = PC_MACHINE(obj); 2617 2618 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2619 } 2620 2621 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2622 { 2623 bool smm_available = false; 2624 2625 if (pcms->smm == ON_OFF_AUTO_OFF) { 2626 return false; 2627 } 2628 2629 if (tcg_enabled() || qtest_enabled()) { 2630 smm_available = true; 2631 } else if (kvm_enabled()) { 2632 smm_available = kvm_has_smm(); 2633 } 2634 2635 if (smm_available) { 2636 return true; 2637 } 2638 2639 if (pcms->smm == ON_OFF_AUTO_ON) { 2640 error_report("System Management Mode not supported by this hypervisor."); 2641 exit(1); 2642 } 2643 return false; 2644 } 2645 2646 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2647 void *opaque, Error **errp) 2648 { 2649 PCMachineState *pcms = PC_MACHINE(obj); 2650 OnOffAuto smm = pcms->smm; 2651 2652 visit_type_OnOffAuto(v, name, &smm, errp); 2653 } 2654 2655 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2656 void *opaque, Error **errp) 2657 { 2658 PCMachineState *pcms = PC_MACHINE(obj); 2659 2660 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2661 } 2662 2663 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2664 { 2665 PCMachineState *pcms = PC_MACHINE(obj); 2666 2667 return pcms->smbus_enabled; 2668 } 2669 2670 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2671 { 2672 PCMachineState *pcms = PC_MACHINE(obj); 2673 2674 pcms->smbus_enabled = value; 2675 } 2676 2677 static bool pc_machine_get_sata(Object *obj, Error **errp) 2678 { 2679 PCMachineState *pcms = PC_MACHINE(obj); 2680 2681 return pcms->sata_enabled; 2682 } 2683 2684 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2685 { 2686 PCMachineState *pcms = PC_MACHINE(obj); 2687 2688 pcms->sata_enabled = value; 2689 } 2690 2691 static bool pc_machine_get_pit(Object *obj, Error **errp) 2692 { 2693 PCMachineState *pcms = PC_MACHINE(obj); 2694 2695 return pcms->pit_enabled; 2696 } 2697 2698 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2699 { 2700 PCMachineState *pcms = PC_MACHINE(obj); 2701 2702 pcms->pit_enabled = value; 2703 } 2704 2705 static void pc_machine_initfn(Object *obj) 2706 { 2707 PCMachineState *pcms = PC_MACHINE(obj); 2708 2709 pcms->max_ram_below_4g = 0; /* use default */ 2710 pcms->smm = ON_OFF_AUTO_AUTO; 2711 pcms->vmport = ON_OFF_AUTO_AUTO; 2712 /* acpi build is enabled by default if machine supports it */ 2713 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2714 pcms->smbus_enabled = true; 2715 pcms->sata_enabled = true; 2716 pcms->pit_enabled = true; 2717 pcms->smp_dies = 1; 2718 2719 pc_system_flash_create(pcms); 2720 } 2721 2722 static void pc_machine_reset(MachineState *machine) 2723 { 2724 CPUState *cs; 2725 X86CPU *cpu; 2726 2727 qemu_devices_reset(); 2728 2729 /* Reset APIC after devices have been reset to cancel 2730 * any changes that qemu_devices_reset() might have done. 2731 */ 2732 CPU_FOREACH(cs) { 2733 cpu = X86_CPU(cs); 2734 2735 if (cpu->apic_state) { 2736 device_reset(cpu->apic_state); 2737 } 2738 } 2739 } 2740 2741 static CpuInstanceProperties 2742 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2743 { 2744 MachineClass *mc = MACHINE_GET_CLASS(ms); 2745 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2746 2747 assert(cpu_index < possible_cpus->len); 2748 return possible_cpus->cpus[cpu_index].props; 2749 } 2750 2751 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2752 { 2753 X86CPUTopoInfo topo; 2754 PCMachineState *pcms = PC_MACHINE(ms); 2755 2756 assert(idx < ms->possible_cpus->len); 2757 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2758 pcms->smp_dies, ms->smp.cores, 2759 ms->smp.threads, &topo); 2760 return topo.pkg_id % nb_numa_nodes; 2761 } 2762 2763 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2764 { 2765 PCMachineState *pcms = PC_MACHINE(ms); 2766 int i; 2767 unsigned int max_cpus = ms->smp.max_cpus; 2768 2769 if (ms->possible_cpus) { 2770 /* 2771 * make sure that max_cpus hasn't changed since the first use, i.e. 2772 * -smp hasn't been parsed after it 2773 */ 2774 assert(ms->possible_cpus->len == max_cpus); 2775 return ms->possible_cpus; 2776 } 2777 2778 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2779 sizeof(CPUArchId) * max_cpus); 2780 ms->possible_cpus->len = max_cpus; 2781 for (i = 0; i < ms->possible_cpus->len; i++) { 2782 X86CPUTopoInfo topo; 2783 2784 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2785 ms->possible_cpus->cpus[i].vcpus_count = 1; 2786 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); 2787 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2788 pcms->smp_dies, ms->smp.cores, 2789 ms->smp.threads, &topo); 2790 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2791 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2792 ms->possible_cpus->cpus[i].props.has_die_id = true; 2793 ms->possible_cpus->cpus[i].props.die_id = topo.die_id; 2794 ms->possible_cpus->cpus[i].props.has_core_id = true; 2795 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2796 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2797 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2798 } 2799 return ms->possible_cpus; 2800 } 2801 2802 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2803 { 2804 /* cpu index isn't used */ 2805 CPUState *cs; 2806 2807 CPU_FOREACH(cs) { 2808 X86CPU *cpu = X86_CPU(cs); 2809 2810 if (!cpu->apic_state) { 2811 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2812 } else { 2813 apic_deliver_nmi(cpu->apic_state); 2814 } 2815 } 2816 } 2817 2818 static void pc_machine_class_init(ObjectClass *oc, void *data) 2819 { 2820 MachineClass *mc = MACHINE_CLASS(oc); 2821 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2822 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2823 NMIClass *nc = NMI_CLASS(oc); 2824 2825 pcmc->pci_enabled = true; 2826 pcmc->has_acpi_build = true; 2827 pcmc->rsdp_in_ram = true; 2828 pcmc->smbios_defaults = true; 2829 pcmc->smbios_uuid_encoded = true; 2830 pcmc->gigabyte_align = true; 2831 pcmc->has_reserved_memory = true; 2832 pcmc->kvmclock_enabled = true; 2833 pcmc->enforce_aligned_dimm = true; 2834 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2835 * to be used at the moment, 32K should be enough for a while. */ 2836 pcmc->acpi_data_size = 0x20000 + 0x8000; 2837 pcmc->save_tsc_khz = true; 2838 pcmc->linuxboot_dma_enabled = true; 2839 pcmc->pvh_enabled = true; 2840 assert(!mc->get_hotplug_handler); 2841 mc->get_hotplug_handler = pc_get_hotplug_handler; 2842 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2843 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2844 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2845 mc->auto_enable_numa_with_memhp = true; 2846 mc->has_hotpluggable_cpus = true; 2847 mc->default_boot_order = "cad"; 2848 mc->hot_add_cpu = pc_hot_add_cpu; 2849 mc->block_default_type = IF_IDE; 2850 mc->max_cpus = 255; 2851 mc->reset = pc_machine_reset; 2852 hc->pre_plug = pc_machine_device_pre_plug_cb; 2853 hc->plug = pc_machine_device_plug_cb; 2854 hc->unplug_request = pc_machine_device_unplug_request_cb; 2855 hc->unplug = pc_machine_device_unplug_cb; 2856 nc->nmi_monitor_handler = x86_nmi; 2857 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2858 mc->nvdimm_supported = true; 2859 mc->numa_mem_supported = true; 2860 2861 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2862 pc_machine_get_device_memory_region_size, NULL, 2863 NULL, NULL, &error_abort); 2864 2865 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2866 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2867 NULL, NULL, &error_abort); 2868 2869 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2870 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2871 2872 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2873 pc_machine_get_smm, pc_machine_set_smm, 2874 NULL, NULL, &error_abort); 2875 object_class_property_set_description(oc, PC_MACHINE_SMM, 2876 "Enable SMM (pc & q35)", &error_abort); 2877 2878 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2879 pc_machine_get_vmport, pc_machine_set_vmport, 2880 NULL, NULL, &error_abort); 2881 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2882 "Enable vmport (pc & q35)", &error_abort); 2883 2884 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2885 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2886 2887 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2888 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2889 2890 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2891 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2892 } 2893 2894 static const TypeInfo pc_machine_info = { 2895 .name = TYPE_PC_MACHINE, 2896 .parent = TYPE_MACHINE, 2897 .abstract = true, 2898 .instance_size = sizeof(PCMachineState), 2899 .instance_init = pc_machine_initfn, 2900 .class_size = sizeof(PCMachineClass), 2901 .class_init = pc_machine_class_init, 2902 .interfaces = (InterfaceInfo[]) { 2903 { TYPE_HOTPLUG_HANDLER }, 2904 { TYPE_NMI }, 2905 { } 2906 }, 2907 }; 2908 2909 static void pc_machine_register_types(void) 2910 { 2911 type_register_static(&pc_machine_info); 2912 } 2913 2914 type_init(pc_machine_register_types) 2915