1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_9_0[] = { 82 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 83 { "sev-guest", "legacy-vm-type", "true" }, 84 }; 85 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 86 87 GlobalProperty pc_compat_8_2[] = {}; 88 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 89 90 GlobalProperty pc_compat_8_1[] = {}; 91 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 92 93 GlobalProperty pc_compat_8_0[] = { 94 { "virtio-mem", "unplugged-inaccessible", "auto" }, 95 }; 96 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 97 98 GlobalProperty pc_compat_7_2[] = { 99 { "ICH9-LPC", "noreboot", "true" }, 100 }; 101 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 102 103 GlobalProperty pc_compat_7_1[] = {}; 104 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 105 106 GlobalProperty pc_compat_7_0[] = {}; 107 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 108 109 GlobalProperty pc_compat_6_2[] = { 110 { "virtio-mem", "unplugged-inaccessible", "off" }, 111 }; 112 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 113 114 GlobalProperty pc_compat_6_1[] = { 115 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 116 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 117 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 118 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 119 }; 120 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 121 122 GlobalProperty pc_compat_6_0[] = { 123 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 124 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 125 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 126 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 127 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 128 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 129 }; 130 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 131 132 GlobalProperty pc_compat_5_2[] = { 133 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 134 }; 135 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 136 137 GlobalProperty pc_compat_5_1[] = { 138 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 139 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 140 }; 141 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 142 143 GlobalProperty pc_compat_5_0[] = { 144 }; 145 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 146 147 GlobalProperty pc_compat_4_2[] = { 148 { "mch", "smbase-smram", "off" }, 149 }; 150 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 151 152 GlobalProperty pc_compat_4_1[] = {}; 153 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 154 155 GlobalProperty pc_compat_4_0[] = {}; 156 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 157 158 GlobalProperty pc_compat_3_1[] = { 159 { "intel-iommu", "dma-drain", "off" }, 160 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 161 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 162 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 163 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 164 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 165 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 166 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 167 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 168 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 169 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 170 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 171 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 173 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 174 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 175 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 176 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 177 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 178 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 179 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 180 }; 181 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 182 183 GlobalProperty pc_compat_3_0[] = { 184 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 185 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 186 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 187 }; 188 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 189 190 GlobalProperty pc_compat_2_12[] = { 191 { TYPE_X86_CPU, "legacy-cache", "on" }, 192 { TYPE_X86_CPU, "topoext", "off" }, 193 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 194 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 195 }; 196 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 197 198 GlobalProperty pc_compat_2_11[] = { 199 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 200 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 201 }; 202 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 203 204 GlobalProperty pc_compat_2_10[] = { 205 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 206 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 207 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 208 }; 209 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 210 211 GlobalProperty pc_compat_2_9[] = { 212 { "mch", "extended-tseg-mbytes", "0" }, 213 }; 214 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 215 216 GlobalProperty pc_compat_2_8[] = { 217 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 218 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 219 { "ICH9-LPC", "x-smi-broadcast", "off" }, 220 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 221 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 222 }; 223 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 224 225 GlobalProperty pc_compat_2_7[] = { 226 { TYPE_X86_CPU, "l3-cache", "off" }, 227 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 228 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 229 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 230 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 231 { "isa-pcspk", "migrate", "off" }, 232 }; 233 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 234 235 GlobalProperty pc_compat_2_6[] = { 236 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 237 { "vmxnet3", "romfile", "" }, 238 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 239 { "apic-common", "legacy-instance-id", "on", } 240 }; 241 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 242 243 GlobalProperty pc_compat_2_5[] = {}; 244 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 245 246 GlobalProperty pc_compat_2_4[] = { 247 PC_CPU_MODEL_IDS("2.4.0") 248 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 249 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 250 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 251 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 252 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 253 { TYPE_X86_CPU, "check", "off" }, 254 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 255 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 256 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 257 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 258 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 259 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 260 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 261 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 262 }; 263 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 264 265 GlobalProperty pc_compat_2_3[] = { 266 PC_CPU_MODEL_IDS("2.3.0") 267 { TYPE_X86_CPU, "arat", "off" }, 268 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 270 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 271 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 272 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 273 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 274 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 275 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 281 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 282 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 283 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 284 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 285 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 286 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 287 }; 288 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 289 290 GlobalProperty pc_compat_2_2[] = { 291 PC_CPU_MODEL_IDS("2.2.0") 292 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 301 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 302 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 303 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 304 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 305 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 306 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 307 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 308 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 309 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 310 }; 311 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 312 313 GlobalProperty pc_compat_2_1[] = { 314 PC_CPU_MODEL_IDS("2.1.0") 315 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 316 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 317 }; 318 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 319 320 GlobalProperty pc_compat_2_0[] = { 321 PC_CPU_MODEL_IDS("2.0.0") 322 { "virtio-scsi-pci", "any_layout", "off" }, 323 { "PIIX4_PM", "memory-hotplug-support", "off" }, 324 { "apic", "version", "0x11" }, 325 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 326 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 327 { "pci-serial", "prog_if", "0" }, 328 { "pci-serial-2x", "prog_if", "0" }, 329 { "pci-serial-4x", "prog_if", "0" }, 330 { "virtio-net-pci", "guest_announce", "off" }, 331 { "ICH9-LPC", "memory-hotplug-support", "off" }, 332 }; 333 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 334 335 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 336 { 337 GSIState *s; 338 339 s = g_new0(GSIState, 1); 340 if (kvm_ioapic_in_kernel()) { 341 kvm_pc_setup_irq_routing(pci_enabled); 342 } 343 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 344 345 return s; 346 } 347 348 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 349 unsigned size) 350 { 351 } 352 353 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 354 { 355 return 0xffffffffffffffffULL; 356 } 357 358 /* MS-DOS compatibility mode FPU exception support */ 359 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 360 unsigned size) 361 { 362 if (tcg_enabled()) { 363 cpu_set_ignne(); 364 } 365 } 366 367 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 368 { 369 return 0xffffffffffffffffULL; 370 } 371 372 /* PC cmos mappings */ 373 374 #define REG_EQUIPMENT_BYTE 0x14 375 376 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 377 int16_t cylinders, int8_t heads, int8_t sectors) 378 { 379 mc146818rtc_set_cmos_data(s, type_ofs, 47); 380 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 381 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 382 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 383 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 384 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 385 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 386 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 387 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 388 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 389 } 390 391 /* convert boot_device letter to something recognizable by the bios */ 392 static int boot_device2nibble(char boot_device) 393 { 394 switch(boot_device) { 395 case 'a': 396 case 'b': 397 return 0x01; /* floppy boot */ 398 case 'c': 399 return 0x02; /* hard drive boot */ 400 case 'd': 401 return 0x03; /* CD-ROM boot */ 402 case 'n': 403 return 0x04; /* Network boot */ 404 } 405 return 0; 406 } 407 408 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 409 const char *boot_device, Error **errp) 410 { 411 #define PC_MAX_BOOT_DEVICES 3 412 int nbds, bds[3] = { 0, }; 413 int i; 414 415 nbds = strlen(boot_device); 416 if (nbds > PC_MAX_BOOT_DEVICES) { 417 error_setg(errp, "Too many boot devices for PC"); 418 return; 419 } 420 for (i = 0; i < nbds; i++) { 421 bds[i] = boot_device2nibble(boot_device[i]); 422 if (bds[i] == 0) { 423 error_setg(errp, "Invalid boot device for PC: '%c'", 424 boot_device[i]); 425 return; 426 } 427 } 428 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 429 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 430 } 431 432 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 433 { 434 PCMachineState *pcms = opaque; 435 X86MachineState *x86ms = X86_MACHINE(pcms); 436 437 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 438 } 439 440 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 441 { 442 int val, nb, i; 443 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 444 FLOPPY_DRIVE_TYPE_NONE }; 445 446 /* floppy type */ 447 if (floppy) { 448 for (i = 0; i < 2; i++) { 449 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 450 } 451 } 452 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 453 cmos_get_fd_drive_type(fd_type[1]); 454 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 455 456 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 457 nb = 0; 458 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 459 nb++; 460 } 461 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 462 nb++; 463 } 464 switch (nb) { 465 case 0: 466 break; 467 case 1: 468 val |= 0x01; /* 1 drive, ready for boot */ 469 break; 470 case 2: 471 val |= 0x41; /* 2 drives, ready for boot */ 472 break; 473 } 474 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 475 } 476 477 typedef struct check_fdc_state { 478 ISADevice *floppy; 479 bool multiple; 480 } CheckFdcState; 481 482 static int check_fdc(Object *obj, void *opaque) 483 { 484 CheckFdcState *state = opaque; 485 Object *fdc; 486 uint32_t iobase; 487 Error *local_err = NULL; 488 489 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 490 if (!fdc) { 491 return 0; 492 } 493 494 iobase = object_property_get_uint(obj, "iobase", &local_err); 495 if (local_err || iobase != 0x3f0) { 496 error_free(local_err); 497 return 0; 498 } 499 500 if (state->floppy) { 501 state->multiple = true; 502 } else { 503 state->floppy = ISA_DEVICE(obj); 504 } 505 return 0; 506 } 507 508 static const char * const fdc_container_path[] = { 509 "/unattached", "/peripheral", "/peripheral-anon" 510 }; 511 512 /* 513 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 514 * and ACPI objects. 515 */ 516 static ISADevice *pc_find_fdc0(void) 517 { 518 int i; 519 Object *container; 520 CheckFdcState state = { 0 }; 521 522 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 523 container = container_get(qdev_get_machine(), fdc_container_path[i]); 524 object_child_foreach(container, check_fdc, &state); 525 } 526 527 if (state.multiple) { 528 warn_report("multiple floppy disk controllers with " 529 "iobase=0x3f0 have been found"); 530 error_printf("the one being picked for CMOS setup might not reflect " 531 "your intent"); 532 } 533 534 return state.floppy; 535 } 536 537 static void pc_cmos_init_late(PCMachineState *pcms) 538 { 539 X86MachineState *x86ms = X86_MACHINE(pcms); 540 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 541 int16_t cylinders; 542 int8_t heads, sectors; 543 int val; 544 int i, trans; 545 546 val = 0; 547 if (pcms->idebus[0] && 548 ide_get_geometry(pcms->idebus[0], 0, 549 &cylinders, &heads, §ors) >= 0) { 550 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 551 val |= 0xf0; 552 } 553 if (pcms->idebus[0] && 554 ide_get_geometry(pcms->idebus[0], 1, 555 &cylinders, &heads, §ors) >= 0) { 556 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 557 val |= 0x0f; 558 } 559 mc146818rtc_set_cmos_data(s, 0x12, val); 560 561 val = 0; 562 for (i = 0; i < 4; i++) { 563 /* NOTE: ide_get_geometry() returns the physical 564 geometry. It is always such that: 1 <= sects <= 63, 1 565 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 566 geometry can be different if a translation is done. */ 567 BusState *idebus = pcms->idebus[i / 2]; 568 if (idebus && 569 ide_get_geometry(idebus, i % 2, 570 &cylinders, &heads, §ors) >= 0) { 571 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 572 assert((trans & ~3) == 0); 573 val |= trans << (i * 2); 574 } 575 } 576 mc146818rtc_set_cmos_data(s, 0x39, val); 577 578 pc_cmos_init_floppy(s, pc_find_fdc0()); 579 580 /* various important CMOS locations needed by PC/Bochs bios */ 581 582 /* memory size */ 583 /* base memory (first MiB) */ 584 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 585 mc146818rtc_set_cmos_data(s, 0x15, val); 586 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 587 /* extended memory (next 64MiB) */ 588 if (x86ms->below_4g_mem_size > 1 * MiB) { 589 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 590 } else { 591 val = 0; 592 } 593 if (val > 65535) 594 val = 65535; 595 mc146818rtc_set_cmos_data(s, 0x17, val); 596 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 597 mc146818rtc_set_cmos_data(s, 0x30, val); 598 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 599 /* memory between 16MiB and 4GiB */ 600 if (x86ms->below_4g_mem_size > 16 * MiB) { 601 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 602 } else { 603 val = 0; 604 } 605 if (val > 65535) 606 val = 65535; 607 mc146818rtc_set_cmos_data(s, 0x34, val); 608 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 609 /* memory above 4GiB */ 610 val = x86ms->above_4g_mem_size / 65536; 611 mc146818rtc_set_cmos_data(s, 0x5b, val); 612 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 613 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 614 615 val = 0; 616 val |= 0x02; /* FPU is there */ 617 val |= 0x04; /* PS/2 mouse installed */ 618 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 619 } 620 621 static void handle_a20_line_change(void *opaque, int irq, int level) 622 { 623 X86CPU *cpu = opaque; 624 625 /* XXX: send to all CPUs ? */ 626 /* XXX: add logic to handle multiple A20 line sources */ 627 x86_cpu_set_a20(cpu, level); 628 } 629 630 #define NE2000_NB_MAX 6 631 632 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 633 0x280, 0x380 }; 634 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 635 636 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 637 { 638 static int nb_ne2k = 0; 639 640 if (nb_ne2k == NE2000_NB_MAX) { 641 error_setg(errp, 642 "maximum number of ISA NE2000 devices exceeded"); 643 return false; 644 } 645 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 646 ne2000_irq[nb_ne2k], nd); 647 nb_ne2k++; 648 return true; 649 } 650 651 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 652 { 653 X86CPU *cpu = opaque; 654 655 if (level) { 656 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 657 } 658 } 659 660 static 661 void pc_machine_done(Notifier *notifier, void *data) 662 { 663 PCMachineState *pcms = container_of(notifier, 664 PCMachineState, machine_done); 665 X86MachineState *x86ms = X86_MACHINE(pcms); 666 667 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 668 &error_fatal); 669 670 if (pcms->cxl_devices_state.is_enabled) { 671 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 672 } 673 674 /* set the number of CPUs */ 675 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 676 677 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 678 679 acpi_setup(); 680 if (x86ms->fw_cfg) { 681 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 682 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 683 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 684 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 685 } 686 687 pc_cmos_init_late(pcms); 688 } 689 690 /* setup pci memory address space mapping into system address space */ 691 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 692 MemoryRegion *pci_address_space) 693 { 694 /* Set to lower priority than RAM */ 695 memory_region_add_subregion_overlap(system_memory, 0x0, 696 pci_address_space, -1); 697 } 698 699 void xen_load_linux(PCMachineState *pcms) 700 { 701 int i; 702 FWCfgState *fw_cfg; 703 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 704 X86MachineState *x86ms = X86_MACHINE(pcms); 705 706 assert(MACHINE(pcms)->kernel_filename != NULL); 707 708 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 709 &address_space_memory); 710 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 711 rom_set_fw(fw_cfg); 712 713 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 714 pcmc->pvh_enabled); 715 for (i = 0; i < nb_option_roms; i++) { 716 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 717 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 718 !strcmp(option_rom[i].name, "pvh.bin") || 719 !strcmp(option_rom[i].name, "multiboot.bin") || 720 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 721 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 722 } 723 x86ms->fw_cfg = fw_cfg; 724 } 725 726 #define PC_ROM_MIN_VGA 0xc0000 727 #define PC_ROM_MIN_OPTION 0xc8000 728 #define PC_ROM_MAX 0xe0000 729 #define PC_ROM_ALIGN 0x800 730 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 731 732 static hwaddr pc_above_4g_end(PCMachineState *pcms) 733 { 734 X86MachineState *x86ms = X86_MACHINE(pcms); 735 736 if (pcms->sgx_epc.size != 0) { 737 return sgx_epc_above_4g_end(&pcms->sgx_epc); 738 } 739 740 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 741 } 742 743 static void pc_get_device_memory_range(PCMachineState *pcms, 744 hwaddr *base, 745 ram_addr_t *device_mem_size) 746 { 747 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 748 MachineState *machine = MACHINE(pcms); 749 ram_addr_t size; 750 hwaddr addr; 751 752 size = machine->maxram_size - machine->ram_size; 753 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 754 755 if (pcmc->enforce_aligned_dimm) { 756 /* size device region assuming 1G page max alignment per slot */ 757 size += (1 * GiB) * machine->ram_slots; 758 } 759 760 *base = addr; 761 *device_mem_size = size; 762 } 763 764 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 765 { 766 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 767 MachineState *ms = MACHINE(pcms); 768 hwaddr cxl_base; 769 ram_addr_t size; 770 771 if (pcmc->has_reserved_memory && 772 (ms->ram_size < ms->maxram_size)) { 773 pc_get_device_memory_range(pcms, &cxl_base, &size); 774 cxl_base += size; 775 } else { 776 cxl_base = pc_above_4g_end(pcms); 777 } 778 779 return cxl_base; 780 } 781 782 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 783 { 784 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 785 786 if (pcms->cxl_devices_state.fixed_windows) { 787 GList *it; 788 789 start = ROUND_UP(start, 256 * MiB); 790 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 791 CXLFixedWindow *fw = it->data; 792 start += fw->size; 793 } 794 } 795 796 return start; 797 } 798 799 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 800 { 801 X86CPU *cpu = X86_CPU(first_cpu); 802 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 803 MachineState *ms = MACHINE(pcms); 804 805 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 806 /* 64-bit systems */ 807 return pc_pci_hole64_start() + pci_hole64_size - 1; 808 } 809 810 /* 32-bit systems */ 811 if (pcmc->broken_32bit_mem_addr_check) { 812 /* old value for compatibility reasons */ 813 return ((hwaddr)1 << cpu->phys_bits) - 1; 814 } 815 816 /* 817 * 32-bit systems don't have hole64 but they might have a region for 818 * memory devices. Even if additional hotplugged memory devices might 819 * not be usable by most guest OSes, we need to still consider them for 820 * calculating the highest possible GPA so that we can properly report 821 * if someone configures them on a CPU that cannot possibly address them. 822 */ 823 if (pcmc->has_reserved_memory && 824 (ms->ram_size < ms->maxram_size)) { 825 hwaddr devmem_start; 826 ram_addr_t devmem_size; 827 828 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 829 devmem_start += devmem_size; 830 return devmem_start - 1; 831 } 832 833 /* configuration without any memory hotplug */ 834 return pc_above_4g_end(pcms) - 1; 835 } 836 837 /* 838 * AMD systems with an IOMMU have an additional hole close to the 839 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 840 * on kernel version, VFIO may or may not let you DMA map those ranges. 841 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 842 * with certain memory sizes. It's also wrong to use those IOVA ranges 843 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 844 * The ranges reserved for Hyper-Transport are: 845 * 846 * FD_0000_0000h - FF_FFFF_FFFFh 847 * 848 * The ranges represent the following: 849 * 850 * Base Address Top Address Use 851 * 852 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 853 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 854 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 855 * FD_F910_0000h FD_F91F_FFFFh System Management 856 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 857 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 858 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 859 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 860 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 861 * FE_2000_0000h FF_FFFF_FFFFh Reserved 862 * 863 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 864 * Table 3: Special Address Controls (GPA) for more information. 865 */ 866 #define AMD_HT_START 0xfd00000000UL 867 #define AMD_HT_END 0xffffffffffUL 868 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 869 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 870 871 void pc_memory_init(PCMachineState *pcms, 872 MemoryRegion *system_memory, 873 MemoryRegion *rom_memory, 874 uint64_t pci_hole64_size) 875 { 876 int linux_boot, i; 877 MemoryRegion *option_rom_mr; 878 MemoryRegion *ram_below_4g, *ram_above_4g; 879 FWCfgState *fw_cfg; 880 MachineState *machine = MACHINE(pcms); 881 MachineClass *mc = MACHINE_GET_CLASS(machine); 882 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 883 X86MachineState *x86ms = X86_MACHINE(pcms); 884 hwaddr maxphysaddr, maxusedaddr; 885 hwaddr cxl_base, cxl_resv_end = 0; 886 X86CPU *cpu = X86_CPU(first_cpu); 887 888 assert(machine->ram_size == x86ms->below_4g_mem_size + 889 x86ms->above_4g_mem_size); 890 891 linux_boot = (machine->kernel_filename != NULL); 892 893 /* 894 * The HyperTransport range close to the 1T boundary is unique to AMD 895 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 896 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 897 * older machine types (<= 7.0) for compatibility purposes. 898 */ 899 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 900 /* Bail out if max possible address does not cross HT range */ 901 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 902 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 903 } 904 905 /* 906 * Advertise the HT region if address space covers the reserved 907 * region or if we relocate. 908 */ 909 if (cpu->phys_bits >= 40) { 910 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 911 } 912 } 913 914 /* 915 * phys-bits is required to be appropriately configured 916 * to make sure max used GPA is reachable. 917 */ 918 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 919 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 920 if (maxphysaddr < maxusedaddr) { 921 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 922 " phys-bits too low (%u)", 923 maxphysaddr, maxusedaddr, cpu->phys_bits); 924 exit(EXIT_FAILURE); 925 } 926 927 /* 928 * Split single memory region and use aliases to address portions of it, 929 * done for backwards compatibility with older qemus. 930 */ 931 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 932 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 933 0, x86ms->below_4g_mem_size); 934 memory_region_add_subregion(system_memory, 0, ram_below_4g); 935 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 936 if (x86ms->above_4g_mem_size > 0) { 937 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 938 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 939 machine->ram, 940 x86ms->below_4g_mem_size, 941 x86ms->above_4g_mem_size); 942 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 943 ram_above_4g); 944 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 945 E820_RAM); 946 } 947 948 if (pcms->sgx_epc.size != 0) { 949 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 950 } 951 952 if (!pcmc->has_reserved_memory && 953 (machine->ram_slots || 954 (machine->maxram_size > machine->ram_size))) { 955 956 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 957 mc->name); 958 exit(EXIT_FAILURE); 959 } 960 961 /* initialize device memory address space */ 962 if (pcmc->has_reserved_memory && 963 (machine->ram_size < machine->maxram_size)) { 964 ram_addr_t device_mem_size; 965 hwaddr device_mem_base; 966 967 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 968 error_report("unsupported amount of memory slots: %"PRIu64, 969 machine->ram_slots); 970 exit(EXIT_FAILURE); 971 } 972 973 if (QEMU_ALIGN_UP(machine->maxram_size, 974 TARGET_PAGE_SIZE) != machine->maxram_size) { 975 error_report("maximum memory size must by aligned to multiple of " 976 "%d bytes", TARGET_PAGE_SIZE); 977 exit(EXIT_FAILURE); 978 } 979 980 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 981 982 if (device_mem_base + device_mem_size < device_mem_size) { 983 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 984 machine->maxram_size); 985 exit(EXIT_FAILURE); 986 } 987 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 988 } 989 990 if (pcms->cxl_devices_state.is_enabled) { 991 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 992 hwaddr cxl_size = MiB; 993 994 cxl_base = pc_get_cxl_range_start(pcms); 995 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 996 memory_region_add_subregion(system_memory, cxl_base, mr); 997 cxl_resv_end = cxl_base + cxl_size; 998 if (pcms->cxl_devices_state.fixed_windows) { 999 hwaddr cxl_fmw_base; 1000 GList *it; 1001 1002 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1003 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1004 CXLFixedWindow *fw = it->data; 1005 1006 fw->base = cxl_fmw_base; 1007 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1008 "cxl-fixed-memory-region", fw->size); 1009 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1010 cxl_fmw_base += fw->size; 1011 cxl_resv_end = cxl_fmw_base; 1012 } 1013 } 1014 } 1015 1016 /* Initialize PC system firmware */ 1017 pc_system_firmware_init(pcms, rom_memory); 1018 1019 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1020 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1021 &error_fatal); 1022 if (pcmc->pci_enabled) { 1023 memory_region_set_readonly(option_rom_mr, true); 1024 } 1025 memory_region_add_subregion_overlap(rom_memory, 1026 PC_ROM_MIN_VGA, 1027 option_rom_mr, 1028 1); 1029 1030 fw_cfg = fw_cfg_arch_create(machine, 1031 x86ms->boot_cpus, x86ms->apic_id_limit); 1032 1033 rom_set_fw(fw_cfg); 1034 1035 if (machine->device_memory) { 1036 uint64_t *val = g_malloc(sizeof(*val)); 1037 uint64_t res_mem_end = machine->device_memory->base; 1038 1039 if (!pcmc->broken_reserved_end) { 1040 res_mem_end += memory_region_size(&machine->device_memory->mr); 1041 } 1042 1043 if (pcms->cxl_devices_state.is_enabled) { 1044 res_mem_end = cxl_resv_end; 1045 } 1046 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1047 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1048 } 1049 1050 if (linux_boot) { 1051 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1052 pcmc->pvh_enabled); 1053 } 1054 1055 for (i = 0; i < nb_option_roms; i++) { 1056 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1057 } 1058 x86ms->fw_cfg = fw_cfg; 1059 1060 /* Init default IOAPIC address space */ 1061 x86ms->ioapic_as = &address_space_memory; 1062 1063 /* Init ACPI memory hotplug IO base address */ 1064 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1065 } 1066 1067 /* 1068 * The 64bit pci hole starts after "above 4G RAM" and 1069 * potentially the space reserved for memory hotplug. 1070 */ 1071 uint64_t pc_pci_hole64_start(void) 1072 { 1073 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1074 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1075 MachineState *ms = MACHINE(pcms); 1076 uint64_t hole64_start = 0; 1077 ram_addr_t size = 0; 1078 1079 if (pcms->cxl_devices_state.is_enabled) { 1080 hole64_start = pc_get_cxl_range_end(pcms); 1081 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1082 pc_get_device_memory_range(pcms, &hole64_start, &size); 1083 if (!pcmc->broken_reserved_end) { 1084 hole64_start += size; 1085 } 1086 } else { 1087 hole64_start = pc_above_4g_end(pcms); 1088 } 1089 1090 return ROUND_UP(hole64_start, 1 * GiB); 1091 } 1092 1093 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1094 { 1095 DeviceState *dev = NULL; 1096 1097 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1098 if (pci_bus) { 1099 PCIDevice *pcidev = pci_vga_init(pci_bus); 1100 dev = pcidev ? &pcidev->qdev : NULL; 1101 } else if (isa_bus) { 1102 ISADevice *isadev = isa_vga_init(isa_bus); 1103 dev = isadev ? DEVICE(isadev) : NULL; 1104 } 1105 rom_reset_order_override(); 1106 return dev; 1107 } 1108 1109 static const MemoryRegionOps ioport80_io_ops = { 1110 .write = ioport80_write, 1111 .read = ioport80_read, 1112 .endianness = DEVICE_NATIVE_ENDIAN, 1113 .impl = { 1114 .min_access_size = 1, 1115 .max_access_size = 1, 1116 }, 1117 }; 1118 1119 static const MemoryRegionOps ioportF0_io_ops = { 1120 .write = ioportF0_write, 1121 .read = ioportF0_read, 1122 .endianness = DEVICE_NATIVE_ENDIAN, 1123 .impl = { 1124 .min_access_size = 1, 1125 .max_access_size = 1, 1126 }, 1127 }; 1128 1129 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1130 bool create_i8042, bool no_vmport) 1131 { 1132 int i; 1133 DriveInfo *fd[MAX_FD]; 1134 qemu_irq *a20_line; 1135 ISADevice *fdc, *i8042, *port92, *vmmouse; 1136 1137 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1138 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1139 1140 for (i = 0; i < MAX_FD; i++) { 1141 fd[i] = drive_get(IF_FLOPPY, 0, i); 1142 create_fdctrl |= !!fd[i]; 1143 } 1144 if (create_fdctrl) { 1145 fdc = isa_new(TYPE_ISA_FDC); 1146 if (fdc) { 1147 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1148 isa_fdc_init_drives(fdc, fd); 1149 } 1150 } 1151 1152 if (!create_i8042) { 1153 return; 1154 } 1155 1156 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1157 if (!no_vmport) { 1158 isa_create_simple(isa_bus, TYPE_VMPORT); 1159 vmmouse = isa_try_new("vmmouse"); 1160 } else { 1161 vmmouse = NULL; 1162 } 1163 if (vmmouse) { 1164 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1165 &error_abort); 1166 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1167 } 1168 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1169 1170 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1171 qdev_connect_gpio_out_named(DEVICE(i8042), 1172 I8042_A20_LINE, 0, a20_line[0]); 1173 qdev_connect_gpio_out_named(DEVICE(port92), 1174 PORT92_A20_LINE, 0, a20_line[1]); 1175 g_free(a20_line); 1176 } 1177 1178 void pc_basic_device_init(struct PCMachineState *pcms, 1179 ISABus *isa_bus, qemu_irq *gsi, 1180 ISADevice *rtc_state, 1181 bool create_fdctrl, 1182 uint32_t hpet_irqs) 1183 { 1184 int i; 1185 DeviceState *hpet = NULL; 1186 int pit_isa_irq = 0; 1187 qemu_irq pit_alt_irq = NULL; 1188 ISADevice *pit = NULL; 1189 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1190 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1191 X86MachineState *x86ms = X86_MACHINE(pcms); 1192 1193 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1194 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1195 1196 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1197 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1198 1199 /* 1200 * Check if an HPET shall be created. 1201 */ 1202 if (pcms->hpet_enabled) { 1203 qemu_irq rtc_irq; 1204 1205 hpet = qdev_try_new(TYPE_HPET); 1206 if (!hpet) { 1207 error_report("couldn't create HPET device"); 1208 exit(1); 1209 } 1210 /* 1211 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1212 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1213 * the property, use whatever mask they specified. 1214 */ 1215 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1216 HPET_INTCAP, NULL); 1217 if (!compat) { 1218 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1219 } 1220 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1221 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1222 1223 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1224 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1225 } 1226 pit_isa_irq = -1; 1227 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1228 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1229 1230 /* overwrite connection created by south bridge */ 1231 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1232 } 1233 1234 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1235 "date"); 1236 1237 #ifdef CONFIG_XEN_EMU 1238 if (xen_mode == XEN_EMULATE) { 1239 xen_overlay_create(); 1240 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1241 xen_gnttab_create(); 1242 xen_xenstore_create(); 1243 if (pcms->pcibus) { 1244 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1245 } 1246 xen_bus_init(); 1247 xen_be_init(); 1248 } 1249 #endif 1250 1251 qemu_register_boot_set(pc_boot_set, pcms); 1252 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1253 MACHINE(pcms)->boot_config.order, &error_fatal); 1254 1255 if (!xen_enabled() && 1256 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1257 if (kvm_pit_in_kernel()) { 1258 pit = kvm_pit_init(isa_bus, 0x40); 1259 } else { 1260 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1261 } 1262 if (hpet) { 1263 /* connect PIT to output control line of the HPET */ 1264 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1265 } 1266 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1267 OBJECT(pit), &error_fatal); 1268 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1269 } 1270 1271 /* Super I/O */ 1272 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1273 pcms->vmport != ON_OFF_AUTO_ON); 1274 } 1275 1276 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1277 { 1278 MachineClass *mc = MACHINE_CLASS(pcmc); 1279 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1280 NICInfo *nd; 1281 1282 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1283 1284 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1285 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1286 } 1287 1288 /* Anything remaining should be a PCI NIC */ 1289 pci_init_nic_devices(pci_bus, mc->default_nic); 1290 1291 rom_reset_order_override(); 1292 } 1293 1294 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1295 { 1296 qemu_irq *i8259; 1297 1298 if (kvm_pic_in_kernel()) { 1299 i8259 = kvm_i8259_init(isa_bus); 1300 } else if (xen_enabled()) { 1301 i8259 = xen_interrupt_controller_init(); 1302 } else { 1303 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1304 } 1305 1306 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1307 i8259_irqs[i] = i8259[i]; 1308 } 1309 1310 g_free(i8259); 1311 } 1312 1313 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1314 Error **errp) 1315 { 1316 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1317 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1318 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1319 const MachineState *ms = MACHINE(hotplug_dev); 1320 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1321 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1322 Error *local_err = NULL; 1323 1324 /* 1325 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1326 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1327 * addition to cover this case. 1328 */ 1329 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1330 error_setg(errp, 1331 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1332 return; 1333 } 1334 1335 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1336 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1337 return; 1338 } 1339 1340 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1341 if (local_err) { 1342 error_propagate(errp, local_err); 1343 return; 1344 } 1345 1346 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1347 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1348 } 1349 1350 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1351 DeviceState *dev, Error **errp) 1352 { 1353 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1354 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1355 MachineState *ms = MACHINE(hotplug_dev); 1356 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1357 1358 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1359 1360 if (is_nvdimm) { 1361 nvdimm_plug(ms->nvdimms_state); 1362 } 1363 1364 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1365 } 1366 1367 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1371 1372 /* 1373 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1374 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1375 * addition to cover this case. 1376 */ 1377 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1378 error_setg(errp, 1379 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1380 return; 1381 } 1382 1383 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1384 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1385 return; 1386 } 1387 1388 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1389 errp); 1390 } 1391 1392 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1393 DeviceState *dev, Error **errp) 1394 { 1395 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1396 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1397 Error *local_err = NULL; 1398 1399 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1400 if (local_err) { 1401 goto out; 1402 } 1403 1404 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1405 qdev_unrealize(dev); 1406 out: 1407 error_propagate(errp, local_err); 1408 } 1409 1410 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1411 DeviceState *dev, Error **errp) 1412 { 1413 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1414 g_assert(!dev->hotplugged); 1415 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1416 errp); 1417 } 1418 1419 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1420 DeviceState *dev, Error **errp) 1421 { 1422 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1423 } 1424 1425 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1426 DeviceState *dev, Error **errp) 1427 { 1428 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1429 pc_memory_pre_plug(hotplug_dev, dev, errp); 1430 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1431 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1433 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1435 /* Declare the APIC range as the reserved MSI region */ 1436 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1437 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1438 QList *reserved_regions = qlist_new(); 1439 1440 qlist_append_str(reserved_regions, resv_prop_str); 1441 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1442 1443 g_free(resv_prop_str); 1444 } 1445 1446 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1447 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1448 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1449 1450 if (pcms->iommu) { 1451 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1452 "for x86 yet."); 1453 return; 1454 } 1455 pcms->iommu = dev; 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1457 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1458 } 1459 } 1460 1461 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1462 DeviceState *dev, Error **errp) 1463 { 1464 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1465 pc_memory_plug(hotplug_dev, dev, errp); 1466 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1467 x86_cpu_plug(hotplug_dev, dev, errp); 1468 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1469 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1470 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1471 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1472 } 1473 } 1474 1475 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1476 DeviceState *dev, Error **errp) 1477 { 1478 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1479 pc_memory_unplug_request(hotplug_dev, dev, errp); 1480 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1481 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1482 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1483 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1484 errp); 1485 } else { 1486 error_setg(errp, "acpi: device unplug request for not supported device" 1487 " type: %s", object_get_typename(OBJECT(dev))); 1488 } 1489 } 1490 1491 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1492 DeviceState *dev, Error **errp) 1493 { 1494 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1495 pc_memory_unplug(hotplug_dev, dev, errp); 1496 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1497 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1498 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1499 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1500 } else { 1501 error_setg(errp, "acpi: device unplug for not supported device" 1502 " type: %s", object_get_typename(OBJECT(dev))); 1503 } 1504 } 1505 1506 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1507 DeviceState *dev) 1508 { 1509 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1510 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1511 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1512 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1513 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1514 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1515 return HOTPLUG_HANDLER(machine); 1516 } 1517 1518 return NULL; 1519 } 1520 1521 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1522 void *opaque, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 OnOffAuto vmport = pcms->vmport; 1526 1527 visit_type_OnOffAuto(v, name, &vmport, errp); 1528 } 1529 1530 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1531 void *opaque, Error **errp) 1532 { 1533 PCMachineState *pcms = PC_MACHINE(obj); 1534 1535 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1536 } 1537 1538 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1539 { 1540 PCMachineState *pcms = PC_MACHINE(obj); 1541 1542 return pcms->fd_bootchk; 1543 } 1544 1545 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1546 { 1547 PCMachineState *pcms = PC_MACHINE(obj); 1548 1549 pcms->fd_bootchk = value; 1550 } 1551 1552 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1553 { 1554 PCMachineState *pcms = PC_MACHINE(obj); 1555 1556 return pcms->smbus_enabled; 1557 } 1558 1559 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1560 { 1561 PCMachineState *pcms = PC_MACHINE(obj); 1562 1563 pcms->smbus_enabled = value; 1564 } 1565 1566 static bool pc_machine_get_sata(Object *obj, Error **errp) 1567 { 1568 PCMachineState *pcms = PC_MACHINE(obj); 1569 1570 return pcms->sata_enabled; 1571 } 1572 1573 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1574 { 1575 PCMachineState *pcms = PC_MACHINE(obj); 1576 1577 pcms->sata_enabled = value; 1578 } 1579 1580 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1581 { 1582 PCMachineState *pcms = PC_MACHINE(obj); 1583 1584 return pcms->hpet_enabled; 1585 } 1586 1587 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1588 { 1589 PCMachineState *pcms = PC_MACHINE(obj); 1590 1591 pcms->hpet_enabled = value; 1592 } 1593 1594 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1595 { 1596 PCMachineState *pcms = PC_MACHINE(obj); 1597 1598 return pcms->i8042_enabled; 1599 } 1600 1601 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1602 { 1603 PCMachineState *pcms = PC_MACHINE(obj); 1604 1605 pcms->i8042_enabled = value; 1606 } 1607 1608 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1609 { 1610 PCMachineState *pcms = PC_MACHINE(obj); 1611 1612 return pcms->default_bus_bypass_iommu; 1613 } 1614 1615 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1616 Error **errp) 1617 { 1618 PCMachineState *pcms = PC_MACHINE(obj); 1619 1620 pcms->default_bus_bypass_iommu = value; 1621 } 1622 1623 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1624 void *opaque, Error **errp) 1625 { 1626 PCMachineState *pcms = PC_MACHINE(obj); 1627 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1628 1629 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1630 } 1631 1632 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1633 void *opaque, Error **errp) 1634 { 1635 PCMachineState *pcms = PC_MACHINE(obj); 1636 1637 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1638 } 1639 1640 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1641 const char *name, void *opaque, 1642 Error **errp) 1643 { 1644 PCMachineState *pcms = PC_MACHINE(obj); 1645 uint64_t value = pcms->max_ram_below_4g; 1646 1647 visit_type_size(v, name, &value, errp); 1648 } 1649 1650 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1651 const char *name, void *opaque, 1652 Error **errp) 1653 { 1654 PCMachineState *pcms = PC_MACHINE(obj); 1655 uint64_t value; 1656 1657 if (!visit_type_size(v, name, &value, errp)) { 1658 return; 1659 } 1660 if (value > 4 * GiB) { 1661 error_setg(errp, 1662 "Machine option 'max-ram-below-4g=%"PRIu64 1663 "' expects size less than or equal to 4G", value); 1664 return; 1665 } 1666 1667 if (value < 1 * MiB) { 1668 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1669 "BIOS may not work with less than 1MiB", value); 1670 } 1671 1672 pcms->max_ram_below_4g = value; 1673 } 1674 1675 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1676 const char *name, void *opaque, 1677 Error **errp) 1678 { 1679 PCMachineState *pcms = PC_MACHINE(obj); 1680 uint64_t value = pcms->max_fw_size; 1681 1682 visit_type_size(v, name, &value, errp); 1683 } 1684 1685 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1686 const char *name, void *opaque, 1687 Error **errp) 1688 { 1689 PCMachineState *pcms = PC_MACHINE(obj); 1690 uint64_t value; 1691 1692 if (!visit_type_size(v, name, &value, errp)) { 1693 return; 1694 } 1695 1696 /* 1697 * We don't have a theoretically justifiable exact lower bound on the base 1698 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1699 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1700 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1701 * 16MiB in size. 1702 */ 1703 if (value > 16 * MiB) { 1704 error_setg(errp, 1705 "User specified max allowed firmware size %" PRIu64 " is " 1706 "greater than 16MiB. If combined firmware size exceeds " 1707 "16MiB the system may not boot, or experience intermittent" 1708 "stability issues.", 1709 value); 1710 return; 1711 } 1712 1713 pcms->max_fw_size = value; 1714 } 1715 1716 1717 static void pc_machine_initfn(Object *obj) 1718 { 1719 PCMachineState *pcms = PC_MACHINE(obj); 1720 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1721 1722 #ifdef CONFIG_VMPORT 1723 pcms->vmport = ON_OFF_AUTO_AUTO; 1724 #else 1725 pcms->vmport = ON_OFF_AUTO_OFF; 1726 #endif /* CONFIG_VMPORT */ 1727 pcms->max_ram_below_4g = 0; /* use default */ 1728 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1729 pcms->south_bridge = pcmc->default_south_bridge; 1730 1731 /* acpi build is enabled by default if machine supports it */ 1732 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1733 pcms->smbus_enabled = true; 1734 pcms->sata_enabled = true; 1735 pcms->i8042_enabled = true; 1736 pcms->max_fw_size = 8 * MiB; 1737 #ifdef CONFIG_HPET 1738 pcms->hpet_enabled = true; 1739 #endif 1740 pcms->fd_bootchk = true; 1741 pcms->default_bus_bypass_iommu = false; 1742 1743 pc_system_flash_create(pcms); 1744 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1745 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1746 OBJECT(pcms->pcspk), "audiodev"); 1747 if (pcmc->pci_enabled) { 1748 cxl_machine_init(obj, &pcms->cxl_devices_state); 1749 } 1750 1751 pcms->machine_done.notify = pc_machine_done; 1752 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1753 } 1754 1755 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1756 { 1757 CPUState *cs; 1758 X86CPU *cpu; 1759 1760 qemu_devices_reset(reason); 1761 1762 /* Reset APIC after devices have been reset to cancel 1763 * any changes that qemu_devices_reset() might have done. 1764 */ 1765 CPU_FOREACH(cs) { 1766 cpu = X86_CPU(cs); 1767 1768 x86_cpu_after_reset(cpu); 1769 } 1770 } 1771 1772 static void pc_machine_wakeup(MachineState *machine) 1773 { 1774 cpu_synchronize_all_states(); 1775 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1776 cpu_synchronize_all_post_reset(); 1777 } 1778 1779 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1780 { 1781 X86IOMMUState *iommu = x86_iommu_get_default(); 1782 IntelIOMMUState *intel_iommu; 1783 1784 if (iommu && 1785 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1786 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1787 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1788 if (!intel_iommu->caching_mode) { 1789 error_setg(errp, "Device assignment is not allowed without " 1790 "enabling caching-mode=on for Intel IOMMU."); 1791 return false; 1792 } 1793 } 1794 1795 return true; 1796 } 1797 1798 static void pc_machine_class_init(ObjectClass *oc, void *data) 1799 { 1800 MachineClass *mc = MACHINE_CLASS(oc); 1801 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1802 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1803 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1804 1805 pcmc->pci_enabled = true; 1806 pcmc->has_acpi_build = true; 1807 pcmc->rsdp_in_ram = true; 1808 pcmc->smbios_defaults = true; 1809 pcmc->smbios_uuid_encoded = true; 1810 pcmc->gigabyte_align = true; 1811 pcmc->has_reserved_memory = true; 1812 pcmc->enforce_aligned_dimm = true; 1813 pcmc->enforce_amd_1tb_hole = true; 1814 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1815 * to be used at the moment, 32K should be enough for a while. */ 1816 pcmc->acpi_data_size = 0x20000 + 0x8000; 1817 pcmc->pvh_enabled = true; 1818 pcmc->kvmclock_create_always = true; 1819 pcmc->resizable_acpi_blob = true; 1820 x86mc->apic_xrupt_override = true; 1821 assert(!mc->get_hotplug_handler); 1822 mc->get_hotplug_handler = pc_get_hotplug_handler; 1823 mc->hotplug_allowed = pc_hotplug_allowed; 1824 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1825 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1826 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1827 mc->auto_enable_numa_with_memhp = true; 1828 mc->auto_enable_numa_with_memdev = true; 1829 mc->has_hotpluggable_cpus = true; 1830 mc->default_boot_order = "cad"; 1831 mc->block_default_type = IF_IDE; 1832 mc->max_cpus = 255; 1833 mc->reset = pc_machine_reset; 1834 mc->wakeup = pc_machine_wakeup; 1835 hc->pre_plug = pc_machine_device_pre_plug_cb; 1836 hc->plug = pc_machine_device_plug_cb; 1837 hc->unplug_request = pc_machine_device_unplug_request_cb; 1838 hc->unplug = pc_machine_device_unplug_cb; 1839 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1840 mc->nvdimm_supported = true; 1841 mc->smp_props.dies_supported = true; 1842 mc->default_ram_id = "pc.ram"; 1843 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1844 1845 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1846 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1847 NULL, NULL); 1848 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1849 "Maximum ram below the 4G boundary (32bit boundary)"); 1850 1851 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1852 pc_machine_get_vmport, pc_machine_set_vmport, 1853 NULL, NULL); 1854 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1855 "Enable vmport (pc & q35)"); 1856 1857 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1858 pc_machine_get_smbus, pc_machine_set_smbus); 1859 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1860 "Enable/disable system management bus"); 1861 1862 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1863 pc_machine_get_sata, pc_machine_set_sata); 1864 object_class_property_set_description(oc, PC_MACHINE_SATA, 1865 "Enable/disable Serial ATA bus"); 1866 1867 object_class_property_add_bool(oc, "hpet", 1868 pc_machine_get_hpet, pc_machine_set_hpet); 1869 object_class_property_set_description(oc, "hpet", 1870 "Enable/disable high precision event timer emulation"); 1871 1872 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1873 pc_machine_get_i8042, pc_machine_set_i8042); 1874 1875 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1876 pc_machine_get_default_bus_bypass_iommu, 1877 pc_machine_set_default_bus_bypass_iommu); 1878 1879 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1880 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1881 NULL, NULL); 1882 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1883 "Maximum combined firmware size"); 1884 1885 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1886 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1887 NULL, NULL); 1888 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1889 "SMBIOS Entry Point type [32, 64]"); 1890 1891 object_class_property_add_bool(oc, "fd-bootchk", 1892 pc_machine_get_fd_bootchk, 1893 pc_machine_set_fd_bootchk); 1894 } 1895 1896 static const TypeInfo pc_machine_info = { 1897 .name = TYPE_PC_MACHINE, 1898 .parent = TYPE_X86_MACHINE, 1899 .abstract = true, 1900 .instance_size = sizeof(PCMachineState), 1901 .instance_init = pc_machine_initfn, 1902 .class_size = sizeof(PCMachineClass), 1903 .class_init = pc_machine_class_init, 1904 .interfaces = (InterfaceInfo[]) { 1905 { TYPE_HOTPLUG_HANDLER }, 1906 { } 1907 }, 1908 }; 1909 1910 static void pc_machine_register_types(void) 1911 { 1912 type_register_static(&pc_machine_info); 1913 } 1914 1915 type_init(pc_machine_register_types) 1916