1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "hw/cxl/cxl.h" 79 #include "qapi/error.h" 80 #include "qapi/qapi-visit-common.h" 81 #include "qapi/qapi-visit-machine.h" 82 #include "qapi/visitor.h" 83 #include "hw/core/cpu.h" 84 #include "hw/usb.h" 85 #include "hw/i386/intel_iommu.h" 86 #include "hw/net/ne2000-isa.h" 87 #include "standard-headers/asm-x86/bootparam.h" 88 #include "hw/virtio/virtio-iommu.h" 89 #include "hw/virtio/virtio-pmem-pci.h" 90 #include "hw/virtio/virtio-mem-pci.h" 91 #include "hw/mem/memory-device.h" 92 #include "sysemu/replay.h" 93 #include "qapi/qmp/qerror.h" 94 #include "e820_memory_layout.h" 95 #include "fw_cfg.h" 96 #include "trace.h" 97 #include CONFIG_DEVICES 98 99 GlobalProperty pc_compat_7_0[] = {}; 100 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 101 102 GlobalProperty pc_compat_6_2[] = { 103 { "virtio-mem", "unplugged-inaccessible", "off" }, 104 }; 105 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 106 107 GlobalProperty pc_compat_6_1[] = { 108 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 109 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 110 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 111 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 112 }; 113 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 114 115 GlobalProperty pc_compat_6_0[] = { 116 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 117 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 119 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 120 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 121 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 122 }; 123 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 124 125 GlobalProperty pc_compat_5_2[] = { 126 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 127 }; 128 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 129 130 GlobalProperty pc_compat_5_1[] = { 131 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 132 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 133 }; 134 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 135 136 GlobalProperty pc_compat_5_0[] = { 137 }; 138 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 139 140 GlobalProperty pc_compat_4_2[] = { 141 { "mch", "smbase-smram", "off" }, 142 }; 143 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 144 145 GlobalProperty pc_compat_4_1[] = {}; 146 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 147 148 GlobalProperty pc_compat_4_0[] = {}; 149 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 150 151 GlobalProperty pc_compat_3_1[] = { 152 { "intel-iommu", "dma-drain", "off" }, 153 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 154 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 157 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 160 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 162 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 164 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 165 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 172 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 173 }; 174 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 175 176 GlobalProperty pc_compat_3_0[] = { 177 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 178 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 179 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 180 }; 181 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 182 183 GlobalProperty pc_compat_2_12[] = { 184 { TYPE_X86_CPU, "legacy-cache", "on" }, 185 { TYPE_X86_CPU, "topoext", "off" }, 186 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 187 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 }; 189 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 190 191 GlobalProperty pc_compat_2_11[] = { 192 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 193 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 194 }; 195 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 196 197 GlobalProperty pc_compat_2_10[] = { 198 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 199 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 200 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 201 }; 202 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 203 204 GlobalProperty pc_compat_2_9[] = { 205 { "mch", "extended-tseg-mbytes", "0" }, 206 }; 207 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 208 209 GlobalProperty pc_compat_2_8[] = { 210 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 211 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 212 { "ICH9-LPC", "x-smi-broadcast", "off" }, 213 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 214 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 215 }; 216 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 217 218 GlobalProperty pc_compat_2_7[] = { 219 { TYPE_X86_CPU, "l3-cache", "off" }, 220 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 221 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 224 { "isa-pcspk", "migrate", "off" }, 225 }; 226 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 227 228 GlobalProperty pc_compat_2_6[] = { 229 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 230 { "vmxnet3", "romfile", "" }, 231 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 232 { "apic-common", "legacy-instance-id", "on", } 233 }; 234 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 235 236 GlobalProperty pc_compat_2_5[] = {}; 237 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 238 239 GlobalProperty pc_compat_2_4[] = { 240 PC_CPU_MODEL_IDS("2.4.0") 241 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 242 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 243 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 245 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 246 { TYPE_X86_CPU, "check", "off" }, 247 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 248 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 250 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 252 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 255 }; 256 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 257 258 GlobalProperty pc_compat_2_3[] = { 259 PC_CPU_MODEL_IDS("2.3.0") 260 { TYPE_X86_CPU, "arat", "off" }, 261 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 262 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 263 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 264 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 265 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 266 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 269 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 280 }; 281 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 282 283 GlobalProperty pc_compat_2_2[] = { 284 PC_CPU_MODEL_IDS("2.2.0") 285 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 286 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 301 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 303 }; 304 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 305 306 GlobalProperty pc_compat_2_1[] = { 307 PC_CPU_MODEL_IDS("2.1.0") 308 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 309 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 }; 311 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 312 313 GlobalProperty pc_compat_2_0[] = { 314 PC_CPU_MODEL_IDS("2.0.0") 315 { "virtio-scsi-pci", "any_layout", "off" }, 316 { "PIIX4_PM", "memory-hotplug-support", "off" }, 317 { "apic", "version", "0x11" }, 318 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 319 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 320 { "pci-serial", "prog_if", "0" }, 321 { "pci-serial-2x", "prog_if", "0" }, 322 { "pci-serial-4x", "prog_if", "0" }, 323 { "virtio-net-pci", "guest_announce", "off" }, 324 { "ICH9-LPC", "memory-hotplug-support", "off" }, 325 }; 326 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 327 328 GlobalProperty pc_compat_1_7[] = { 329 PC_CPU_MODEL_IDS("1.7.0") 330 { TYPE_USB_DEVICE, "msos-desc", "no" }, 331 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 332 { "hpet", HPET_INTCAP, "4" }, 333 }; 334 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 335 336 GlobalProperty pc_compat_1_6[] = { 337 PC_CPU_MODEL_IDS("1.6.0") 338 { "e1000", "mitigation", "off" }, 339 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 340 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 341 { "i440FX-pcihost", "short_root_bus", "1" }, 342 { "q35-pcihost", "short_root_bus", "1" }, 343 }; 344 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 345 346 GlobalProperty pc_compat_1_5[] = { 347 PC_CPU_MODEL_IDS("1.5.0") 348 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 349 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 350 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 351 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 352 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 353 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 354 { "virtio-net-pci", "any_layout", "off" }, 355 { TYPE_X86_CPU, "pmu", "on" }, 356 { "i440FX-pcihost", "short_root_bus", "0" }, 357 { "q35-pcihost", "short_root_bus", "0" }, 358 }; 359 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 360 361 GlobalProperty pc_compat_1_4[] = { 362 PC_CPU_MODEL_IDS("1.4.0") 363 { "scsi-hd", "discard_granularity", "0" }, 364 { "scsi-cd", "discard_granularity", "0" }, 365 { "ide-hd", "discard_granularity", "0" }, 366 { "ide-cd", "discard_granularity", "0" }, 367 { "virtio-blk-pci", "discard_granularity", "0" }, 368 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 369 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 370 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 371 { "e1000", "romfile", "pxe-e1000.rom" }, 372 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 373 { "pcnet", "romfile", "pxe-pcnet.rom" }, 374 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 375 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 376 { "486-" TYPE_X86_CPU, "model", "0" }, 377 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 378 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 379 }; 380 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 381 382 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 383 { 384 GSIState *s; 385 386 s = g_new0(GSIState, 1); 387 if (kvm_ioapic_in_kernel()) { 388 kvm_pc_setup_irq_routing(pci_enabled); 389 } 390 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 391 392 return s; 393 } 394 395 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 396 unsigned size) 397 { 398 } 399 400 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 401 { 402 return 0xffffffffffffffffULL; 403 } 404 405 /* MSDOS compatibility mode FPU exception support */ 406 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 407 unsigned size) 408 { 409 if (tcg_enabled()) { 410 cpu_set_ignne(); 411 } 412 } 413 414 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 415 { 416 return 0xffffffffffffffffULL; 417 } 418 419 /* PC cmos mappings */ 420 421 #define REG_EQUIPMENT_BYTE 0x14 422 423 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 424 int16_t cylinders, int8_t heads, int8_t sectors) 425 { 426 rtc_set_memory(s, type_ofs, 47); 427 rtc_set_memory(s, info_ofs, cylinders); 428 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 429 rtc_set_memory(s, info_ofs + 2, heads); 430 rtc_set_memory(s, info_ofs + 3, 0xff); 431 rtc_set_memory(s, info_ofs + 4, 0xff); 432 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 433 rtc_set_memory(s, info_ofs + 6, cylinders); 434 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 435 rtc_set_memory(s, info_ofs + 8, sectors); 436 } 437 438 /* convert boot_device letter to something recognizable by the bios */ 439 static int boot_device2nibble(char boot_device) 440 { 441 switch(boot_device) { 442 case 'a': 443 case 'b': 444 return 0x01; /* floppy boot */ 445 case 'c': 446 return 0x02; /* hard drive boot */ 447 case 'd': 448 return 0x03; /* CD-ROM boot */ 449 case 'n': 450 return 0x04; /* Network boot */ 451 } 452 return 0; 453 } 454 455 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 456 { 457 #define PC_MAX_BOOT_DEVICES 3 458 int nbds, bds[3] = { 0, }; 459 int i; 460 461 nbds = strlen(boot_device); 462 if (nbds > PC_MAX_BOOT_DEVICES) { 463 error_setg(errp, "Too many boot devices for PC"); 464 return; 465 } 466 for (i = 0; i < nbds; i++) { 467 bds[i] = boot_device2nibble(boot_device[i]); 468 if (bds[i] == 0) { 469 error_setg(errp, "Invalid boot device for PC: '%c'", 470 boot_device[i]); 471 return; 472 } 473 } 474 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 475 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 476 } 477 478 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 479 { 480 set_boot_dev(opaque, boot_device, errp); 481 } 482 483 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 484 { 485 int val, nb, i; 486 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 487 FLOPPY_DRIVE_TYPE_NONE }; 488 489 /* floppy type */ 490 if (floppy) { 491 for (i = 0; i < 2; i++) { 492 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 493 } 494 } 495 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 496 cmos_get_fd_drive_type(fd_type[1]); 497 rtc_set_memory(rtc_state, 0x10, val); 498 499 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 500 nb = 0; 501 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 502 nb++; 503 } 504 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 505 nb++; 506 } 507 switch (nb) { 508 case 0: 509 break; 510 case 1: 511 val |= 0x01; /* 1 drive, ready for boot */ 512 break; 513 case 2: 514 val |= 0x41; /* 2 drives, ready for boot */ 515 break; 516 } 517 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 518 } 519 520 typedef struct pc_cmos_init_late_arg { 521 ISADevice *rtc_state; 522 BusState *idebus[2]; 523 } pc_cmos_init_late_arg; 524 525 typedef struct check_fdc_state { 526 ISADevice *floppy; 527 bool multiple; 528 } CheckFdcState; 529 530 static int check_fdc(Object *obj, void *opaque) 531 { 532 CheckFdcState *state = opaque; 533 Object *fdc; 534 uint32_t iobase; 535 Error *local_err = NULL; 536 537 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 538 if (!fdc) { 539 return 0; 540 } 541 542 iobase = object_property_get_uint(obj, "iobase", &local_err); 543 if (local_err || iobase != 0x3f0) { 544 error_free(local_err); 545 return 0; 546 } 547 548 if (state->floppy) { 549 state->multiple = true; 550 } else { 551 state->floppy = ISA_DEVICE(obj); 552 } 553 return 0; 554 } 555 556 static const char * const fdc_container_path[] = { 557 "/unattached", "/peripheral", "/peripheral-anon" 558 }; 559 560 /* 561 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 562 * and ACPI objects. 563 */ 564 ISADevice *pc_find_fdc0(void) 565 { 566 int i; 567 Object *container; 568 CheckFdcState state = { 0 }; 569 570 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 571 container = container_get(qdev_get_machine(), fdc_container_path[i]); 572 object_child_foreach(container, check_fdc, &state); 573 } 574 575 if (state.multiple) { 576 warn_report("multiple floppy disk controllers with " 577 "iobase=0x3f0 have been found"); 578 error_printf("the one being picked for CMOS setup might not reflect " 579 "your intent"); 580 } 581 582 return state.floppy; 583 } 584 585 static void pc_cmos_init_late(void *opaque) 586 { 587 pc_cmos_init_late_arg *arg = opaque; 588 ISADevice *s = arg->rtc_state; 589 int16_t cylinders; 590 int8_t heads, sectors; 591 int val; 592 int i, trans; 593 594 val = 0; 595 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 596 &cylinders, &heads, §ors) >= 0) { 597 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 598 val |= 0xf0; 599 } 600 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 601 &cylinders, &heads, §ors) >= 0) { 602 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 603 val |= 0x0f; 604 } 605 rtc_set_memory(s, 0x12, val); 606 607 val = 0; 608 for (i = 0; i < 4; i++) { 609 /* NOTE: ide_get_geometry() returns the physical 610 geometry. It is always such that: 1 <= sects <= 63, 1 611 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 612 geometry can be different if a translation is done. */ 613 if (arg->idebus[i / 2] && 614 ide_get_geometry(arg->idebus[i / 2], i % 2, 615 &cylinders, &heads, §ors) >= 0) { 616 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 617 assert((trans & ~3) == 0); 618 val |= trans << (i * 2); 619 } 620 } 621 rtc_set_memory(s, 0x39, val); 622 623 pc_cmos_init_floppy(s, pc_find_fdc0()); 624 625 qemu_unregister_reset(pc_cmos_init_late, opaque); 626 } 627 628 void pc_cmos_init(PCMachineState *pcms, 629 BusState *idebus0, BusState *idebus1, 630 ISADevice *s) 631 { 632 int val; 633 static pc_cmos_init_late_arg arg; 634 X86MachineState *x86ms = X86_MACHINE(pcms); 635 636 /* various important CMOS locations needed by PC/Bochs bios */ 637 638 /* memory size */ 639 /* base memory (first MiB) */ 640 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 641 rtc_set_memory(s, 0x15, val); 642 rtc_set_memory(s, 0x16, val >> 8); 643 /* extended memory (next 64MiB) */ 644 if (x86ms->below_4g_mem_size > 1 * MiB) { 645 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 646 } else { 647 val = 0; 648 } 649 if (val > 65535) 650 val = 65535; 651 rtc_set_memory(s, 0x17, val); 652 rtc_set_memory(s, 0x18, val >> 8); 653 rtc_set_memory(s, 0x30, val); 654 rtc_set_memory(s, 0x31, val >> 8); 655 /* memory between 16MiB and 4GiB */ 656 if (x86ms->below_4g_mem_size > 16 * MiB) { 657 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 658 } else { 659 val = 0; 660 } 661 if (val > 65535) 662 val = 65535; 663 rtc_set_memory(s, 0x34, val); 664 rtc_set_memory(s, 0x35, val >> 8); 665 /* memory above 4GiB */ 666 val = x86ms->above_4g_mem_size / 65536; 667 rtc_set_memory(s, 0x5b, val); 668 rtc_set_memory(s, 0x5c, val >> 8); 669 rtc_set_memory(s, 0x5d, val >> 16); 670 671 object_property_add_link(OBJECT(pcms), "rtc_state", 672 TYPE_ISA_DEVICE, 673 (Object **)&x86ms->rtc, 674 object_property_allow_set_link, 675 OBJ_PROP_LINK_STRONG); 676 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 677 &error_abort); 678 679 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 680 681 val = 0; 682 val |= 0x02; /* FPU is there */ 683 val |= 0x04; /* PS/2 mouse installed */ 684 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 685 686 /* hard drives and FDC */ 687 arg.rtc_state = s; 688 arg.idebus[0] = idebus0; 689 arg.idebus[1] = idebus1; 690 qemu_register_reset(pc_cmos_init_late, &arg); 691 } 692 693 static void handle_a20_line_change(void *opaque, int irq, int level) 694 { 695 X86CPU *cpu = opaque; 696 697 /* XXX: send to all CPUs ? */ 698 /* XXX: add logic to handle multiple A20 line sources */ 699 x86_cpu_set_a20(cpu, level); 700 } 701 702 #define NE2000_NB_MAX 6 703 704 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 705 0x280, 0x380 }; 706 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 707 708 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 709 { 710 static int nb_ne2k = 0; 711 712 if (nb_ne2k == NE2000_NB_MAX) 713 return; 714 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 715 ne2000_irq[nb_ne2k], nd); 716 nb_ne2k++; 717 } 718 719 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 720 { 721 X86CPU *cpu = opaque; 722 723 if (level) { 724 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 725 } 726 } 727 728 static 729 void pc_machine_done(Notifier *notifier, void *data) 730 { 731 PCMachineState *pcms = container_of(notifier, 732 PCMachineState, machine_done); 733 X86MachineState *x86ms = X86_MACHINE(pcms); 734 735 /* set the number of CPUs */ 736 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 737 738 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 739 740 acpi_setup(); 741 if (x86ms->fw_cfg) { 742 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 743 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 744 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 745 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 746 } 747 } 748 749 void pc_guest_info_init(PCMachineState *pcms) 750 { 751 X86MachineState *x86ms = X86_MACHINE(pcms); 752 753 x86ms->apic_xrupt_override = true; 754 pcms->machine_done.notify = pc_machine_done; 755 qemu_add_machine_init_done_notifier(&pcms->machine_done); 756 } 757 758 /* setup pci memory address space mapping into system address space */ 759 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 760 MemoryRegion *pci_address_space) 761 { 762 /* Set to lower priority than RAM */ 763 memory_region_add_subregion_overlap(system_memory, 0x0, 764 pci_address_space, -1); 765 } 766 767 void xen_load_linux(PCMachineState *pcms) 768 { 769 int i; 770 FWCfgState *fw_cfg; 771 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 772 X86MachineState *x86ms = X86_MACHINE(pcms); 773 774 assert(MACHINE(pcms)->kernel_filename != NULL); 775 776 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 777 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 778 rom_set_fw(fw_cfg); 779 780 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 781 pcmc->pvh_enabled); 782 for (i = 0; i < nb_option_roms; i++) { 783 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 784 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 785 !strcmp(option_rom[i].name, "pvh.bin") || 786 !strcmp(option_rom[i].name, "multiboot.bin") || 787 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 788 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 789 } 790 x86ms->fw_cfg = fw_cfg; 791 } 792 793 #define PC_ROM_MIN_VGA 0xc0000 794 #define PC_ROM_MIN_OPTION 0xc8000 795 #define PC_ROM_MAX 0xe0000 796 #define PC_ROM_ALIGN 0x800 797 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 798 799 void pc_memory_init(PCMachineState *pcms, 800 MemoryRegion *system_memory, 801 MemoryRegion *rom_memory, 802 MemoryRegion **ram_memory) 803 { 804 int linux_boot, i; 805 MemoryRegion *option_rom_mr; 806 MemoryRegion *ram_below_4g, *ram_above_4g; 807 FWCfgState *fw_cfg; 808 MachineState *machine = MACHINE(pcms); 809 MachineClass *mc = MACHINE_GET_CLASS(machine); 810 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 811 X86MachineState *x86ms = X86_MACHINE(pcms); 812 hwaddr cxl_base, cxl_resv_end = 0; 813 814 assert(machine->ram_size == x86ms->below_4g_mem_size + 815 x86ms->above_4g_mem_size); 816 817 linux_boot = (machine->kernel_filename != NULL); 818 819 /* 820 * Split single memory region and use aliases to address portions of it, 821 * done for backwards compatibility with older qemus. 822 */ 823 *ram_memory = machine->ram; 824 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 825 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 826 0, x86ms->below_4g_mem_size); 827 memory_region_add_subregion(system_memory, 0, ram_below_4g); 828 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 829 if (x86ms->above_4g_mem_size > 0) { 830 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 831 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 832 machine->ram, 833 x86ms->below_4g_mem_size, 834 x86ms->above_4g_mem_size); 835 memory_region_add_subregion(system_memory, 0x100000000ULL, 836 ram_above_4g); 837 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 838 } 839 840 if (pcms->sgx_epc.size != 0) { 841 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 842 } 843 844 if (!pcmc->has_reserved_memory && 845 (machine->ram_slots || 846 (machine->maxram_size > machine->ram_size))) { 847 848 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 849 mc->name); 850 exit(EXIT_FAILURE); 851 } 852 853 /* always allocate the device memory information */ 854 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 855 856 /* initialize device memory address space */ 857 if (pcmc->has_reserved_memory && 858 (machine->ram_size < machine->maxram_size)) { 859 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 860 861 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 862 error_report("unsupported amount of memory slots: %"PRIu64, 863 machine->ram_slots); 864 exit(EXIT_FAILURE); 865 } 866 867 if (QEMU_ALIGN_UP(machine->maxram_size, 868 TARGET_PAGE_SIZE) != machine->maxram_size) { 869 error_report("maximum memory size must by aligned to multiple of " 870 "%d bytes", TARGET_PAGE_SIZE); 871 exit(EXIT_FAILURE); 872 } 873 874 if (pcms->sgx_epc.size != 0) { 875 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 876 } else { 877 machine->device_memory->base = 878 0x100000000ULL + x86ms->above_4g_mem_size; 879 } 880 881 machine->device_memory->base = 882 ROUND_UP(machine->device_memory->base, 1 * GiB); 883 884 if (pcmc->enforce_aligned_dimm) { 885 /* size device region assuming 1G page max alignment per slot */ 886 device_mem_size += (1 * GiB) * machine->ram_slots; 887 } 888 889 if ((machine->device_memory->base + device_mem_size) < 890 device_mem_size) { 891 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 892 machine->maxram_size); 893 exit(EXIT_FAILURE); 894 } 895 896 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 897 "device-memory", device_mem_size); 898 memory_region_add_subregion(system_memory, machine->device_memory->base, 899 &machine->device_memory->mr); 900 } 901 902 if (machine->cxl_devices_state->is_enabled) { 903 MemoryRegion *mr = &machine->cxl_devices_state->host_mr; 904 hwaddr cxl_size = MiB; 905 906 if (pcmc->has_reserved_memory && machine->device_memory->base) { 907 cxl_base = machine->device_memory->base; 908 if (!pcmc->broken_reserved_end) { 909 cxl_base += memory_region_size(&machine->device_memory->mr); 910 } 911 } else if (pcms->sgx_epc.size != 0) { 912 cxl_base = sgx_epc_above_4g_end(&pcms->sgx_epc); 913 } else { 914 cxl_base = 0x100000000ULL + x86ms->above_4g_mem_size; 915 } 916 917 e820_add_entry(cxl_base, cxl_size, E820_RESERVED); 918 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 919 memory_region_add_subregion(system_memory, cxl_base, mr); 920 cxl_resv_end = cxl_base + cxl_size; 921 if (machine->cxl_devices_state->fixed_windows) { 922 hwaddr cxl_fmw_base; 923 GList *it; 924 925 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 926 for (it = machine->cxl_devices_state->fixed_windows; it; it = it->next) { 927 CXLFixedWindow *fw = it->data; 928 929 fw->base = cxl_fmw_base; 930 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 931 "cxl-fixed-memory-region", fw->size); 932 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 933 e820_add_entry(fw->base, fw->size, E820_RESERVED); 934 cxl_fmw_base += fw->size; 935 cxl_resv_end = cxl_fmw_base; 936 } 937 } 938 } 939 940 /* Initialize PC system firmware */ 941 pc_system_firmware_init(pcms, rom_memory); 942 943 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 944 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 945 &error_fatal); 946 if (pcmc->pci_enabled) { 947 memory_region_set_readonly(option_rom_mr, true); 948 } 949 memory_region_add_subregion_overlap(rom_memory, 950 PC_ROM_MIN_VGA, 951 option_rom_mr, 952 1); 953 954 fw_cfg = fw_cfg_arch_create(machine, 955 x86ms->boot_cpus, x86ms->apic_id_limit); 956 957 rom_set_fw(fw_cfg); 958 959 if (pcmc->has_reserved_memory && machine->device_memory->base) { 960 uint64_t *val = g_malloc(sizeof(*val)); 961 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 962 uint64_t res_mem_end = machine->device_memory->base; 963 964 if (!pcmc->broken_reserved_end) { 965 res_mem_end += memory_region_size(&machine->device_memory->mr); 966 } 967 968 if (machine->cxl_devices_state->is_enabled) { 969 res_mem_end = cxl_resv_end; 970 } 971 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 972 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 973 } 974 975 if (linux_boot) { 976 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 977 pcmc->pvh_enabled); 978 } 979 980 for (i = 0; i < nb_option_roms; i++) { 981 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 982 } 983 x86ms->fw_cfg = fw_cfg; 984 985 /* Init default IOAPIC address space */ 986 x86ms->ioapic_as = &address_space_memory; 987 988 /* Init ACPI memory hotplug IO base address */ 989 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 990 } 991 992 /* 993 * The 64bit pci hole starts after "above 4G RAM" and 994 * potentially the space reserved for memory hotplug. 995 */ 996 uint64_t pc_pci_hole64_start(void) 997 { 998 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 999 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1000 MachineState *ms = MACHINE(pcms); 1001 X86MachineState *x86ms = X86_MACHINE(pcms); 1002 uint64_t hole64_start = 0; 1003 1004 if (ms->cxl_devices_state->host_mr.addr) { 1005 hole64_start = ms->cxl_devices_state->host_mr.addr + 1006 memory_region_size(&ms->cxl_devices_state->host_mr); 1007 if (ms->cxl_devices_state->fixed_windows) { 1008 GList *it; 1009 for (it = ms->cxl_devices_state->fixed_windows; it; it = it->next) { 1010 CXLFixedWindow *fw = it->data; 1011 hole64_start = fw->mr.addr + memory_region_size(&fw->mr); 1012 } 1013 } 1014 } else if (pcmc->has_reserved_memory && ms->device_memory->base) { 1015 hole64_start = ms->device_memory->base; 1016 if (!pcmc->broken_reserved_end) { 1017 hole64_start += memory_region_size(&ms->device_memory->mr); 1018 } 1019 } else if (pcms->sgx_epc.size != 0) { 1020 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 1021 } else { 1022 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1023 } 1024 1025 return ROUND_UP(hole64_start, 1 * GiB); 1026 } 1027 1028 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1029 { 1030 DeviceState *dev = NULL; 1031 1032 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1033 if (pci_bus) { 1034 PCIDevice *pcidev = pci_vga_init(pci_bus); 1035 dev = pcidev ? &pcidev->qdev : NULL; 1036 } else if (isa_bus) { 1037 ISADevice *isadev = isa_vga_init(isa_bus); 1038 dev = isadev ? DEVICE(isadev) : NULL; 1039 } 1040 rom_reset_order_override(); 1041 return dev; 1042 } 1043 1044 static const MemoryRegionOps ioport80_io_ops = { 1045 .write = ioport80_write, 1046 .read = ioport80_read, 1047 .endianness = DEVICE_NATIVE_ENDIAN, 1048 .impl = { 1049 .min_access_size = 1, 1050 .max_access_size = 1, 1051 }, 1052 }; 1053 1054 static const MemoryRegionOps ioportF0_io_ops = { 1055 .write = ioportF0_write, 1056 .read = ioportF0_read, 1057 .endianness = DEVICE_NATIVE_ENDIAN, 1058 .impl = { 1059 .min_access_size = 1, 1060 .max_access_size = 1, 1061 }, 1062 }; 1063 1064 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1065 bool create_i8042, bool no_vmport) 1066 { 1067 int i; 1068 DriveInfo *fd[MAX_FD]; 1069 qemu_irq *a20_line; 1070 ISADevice *fdc, *i8042, *port92, *vmmouse; 1071 1072 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1073 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1074 1075 for (i = 0; i < MAX_FD; i++) { 1076 fd[i] = drive_get(IF_FLOPPY, 0, i); 1077 create_fdctrl |= !!fd[i]; 1078 } 1079 if (create_fdctrl) { 1080 fdc = isa_new(TYPE_ISA_FDC); 1081 if (fdc) { 1082 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1083 isa_fdc_init_drives(fdc, fd); 1084 } 1085 } 1086 1087 if (!create_i8042) { 1088 return; 1089 } 1090 1091 i8042 = isa_create_simple(isa_bus, "i8042"); 1092 if (!no_vmport) { 1093 isa_create_simple(isa_bus, TYPE_VMPORT); 1094 vmmouse = isa_try_new("vmmouse"); 1095 } else { 1096 vmmouse = NULL; 1097 } 1098 if (vmmouse) { 1099 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1100 &error_abort); 1101 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1102 } 1103 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1104 1105 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1106 i8042_setup_a20_line(i8042, a20_line[0]); 1107 qdev_connect_gpio_out_named(DEVICE(port92), 1108 PORT92_A20_LINE, 0, a20_line[1]); 1109 g_free(a20_line); 1110 } 1111 1112 void pc_basic_device_init(struct PCMachineState *pcms, 1113 ISABus *isa_bus, qemu_irq *gsi, 1114 ISADevice **rtc_state, 1115 bool create_fdctrl, 1116 uint32_t hpet_irqs) 1117 { 1118 int i; 1119 DeviceState *hpet = NULL; 1120 int pit_isa_irq = 0; 1121 qemu_irq pit_alt_irq = NULL; 1122 qemu_irq rtc_irq = NULL; 1123 ISADevice *pit = NULL; 1124 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1125 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1126 1127 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1128 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1129 1130 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1131 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1132 1133 /* 1134 * Check if an HPET shall be created. 1135 * 1136 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1137 * when the HPET wants to take over. Thus we have to disable the latter. 1138 */ 1139 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1140 kvm_has_pit_state2())) { 1141 hpet = qdev_try_new(TYPE_HPET); 1142 if (!hpet) { 1143 error_report("couldn't create HPET device"); 1144 exit(1); 1145 } 1146 /* 1147 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1148 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1149 * IRQ2. 1150 */ 1151 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1152 HPET_INTCAP, NULL); 1153 if (!compat) { 1154 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1155 } 1156 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1157 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1158 1159 for (i = 0; i < GSI_NUM_PINS; i++) { 1160 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1161 } 1162 pit_isa_irq = -1; 1163 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1164 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1165 } 1166 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1167 1168 qemu_register_boot_set(pc_boot_set, *rtc_state); 1169 1170 if (!xen_enabled() && pcms->pit_enabled) { 1171 if (kvm_pit_in_kernel()) { 1172 pit = kvm_pit_init(isa_bus, 0x40); 1173 } else { 1174 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1175 } 1176 if (hpet) { 1177 /* connect PIT to output control line of the HPET */ 1178 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1179 } 1180 pcspk_init(pcms->pcspk, isa_bus, pit); 1181 } 1182 1183 i8257_dma_init(isa_bus, 0); 1184 1185 /* Super I/O */ 1186 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1187 pcms->vmport != ON_OFF_AUTO_ON); 1188 } 1189 1190 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1191 { 1192 int i; 1193 1194 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1195 for (i = 0; i < nb_nics; i++) { 1196 NICInfo *nd = &nd_table[i]; 1197 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1198 1199 if (g_str_equal(model, "ne2k_isa")) { 1200 pc_init_ne2k_isa(isa_bus, nd); 1201 } else { 1202 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1203 } 1204 } 1205 rom_reset_order_override(); 1206 } 1207 1208 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1209 { 1210 qemu_irq *i8259; 1211 1212 if (kvm_pic_in_kernel()) { 1213 i8259 = kvm_i8259_init(isa_bus); 1214 } else if (xen_enabled()) { 1215 i8259 = xen_interrupt_controller_init(); 1216 } else { 1217 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1218 } 1219 1220 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1221 i8259_irqs[i] = i8259[i]; 1222 } 1223 1224 g_free(i8259); 1225 } 1226 1227 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1228 Error **errp) 1229 { 1230 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1231 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1232 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1233 const MachineState *ms = MACHINE(hotplug_dev); 1234 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1235 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1236 Error *local_err = NULL; 1237 1238 /* 1239 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1240 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1241 * addition to cover this case. 1242 */ 1243 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1244 error_setg(errp, 1245 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1246 return; 1247 } 1248 1249 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1250 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1251 return; 1252 } 1253 1254 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1255 if (local_err) { 1256 error_propagate(errp, local_err); 1257 return; 1258 } 1259 1260 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1261 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1262 } 1263 1264 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1265 DeviceState *dev, Error **errp) 1266 { 1267 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1268 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1269 MachineState *ms = MACHINE(hotplug_dev); 1270 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1271 1272 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1273 1274 if (is_nvdimm) { 1275 nvdimm_plug(ms->nvdimms_state); 1276 } 1277 1278 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1279 } 1280 1281 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1282 DeviceState *dev, Error **errp) 1283 { 1284 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1285 1286 /* 1287 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1288 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1289 * addition to cover this case. 1290 */ 1291 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1292 error_setg(errp, 1293 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1294 return; 1295 } 1296 1297 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1298 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1299 return; 1300 } 1301 1302 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1303 errp); 1304 } 1305 1306 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1307 DeviceState *dev, Error **errp) 1308 { 1309 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1310 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1311 Error *local_err = NULL; 1312 1313 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1314 if (local_err) { 1315 goto out; 1316 } 1317 1318 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1319 qdev_unrealize(dev); 1320 out: 1321 error_propagate(errp, local_err); 1322 } 1323 1324 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1325 DeviceState *dev, Error **errp) 1326 { 1327 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1328 Error *local_err = NULL; 1329 1330 if (!hotplug_dev2 && dev->hotplugged) { 1331 /* 1332 * Without a bus hotplug handler, we cannot control the plug/unplug 1333 * order. We should never reach this point when hotplugging on x86, 1334 * however, better add a safety net. 1335 */ 1336 error_setg(errp, "hotplug of virtio based memory devices not supported" 1337 " on this bus."); 1338 return; 1339 } 1340 /* 1341 * First, see if we can plug this memory device at all. If that 1342 * succeeds, branch of to the actual hotplug handler. 1343 */ 1344 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1345 &local_err); 1346 if (!local_err && hotplug_dev2) { 1347 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1348 } 1349 error_propagate(errp, local_err); 1350 } 1351 1352 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1353 DeviceState *dev, Error **errp) 1354 { 1355 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1356 Error *local_err = NULL; 1357 1358 /* 1359 * Plug the memory device first and then branch off to the actual 1360 * hotplug handler. If that one fails, we can easily undo the memory 1361 * device bits. 1362 */ 1363 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1364 if (hotplug_dev2) { 1365 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1366 if (local_err) { 1367 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1368 } 1369 } 1370 error_propagate(errp, local_err); 1371 } 1372 1373 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1374 DeviceState *dev, Error **errp) 1375 { 1376 /* We don't support hot unplug of virtio based memory devices */ 1377 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1378 } 1379 1380 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1381 DeviceState *dev, Error **errp) 1382 { 1383 /* We don't support hot unplug of virtio based memory devices */ 1384 } 1385 1386 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1387 DeviceState *dev, Error **errp) 1388 { 1389 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1390 pc_memory_pre_plug(hotplug_dev, dev, errp); 1391 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1392 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1393 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1394 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1395 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1396 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1397 /* Declare the APIC range as the reserved MSI region */ 1398 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1399 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1400 1401 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1402 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1403 resv_prop_str, errp); 1404 g_free(resv_prop_str); 1405 } 1406 1407 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1408 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1409 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1410 1411 if (pcms->iommu) { 1412 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1413 "for x86 yet."); 1414 return; 1415 } 1416 pcms->iommu = dev; 1417 } 1418 } 1419 1420 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1421 DeviceState *dev, Error **errp) 1422 { 1423 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1424 pc_memory_plug(hotplug_dev, dev, errp); 1425 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1426 x86_cpu_plug(hotplug_dev, dev, errp); 1427 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1428 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1429 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1430 } 1431 } 1432 1433 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1434 DeviceState *dev, Error **errp) 1435 { 1436 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1437 pc_memory_unplug_request(hotplug_dev, dev, errp); 1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1439 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1441 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1442 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1443 } else { 1444 error_setg(errp, "acpi: device unplug request for not supported device" 1445 " type: %s", object_get_typename(OBJECT(dev))); 1446 } 1447 } 1448 1449 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1450 DeviceState *dev, Error **errp) 1451 { 1452 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1453 pc_memory_unplug(hotplug_dev, dev, errp); 1454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1455 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1457 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1458 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1459 } else { 1460 error_setg(errp, "acpi: device unplug for not supported device" 1461 " type: %s", object_get_typename(OBJECT(dev))); 1462 } 1463 } 1464 1465 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1466 DeviceState *dev) 1467 { 1468 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1469 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1470 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1471 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1472 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1473 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1474 return HOTPLUG_HANDLER(machine); 1475 } 1476 1477 return NULL; 1478 } 1479 1480 static void 1481 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1482 const char *name, void *opaque, 1483 Error **errp) 1484 { 1485 MachineState *ms = MACHINE(obj); 1486 int64_t value = 0; 1487 1488 if (ms->device_memory) { 1489 value = memory_region_size(&ms->device_memory->mr); 1490 } 1491 1492 visit_type_int(v, name, &value, errp); 1493 } 1494 1495 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1496 void *opaque, Error **errp) 1497 { 1498 PCMachineState *pcms = PC_MACHINE(obj); 1499 OnOffAuto vmport = pcms->vmport; 1500 1501 visit_type_OnOffAuto(v, name, &vmport, errp); 1502 } 1503 1504 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1505 void *opaque, Error **errp) 1506 { 1507 PCMachineState *pcms = PC_MACHINE(obj); 1508 1509 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1510 } 1511 1512 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1513 { 1514 PCMachineState *pcms = PC_MACHINE(obj); 1515 1516 return pcms->smbus_enabled; 1517 } 1518 1519 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1520 { 1521 PCMachineState *pcms = PC_MACHINE(obj); 1522 1523 pcms->smbus_enabled = value; 1524 } 1525 1526 static bool pc_machine_get_sata(Object *obj, Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 1530 return pcms->sata_enabled; 1531 } 1532 1533 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1534 { 1535 PCMachineState *pcms = PC_MACHINE(obj); 1536 1537 pcms->sata_enabled = value; 1538 } 1539 1540 static bool pc_machine_get_pit(Object *obj, Error **errp) 1541 { 1542 PCMachineState *pcms = PC_MACHINE(obj); 1543 1544 return pcms->pit_enabled; 1545 } 1546 1547 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1548 { 1549 PCMachineState *pcms = PC_MACHINE(obj); 1550 1551 pcms->pit_enabled = value; 1552 } 1553 1554 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(obj); 1557 1558 return pcms->hpet_enabled; 1559 } 1560 1561 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1562 { 1563 PCMachineState *pcms = PC_MACHINE(obj); 1564 1565 pcms->hpet_enabled = value; 1566 } 1567 1568 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1569 { 1570 PCMachineState *pcms = PC_MACHINE(obj); 1571 1572 return pcms->i8042_enabled; 1573 } 1574 1575 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1576 { 1577 PCMachineState *pcms = PC_MACHINE(obj); 1578 1579 pcms->i8042_enabled = value; 1580 } 1581 1582 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1583 { 1584 PCMachineState *pcms = PC_MACHINE(obj); 1585 1586 return pcms->default_bus_bypass_iommu; 1587 } 1588 1589 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1590 Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 1594 pcms->default_bus_bypass_iommu = value; 1595 } 1596 1597 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1598 void *opaque, Error **errp) 1599 { 1600 PCMachineState *pcms = PC_MACHINE(obj); 1601 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1602 1603 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1604 } 1605 1606 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1607 void *opaque, Error **errp) 1608 { 1609 PCMachineState *pcms = PC_MACHINE(obj); 1610 1611 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1612 } 1613 1614 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1615 const char *name, void *opaque, 1616 Error **errp) 1617 { 1618 PCMachineState *pcms = PC_MACHINE(obj); 1619 uint64_t value = pcms->max_ram_below_4g; 1620 1621 visit_type_size(v, name, &value, errp); 1622 } 1623 1624 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1625 const char *name, void *opaque, 1626 Error **errp) 1627 { 1628 PCMachineState *pcms = PC_MACHINE(obj); 1629 uint64_t value; 1630 1631 if (!visit_type_size(v, name, &value, errp)) { 1632 return; 1633 } 1634 if (value > 4 * GiB) { 1635 error_setg(errp, 1636 "Machine option 'max-ram-below-4g=%"PRIu64 1637 "' expects size less than or equal to 4G", value); 1638 return; 1639 } 1640 1641 if (value < 1 * MiB) { 1642 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1643 "BIOS may not work with less than 1MiB", value); 1644 } 1645 1646 pcms->max_ram_below_4g = value; 1647 } 1648 1649 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1650 const char *name, void *opaque, 1651 Error **errp) 1652 { 1653 PCMachineState *pcms = PC_MACHINE(obj); 1654 uint64_t value = pcms->max_fw_size; 1655 1656 visit_type_size(v, name, &value, errp); 1657 } 1658 1659 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1660 const char *name, void *opaque, 1661 Error **errp) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(obj); 1664 Error *error = NULL; 1665 uint64_t value; 1666 1667 visit_type_size(v, name, &value, &error); 1668 if (error) { 1669 error_propagate(errp, error); 1670 return; 1671 } 1672 1673 /* 1674 * We don't have a theoretically justifiable exact lower bound on the base 1675 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1676 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1677 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1678 * size. 1679 */ 1680 if (value > 16 * MiB) { 1681 error_setg(errp, 1682 "User specified max allowed firmware size %" PRIu64 " is " 1683 "greater than 16MiB. If combined firwmare size exceeds " 1684 "16MiB the system may not boot, or experience intermittent" 1685 "stability issues.", 1686 value); 1687 return; 1688 } 1689 1690 pcms->max_fw_size = value; 1691 } 1692 1693 1694 static void pc_machine_initfn(Object *obj) 1695 { 1696 PCMachineState *pcms = PC_MACHINE(obj); 1697 1698 #ifdef CONFIG_VMPORT 1699 pcms->vmport = ON_OFF_AUTO_AUTO; 1700 #else 1701 pcms->vmport = ON_OFF_AUTO_OFF; 1702 #endif /* CONFIG_VMPORT */ 1703 pcms->max_ram_below_4g = 0; /* use default */ 1704 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1705 1706 /* acpi build is enabled by default if machine supports it */ 1707 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1708 pcms->smbus_enabled = true; 1709 pcms->sata_enabled = true; 1710 pcms->pit_enabled = true; 1711 pcms->i8042_enabled = true; 1712 pcms->max_fw_size = 8 * MiB; 1713 #ifdef CONFIG_HPET 1714 pcms->hpet_enabled = true; 1715 #endif 1716 pcms->default_bus_bypass_iommu = false; 1717 1718 pc_system_flash_create(pcms); 1719 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1720 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1721 OBJECT(pcms->pcspk), "audiodev"); 1722 } 1723 1724 static void pc_machine_reset(MachineState *machine) 1725 { 1726 CPUState *cs; 1727 X86CPU *cpu; 1728 1729 qemu_devices_reset(); 1730 1731 /* Reset APIC after devices have been reset to cancel 1732 * any changes that qemu_devices_reset() might have done. 1733 */ 1734 CPU_FOREACH(cs) { 1735 cpu = X86_CPU(cs); 1736 1737 if (cpu->apic_state) { 1738 device_legacy_reset(cpu->apic_state); 1739 } 1740 } 1741 } 1742 1743 static void pc_machine_wakeup(MachineState *machine) 1744 { 1745 cpu_synchronize_all_states(); 1746 pc_machine_reset(machine); 1747 cpu_synchronize_all_post_reset(); 1748 } 1749 1750 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1751 { 1752 X86IOMMUState *iommu = x86_iommu_get_default(); 1753 IntelIOMMUState *intel_iommu; 1754 1755 if (iommu && 1756 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1757 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1758 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1759 if (!intel_iommu->caching_mode) { 1760 error_setg(errp, "Device assignment is not allowed without " 1761 "enabling caching-mode=on for Intel IOMMU."); 1762 return false; 1763 } 1764 } 1765 1766 return true; 1767 } 1768 1769 static void pc_machine_class_init(ObjectClass *oc, void *data) 1770 { 1771 MachineClass *mc = MACHINE_CLASS(oc); 1772 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1773 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1774 1775 pcmc->pci_enabled = true; 1776 pcmc->has_acpi_build = true; 1777 pcmc->rsdp_in_ram = true; 1778 pcmc->smbios_defaults = true; 1779 pcmc->smbios_uuid_encoded = true; 1780 pcmc->gigabyte_align = true; 1781 pcmc->has_reserved_memory = true; 1782 pcmc->kvmclock_enabled = true; 1783 pcmc->enforce_aligned_dimm = true; 1784 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1785 * to be used at the moment, 32K should be enough for a while. */ 1786 pcmc->acpi_data_size = 0x20000 + 0x8000; 1787 pcmc->pvh_enabled = true; 1788 pcmc->kvmclock_create_always = true; 1789 assert(!mc->get_hotplug_handler); 1790 mc->get_hotplug_handler = pc_get_hotplug_handler; 1791 mc->hotplug_allowed = pc_hotplug_allowed; 1792 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1793 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1794 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1795 mc->auto_enable_numa_with_memhp = true; 1796 mc->auto_enable_numa_with_memdev = true; 1797 mc->has_hotpluggable_cpus = true; 1798 mc->default_boot_order = "cad"; 1799 mc->block_default_type = IF_IDE; 1800 mc->max_cpus = 255; 1801 mc->reset = pc_machine_reset; 1802 mc->wakeup = pc_machine_wakeup; 1803 hc->pre_plug = pc_machine_device_pre_plug_cb; 1804 hc->plug = pc_machine_device_plug_cb; 1805 hc->unplug_request = pc_machine_device_unplug_request_cb; 1806 hc->unplug = pc_machine_device_unplug_cb; 1807 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1808 mc->nvdimm_supported = true; 1809 mc->smp_props.dies_supported = true; 1810 mc->cxl_supported = true; 1811 mc->default_ram_id = "pc.ram"; 1812 1813 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1814 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1815 NULL, NULL); 1816 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1817 "Maximum ram below the 4G boundary (32bit boundary)"); 1818 1819 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1820 pc_machine_get_device_memory_region_size, NULL, 1821 NULL, NULL); 1822 1823 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1824 pc_machine_get_vmport, pc_machine_set_vmport, 1825 NULL, NULL); 1826 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1827 "Enable vmport (pc & q35)"); 1828 1829 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1830 pc_machine_get_smbus, pc_machine_set_smbus); 1831 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1832 "Enable/disable system management bus"); 1833 1834 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1835 pc_machine_get_sata, pc_machine_set_sata); 1836 object_class_property_set_description(oc, PC_MACHINE_SATA, 1837 "Enable/disable Serial ATA bus"); 1838 1839 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1840 pc_machine_get_pit, pc_machine_set_pit); 1841 object_class_property_set_description(oc, PC_MACHINE_PIT, 1842 "Enable/disable Intel 8254 programmable interval timer emulation"); 1843 1844 object_class_property_add_bool(oc, "hpet", 1845 pc_machine_get_hpet, pc_machine_set_hpet); 1846 object_class_property_set_description(oc, "hpet", 1847 "Enable/disable high precision event timer emulation"); 1848 1849 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1850 pc_machine_get_i8042, pc_machine_set_i8042); 1851 1852 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1853 pc_machine_get_default_bus_bypass_iommu, 1854 pc_machine_set_default_bus_bypass_iommu); 1855 1856 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1857 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1858 NULL, NULL); 1859 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1860 "Maximum combined firmware size"); 1861 1862 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1863 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1864 NULL, NULL); 1865 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1866 "SMBIOS Entry Point type [32, 64]"); 1867 } 1868 1869 static const TypeInfo pc_machine_info = { 1870 .name = TYPE_PC_MACHINE, 1871 .parent = TYPE_X86_MACHINE, 1872 .abstract = true, 1873 .instance_size = sizeof(PCMachineState), 1874 .instance_init = pc_machine_initfn, 1875 .class_size = sizeof(PCMachineClass), 1876 .class_init = pc_machine_class_init, 1877 .interfaces = (InterfaceInfo[]) { 1878 { TYPE_HOTPLUG_HANDLER }, 1879 { } 1880 }, 1881 }; 1882 1883 static void pc_machine_register_types(void) 1884 { 1885 type_register_static(&pc_machine_info); 1886 } 1887 1888 type_init(pc_machine_register_types) 1889