1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_9_0[] = { 83 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 84 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 85 { "sev-guest", "legacy-vm-type", "true" }, 86 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 87 }; 88 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 89 90 GlobalProperty pc_compat_8_2[] = {}; 91 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 92 93 GlobalProperty pc_compat_8_1[] = {}; 94 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 95 96 GlobalProperty pc_compat_8_0[] = { 97 { "virtio-mem", "unplugged-inaccessible", "auto" }, 98 }; 99 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 100 101 GlobalProperty pc_compat_7_2[] = { 102 { "ICH9-LPC", "noreboot", "true" }, 103 }; 104 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 105 106 GlobalProperty pc_compat_7_1[] = {}; 107 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 108 109 GlobalProperty pc_compat_7_0[] = {}; 110 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 111 112 GlobalProperty pc_compat_6_2[] = { 113 { "virtio-mem", "unplugged-inaccessible", "off" }, 114 }; 115 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 116 117 GlobalProperty pc_compat_6_1[] = { 118 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 119 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 120 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 121 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 122 }; 123 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 124 125 GlobalProperty pc_compat_6_0[] = { 126 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 127 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 128 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 129 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 130 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 131 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 132 }; 133 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 134 135 GlobalProperty pc_compat_5_2[] = { 136 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 137 }; 138 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 139 140 GlobalProperty pc_compat_5_1[] = { 141 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 142 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 143 }; 144 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 145 146 GlobalProperty pc_compat_5_0[] = { 147 }; 148 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 149 150 GlobalProperty pc_compat_4_2[] = { 151 { "mch", "smbase-smram", "off" }, 152 }; 153 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 154 155 GlobalProperty pc_compat_4_1[] = {}; 156 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 157 158 GlobalProperty pc_compat_4_0[] = {}; 159 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 160 161 GlobalProperty pc_compat_3_1[] = { 162 { "intel-iommu", "dma-drain", "off" }, 163 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 164 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 165 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 166 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 167 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 168 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 169 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 170 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 171 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 172 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 173 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 174 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 175 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 176 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 177 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 178 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 179 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 180 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 181 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 182 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 183 }; 184 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 185 186 GlobalProperty pc_compat_3_0[] = { 187 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 188 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 189 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 190 }; 191 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 192 193 GlobalProperty pc_compat_2_12[] = { 194 { TYPE_X86_CPU, "legacy-cache", "on" }, 195 { TYPE_X86_CPU, "topoext", "off" }, 196 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 197 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 198 }; 199 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 200 201 GlobalProperty pc_compat_2_11[] = { 202 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 203 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 204 }; 205 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 206 207 GlobalProperty pc_compat_2_10[] = { 208 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 209 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 210 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 211 }; 212 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 213 214 GlobalProperty pc_compat_2_9[] = { 215 { "mch", "extended-tseg-mbytes", "0" }, 216 }; 217 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 218 219 GlobalProperty pc_compat_2_8[] = { 220 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 221 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 222 { "ICH9-LPC", "x-smi-broadcast", "off" }, 223 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 224 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 225 }; 226 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 227 228 GlobalProperty pc_compat_2_7[] = { 229 { TYPE_X86_CPU, "l3-cache", "off" }, 230 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 231 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 232 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 233 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 234 { "isa-pcspk", "migrate", "off" }, 235 }; 236 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 237 238 GlobalProperty pc_compat_2_6[] = { 239 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 240 { "vmxnet3", "romfile", "" }, 241 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 242 { "apic-common", "legacy-instance-id", "on", } 243 }; 244 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 245 246 GlobalProperty pc_compat_2_5[] = {}; 247 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 248 249 GlobalProperty pc_compat_2_4[] = { 250 PC_CPU_MODEL_IDS("2.4.0") 251 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 252 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 253 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 254 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 255 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 256 { TYPE_X86_CPU, "check", "off" }, 257 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 258 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 259 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 260 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 261 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 262 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 263 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 264 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 265 }; 266 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 267 268 /* 269 * @PC_FW_DATA: 270 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 271 * and other BIOS datastructures. 272 * 273 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 274 * reported to be used at the moment, 32K should be enough for a while. 275 */ 276 #define PC_FW_DATA (0x20000 + 0x8000) 277 278 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 279 { 280 GSIState *s; 281 282 s = g_new0(GSIState, 1); 283 if (kvm_ioapic_in_kernel()) { 284 kvm_pc_setup_irq_routing(pci_enabled); 285 } 286 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 287 288 return s; 289 } 290 291 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 292 unsigned size) 293 { 294 } 295 296 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 297 { 298 return 0xffffffffffffffffULL; 299 } 300 301 /* MS-DOS compatibility mode FPU exception support */ 302 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 303 unsigned size) 304 { 305 if (tcg_enabled()) { 306 cpu_set_ignne(); 307 } 308 } 309 310 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 311 { 312 return 0xffffffffffffffffULL; 313 } 314 315 /* PC cmos mappings */ 316 317 #define REG_EQUIPMENT_BYTE 0x14 318 319 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 320 int16_t cylinders, int8_t heads, int8_t sectors) 321 { 322 mc146818rtc_set_cmos_data(s, type_ofs, 47); 323 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 324 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 325 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 326 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 327 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 328 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 329 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 330 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 331 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 332 } 333 334 /* convert boot_device letter to something recognizable by the bios */ 335 static int boot_device2nibble(char boot_device) 336 { 337 switch(boot_device) { 338 case 'a': 339 case 'b': 340 return 0x01; /* floppy boot */ 341 case 'c': 342 return 0x02; /* hard drive boot */ 343 case 'd': 344 return 0x03; /* CD-ROM boot */ 345 case 'n': 346 return 0x04; /* Network boot */ 347 } 348 return 0; 349 } 350 351 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 352 const char *boot_device, Error **errp) 353 { 354 #define PC_MAX_BOOT_DEVICES 3 355 int nbds, bds[3] = { 0, }; 356 int i; 357 358 nbds = strlen(boot_device); 359 if (nbds > PC_MAX_BOOT_DEVICES) { 360 error_setg(errp, "Too many boot devices for PC"); 361 return; 362 } 363 for (i = 0; i < nbds; i++) { 364 bds[i] = boot_device2nibble(boot_device[i]); 365 if (bds[i] == 0) { 366 error_setg(errp, "Invalid boot device for PC: '%c'", 367 boot_device[i]); 368 return; 369 } 370 } 371 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 372 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 373 } 374 375 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 376 { 377 PCMachineState *pcms = opaque; 378 X86MachineState *x86ms = X86_MACHINE(pcms); 379 380 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 381 } 382 383 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 384 { 385 int val, nb; 386 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 387 FLOPPY_DRIVE_TYPE_NONE }; 388 389 #ifdef CONFIG_FDC_ISA 390 /* floppy type */ 391 if (floppy) { 392 for (int i = 0; i < 2; i++) { 393 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 394 } 395 } 396 #endif 397 398 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 399 cmos_get_fd_drive_type(fd_type[1]); 400 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 401 402 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 403 nb = 0; 404 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 405 nb++; 406 } 407 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 408 nb++; 409 } 410 switch (nb) { 411 case 0: 412 break; 413 case 1: 414 val |= 0x01; /* 1 drive, ready for boot */ 415 break; 416 case 2: 417 val |= 0x41; /* 2 drives, ready for boot */ 418 break; 419 } 420 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 421 } 422 423 typedef struct check_fdc_state { 424 ISADevice *floppy; 425 bool multiple; 426 } CheckFdcState; 427 428 static int check_fdc(Object *obj, void *opaque) 429 { 430 CheckFdcState *state = opaque; 431 Object *fdc; 432 uint32_t iobase; 433 Error *local_err = NULL; 434 435 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 436 if (!fdc) { 437 return 0; 438 } 439 440 iobase = object_property_get_uint(obj, "iobase", &local_err); 441 if (local_err || iobase != 0x3f0) { 442 error_free(local_err); 443 return 0; 444 } 445 446 if (state->floppy) { 447 state->multiple = true; 448 } else { 449 state->floppy = ISA_DEVICE(obj); 450 } 451 return 0; 452 } 453 454 static const char * const fdc_container_path[] = { 455 "/unattached", "/peripheral", "/peripheral-anon" 456 }; 457 458 /* 459 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 460 * and ACPI objects. 461 */ 462 static ISADevice *pc_find_fdc0(void) 463 { 464 int i; 465 Object *container; 466 CheckFdcState state = { 0 }; 467 468 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 469 container = container_get(qdev_get_machine(), fdc_container_path[i]); 470 object_child_foreach(container, check_fdc, &state); 471 } 472 473 if (state.multiple) { 474 warn_report("multiple floppy disk controllers with " 475 "iobase=0x3f0 have been found"); 476 error_printf("the one being picked for CMOS setup might not reflect " 477 "your intent"); 478 } 479 480 return state.floppy; 481 } 482 483 static void pc_cmos_init_late(PCMachineState *pcms) 484 { 485 X86MachineState *x86ms = X86_MACHINE(pcms); 486 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 487 int16_t cylinders; 488 int8_t heads, sectors; 489 int val; 490 int i, trans; 491 492 val = 0; 493 if (pcms->idebus[0] && 494 ide_get_geometry(pcms->idebus[0], 0, 495 &cylinders, &heads, §ors) >= 0) { 496 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 497 val |= 0xf0; 498 } 499 if (pcms->idebus[0] && 500 ide_get_geometry(pcms->idebus[0], 1, 501 &cylinders, &heads, §ors) >= 0) { 502 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 503 val |= 0x0f; 504 } 505 mc146818rtc_set_cmos_data(s, 0x12, val); 506 507 val = 0; 508 for (i = 0; i < 4; i++) { 509 /* NOTE: ide_get_geometry() returns the physical 510 geometry. It is always such that: 1 <= sects <= 63, 1 511 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 512 geometry can be different if a translation is done. */ 513 BusState *idebus = pcms->idebus[i / 2]; 514 if (idebus && 515 ide_get_geometry(idebus, i % 2, 516 &cylinders, &heads, §ors) >= 0) { 517 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 518 assert((trans & ~3) == 0); 519 val |= trans << (i * 2); 520 } 521 } 522 mc146818rtc_set_cmos_data(s, 0x39, val); 523 524 pc_cmos_init_floppy(s, pc_find_fdc0()); 525 526 /* various important CMOS locations needed by PC/Bochs bios */ 527 528 /* memory size */ 529 /* base memory (first MiB) */ 530 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 531 mc146818rtc_set_cmos_data(s, 0x15, val); 532 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 533 /* extended memory (next 64MiB) */ 534 if (x86ms->below_4g_mem_size > 1 * MiB) { 535 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 536 } else { 537 val = 0; 538 } 539 if (val > 65535) 540 val = 65535; 541 mc146818rtc_set_cmos_data(s, 0x17, val); 542 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 543 mc146818rtc_set_cmos_data(s, 0x30, val); 544 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 545 /* memory between 16MiB and 4GiB */ 546 if (x86ms->below_4g_mem_size > 16 * MiB) { 547 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 548 } else { 549 val = 0; 550 } 551 if (val > 65535) 552 val = 65535; 553 mc146818rtc_set_cmos_data(s, 0x34, val); 554 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 555 /* memory above 4GiB */ 556 val = x86ms->above_4g_mem_size / 65536; 557 mc146818rtc_set_cmos_data(s, 0x5b, val); 558 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 559 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 560 561 val = 0; 562 val |= 0x02; /* FPU is there */ 563 val |= 0x04; /* PS/2 mouse installed */ 564 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 565 } 566 567 static void handle_a20_line_change(void *opaque, int irq, int level) 568 { 569 X86CPU *cpu = opaque; 570 571 /* XXX: send to all CPUs ? */ 572 /* XXX: add logic to handle multiple A20 line sources */ 573 x86_cpu_set_a20(cpu, level); 574 } 575 576 #define NE2000_NB_MAX 6 577 578 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 579 0x280, 0x380 }; 580 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 581 582 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 583 { 584 static int nb_ne2k = 0; 585 586 if (nb_ne2k == NE2000_NB_MAX) { 587 error_setg(errp, 588 "maximum number of ISA NE2000 devices exceeded"); 589 return false; 590 } 591 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 592 ne2000_irq[nb_ne2k], nd); 593 nb_ne2k++; 594 return true; 595 } 596 597 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 598 { 599 X86CPU *cpu = opaque; 600 601 if (level) { 602 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 603 } 604 } 605 606 static 607 void pc_machine_done(Notifier *notifier, void *data) 608 { 609 PCMachineState *pcms = container_of(notifier, 610 PCMachineState, machine_done); 611 X86MachineState *x86ms = X86_MACHINE(pcms); 612 613 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 614 &error_fatal); 615 616 if (pcms->cxl_devices_state.is_enabled) { 617 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 618 } 619 620 /* set the number of CPUs */ 621 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 622 623 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 624 625 acpi_setup(); 626 if (x86ms->fw_cfg) { 627 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 628 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 629 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 630 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 631 } 632 633 pc_cmos_init_late(pcms); 634 } 635 636 /* setup pci memory address space mapping into system address space */ 637 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 638 MemoryRegion *pci_address_space) 639 { 640 /* Set to lower priority than RAM */ 641 memory_region_add_subregion_overlap(system_memory, 0x0, 642 pci_address_space, -1); 643 } 644 645 void xen_load_linux(PCMachineState *pcms) 646 { 647 int i; 648 FWCfgState *fw_cfg; 649 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 650 X86MachineState *x86ms = X86_MACHINE(pcms); 651 652 assert(MACHINE(pcms)->kernel_filename != NULL); 653 654 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 655 &address_space_memory); 656 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 657 rom_set_fw(fw_cfg); 658 659 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 660 for (i = 0; i < nb_option_roms; i++) { 661 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 662 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 663 !strcmp(option_rom[i].name, "pvh.bin") || 664 !strcmp(option_rom[i].name, "multiboot.bin") || 665 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 666 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 667 } 668 x86ms->fw_cfg = fw_cfg; 669 } 670 671 #define PC_ROM_MIN_VGA 0xc0000 672 #define PC_ROM_MIN_OPTION 0xc8000 673 #define PC_ROM_MAX 0xe0000 674 #define PC_ROM_ALIGN 0x800 675 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 676 677 static hwaddr pc_above_4g_end(PCMachineState *pcms) 678 { 679 X86MachineState *x86ms = X86_MACHINE(pcms); 680 681 if (pcms->sgx_epc.size != 0) { 682 return sgx_epc_above_4g_end(&pcms->sgx_epc); 683 } 684 685 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 686 } 687 688 static void pc_get_device_memory_range(PCMachineState *pcms, 689 hwaddr *base, 690 ram_addr_t *device_mem_size) 691 { 692 MachineState *machine = MACHINE(pcms); 693 ram_addr_t size; 694 hwaddr addr; 695 696 size = machine->maxram_size - machine->ram_size; 697 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 698 699 /* size device region assuming 1G page max alignment per slot */ 700 size += (1 * GiB) * machine->ram_slots; 701 702 *base = addr; 703 *device_mem_size = size; 704 } 705 706 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 707 { 708 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 709 MachineState *ms = MACHINE(pcms); 710 hwaddr cxl_base; 711 ram_addr_t size; 712 713 if (pcmc->has_reserved_memory && 714 (ms->ram_size < ms->maxram_size)) { 715 pc_get_device_memory_range(pcms, &cxl_base, &size); 716 cxl_base += size; 717 } else { 718 cxl_base = pc_above_4g_end(pcms); 719 } 720 721 return cxl_base; 722 } 723 724 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 725 { 726 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 727 728 if (pcms->cxl_devices_state.fixed_windows) { 729 GList *it; 730 731 start = ROUND_UP(start, 256 * MiB); 732 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 733 CXLFixedWindow *fw = it->data; 734 start += fw->size; 735 } 736 } 737 738 return start; 739 } 740 741 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 742 { 743 X86CPU *cpu = X86_CPU(first_cpu); 744 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 745 MachineState *ms = MACHINE(pcms); 746 747 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 748 /* 64-bit systems */ 749 return pc_pci_hole64_start() + pci_hole64_size - 1; 750 } 751 752 /* 32-bit systems */ 753 if (pcmc->broken_32bit_mem_addr_check) { 754 /* old value for compatibility reasons */ 755 return ((hwaddr)1 << cpu->phys_bits) - 1; 756 } 757 758 /* 759 * 32-bit systems don't have hole64 but they might have a region for 760 * memory devices. Even if additional hotplugged memory devices might 761 * not be usable by most guest OSes, we need to still consider them for 762 * calculating the highest possible GPA so that we can properly report 763 * if someone configures them on a CPU that cannot possibly address them. 764 */ 765 if (pcmc->has_reserved_memory && 766 (ms->ram_size < ms->maxram_size)) { 767 hwaddr devmem_start; 768 ram_addr_t devmem_size; 769 770 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 771 devmem_start += devmem_size; 772 return devmem_start - 1; 773 } 774 775 /* configuration without any memory hotplug */ 776 return pc_above_4g_end(pcms) - 1; 777 } 778 779 /* 780 * AMD systems with an IOMMU have an additional hole close to the 781 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 782 * on kernel version, VFIO may or may not let you DMA map those ranges. 783 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 784 * with certain memory sizes. It's also wrong to use those IOVA ranges 785 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 786 * The ranges reserved for Hyper-Transport are: 787 * 788 * FD_0000_0000h - FF_FFFF_FFFFh 789 * 790 * The ranges represent the following: 791 * 792 * Base Address Top Address Use 793 * 794 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 795 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 796 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 797 * FD_F910_0000h FD_F91F_FFFFh System Management 798 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 799 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 800 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 801 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 802 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 803 * FE_2000_0000h FF_FFFF_FFFFh Reserved 804 * 805 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 806 * Table 3: Special Address Controls (GPA) for more information. 807 */ 808 #define AMD_HT_START 0xfd00000000UL 809 #define AMD_HT_END 0xffffffffffUL 810 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 811 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 812 813 void pc_memory_init(PCMachineState *pcms, 814 MemoryRegion *system_memory, 815 MemoryRegion *rom_memory, 816 uint64_t pci_hole64_size) 817 { 818 int linux_boot, i; 819 MemoryRegion *option_rom_mr; 820 MemoryRegion *ram_below_4g, *ram_above_4g; 821 FWCfgState *fw_cfg; 822 MachineState *machine = MACHINE(pcms); 823 MachineClass *mc = MACHINE_GET_CLASS(machine); 824 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 825 X86MachineState *x86ms = X86_MACHINE(pcms); 826 hwaddr maxphysaddr, maxusedaddr; 827 hwaddr cxl_base, cxl_resv_end = 0; 828 X86CPU *cpu = X86_CPU(first_cpu); 829 830 assert(machine->ram_size == x86ms->below_4g_mem_size + 831 x86ms->above_4g_mem_size); 832 833 linux_boot = (machine->kernel_filename != NULL); 834 835 /* 836 * The HyperTransport range close to the 1T boundary is unique to AMD 837 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 838 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 839 * older machine types (<= 7.0) for compatibility purposes. 840 */ 841 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 842 /* Bail out if max possible address does not cross HT range */ 843 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 844 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 845 } 846 847 /* 848 * Advertise the HT region if address space covers the reserved 849 * region or if we relocate. 850 */ 851 if (cpu->phys_bits >= 40) { 852 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 853 } 854 } 855 856 /* 857 * phys-bits is required to be appropriately configured 858 * to make sure max used GPA is reachable. 859 */ 860 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 861 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 862 if (maxphysaddr < maxusedaddr) { 863 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 864 " phys-bits too low (%u)", 865 maxphysaddr, maxusedaddr, cpu->phys_bits); 866 exit(EXIT_FAILURE); 867 } 868 869 /* 870 * Split single memory region and use aliases to address portions of it, 871 * done for backwards compatibility with older qemus. 872 */ 873 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 874 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 875 0, x86ms->below_4g_mem_size); 876 memory_region_add_subregion(system_memory, 0, ram_below_4g); 877 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 878 if (x86ms->above_4g_mem_size > 0) { 879 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 880 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 881 machine->ram, 882 x86ms->below_4g_mem_size, 883 x86ms->above_4g_mem_size); 884 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 885 ram_above_4g); 886 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 887 E820_RAM); 888 } 889 890 if (pcms->sgx_epc.size != 0) { 891 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 892 } 893 894 if (!pcmc->has_reserved_memory && 895 (machine->ram_slots || 896 (machine->maxram_size > machine->ram_size))) { 897 898 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 899 mc->name); 900 exit(EXIT_FAILURE); 901 } 902 903 /* initialize device memory address space */ 904 if (pcmc->has_reserved_memory && 905 (machine->ram_size < machine->maxram_size)) { 906 ram_addr_t device_mem_size; 907 hwaddr device_mem_base; 908 909 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 910 error_report("unsupported amount of memory slots: %"PRIu64, 911 machine->ram_slots); 912 exit(EXIT_FAILURE); 913 } 914 915 if (QEMU_ALIGN_UP(machine->maxram_size, 916 TARGET_PAGE_SIZE) != machine->maxram_size) { 917 error_report("maximum memory size must by aligned to multiple of " 918 "%d bytes", TARGET_PAGE_SIZE); 919 exit(EXIT_FAILURE); 920 } 921 922 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 923 924 if (device_mem_base + device_mem_size < device_mem_size) { 925 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 926 machine->maxram_size); 927 exit(EXIT_FAILURE); 928 } 929 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 930 } 931 932 if (pcms->cxl_devices_state.is_enabled) { 933 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 934 hwaddr cxl_size = MiB; 935 936 cxl_base = pc_get_cxl_range_start(pcms); 937 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 938 memory_region_add_subregion(system_memory, cxl_base, mr); 939 cxl_resv_end = cxl_base + cxl_size; 940 if (pcms->cxl_devices_state.fixed_windows) { 941 hwaddr cxl_fmw_base; 942 GList *it; 943 944 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 945 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 946 CXLFixedWindow *fw = it->data; 947 948 fw->base = cxl_fmw_base; 949 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 950 "cxl-fixed-memory-region", fw->size); 951 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 952 cxl_fmw_base += fw->size; 953 cxl_resv_end = cxl_fmw_base; 954 } 955 } 956 } 957 958 /* Initialize PC system firmware */ 959 pc_system_firmware_init(pcms, rom_memory); 960 961 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 962 if (machine_require_guest_memfd(machine)) { 963 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 964 PC_ROM_SIZE, &error_fatal); 965 } else { 966 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 967 &error_fatal); 968 if (pcmc->pci_enabled) { 969 memory_region_set_readonly(option_rom_mr, true); 970 } 971 } 972 memory_region_add_subregion_overlap(rom_memory, 973 PC_ROM_MIN_VGA, 974 option_rom_mr, 975 1); 976 977 fw_cfg = fw_cfg_arch_create(machine, 978 x86ms->boot_cpus, x86ms->apic_id_limit); 979 980 rom_set_fw(fw_cfg); 981 982 if (machine->device_memory) { 983 uint64_t *val = g_malloc(sizeof(*val)); 984 uint64_t res_mem_end = machine->device_memory->base; 985 986 if (!pcmc->broken_reserved_end) { 987 res_mem_end += memory_region_size(&machine->device_memory->mr); 988 } 989 990 if (pcms->cxl_devices_state.is_enabled) { 991 res_mem_end = cxl_resv_end; 992 } 993 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 994 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 995 } 996 997 if (linux_boot) { 998 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 999 } 1000 1001 for (i = 0; i < nb_option_roms; i++) { 1002 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1003 } 1004 x86ms->fw_cfg = fw_cfg; 1005 1006 /* Init default IOAPIC address space */ 1007 x86ms->ioapic_as = &address_space_memory; 1008 1009 /* Init ACPI memory hotplug IO base address */ 1010 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1011 } 1012 1013 /* 1014 * The 64bit pci hole starts after "above 4G RAM" and 1015 * potentially the space reserved for memory hotplug. 1016 */ 1017 uint64_t pc_pci_hole64_start(void) 1018 { 1019 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1020 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1021 MachineState *ms = MACHINE(pcms); 1022 uint64_t hole64_start = 0; 1023 ram_addr_t size = 0; 1024 1025 if (pcms->cxl_devices_state.is_enabled) { 1026 hole64_start = pc_get_cxl_range_end(pcms); 1027 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1028 pc_get_device_memory_range(pcms, &hole64_start, &size); 1029 if (!pcmc->broken_reserved_end) { 1030 hole64_start += size; 1031 } 1032 } else { 1033 hole64_start = pc_above_4g_end(pcms); 1034 } 1035 1036 return ROUND_UP(hole64_start, 1 * GiB); 1037 } 1038 1039 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1040 { 1041 DeviceState *dev = NULL; 1042 1043 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1044 if (pci_bus) { 1045 PCIDevice *pcidev = pci_vga_init(pci_bus); 1046 dev = pcidev ? &pcidev->qdev : NULL; 1047 } else if (isa_bus) { 1048 ISADevice *isadev = isa_vga_init(isa_bus); 1049 dev = isadev ? DEVICE(isadev) : NULL; 1050 } 1051 rom_reset_order_override(); 1052 return dev; 1053 } 1054 1055 static const MemoryRegionOps ioport80_io_ops = { 1056 .write = ioport80_write, 1057 .read = ioport80_read, 1058 .endianness = DEVICE_NATIVE_ENDIAN, 1059 .impl = { 1060 .min_access_size = 1, 1061 .max_access_size = 1, 1062 }, 1063 }; 1064 1065 static const MemoryRegionOps ioportF0_io_ops = { 1066 .write = ioportF0_write, 1067 .read = ioportF0_read, 1068 .endianness = DEVICE_NATIVE_ENDIAN, 1069 .impl = { 1070 .min_access_size = 1, 1071 .max_access_size = 1, 1072 }, 1073 }; 1074 1075 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1076 bool create_i8042, bool no_vmport) 1077 { 1078 int i; 1079 DriveInfo *fd[MAX_FD]; 1080 qemu_irq *a20_line; 1081 ISADevice *i8042, *port92, *vmmouse; 1082 1083 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1084 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1085 1086 for (i = 0; i < MAX_FD; i++) { 1087 fd[i] = drive_get(IF_FLOPPY, 0, i); 1088 create_fdctrl |= !!fd[i]; 1089 } 1090 if (create_fdctrl) { 1091 #ifdef CONFIG_FDC_ISA 1092 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1093 if (fdc) { 1094 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1095 isa_fdc_init_drives(fdc, fd); 1096 } 1097 #endif 1098 } 1099 1100 if (!create_i8042) { 1101 return; 1102 } 1103 1104 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1105 if (!no_vmport) { 1106 isa_create_simple(isa_bus, TYPE_VMPORT); 1107 vmmouse = isa_try_new("vmmouse"); 1108 } else { 1109 vmmouse = NULL; 1110 } 1111 if (vmmouse) { 1112 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1113 &error_abort); 1114 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1115 } 1116 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1117 1118 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1119 qdev_connect_gpio_out_named(DEVICE(i8042), 1120 I8042_A20_LINE, 0, a20_line[0]); 1121 qdev_connect_gpio_out_named(DEVICE(port92), 1122 PORT92_A20_LINE, 0, a20_line[1]); 1123 g_free(a20_line); 1124 } 1125 1126 void pc_basic_device_init(struct PCMachineState *pcms, 1127 ISABus *isa_bus, qemu_irq *gsi, 1128 ISADevice *rtc_state, 1129 bool create_fdctrl, 1130 uint32_t hpet_irqs) 1131 { 1132 int i; 1133 DeviceState *hpet = NULL; 1134 int pit_isa_irq = 0; 1135 qemu_irq pit_alt_irq = NULL; 1136 ISADevice *pit = NULL; 1137 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1138 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1139 X86MachineState *x86ms = X86_MACHINE(pcms); 1140 1141 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1142 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1143 1144 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1145 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1146 1147 /* 1148 * Check if an HPET shall be created. 1149 */ 1150 if (pcms->hpet_enabled) { 1151 qemu_irq rtc_irq; 1152 1153 hpet = qdev_try_new(TYPE_HPET); 1154 if (!hpet) { 1155 error_report("couldn't create HPET device"); 1156 exit(1); 1157 } 1158 /* 1159 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1160 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1161 * the property, use whatever mask they specified. 1162 */ 1163 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1164 HPET_INTCAP, NULL); 1165 if (!compat) { 1166 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1167 } 1168 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1169 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1170 1171 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1172 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1173 } 1174 pit_isa_irq = -1; 1175 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1176 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1177 1178 /* overwrite connection created by south bridge */ 1179 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1180 } 1181 1182 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1183 "date"); 1184 1185 #ifdef CONFIG_XEN_EMU 1186 if (xen_mode == XEN_EMULATE) { 1187 xen_overlay_create(); 1188 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1189 xen_gnttab_create(); 1190 xen_xenstore_create(); 1191 if (pcms->pcibus) { 1192 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1193 } 1194 xen_bus_init(); 1195 } 1196 #endif 1197 1198 qemu_register_boot_set(pc_boot_set, pcms); 1199 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1200 MACHINE(pcms)->boot_config.order, &error_fatal); 1201 1202 if (!xen_enabled() && 1203 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1204 if (kvm_pit_in_kernel()) { 1205 pit = kvm_pit_init(isa_bus, 0x40); 1206 } else { 1207 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1208 } 1209 if (hpet) { 1210 /* connect PIT to output control line of the HPET */ 1211 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1212 } 1213 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1214 OBJECT(pit), &error_fatal); 1215 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1216 } 1217 1218 /* Super I/O */ 1219 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1220 pcms->vmport != ON_OFF_AUTO_ON); 1221 } 1222 1223 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1224 { 1225 MachineClass *mc = MACHINE_CLASS(pcmc); 1226 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1227 NICInfo *nd; 1228 1229 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1230 1231 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1232 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1233 } 1234 1235 /* Anything remaining should be a PCI NIC */ 1236 pci_init_nic_devices(pci_bus, mc->default_nic); 1237 1238 rom_reset_order_override(); 1239 } 1240 1241 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1242 { 1243 qemu_irq *i8259; 1244 1245 if (kvm_pic_in_kernel()) { 1246 i8259 = kvm_i8259_init(isa_bus); 1247 } else if (xen_enabled()) { 1248 i8259 = xen_interrupt_controller_init(); 1249 } else { 1250 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1251 } 1252 1253 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1254 i8259_irqs[i] = i8259[i]; 1255 } 1256 1257 g_free(i8259); 1258 } 1259 1260 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1261 Error **errp) 1262 { 1263 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1264 const MachineState *ms = MACHINE(hotplug_dev); 1265 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1266 Error *local_err = NULL; 1267 1268 /* 1269 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1270 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1271 * addition to cover this case. 1272 */ 1273 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1274 error_setg(errp, 1275 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1276 return; 1277 } 1278 1279 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1280 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1281 return; 1282 } 1283 1284 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1285 if (local_err) { 1286 error_propagate(errp, local_err); 1287 return; 1288 } 1289 1290 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1291 } 1292 1293 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1294 DeviceState *dev, Error **errp) 1295 { 1296 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1297 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1298 MachineState *ms = MACHINE(hotplug_dev); 1299 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1300 1301 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1302 1303 if (is_nvdimm) { 1304 nvdimm_plug(ms->nvdimms_state); 1305 } 1306 1307 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1308 } 1309 1310 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1311 DeviceState *dev, Error **errp) 1312 { 1313 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1314 1315 /* 1316 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1317 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1318 * addition to cover this case. 1319 */ 1320 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1321 error_setg(errp, 1322 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1323 return; 1324 } 1325 1326 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1327 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1328 return; 1329 } 1330 1331 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1332 errp); 1333 } 1334 1335 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1336 DeviceState *dev, Error **errp) 1337 { 1338 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1339 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1340 Error *local_err = NULL; 1341 1342 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1343 if (local_err) { 1344 goto out; 1345 } 1346 1347 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1348 qdev_unrealize(dev); 1349 out: 1350 error_propagate(errp, local_err); 1351 } 1352 1353 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1354 DeviceState *dev, Error **errp) 1355 { 1356 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1357 g_assert(!dev->hotplugged); 1358 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1359 } 1360 1361 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1362 DeviceState *dev, Error **errp) 1363 { 1364 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1365 } 1366 1367 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1371 pc_memory_pre_plug(hotplug_dev, dev, errp); 1372 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1373 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1374 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1375 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1376 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1377 /* Declare the APIC range as the reserved MSI region */ 1378 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1379 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1380 QList *reserved_regions = qlist_new(); 1381 1382 qlist_append_str(reserved_regions, resv_prop_str); 1383 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1384 1385 g_free(resv_prop_str); 1386 } 1387 1388 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1389 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1390 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1391 1392 if (pcms->iommu) { 1393 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1394 "for x86 yet."); 1395 return; 1396 } 1397 pcms->iommu = dev; 1398 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1399 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1400 } 1401 } 1402 1403 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1404 DeviceState *dev, Error **errp) 1405 { 1406 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1407 pc_memory_plug(hotplug_dev, dev, errp); 1408 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1409 x86_cpu_plug(hotplug_dev, dev, errp); 1410 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1411 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1413 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1414 } 1415 } 1416 1417 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1418 DeviceState *dev, Error **errp) 1419 { 1420 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1421 pc_memory_unplug_request(hotplug_dev, dev, errp); 1422 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1423 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1424 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1425 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1426 errp); 1427 } else { 1428 error_setg(errp, "acpi: device unplug request for not supported device" 1429 " type: %s", object_get_typename(OBJECT(dev))); 1430 } 1431 } 1432 1433 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1434 DeviceState *dev, Error **errp) 1435 { 1436 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1437 pc_memory_unplug(hotplug_dev, dev, errp); 1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1439 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1440 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1441 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1442 } else { 1443 error_setg(errp, "acpi: device unplug for not supported device" 1444 " type: %s", object_get_typename(OBJECT(dev))); 1445 } 1446 } 1447 1448 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1449 DeviceState *dev) 1450 { 1451 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1452 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1453 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1454 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1455 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1456 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1457 return HOTPLUG_HANDLER(machine); 1458 } 1459 1460 return NULL; 1461 } 1462 1463 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1464 void *opaque, Error **errp) 1465 { 1466 PCMachineState *pcms = PC_MACHINE(obj); 1467 OnOffAuto vmport = pcms->vmport; 1468 1469 visit_type_OnOffAuto(v, name, &vmport, errp); 1470 } 1471 1472 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1473 void *opaque, Error **errp) 1474 { 1475 PCMachineState *pcms = PC_MACHINE(obj); 1476 1477 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1478 } 1479 1480 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1481 { 1482 PCMachineState *pcms = PC_MACHINE(obj); 1483 1484 return pcms->fd_bootchk; 1485 } 1486 1487 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1488 { 1489 PCMachineState *pcms = PC_MACHINE(obj); 1490 1491 pcms->fd_bootchk = value; 1492 } 1493 1494 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1495 { 1496 PCMachineState *pcms = PC_MACHINE(obj); 1497 1498 return pcms->smbus_enabled; 1499 } 1500 1501 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1502 { 1503 PCMachineState *pcms = PC_MACHINE(obj); 1504 1505 pcms->smbus_enabled = value; 1506 } 1507 1508 static bool pc_machine_get_sata(Object *obj, Error **errp) 1509 { 1510 PCMachineState *pcms = PC_MACHINE(obj); 1511 1512 return pcms->sata_enabled; 1513 } 1514 1515 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 pcms->sata_enabled = value; 1520 } 1521 1522 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 1526 return pcms->hpet_enabled; 1527 } 1528 1529 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1530 { 1531 PCMachineState *pcms = PC_MACHINE(obj); 1532 1533 pcms->hpet_enabled = value; 1534 } 1535 1536 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 1540 return pcms->i8042_enabled; 1541 } 1542 1543 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1544 { 1545 PCMachineState *pcms = PC_MACHINE(obj); 1546 1547 pcms->i8042_enabled = value; 1548 } 1549 1550 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1551 { 1552 PCMachineState *pcms = PC_MACHINE(obj); 1553 1554 return pcms->default_bus_bypass_iommu; 1555 } 1556 1557 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1558 Error **errp) 1559 { 1560 PCMachineState *pcms = PC_MACHINE(obj); 1561 1562 pcms->default_bus_bypass_iommu = value; 1563 } 1564 1565 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1566 void *opaque, Error **errp) 1567 { 1568 PCMachineState *pcms = PC_MACHINE(obj); 1569 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1570 1571 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1572 } 1573 1574 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1575 void *opaque, Error **errp) 1576 { 1577 PCMachineState *pcms = PC_MACHINE(obj); 1578 1579 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1580 } 1581 1582 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1583 const char *name, void *opaque, 1584 Error **errp) 1585 { 1586 PCMachineState *pcms = PC_MACHINE(obj); 1587 uint64_t value = pcms->max_ram_below_4g; 1588 1589 visit_type_size(v, name, &value, errp); 1590 } 1591 1592 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1593 const char *name, void *opaque, 1594 Error **errp) 1595 { 1596 PCMachineState *pcms = PC_MACHINE(obj); 1597 uint64_t value; 1598 1599 if (!visit_type_size(v, name, &value, errp)) { 1600 return; 1601 } 1602 if (value > 4 * GiB) { 1603 error_setg(errp, 1604 "Machine option 'max-ram-below-4g=%"PRIu64 1605 "' expects size less than or equal to 4G", value); 1606 return; 1607 } 1608 1609 if (value < 1 * MiB) { 1610 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1611 "BIOS may not work with less than 1MiB", value); 1612 } 1613 1614 pcms->max_ram_below_4g = value; 1615 } 1616 1617 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1618 const char *name, void *opaque, 1619 Error **errp) 1620 { 1621 PCMachineState *pcms = PC_MACHINE(obj); 1622 uint64_t value = pcms->max_fw_size; 1623 1624 visit_type_size(v, name, &value, errp); 1625 } 1626 1627 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1628 const char *name, void *opaque, 1629 Error **errp) 1630 { 1631 PCMachineState *pcms = PC_MACHINE(obj); 1632 uint64_t value; 1633 1634 if (!visit_type_size(v, name, &value, errp)) { 1635 return; 1636 } 1637 1638 /* 1639 * We don't have a theoretically justifiable exact lower bound on the base 1640 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1641 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1642 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1643 * 16MiB in size. 1644 */ 1645 if (value > 16 * MiB) { 1646 error_setg(errp, 1647 "User specified max allowed firmware size %" PRIu64 " is " 1648 "greater than 16MiB. If combined firmware size exceeds " 1649 "16MiB the system may not boot, or experience intermittent" 1650 "stability issues.", 1651 value); 1652 return; 1653 } 1654 1655 pcms->max_fw_size = value; 1656 } 1657 1658 1659 static void pc_machine_initfn(Object *obj) 1660 { 1661 PCMachineState *pcms = PC_MACHINE(obj); 1662 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1663 1664 #ifdef CONFIG_VMPORT 1665 pcms->vmport = ON_OFF_AUTO_AUTO; 1666 #else 1667 pcms->vmport = ON_OFF_AUTO_OFF; 1668 #endif /* CONFIG_VMPORT */ 1669 pcms->max_ram_below_4g = 0; /* use default */ 1670 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1671 pcms->south_bridge = pcmc->default_south_bridge; 1672 1673 /* acpi build is enabled by default if machine supports it */ 1674 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1675 pcms->smbus_enabled = true; 1676 pcms->sata_enabled = true; 1677 pcms->i8042_enabled = true; 1678 pcms->max_fw_size = 8 * MiB; 1679 #ifdef CONFIG_HPET 1680 pcms->hpet_enabled = true; 1681 #endif 1682 pcms->fd_bootchk = true; 1683 pcms->default_bus_bypass_iommu = false; 1684 1685 pc_system_flash_create(pcms); 1686 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1687 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1688 OBJECT(pcms->pcspk), "audiodev"); 1689 if (pcmc->pci_enabled) { 1690 cxl_machine_init(obj, &pcms->cxl_devices_state); 1691 } 1692 1693 pcms->machine_done.notify = pc_machine_done; 1694 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1695 } 1696 1697 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1698 { 1699 CPUState *cs; 1700 X86CPU *cpu; 1701 1702 qemu_devices_reset(reason); 1703 1704 /* Reset APIC after devices have been reset to cancel 1705 * any changes that qemu_devices_reset() might have done. 1706 */ 1707 CPU_FOREACH(cs) { 1708 cpu = X86_CPU(cs); 1709 1710 x86_cpu_after_reset(cpu); 1711 } 1712 } 1713 1714 static void pc_machine_wakeup(MachineState *machine) 1715 { 1716 cpu_synchronize_all_states(); 1717 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1718 cpu_synchronize_all_post_reset(); 1719 } 1720 1721 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1722 { 1723 X86IOMMUState *iommu = x86_iommu_get_default(); 1724 IntelIOMMUState *intel_iommu; 1725 1726 if (iommu && 1727 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1728 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1729 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1730 if (!intel_iommu->caching_mode) { 1731 error_setg(errp, "Device assignment is not allowed without " 1732 "enabling caching-mode=on for Intel IOMMU."); 1733 return false; 1734 } 1735 } 1736 1737 return true; 1738 } 1739 1740 static void pc_machine_class_init(ObjectClass *oc, void *data) 1741 { 1742 MachineClass *mc = MACHINE_CLASS(oc); 1743 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1744 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1745 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1746 1747 pcmc->pci_enabled = true; 1748 pcmc->has_acpi_build = true; 1749 pcmc->smbios_defaults = true; 1750 pcmc->gigabyte_align = true; 1751 pcmc->has_reserved_memory = true; 1752 pcmc->enforce_amd_1tb_hole = true; 1753 pcmc->isa_bios_alias = true; 1754 pcmc->pvh_enabled = true; 1755 pcmc->kvmclock_create_always = true; 1756 x86mc->apic_xrupt_override = true; 1757 assert(!mc->get_hotplug_handler); 1758 mc->get_hotplug_handler = pc_get_hotplug_handler; 1759 mc->hotplug_allowed = pc_hotplug_allowed; 1760 mc->auto_enable_numa_with_memhp = true; 1761 mc->auto_enable_numa_with_memdev = true; 1762 mc->has_hotpluggable_cpus = true; 1763 mc->default_boot_order = "cad"; 1764 mc->block_default_type = IF_IDE; 1765 mc->max_cpus = 255; 1766 mc->reset = pc_machine_reset; 1767 mc->wakeup = pc_machine_wakeup; 1768 hc->pre_plug = pc_machine_device_pre_plug_cb; 1769 hc->plug = pc_machine_device_plug_cb; 1770 hc->unplug_request = pc_machine_device_unplug_request_cb; 1771 hc->unplug = pc_machine_device_unplug_cb; 1772 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1773 mc->nvdimm_supported = true; 1774 mc->smp_props.dies_supported = true; 1775 mc->smp_props.modules_supported = true; 1776 mc->default_ram_id = "pc.ram"; 1777 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1778 1779 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1780 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1781 NULL, NULL); 1782 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1783 "Maximum ram below the 4G boundary (32bit boundary)"); 1784 1785 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1786 pc_machine_get_vmport, pc_machine_set_vmport, 1787 NULL, NULL); 1788 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1789 "Enable vmport (pc & q35)"); 1790 1791 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1792 pc_machine_get_smbus, pc_machine_set_smbus); 1793 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1794 "Enable/disable system management bus"); 1795 1796 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1797 pc_machine_get_sata, pc_machine_set_sata); 1798 object_class_property_set_description(oc, PC_MACHINE_SATA, 1799 "Enable/disable Serial ATA bus"); 1800 1801 object_class_property_add_bool(oc, "hpet", 1802 pc_machine_get_hpet, pc_machine_set_hpet); 1803 object_class_property_set_description(oc, "hpet", 1804 "Enable/disable high precision event timer emulation"); 1805 1806 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1807 pc_machine_get_i8042, pc_machine_set_i8042); 1808 1809 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1810 pc_machine_get_default_bus_bypass_iommu, 1811 pc_machine_set_default_bus_bypass_iommu); 1812 1813 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1814 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1815 NULL, NULL); 1816 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1817 "Maximum combined firmware size"); 1818 1819 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1820 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1821 NULL, NULL); 1822 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1823 "SMBIOS Entry Point type [32, 64]"); 1824 1825 object_class_property_add_bool(oc, "fd-bootchk", 1826 pc_machine_get_fd_bootchk, 1827 pc_machine_set_fd_bootchk); 1828 } 1829 1830 static const TypeInfo pc_machine_info = { 1831 .name = TYPE_PC_MACHINE, 1832 .parent = TYPE_X86_MACHINE, 1833 .abstract = true, 1834 .instance_size = sizeof(PCMachineState), 1835 .instance_init = pc_machine_initfn, 1836 .class_size = sizeof(PCMachineClass), 1837 .class_init = pc_machine_class_init, 1838 .interfaces = (InterfaceInfo[]) { 1839 { TYPE_HOTPLUG_HANDLER }, 1840 { } 1841 }, 1842 }; 1843 1844 static void pc_machine_register_types(void) 1845 { 1846 type_register_static(&pc_machine_info); 1847 } 1848 1849 type_init(pc_machine_register_types) 1850