1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/smbios/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/boards.h" 63 #include "hw/pci/pci_host.h" 64 #include "acpi-build.h" 65 #include "hw/mem/pc-dimm.h" 66 #include "qapi/visitor.h" 67 #include "qapi-visit.h" 68 #include "qom/cpu.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 81 * (128K) and other BIOS datastructures (less than 4K reported to be used at 82 * the moment, 32K should be enough for a while). */ 83 static unsigned acpi_data_size = 0x20000 + 0x8000; 84 void pc_set_legacy_acpi_data_size(void) 85 { 86 acpi_data_size = 0x10000; 87 } 88 89 #define BIOS_CFG_IOPORT 0x510 90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 95 96 #define E820_NR_ENTRIES 16 97 98 struct e820_entry { 99 uint64_t address; 100 uint64_t length; 101 uint32_t type; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 struct e820_table { 105 uint32_t count; 106 struct e820_entry entry[E820_NR_ENTRIES]; 107 } QEMU_PACKED __attribute((__aligned__(4))); 108 109 static struct e820_table e820_reserve; 110 static struct e820_entry *e820_table; 111 static unsigned e820_entries; 112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 113 114 void gsi_handler(void *opaque, int n, int level) 115 { 116 GSIState *s = opaque; 117 118 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 119 if (n < ISA_NUM_IRQS) { 120 qemu_set_irq(s->i8259_irq[n], level); 121 } 122 qemu_set_irq(s->ioapic_irq[n], level); 123 } 124 125 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 126 unsigned size) 127 { 128 } 129 130 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 131 { 132 return 0xffffffffffffffffULL; 133 } 134 135 /* MSDOS compatibility mode FPU exception support */ 136 static qemu_irq ferr_irq; 137 138 void pc_register_ferr_irq(qemu_irq irq) 139 { 140 ferr_irq = irq; 141 } 142 143 /* XXX: add IGNNE support */ 144 void cpu_set_ferr(CPUX86State *s) 145 { 146 qemu_irq_raise(ferr_irq); 147 } 148 149 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 150 unsigned size) 151 { 152 qemu_irq_lower(ferr_irq); 153 } 154 155 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 156 { 157 return 0xffffffffffffffffULL; 158 } 159 160 /* TSC handling */ 161 uint64_t cpu_get_tsc(CPUX86State *env) 162 { 163 return cpu_get_ticks(); 164 } 165 166 /* IRQ handling */ 167 int cpu_get_pic_interrupt(CPUX86State *env) 168 { 169 X86CPU *cpu = x86_env_get_cpu(env); 170 int intno; 171 172 intno = apic_get_interrupt(cpu->apic_state); 173 if (intno >= 0) { 174 return intno; 175 } 176 /* read the irq from the PIC */ 177 if (!apic_accept_pic_intr(cpu->apic_state)) { 178 return -1; 179 } 180 181 intno = pic_read_irq(isa_pic); 182 return intno; 183 } 184 185 static void pic_irq_request(void *opaque, int irq, int level) 186 { 187 CPUState *cs = first_cpu; 188 X86CPU *cpu = X86_CPU(cs); 189 190 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 191 if (cpu->apic_state) { 192 CPU_FOREACH(cs) { 193 cpu = X86_CPU(cs); 194 if (apic_accept_pic_intr(cpu->apic_state)) { 195 apic_deliver_pic_intr(cpu->apic_state, level); 196 } 197 } 198 } else { 199 if (level) { 200 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 201 } else { 202 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 203 } 204 } 205 } 206 207 /* PC cmos mappings */ 208 209 #define REG_EQUIPMENT_BYTE 0x14 210 211 static int cmos_get_fd_drive_type(FDriveType fd0) 212 { 213 int val; 214 215 switch (fd0) { 216 case FDRIVE_DRV_144: 217 /* 1.44 Mb 3"5 drive */ 218 val = 4; 219 break; 220 case FDRIVE_DRV_288: 221 /* 2.88 Mb 3"5 drive */ 222 val = 5; 223 break; 224 case FDRIVE_DRV_120: 225 /* 1.2 Mb 5"5 drive */ 226 val = 2; 227 break; 228 case FDRIVE_DRV_NONE: 229 default: 230 val = 0; 231 break; 232 } 233 return val; 234 } 235 236 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 237 int16_t cylinders, int8_t heads, int8_t sectors) 238 { 239 rtc_set_memory(s, type_ofs, 47); 240 rtc_set_memory(s, info_ofs, cylinders); 241 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 242 rtc_set_memory(s, info_ofs + 2, heads); 243 rtc_set_memory(s, info_ofs + 3, 0xff); 244 rtc_set_memory(s, info_ofs + 4, 0xff); 245 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 246 rtc_set_memory(s, info_ofs + 6, cylinders); 247 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 248 rtc_set_memory(s, info_ofs + 8, sectors); 249 } 250 251 /* convert boot_device letter to something recognizable by the bios */ 252 static int boot_device2nibble(char boot_device) 253 { 254 switch(boot_device) { 255 case 'a': 256 case 'b': 257 return 0x01; /* floppy boot */ 258 case 'c': 259 return 0x02; /* hard drive boot */ 260 case 'd': 261 return 0x03; /* CD-ROM boot */ 262 case 'n': 263 return 0x04; /* Network boot */ 264 } 265 return 0; 266 } 267 268 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 269 { 270 #define PC_MAX_BOOT_DEVICES 3 271 int nbds, bds[3] = { 0, }; 272 int i; 273 274 nbds = strlen(boot_device); 275 if (nbds > PC_MAX_BOOT_DEVICES) { 276 error_setg(errp, "Too many boot devices for PC"); 277 return; 278 } 279 for (i = 0; i < nbds; i++) { 280 bds[i] = boot_device2nibble(boot_device[i]); 281 if (bds[i] == 0) { 282 error_setg(errp, "Invalid boot device for PC: '%c'", 283 boot_device[i]); 284 return; 285 } 286 } 287 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 288 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 289 } 290 291 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 292 { 293 set_boot_dev(opaque, boot_device, errp); 294 } 295 296 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 297 { 298 int val, nb, i; 299 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 300 301 /* floppy type */ 302 if (floppy) { 303 for (i = 0; i < 2; i++) { 304 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 305 } 306 } 307 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 308 cmos_get_fd_drive_type(fd_type[1]); 309 rtc_set_memory(rtc_state, 0x10, val); 310 311 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 312 nb = 0; 313 if (fd_type[0] < FDRIVE_DRV_NONE) { 314 nb++; 315 } 316 if (fd_type[1] < FDRIVE_DRV_NONE) { 317 nb++; 318 } 319 switch (nb) { 320 case 0: 321 break; 322 case 1: 323 val |= 0x01; /* 1 drive, ready for boot */ 324 break; 325 case 2: 326 val |= 0x41; /* 2 drives, ready for boot */ 327 break; 328 } 329 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 330 } 331 332 typedef struct pc_cmos_init_late_arg { 333 ISADevice *rtc_state; 334 BusState *idebus[2]; 335 } pc_cmos_init_late_arg; 336 337 typedef struct check_fdc_state { 338 ISADevice *floppy; 339 bool multiple; 340 } CheckFdcState; 341 342 static int check_fdc(Object *obj, void *opaque) 343 { 344 CheckFdcState *state = opaque; 345 Object *fdc; 346 uint32_t iobase; 347 Error *local_err = NULL; 348 349 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 350 if (!fdc) { 351 return 0; 352 } 353 354 iobase = object_property_get_int(obj, "iobase", &local_err); 355 if (local_err || iobase != 0x3f0) { 356 error_free(local_err); 357 return 0; 358 } 359 360 if (state->floppy) { 361 state->multiple = true; 362 } else { 363 state->floppy = ISA_DEVICE(obj); 364 } 365 return 0; 366 } 367 368 static const char * const fdc_container_path[] = { 369 "/unattached", "/peripheral", "/peripheral-anon" 370 }; 371 372 static void pc_cmos_init_late(void *opaque) 373 { 374 pc_cmos_init_late_arg *arg = opaque; 375 ISADevice *s = arg->rtc_state; 376 int16_t cylinders; 377 int8_t heads, sectors; 378 int val; 379 int i, trans; 380 Object *container; 381 CheckFdcState state = { 0 }; 382 383 val = 0; 384 if (ide_get_geometry(arg->idebus[0], 0, 385 &cylinders, &heads, §ors) >= 0) { 386 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 387 val |= 0xf0; 388 } 389 if (ide_get_geometry(arg->idebus[0], 1, 390 &cylinders, &heads, §ors) >= 0) { 391 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 392 val |= 0x0f; 393 } 394 rtc_set_memory(s, 0x12, val); 395 396 val = 0; 397 for (i = 0; i < 4; i++) { 398 /* NOTE: ide_get_geometry() returns the physical 399 geometry. It is always such that: 1 <= sects <= 63, 1 400 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 401 geometry can be different if a translation is done. */ 402 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 403 &cylinders, &heads, §ors) >= 0) { 404 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 405 assert((trans & ~3) == 0); 406 val |= trans << (i * 2); 407 } 408 } 409 rtc_set_memory(s, 0x39, val); 410 411 /* 412 * Locate the FDC at IO address 0x3f0, and configure the CMOS registers 413 * accordingly. 414 */ 415 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 416 container = container_get(qdev_get_machine(), fdc_container_path[i]); 417 object_child_foreach(container, check_fdc, &state); 418 } 419 420 if (state.multiple) { 421 error_report("warning: multiple floppy disk controllers with " 422 "iobase=0x3f0 have been found;\n" 423 "the one being picked for CMOS setup might not reflect " 424 "your intent"); 425 } 426 pc_cmos_init_floppy(s, state.floppy); 427 428 qemu_unregister_reset(pc_cmos_init_late, opaque); 429 } 430 431 void pc_cmos_init(PCMachineState *pcms, 432 BusState *idebus0, BusState *idebus1, 433 ISADevice *s) 434 { 435 int val; 436 static pc_cmos_init_late_arg arg; 437 Error *local_err = NULL; 438 439 /* various important CMOS locations needed by PC/Bochs bios */ 440 441 /* memory size */ 442 /* base memory (first MiB) */ 443 val = MIN(pcms->below_4g_mem_size / 1024, 640); 444 rtc_set_memory(s, 0x15, val); 445 rtc_set_memory(s, 0x16, val >> 8); 446 /* extended memory (next 64MiB) */ 447 if (pcms->below_4g_mem_size > 1024 * 1024) { 448 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 449 } else { 450 val = 0; 451 } 452 if (val > 65535) 453 val = 65535; 454 rtc_set_memory(s, 0x17, val); 455 rtc_set_memory(s, 0x18, val >> 8); 456 rtc_set_memory(s, 0x30, val); 457 rtc_set_memory(s, 0x31, val >> 8); 458 /* memory between 16MiB and 4GiB */ 459 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 460 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 461 } else { 462 val = 0; 463 } 464 if (val > 65535) 465 val = 65535; 466 rtc_set_memory(s, 0x34, val); 467 rtc_set_memory(s, 0x35, val >> 8); 468 /* memory above 4GiB */ 469 val = pcms->above_4g_mem_size / 65536; 470 rtc_set_memory(s, 0x5b, val); 471 rtc_set_memory(s, 0x5c, val >> 8); 472 rtc_set_memory(s, 0x5d, val >> 16); 473 474 /* set the number of CPU */ 475 rtc_set_memory(s, 0x5f, smp_cpus - 1); 476 477 object_property_add_link(OBJECT(pcms), "rtc_state", 478 TYPE_ISA_DEVICE, 479 (Object **)&pcms->rtc, 480 object_property_allow_set_link, 481 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 482 object_property_set_link(OBJECT(pcms), OBJECT(s), 483 "rtc_state", &error_abort); 484 485 set_boot_dev(s, MACHINE(pcms)->boot_order, &local_err); 486 if (local_err) { 487 error_report_err(local_err); 488 exit(1); 489 } 490 491 val = 0; 492 val |= 0x02; /* FPU is there */ 493 val |= 0x04; /* PS/2 mouse installed */ 494 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 495 496 /* hard drives and FDC */ 497 arg.rtc_state = s; 498 arg.idebus[0] = idebus0; 499 arg.idebus[1] = idebus1; 500 qemu_register_reset(pc_cmos_init_late, &arg); 501 } 502 503 #define TYPE_PORT92 "port92" 504 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 505 506 /* port 92 stuff: could be split off */ 507 typedef struct Port92State { 508 ISADevice parent_obj; 509 510 MemoryRegion io; 511 uint8_t outport; 512 qemu_irq *a20_out; 513 } Port92State; 514 515 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 516 unsigned size) 517 { 518 Port92State *s = opaque; 519 int oldval = s->outport; 520 521 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 522 s->outport = val; 523 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 524 if ((val & 1) && !(oldval & 1)) { 525 qemu_system_reset_request(); 526 } 527 } 528 529 static uint64_t port92_read(void *opaque, hwaddr addr, 530 unsigned size) 531 { 532 Port92State *s = opaque; 533 uint32_t ret; 534 535 ret = s->outport; 536 DPRINTF("port92: read 0x%02x\n", ret); 537 return ret; 538 } 539 540 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 541 { 542 Port92State *s = PORT92(dev); 543 544 s->a20_out = a20_out; 545 } 546 547 static const VMStateDescription vmstate_port92_isa = { 548 .name = "port92", 549 .version_id = 1, 550 .minimum_version_id = 1, 551 .fields = (VMStateField[]) { 552 VMSTATE_UINT8(outport, Port92State), 553 VMSTATE_END_OF_LIST() 554 } 555 }; 556 557 static void port92_reset(DeviceState *d) 558 { 559 Port92State *s = PORT92(d); 560 561 s->outport &= ~1; 562 } 563 564 static const MemoryRegionOps port92_ops = { 565 .read = port92_read, 566 .write = port92_write, 567 .impl = { 568 .min_access_size = 1, 569 .max_access_size = 1, 570 }, 571 .endianness = DEVICE_LITTLE_ENDIAN, 572 }; 573 574 static void port92_initfn(Object *obj) 575 { 576 Port92State *s = PORT92(obj); 577 578 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 579 580 s->outport = 0; 581 } 582 583 static void port92_realizefn(DeviceState *dev, Error **errp) 584 { 585 ISADevice *isadev = ISA_DEVICE(dev); 586 Port92State *s = PORT92(dev); 587 588 isa_register_ioport(isadev, &s->io, 0x92); 589 } 590 591 static void port92_class_initfn(ObjectClass *klass, void *data) 592 { 593 DeviceClass *dc = DEVICE_CLASS(klass); 594 595 dc->realize = port92_realizefn; 596 dc->reset = port92_reset; 597 dc->vmsd = &vmstate_port92_isa; 598 /* 599 * Reason: unlike ordinary ISA devices, this one needs additional 600 * wiring: its A20 output line needs to be wired up by 601 * port92_init(). 602 */ 603 dc->cannot_instantiate_with_device_add_yet = true; 604 } 605 606 static const TypeInfo port92_info = { 607 .name = TYPE_PORT92, 608 .parent = TYPE_ISA_DEVICE, 609 .instance_size = sizeof(Port92State), 610 .instance_init = port92_initfn, 611 .class_init = port92_class_initfn, 612 }; 613 614 static void port92_register_types(void) 615 { 616 type_register_static(&port92_info); 617 } 618 619 type_init(port92_register_types) 620 621 static void handle_a20_line_change(void *opaque, int irq, int level) 622 { 623 X86CPU *cpu = opaque; 624 625 /* XXX: send to all CPUs ? */ 626 /* XXX: add logic to handle multiple A20 line sources */ 627 x86_cpu_set_a20(cpu, level); 628 } 629 630 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 631 { 632 int index = le32_to_cpu(e820_reserve.count); 633 struct e820_entry *entry; 634 635 if (type != E820_RAM) { 636 /* old FW_CFG_E820_TABLE entry -- reservations only */ 637 if (index >= E820_NR_ENTRIES) { 638 return -EBUSY; 639 } 640 entry = &e820_reserve.entry[index++]; 641 642 entry->address = cpu_to_le64(address); 643 entry->length = cpu_to_le64(length); 644 entry->type = cpu_to_le32(type); 645 646 e820_reserve.count = cpu_to_le32(index); 647 } 648 649 /* new "etc/e820" file -- include ram too */ 650 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 651 e820_table[e820_entries].address = cpu_to_le64(address); 652 e820_table[e820_entries].length = cpu_to_le64(length); 653 e820_table[e820_entries].type = cpu_to_le32(type); 654 e820_entries++; 655 656 return e820_entries; 657 } 658 659 int e820_get_num_entries(void) 660 { 661 return e820_entries; 662 } 663 664 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 665 { 666 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 667 *address = le64_to_cpu(e820_table[idx].address); 668 *length = le64_to_cpu(e820_table[idx].length); 669 return true; 670 } 671 return false; 672 } 673 674 /* Enables contiguous-apic-ID mode, for compatibility */ 675 static bool compat_apic_id_mode; 676 677 void enable_compat_apic_id_mode(void) 678 { 679 compat_apic_id_mode = true; 680 } 681 682 /* Calculates initial APIC ID for a specific CPU index 683 * 684 * Currently we need to be able to calculate the APIC ID from the CPU index 685 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 686 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 687 * all CPUs up to max_cpus. 688 */ 689 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 690 { 691 uint32_t correct_id; 692 static bool warned; 693 694 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 695 if (compat_apic_id_mode) { 696 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 697 error_report("APIC IDs set in compatibility mode, " 698 "CPU topology won't match the configuration"); 699 warned = true; 700 } 701 return cpu_index; 702 } else { 703 return correct_id; 704 } 705 } 706 707 /* Calculates the limit to CPU APIC ID values 708 * 709 * This function returns the limit for the APIC ID value, so that all 710 * CPU APIC IDs are < pc_apic_id_limit(). 711 * 712 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 713 */ 714 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 715 { 716 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 717 } 718 719 static void pc_build_smbios(FWCfgState *fw_cfg) 720 { 721 uint8_t *smbios_tables, *smbios_anchor; 722 size_t smbios_tables_len, smbios_anchor_len; 723 struct smbios_phys_mem_area *mem_array; 724 unsigned i, array_count; 725 726 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 727 if (smbios_tables) { 728 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 729 smbios_tables, smbios_tables_len); 730 } 731 732 /* build the array of physical mem area from e820 table */ 733 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 734 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 735 uint64_t addr, len; 736 737 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 738 mem_array[array_count].address = addr; 739 mem_array[array_count].length = len; 740 array_count++; 741 } 742 } 743 smbios_get_tables(mem_array, array_count, 744 &smbios_tables, &smbios_tables_len, 745 &smbios_anchor, &smbios_anchor_len); 746 g_free(mem_array); 747 748 if (smbios_anchor) { 749 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 750 smbios_tables, smbios_tables_len); 751 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 752 smbios_anchor, smbios_anchor_len); 753 } 754 } 755 756 static FWCfgState *bochs_bios_init(AddressSpace *as) 757 { 758 FWCfgState *fw_cfg; 759 uint64_t *numa_fw_cfg; 760 int i, j; 761 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 762 763 fw_cfg = fw_cfg_init_io_dma(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 4, as); 764 765 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 766 * 767 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 768 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 769 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 770 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 771 * may see". 772 * 773 * So, this means we must not use max_cpus, here, but the maximum possible 774 * APIC ID value, plus one. 775 * 776 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 777 * the APIC ID, not the "CPU index" 778 */ 779 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 780 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 781 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 782 acpi_tables, acpi_tables_len); 783 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 784 785 pc_build_smbios(fw_cfg); 786 787 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 788 &e820_reserve, sizeof(e820_reserve)); 789 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 790 sizeof(struct e820_entry) * e820_entries); 791 792 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 793 /* allocate memory for the NUMA channel: one (64bit) word for the number 794 * of nodes, one word for each VCPU->node and one word for each node to 795 * hold the amount of memory. 796 */ 797 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 798 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 799 for (i = 0; i < max_cpus; i++) { 800 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 801 assert(apic_id < apic_id_limit); 802 for (j = 0; j < nb_numa_nodes; j++) { 803 if (test_bit(i, numa_info[j].node_cpu)) { 804 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 805 break; 806 } 807 } 808 } 809 for (i = 0; i < nb_numa_nodes; i++) { 810 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 811 } 812 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 813 (1 + apic_id_limit + nb_numa_nodes) * 814 sizeof(*numa_fw_cfg)); 815 816 return fw_cfg; 817 } 818 819 static long get_file_size(FILE *f) 820 { 821 long where, size; 822 823 /* XXX: on Unix systems, using fstat() probably makes more sense */ 824 825 where = ftell(f); 826 fseek(f, 0, SEEK_END); 827 size = ftell(f); 828 fseek(f, where, SEEK_SET); 829 830 return size; 831 } 832 833 static void load_linux(PCMachineState *pcms, 834 FWCfgState *fw_cfg) 835 { 836 uint16_t protocol; 837 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 838 uint32_t initrd_max; 839 uint8_t header[8192], *setup, *kernel, *initrd_data; 840 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 841 FILE *f; 842 char *vmode; 843 MachineState *machine = MACHINE(pcms); 844 const char *kernel_filename = machine->kernel_filename; 845 const char *initrd_filename = machine->initrd_filename; 846 const char *kernel_cmdline = machine->kernel_cmdline; 847 848 /* Align to 16 bytes as a paranoia measure */ 849 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 850 851 /* load the kernel header */ 852 f = fopen(kernel_filename, "rb"); 853 if (!f || !(kernel_size = get_file_size(f)) || 854 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 855 MIN(ARRAY_SIZE(header), kernel_size)) { 856 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 857 kernel_filename, strerror(errno)); 858 exit(1); 859 } 860 861 /* kernel protocol version */ 862 #if 0 863 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 864 #endif 865 if (ldl_p(header+0x202) == 0x53726448) { 866 protocol = lduw_p(header+0x206); 867 } else { 868 /* This looks like a multiboot kernel. If it is, let's stop 869 treating it like a Linux kernel. */ 870 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 871 kernel_cmdline, kernel_size, header)) { 872 return; 873 } 874 protocol = 0; 875 } 876 877 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 878 /* Low kernel */ 879 real_addr = 0x90000; 880 cmdline_addr = 0x9a000 - cmdline_size; 881 prot_addr = 0x10000; 882 } else if (protocol < 0x202) { 883 /* High but ancient kernel */ 884 real_addr = 0x90000; 885 cmdline_addr = 0x9a000 - cmdline_size; 886 prot_addr = 0x100000; 887 } else { 888 /* High and recent kernel */ 889 real_addr = 0x10000; 890 cmdline_addr = 0x20000; 891 prot_addr = 0x100000; 892 } 893 894 #if 0 895 fprintf(stderr, 896 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 897 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 898 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 899 real_addr, 900 cmdline_addr, 901 prot_addr); 902 #endif 903 904 /* highest address for loading the initrd */ 905 if (protocol >= 0x203) { 906 initrd_max = ldl_p(header+0x22c); 907 } else { 908 initrd_max = 0x37ffffff; 909 } 910 911 if (initrd_max >= pcms->below_4g_mem_size - acpi_data_size) { 912 initrd_max = pcms->below_4g_mem_size - acpi_data_size - 1; 913 } 914 915 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 916 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 917 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 918 919 if (protocol >= 0x202) { 920 stl_p(header+0x228, cmdline_addr); 921 } else { 922 stw_p(header+0x20, 0xA33F); 923 stw_p(header+0x22, cmdline_addr-real_addr); 924 } 925 926 /* handle vga= parameter */ 927 vmode = strstr(kernel_cmdline, "vga="); 928 if (vmode) { 929 unsigned int video_mode; 930 /* skip "vga=" */ 931 vmode += 4; 932 if (!strncmp(vmode, "normal", 6)) { 933 video_mode = 0xffff; 934 } else if (!strncmp(vmode, "ext", 3)) { 935 video_mode = 0xfffe; 936 } else if (!strncmp(vmode, "ask", 3)) { 937 video_mode = 0xfffd; 938 } else { 939 video_mode = strtol(vmode, NULL, 0); 940 } 941 stw_p(header+0x1fa, video_mode); 942 } 943 944 /* loader type */ 945 /* High nybble = B reserved for QEMU; low nybble is revision number. 946 If this code is substantially changed, you may want to consider 947 incrementing the revision. */ 948 if (protocol >= 0x200) { 949 header[0x210] = 0xB0; 950 } 951 /* heap */ 952 if (protocol >= 0x201) { 953 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 954 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 955 } 956 957 /* load initrd */ 958 if (initrd_filename) { 959 if (protocol < 0x200) { 960 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 961 exit(1); 962 } 963 964 initrd_size = get_image_size(initrd_filename); 965 if (initrd_size < 0) { 966 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 967 initrd_filename, strerror(errno)); 968 exit(1); 969 } 970 971 initrd_addr = (initrd_max-initrd_size) & ~4095; 972 973 initrd_data = g_malloc(initrd_size); 974 load_image(initrd_filename, initrd_data); 975 976 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 977 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 978 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 979 980 stl_p(header+0x218, initrd_addr); 981 stl_p(header+0x21c, initrd_size); 982 } 983 984 /* load kernel and setup */ 985 setup_size = header[0x1f1]; 986 if (setup_size == 0) { 987 setup_size = 4; 988 } 989 setup_size = (setup_size+1)*512; 990 if (setup_size > kernel_size) { 991 fprintf(stderr, "qemu: invalid kernel header\n"); 992 exit(1); 993 } 994 kernel_size -= setup_size; 995 996 setup = g_malloc(setup_size); 997 kernel = g_malloc(kernel_size); 998 fseek(f, 0, SEEK_SET); 999 if (fread(setup, 1, setup_size, f) != setup_size) { 1000 fprintf(stderr, "fread() failed\n"); 1001 exit(1); 1002 } 1003 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1004 fprintf(stderr, "fread() failed\n"); 1005 exit(1); 1006 } 1007 fclose(f); 1008 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1009 1010 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1011 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1012 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1013 1014 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1015 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1016 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1017 1018 option_rom[nb_option_roms].name = "linuxboot.bin"; 1019 option_rom[nb_option_roms].bootindex = 0; 1020 nb_option_roms++; 1021 } 1022 1023 #define NE2000_NB_MAX 6 1024 1025 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1026 0x280, 0x380 }; 1027 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1028 1029 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1030 { 1031 static int nb_ne2k = 0; 1032 1033 if (nb_ne2k == NE2000_NB_MAX) 1034 return; 1035 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1036 ne2000_irq[nb_ne2k], nd); 1037 nb_ne2k++; 1038 } 1039 1040 DeviceState *cpu_get_current_apic(void) 1041 { 1042 if (current_cpu) { 1043 X86CPU *cpu = X86_CPU(current_cpu); 1044 return cpu->apic_state; 1045 } else { 1046 return NULL; 1047 } 1048 } 1049 1050 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1051 { 1052 X86CPU *cpu = opaque; 1053 1054 if (level) { 1055 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1056 } 1057 } 1058 1059 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1060 Error **errp) 1061 { 1062 X86CPU *cpu = NULL; 1063 Error *local_err = NULL; 1064 1065 cpu = cpu_x86_create(cpu_model, &local_err); 1066 if (local_err != NULL) { 1067 goto out; 1068 } 1069 1070 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1071 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1072 1073 out: 1074 if (local_err) { 1075 error_propagate(errp, local_err); 1076 object_unref(OBJECT(cpu)); 1077 cpu = NULL; 1078 } 1079 return cpu; 1080 } 1081 1082 void pc_hot_add_cpu(const int64_t id, Error **errp) 1083 { 1084 X86CPU *cpu; 1085 MachineState *machine = MACHINE(qdev_get_machine()); 1086 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1087 Error *local_err = NULL; 1088 1089 if (id < 0) { 1090 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1091 return; 1092 } 1093 1094 if (cpu_exists(apic_id)) { 1095 error_setg(errp, "Unable to add CPU: %" PRIi64 1096 ", it already exists", id); 1097 return; 1098 } 1099 1100 if (id >= max_cpus) { 1101 error_setg(errp, "Unable to add CPU: %" PRIi64 1102 ", max allowed: %d", id, max_cpus - 1); 1103 return; 1104 } 1105 1106 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1107 error_setg(errp, "Unable to add CPU: %" PRIi64 1108 ", resulting APIC ID (%" PRIi64 ") is too large", 1109 id, apic_id); 1110 return; 1111 } 1112 1113 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1114 if (local_err) { 1115 error_propagate(errp, local_err); 1116 return; 1117 } 1118 object_unref(OBJECT(cpu)); 1119 } 1120 1121 void pc_cpus_init(PCMachineState *pcms) 1122 { 1123 int i; 1124 X86CPU *cpu = NULL; 1125 MachineState *machine = MACHINE(pcms); 1126 Error *error = NULL; 1127 unsigned long apic_id_limit; 1128 1129 /* init CPUs */ 1130 if (machine->cpu_model == NULL) { 1131 #ifdef TARGET_X86_64 1132 machine->cpu_model = "qemu64"; 1133 #else 1134 machine->cpu_model = "qemu32"; 1135 #endif 1136 } 1137 1138 apic_id_limit = pc_apic_id_limit(max_cpus); 1139 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1140 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1141 apic_id_limit - 1); 1142 exit(1); 1143 } 1144 1145 for (i = 0; i < smp_cpus; i++) { 1146 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1147 &error); 1148 if (error) { 1149 error_report_err(error); 1150 exit(1); 1151 } 1152 object_unref(OBJECT(cpu)); 1153 } 1154 1155 /* tell smbios about cpuid version and features */ 1156 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1157 } 1158 1159 /* pci-info ROM file. Little endian format */ 1160 typedef struct PcRomPciInfo { 1161 uint64_t w32_min; 1162 uint64_t w32_max; 1163 uint64_t w64_min; 1164 uint64_t w64_max; 1165 } PcRomPciInfo; 1166 1167 typedef struct PcGuestInfoState { 1168 PcGuestInfo info; 1169 Notifier machine_done; 1170 } PcGuestInfoState; 1171 1172 static 1173 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1174 { 1175 PcGuestInfoState *guest_info_state = container_of(notifier, 1176 PcGuestInfoState, 1177 machine_done); 1178 PCIBus *bus = find_i440fx(); 1179 1180 if (bus) { 1181 int extra_hosts = 0; 1182 1183 QLIST_FOREACH(bus, &bus->child, sibling) { 1184 /* look for expander root buses */ 1185 if (pci_bus_is_root(bus)) { 1186 extra_hosts++; 1187 } 1188 } 1189 if (extra_hosts && guest_info_state->info.fw_cfg) { 1190 uint64_t *val = g_malloc(sizeof(*val)); 1191 *val = cpu_to_le64(extra_hosts); 1192 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1193 "etc/extra-pci-roots", val, sizeof(*val)); 1194 } 1195 } 1196 1197 acpi_setup(&guest_info_state->info); 1198 } 1199 1200 PcGuestInfo *pc_guest_info_init(PCMachineState *pcms) 1201 { 1202 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1203 PcGuestInfo *guest_info = &guest_info_state->info; 1204 int i, j; 1205 1206 guest_info->ram_size_below_4g = pcms->below_4g_mem_size; 1207 guest_info->ram_size = pcms->below_4g_mem_size + pcms->above_4g_mem_size; 1208 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1209 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1210 guest_info->numa_nodes = nb_numa_nodes; 1211 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1212 sizeof *guest_info->node_mem); 1213 for (i = 0; i < nb_numa_nodes; i++) { 1214 guest_info->node_mem[i] = numa_info[i].node_mem; 1215 } 1216 1217 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1218 sizeof *guest_info->node_cpu); 1219 1220 for (i = 0; i < max_cpus; i++) { 1221 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1222 assert(apic_id < guest_info->apic_id_limit); 1223 for (j = 0; j < nb_numa_nodes; j++) { 1224 if (test_bit(i, numa_info[j].node_cpu)) { 1225 guest_info->node_cpu[apic_id] = j; 1226 break; 1227 } 1228 } 1229 } 1230 1231 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1232 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1233 return guest_info; 1234 } 1235 1236 /* setup pci memory address space mapping into system address space */ 1237 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1238 MemoryRegion *pci_address_space) 1239 { 1240 /* Set to lower priority than RAM */ 1241 memory_region_add_subregion_overlap(system_memory, 0x0, 1242 pci_address_space, -1); 1243 } 1244 1245 void pc_acpi_init(const char *default_dsdt) 1246 { 1247 char *filename; 1248 1249 if (acpi_tables != NULL) { 1250 /* manually set via -acpitable, leave it alone */ 1251 return; 1252 } 1253 1254 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1255 if (filename == NULL) { 1256 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1257 } else { 1258 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1259 &error_abort); 1260 Error *err = NULL; 1261 1262 qemu_opt_set(opts, "file", filename, &error_abort); 1263 1264 acpi_table_add_builtin(opts, &err); 1265 if (err) { 1266 error_report("WARNING: failed to load %s: %s", filename, 1267 error_get_pretty(err)); 1268 error_free(err); 1269 } 1270 g_free(filename); 1271 } 1272 } 1273 1274 FWCfgState *xen_load_linux(PCMachineState *pcms, 1275 PcGuestInfo *guest_info) 1276 { 1277 int i; 1278 FWCfgState *fw_cfg; 1279 1280 assert(MACHINE(pcms)->kernel_filename != NULL); 1281 1282 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1283 rom_set_fw(fw_cfg); 1284 1285 load_linux(pcms, fw_cfg); 1286 for (i = 0; i < nb_option_roms; i++) { 1287 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1288 !strcmp(option_rom[i].name, "multiboot.bin")); 1289 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1290 } 1291 guest_info->fw_cfg = fw_cfg; 1292 return fw_cfg; 1293 } 1294 1295 FWCfgState *pc_memory_init(PCMachineState *pcms, 1296 MemoryRegion *system_memory, 1297 MemoryRegion *rom_memory, 1298 MemoryRegion **ram_memory, 1299 PcGuestInfo *guest_info) 1300 { 1301 int linux_boot, i; 1302 MemoryRegion *ram, *option_rom_mr; 1303 MemoryRegion *ram_below_4g, *ram_above_4g; 1304 FWCfgState *fw_cfg; 1305 MachineState *machine = MACHINE(pcms); 1306 1307 assert(machine->ram_size == pcms->below_4g_mem_size + 1308 pcms->above_4g_mem_size); 1309 1310 linux_boot = (machine->kernel_filename != NULL); 1311 1312 /* Allocate RAM. We allocate it as a single memory region and use 1313 * aliases to address portions of it, mostly for backwards compatibility 1314 * with older qemus that used qemu_ram_alloc(). 1315 */ 1316 ram = g_malloc(sizeof(*ram)); 1317 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1318 machine->ram_size); 1319 *ram_memory = ram; 1320 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1321 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1322 0, pcms->below_4g_mem_size); 1323 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1324 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1325 if (pcms->above_4g_mem_size > 0) { 1326 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1327 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1328 pcms->below_4g_mem_size, 1329 pcms->above_4g_mem_size); 1330 memory_region_add_subregion(system_memory, 0x100000000ULL, 1331 ram_above_4g); 1332 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1333 } 1334 1335 if (!guest_info->has_reserved_memory && 1336 (machine->ram_slots || 1337 (machine->maxram_size > machine->ram_size))) { 1338 MachineClass *mc = MACHINE_GET_CLASS(machine); 1339 1340 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1341 mc->name); 1342 exit(EXIT_FAILURE); 1343 } 1344 1345 /* initialize hotplug memory address space */ 1346 if (guest_info->has_reserved_memory && 1347 (machine->ram_size < machine->maxram_size)) { 1348 ram_addr_t hotplug_mem_size = 1349 machine->maxram_size - machine->ram_size; 1350 1351 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1352 error_report("unsupported amount of memory slots: %"PRIu64, 1353 machine->ram_slots); 1354 exit(EXIT_FAILURE); 1355 } 1356 1357 if (QEMU_ALIGN_UP(machine->maxram_size, 1358 TARGET_PAGE_SIZE) != machine->maxram_size) { 1359 error_report("maximum memory size must by aligned to multiple of " 1360 "%d bytes", TARGET_PAGE_SIZE); 1361 exit(EXIT_FAILURE); 1362 } 1363 1364 pcms->hotplug_memory.base = 1365 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1366 1367 if (pcms->enforce_aligned_dimm) { 1368 /* size hotplug region assuming 1G page max alignment per slot */ 1369 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1370 } 1371 1372 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1373 hotplug_mem_size) { 1374 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1375 machine->maxram_size); 1376 exit(EXIT_FAILURE); 1377 } 1378 1379 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1380 "hotplug-memory", hotplug_mem_size); 1381 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1382 &pcms->hotplug_memory.mr); 1383 } 1384 1385 /* Initialize PC system firmware */ 1386 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1387 1388 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1389 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1390 &error_fatal); 1391 vmstate_register_ram_global(option_rom_mr); 1392 memory_region_add_subregion_overlap(rom_memory, 1393 PC_ROM_MIN_VGA, 1394 option_rom_mr, 1395 1); 1396 1397 fw_cfg = bochs_bios_init(&address_space_memory); 1398 1399 rom_set_fw(fw_cfg); 1400 1401 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1402 uint64_t *val = g_malloc(sizeof(*val)); 1403 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1404 uint64_t res_mem_end = pcms->hotplug_memory.base; 1405 1406 if (!pcmc->broken_reserved_end) { 1407 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1408 } 1409 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1410 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1411 } 1412 1413 if (linux_boot) { 1414 load_linux(pcms, fw_cfg); 1415 } 1416 1417 for (i = 0; i < nb_option_roms; i++) { 1418 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1419 } 1420 guest_info->fw_cfg = fw_cfg; 1421 return fw_cfg; 1422 } 1423 1424 qemu_irq pc_allocate_cpu_irq(void) 1425 { 1426 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1427 } 1428 1429 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1430 { 1431 DeviceState *dev = NULL; 1432 1433 if (pci_bus) { 1434 PCIDevice *pcidev = pci_vga_init(pci_bus); 1435 dev = pcidev ? &pcidev->qdev : NULL; 1436 } else if (isa_bus) { 1437 ISADevice *isadev = isa_vga_init(isa_bus); 1438 dev = isadev ? DEVICE(isadev) : NULL; 1439 } 1440 return dev; 1441 } 1442 1443 static const MemoryRegionOps ioport80_io_ops = { 1444 .write = ioport80_write, 1445 .read = ioport80_read, 1446 .endianness = DEVICE_NATIVE_ENDIAN, 1447 .impl = { 1448 .min_access_size = 1, 1449 .max_access_size = 1, 1450 }, 1451 }; 1452 1453 static const MemoryRegionOps ioportF0_io_ops = { 1454 .write = ioportF0_write, 1455 .read = ioportF0_read, 1456 .endianness = DEVICE_NATIVE_ENDIAN, 1457 .impl = { 1458 .min_access_size = 1, 1459 .max_access_size = 1, 1460 }, 1461 }; 1462 1463 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1464 ISADevice **rtc_state, 1465 bool create_fdctrl, 1466 bool no_vmport, 1467 uint32 hpet_irqs) 1468 { 1469 int i; 1470 DriveInfo *fd[MAX_FD]; 1471 DeviceState *hpet = NULL; 1472 int pit_isa_irq = 0; 1473 qemu_irq pit_alt_irq = NULL; 1474 qemu_irq rtc_irq = NULL; 1475 qemu_irq *a20_line; 1476 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1477 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1478 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1479 1480 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1481 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1482 1483 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1484 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1485 1486 /* 1487 * Check if an HPET shall be created. 1488 * 1489 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1490 * when the HPET wants to take over. Thus we have to disable the latter. 1491 */ 1492 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1493 /* In order to set property, here not using sysbus_try_create_simple */ 1494 hpet = qdev_try_create(NULL, TYPE_HPET); 1495 if (hpet) { 1496 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1497 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1498 * IRQ8 and IRQ2. 1499 */ 1500 uint8_t compat = object_property_get_int(OBJECT(hpet), 1501 HPET_INTCAP, NULL); 1502 if (!compat) { 1503 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1504 } 1505 qdev_init_nofail(hpet); 1506 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1507 1508 for (i = 0; i < GSI_NUM_PINS; i++) { 1509 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1510 } 1511 pit_isa_irq = -1; 1512 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1513 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1514 } 1515 } 1516 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1517 1518 qemu_register_boot_set(pc_boot_set, *rtc_state); 1519 1520 if (!xen_enabled()) { 1521 if (kvm_pit_in_kernel()) { 1522 pit = kvm_pit_init(isa_bus, 0x40); 1523 } else { 1524 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1525 } 1526 if (hpet) { 1527 /* connect PIT to output control line of the HPET */ 1528 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1529 } 1530 pcspk_init(isa_bus, pit); 1531 } 1532 1533 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1534 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1535 1536 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1537 i8042 = isa_create_simple(isa_bus, "i8042"); 1538 i8042_setup_a20_line(i8042, &a20_line[0]); 1539 if (!no_vmport) { 1540 vmport_init(isa_bus); 1541 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1542 } else { 1543 vmmouse = NULL; 1544 } 1545 if (vmmouse) { 1546 DeviceState *dev = DEVICE(vmmouse); 1547 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1548 qdev_init_nofail(dev); 1549 } 1550 port92 = isa_create_simple(isa_bus, "port92"); 1551 port92_init(port92, &a20_line[1]); 1552 1553 DMA_init(0); 1554 1555 for(i = 0; i < MAX_FD; i++) { 1556 fd[i] = drive_get(IF_FLOPPY, 0, i); 1557 create_fdctrl |= !!fd[i]; 1558 } 1559 if (create_fdctrl) { 1560 fdctrl_init_isa(isa_bus, fd); 1561 } 1562 } 1563 1564 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1565 { 1566 int i; 1567 1568 for (i = 0; i < nb_nics; i++) { 1569 NICInfo *nd = &nd_table[i]; 1570 1571 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1572 pc_init_ne2k_isa(isa_bus, nd); 1573 } else { 1574 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1575 } 1576 } 1577 } 1578 1579 void pc_pci_device_init(PCIBus *pci_bus) 1580 { 1581 int max_bus; 1582 int bus; 1583 1584 max_bus = drive_get_max_bus(IF_SCSI); 1585 for (bus = 0; bus <= max_bus; bus++) { 1586 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1587 } 1588 } 1589 1590 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1591 { 1592 DeviceState *dev; 1593 SysBusDevice *d; 1594 unsigned int i; 1595 1596 if (kvm_ioapic_in_kernel()) { 1597 dev = qdev_create(NULL, "kvm-ioapic"); 1598 } else { 1599 dev = qdev_create(NULL, "ioapic"); 1600 } 1601 if (parent_name) { 1602 object_property_add_child(object_resolve_path(parent_name, NULL), 1603 "ioapic", OBJECT(dev), NULL); 1604 } 1605 qdev_init_nofail(dev); 1606 d = SYS_BUS_DEVICE(dev); 1607 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1608 1609 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1610 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1611 } 1612 } 1613 1614 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1615 DeviceState *dev, Error **errp) 1616 { 1617 HotplugHandlerClass *hhc; 1618 Error *local_err = NULL; 1619 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1620 PCDIMMDevice *dimm = PC_DIMM(dev); 1621 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1622 MemoryRegion *mr = ddc->get_memory_region(dimm); 1623 uint64_t align = TARGET_PAGE_SIZE; 1624 1625 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1626 align = memory_region_get_alignment(mr); 1627 } 1628 1629 if (!pcms->acpi_dev) { 1630 error_setg(&local_err, 1631 "memory hotplug is not enabled: missing acpi device"); 1632 goto out; 1633 } 1634 1635 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1636 if (local_err) { 1637 goto out; 1638 } 1639 1640 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1641 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1642 out: 1643 error_propagate(errp, local_err); 1644 } 1645 1646 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1647 DeviceState *dev, Error **errp) 1648 { 1649 HotplugHandlerClass *hhc; 1650 Error *local_err = NULL; 1651 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1652 1653 if (!pcms->acpi_dev) { 1654 error_setg(&local_err, 1655 "memory hotplug is not enabled: missing acpi device"); 1656 goto out; 1657 } 1658 1659 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1660 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1661 1662 out: 1663 error_propagate(errp, local_err); 1664 } 1665 1666 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1667 DeviceState *dev, Error **errp) 1668 { 1669 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1670 PCDIMMDevice *dimm = PC_DIMM(dev); 1671 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1672 MemoryRegion *mr = ddc->get_memory_region(dimm); 1673 HotplugHandlerClass *hhc; 1674 Error *local_err = NULL; 1675 1676 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1677 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1678 1679 if (local_err) { 1680 goto out; 1681 } 1682 1683 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1684 object_unparent(OBJECT(dev)); 1685 1686 out: 1687 error_propagate(errp, local_err); 1688 } 1689 1690 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1691 DeviceState *dev, Error **errp) 1692 { 1693 HotplugHandlerClass *hhc; 1694 Error *local_err = NULL; 1695 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1696 1697 if (!dev->hotplugged) { 1698 goto out; 1699 } 1700 1701 if (!pcms->acpi_dev) { 1702 error_setg(&local_err, 1703 "cpu hotplug is not enabled: missing acpi device"); 1704 goto out; 1705 } 1706 1707 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1708 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1709 if (local_err) { 1710 goto out; 1711 } 1712 1713 /* increment the number of CPUs */ 1714 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1715 out: 1716 error_propagate(errp, local_err); 1717 } 1718 1719 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1720 DeviceState *dev, Error **errp) 1721 { 1722 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1723 pc_dimm_plug(hotplug_dev, dev, errp); 1724 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1725 pc_cpu_plug(hotplug_dev, dev, errp); 1726 } 1727 } 1728 1729 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1730 DeviceState *dev, Error **errp) 1731 { 1732 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1733 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1734 } else { 1735 error_setg(errp, "acpi: device unplug request for not supported device" 1736 " type: %s", object_get_typename(OBJECT(dev))); 1737 } 1738 } 1739 1740 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1741 DeviceState *dev, Error **errp) 1742 { 1743 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1744 pc_dimm_unplug(hotplug_dev, dev, errp); 1745 } else { 1746 error_setg(errp, "acpi: device unplug for not supported device" 1747 " type: %s", object_get_typename(OBJECT(dev))); 1748 } 1749 } 1750 1751 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1752 DeviceState *dev) 1753 { 1754 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1755 1756 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1757 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1758 return HOTPLUG_HANDLER(machine); 1759 } 1760 1761 return pcmc->get_hotplug_handler ? 1762 pcmc->get_hotplug_handler(machine, dev) : NULL; 1763 } 1764 1765 static void 1766 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1767 const char *name, Error **errp) 1768 { 1769 PCMachineState *pcms = PC_MACHINE(obj); 1770 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1771 1772 visit_type_int(v, &value, name, errp); 1773 } 1774 1775 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1776 void *opaque, const char *name, 1777 Error **errp) 1778 { 1779 PCMachineState *pcms = PC_MACHINE(obj); 1780 uint64_t value = pcms->max_ram_below_4g; 1781 1782 visit_type_size(v, &value, name, errp); 1783 } 1784 1785 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1786 void *opaque, const char *name, 1787 Error **errp) 1788 { 1789 PCMachineState *pcms = PC_MACHINE(obj); 1790 Error *error = NULL; 1791 uint64_t value; 1792 1793 visit_type_size(v, &value, name, &error); 1794 if (error) { 1795 error_propagate(errp, error); 1796 return; 1797 } 1798 if (value > (1ULL << 32)) { 1799 error_setg(&error, 1800 "Machine option 'max-ram-below-4g=%"PRIu64 1801 "' expects size less than or equal to 4G", value); 1802 error_propagate(errp, error); 1803 return; 1804 } 1805 1806 if (value < (1ULL << 20)) { 1807 error_report("Warning: small max_ram_below_4g(%"PRIu64 1808 ") less than 1M. BIOS may not work..", 1809 value); 1810 } 1811 1812 pcms->max_ram_below_4g = value; 1813 } 1814 1815 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1816 const char *name, Error **errp) 1817 { 1818 PCMachineState *pcms = PC_MACHINE(obj); 1819 OnOffAuto vmport = pcms->vmport; 1820 1821 visit_type_OnOffAuto(v, &vmport, name, errp); 1822 } 1823 1824 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1825 const char *name, Error **errp) 1826 { 1827 PCMachineState *pcms = PC_MACHINE(obj); 1828 1829 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1830 } 1831 1832 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1833 { 1834 bool smm_available = false; 1835 1836 if (pcms->smm == ON_OFF_AUTO_OFF) { 1837 return false; 1838 } 1839 1840 if (tcg_enabled() || qtest_enabled()) { 1841 smm_available = true; 1842 } else if (kvm_enabled()) { 1843 smm_available = kvm_has_smm(); 1844 } 1845 1846 if (smm_available) { 1847 return true; 1848 } 1849 1850 if (pcms->smm == ON_OFF_AUTO_ON) { 1851 error_report("System Management Mode not supported by this hypervisor."); 1852 exit(1); 1853 } 1854 return false; 1855 } 1856 1857 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1858 const char *name, Error **errp) 1859 { 1860 PCMachineState *pcms = PC_MACHINE(obj); 1861 OnOffAuto smm = pcms->smm; 1862 1863 visit_type_OnOffAuto(v, &smm, name, errp); 1864 } 1865 1866 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1867 const char *name, Error **errp) 1868 { 1869 PCMachineState *pcms = PC_MACHINE(obj); 1870 1871 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1872 } 1873 1874 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1875 { 1876 PCMachineState *pcms = PC_MACHINE(obj); 1877 1878 return pcms->enforce_aligned_dimm; 1879 } 1880 1881 static void pc_machine_initfn(Object *obj) 1882 { 1883 PCMachineState *pcms = PC_MACHINE(obj); 1884 1885 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1886 pc_machine_get_hotplug_memory_region_size, 1887 NULL, NULL, NULL, &error_abort); 1888 1889 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1890 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1891 pc_machine_get_max_ram_below_4g, 1892 pc_machine_set_max_ram_below_4g, 1893 NULL, NULL, &error_abort); 1894 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1895 "Maximum ram below the 4G boundary (32bit boundary)", 1896 &error_abort); 1897 1898 pcms->smm = ON_OFF_AUTO_AUTO; 1899 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1900 pc_machine_get_smm, 1901 pc_machine_set_smm, 1902 NULL, NULL, &error_abort); 1903 object_property_set_description(obj, PC_MACHINE_SMM, 1904 "Enable SMM (pc & q35)", 1905 &error_abort); 1906 1907 pcms->vmport = ON_OFF_AUTO_AUTO; 1908 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1909 pc_machine_get_vmport, 1910 pc_machine_set_vmport, 1911 NULL, NULL, &error_abort); 1912 object_property_set_description(obj, PC_MACHINE_VMPORT, 1913 "Enable vmport (pc & q35)", 1914 &error_abort); 1915 1916 pcms->enforce_aligned_dimm = true; 1917 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1918 pc_machine_get_aligned_dimm, 1919 NULL, &error_abort); 1920 } 1921 1922 static void pc_machine_reset(void) 1923 { 1924 CPUState *cs; 1925 X86CPU *cpu; 1926 1927 qemu_devices_reset(); 1928 1929 /* Reset APIC after devices have been reset to cancel 1930 * any changes that qemu_devices_reset() might have done. 1931 */ 1932 CPU_FOREACH(cs) { 1933 cpu = X86_CPU(cs); 1934 1935 if (cpu->apic_state) { 1936 device_reset(cpu->apic_state); 1937 } 1938 } 1939 } 1940 1941 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1942 { 1943 X86CPUTopoInfo topo; 1944 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1945 &topo); 1946 return topo.pkg_id; 1947 } 1948 1949 static void pc_machine_class_init(ObjectClass *oc, void *data) 1950 { 1951 MachineClass *mc = MACHINE_CLASS(oc); 1952 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1953 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1954 1955 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1956 mc->get_hotplug_handler = pc_get_hotpug_handler; 1957 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1958 mc->default_boot_order = "cad"; 1959 mc->hot_add_cpu = pc_hot_add_cpu; 1960 mc->max_cpus = 255; 1961 mc->reset = pc_machine_reset; 1962 hc->plug = pc_machine_device_plug_cb; 1963 hc->unplug_request = pc_machine_device_unplug_request_cb; 1964 hc->unplug = pc_machine_device_unplug_cb; 1965 } 1966 1967 static const TypeInfo pc_machine_info = { 1968 .name = TYPE_PC_MACHINE, 1969 .parent = TYPE_MACHINE, 1970 .abstract = true, 1971 .instance_size = sizeof(PCMachineState), 1972 .instance_init = pc_machine_initfn, 1973 .class_size = sizeof(PCMachineClass), 1974 .class_init = pc_machine_class_init, 1975 .interfaces = (InterfaceInfo[]) { 1976 { TYPE_HOTPLUG_HANDLER }, 1977 { } 1978 }, 1979 }; 1980 1981 static void pc_machine_register_types(void) 1982 { 1983 type_register_static(&pc_machine_info); 1984 } 1985 1986 type_init(pc_machine_register_types) 1987