xref: /openbmc/qemu/hw/i386/pc.c (revision 9f22020b)
1 /*
2  * QEMU PC System Emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/dma/i8257.h"
51 #include "hw/timer/i8254.h"
52 #include "hw/input/i8042.h"
53 #include "hw/irq.h"
54 #include "hw/audio/pcspk.h"
55 #include "hw/pci/msi.h"
56 #include "hw/sysbus.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/tcg.h"
59 #include "sysemu/numa.h"
60 #include "sysemu/kvm.h"
61 #include "sysemu/xen.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm/kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/cxl/cxl.h"
80 #include "hw/cxl/cxl_host.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/qapi-visit-machine.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-iommu.h"
91 #include "hw/virtio/virtio-pmem-pci.h"
92 #include "hw/virtio/virtio-mem-pci.h"
93 #include "hw/mem/memory-device.h"
94 #include "sysemu/replay.h"
95 #include "qapi/qmp/qerror.h"
96 #include "e820_memory_layout.h"
97 #include "fw_cfg.h"
98 #include "trace.h"
99 #include CONFIG_DEVICES
100 
101 /*
102  * Helper for setting model-id for CPU models that changed model-id
103  * depending on QEMU versions up to QEMU 2.4.
104  */
105 #define PC_CPU_MODEL_IDS(v) \
106     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
107     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
108     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
109 
110 GlobalProperty pc_compat_7_1[] = {};
111 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
112 
113 GlobalProperty pc_compat_7_0[] = {};
114 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
115 
116 GlobalProperty pc_compat_6_2[] = {
117     { "virtio-mem", "unplugged-inaccessible", "off" },
118 };
119 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
120 
121 GlobalProperty pc_compat_6_1[] = {
122     { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
123     { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
124     { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
125     { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
126 };
127 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
128 
129 GlobalProperty pc_compat_6_0[] = {
130     { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
131     { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
132     { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
133     { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
134     { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
135     { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
136 };
137 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
138 
139 GlobalProperty pc_compat_5_2[] = {
140     { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
141 };
142 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
143 
144 GlobalProperty pc_compat_5_1[] = {
145     { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
146     { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
147 };
148 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
149 
150 GlobalProperty pc_compat_5_0[] = {
151 };
152 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
153 
154 GlobalProperty pc_compat_4_2[] = {
155     { "mch", "smbase-smram", "off" },
156 };
157 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
158 
159 GlobalProperty pc_compat_4_1[] = {};
160 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
161 
162 GlobalProperty pc_compat_4_0[] = {};
163 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
164 
165 GlobalProperty pc_compat_3_1[] = {
166     { "intel-iommu", "dma-drain", "off" },
167     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
168     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
169     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
170     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
171     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
172     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
173     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
174     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
175     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
176     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
177     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
178     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
179     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
180     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
181     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
182     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
183     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
184     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
185     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
186     { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
187 };
188 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
189 
190 GlobalProperty pc_compat_3_0[] = {
191     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
192     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
193     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
194 };
195 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
196 
197 GlobalProperty pc_compat_2_12[] = {
198     { TYPE_X86_CPU, "legacy-cache", "on" },
199     { TYPE_X86_CPU, "topoext", "off" },
200     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
201     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
202 };
203 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
204 
205 GlobalProperty pc_compat_2_11[] = {
206     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
207     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
208 };
209 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
210 
211 GlobalProperty pc_compat_2_10[] = {
212     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
213     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
214     { "q35-pcihost", "x-pci-hole64-fix", "off" },
215 };
216 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
217 
218 GlobalProperty pc_compat_2_9[] = {
219     { "mch", "extended-tseg-mbytes", "0" },
220 };
221 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
222 
223 GlobalProperty pc_compat_2_8[] = {
224     { TYPE_X86_CPU, "tcg-cpuid", "off" },
225     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
226     { "ICH9-LPC", "x-smi-broadcast", "off" },
227     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
228     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
229 };
230 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
231 
232 GlobalProperty pc_compat_2_7[] = {
233     { TYPE_X86_CPU, "l3-cache", "off" },
234     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
235     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
236     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
237     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
238     { "isa-pcspk", "migrate", "off" },
239 };
240 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
241 
242 GlobalProperty pc_compat_2_6[] = {
243     { TYPE_X86_CPU, "cpuid-0xb", "off" },
244     { "vmxnet3", "romfile", "" },
245     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
246     { "apic-common", "legacy-instance-id", "on", }
247 };
248 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
249 
250 GlobalProperty pc_compat_2_5[] = {};
251 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
252 
253 GlobalProperty pc_compat_2_4[] = {
254     PC_CPU_MODEL_IDS("2.4.0")
255     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
256     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
257     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
258     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
259     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
260     { TYPE_X86_CPU, "check", "off" },
261     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
262     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
263     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
264     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
265     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
266     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
267     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
268     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
269 };
270 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
271 
272 GlobalProperty pc_compat_2_3[] = {
273     PC_CPU_MODEL_IDS("2.3.0")
274     { TYPE_X86_CPU, "arat", "off" },
275     { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
276     { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
277     { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
278     { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
279     { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
280     { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
281     { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
282     { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
283     { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
284     { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
285     { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
286     { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
287     { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288     { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289     { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
290     { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
291     { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
292     { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
293     { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
294 };
295 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
296 
297 GlobalProperty pc_compat_2_2[] = {
298     PC_CPU_MODEL_IDS("2.2.0")
299     { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
300     { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
301     { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
302     { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
303     { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
304     { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
305     { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
306     { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
307     { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
308     { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
309     { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
310     { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
311     { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
312     { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
313     { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
314     { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
315     { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
316     { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
317 };
318 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
319 
320 GlobalProperty pc_compat_2_1[] = {
321     PC_CPU_MODEL_IDS("2.1.0")
322     { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
323     { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
324 };
325 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
326 
327 GlobalProperty pc_compat_2_0[] = {
328     PC_CPU_MODEL_IDS("2.0.0")
329     { "virtio-scsi-pci", "any_layout", "off" },
330     { "PIIX4_PM", "memory-hotplug-support", "off" },
331     { "apic", "version", "0x11" },
332     { "nec-usb-xhci", "superspeed-ports-first", "off" },
333     { "nec-usb-xhci", "force-pcie-endcap", "on" },
334     { "pci-serial", "prog_if", "0" },
335     { "pci-serial-2x", "prog_if", "0" },
336     { "pci-serial-4x", "prog_if", "0" },
337     { "virtio-net-pci", "guest_announce", "off" },
338     { "ICH9-LPC", "memory-hotplug-support", "off" },
339 };
340 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
341 
342 GlobalProperty pc_compat_1_7[] = {
343     PC_CPU_MODEL_IDS("1.7.0")
344     { TYPE_USB_DEVICE, "msos-desc", "no" },
345     { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
346     { "hpet", HPET_INTCAP, "4" },
347 };
348 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
349 
350 GlobalProperty pc_compat_1_6[] = {
351     PC_CPU_MODEL_IDS("1.6.0")
352     { "e1000", "mitigation", "off" },
353     { "qemu64-" TYPE_X86_CPU, "model", "2" },
354     { "qemu32-" TYPE_X86_CPU, "model", "3" },
355     { "i440FX-pcihost", "short_root_bus", "1" },
356     { "q35-pcihost", "short_root_bus", "1" },
357 };
358 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
359 
360 GlobalProperty pc_compat_1_5[] = {
361     PC_CPU_MODEL_IDS("1.5.0")
362     { "Conroe-" TYPE_X86_CPU, "model", "2" },
363     { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
364     { "Penryn-" TYPE_X86_CPU, "model", "2" },
365     { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
366     { "Nehalem-" TYPE_X86_CPU, "model", "2" },
367     { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
368     { "virtio-net-pci", "any_layout", "off" },
369     { TYPE_X86_CPU, "pmu", "on" },
370     { "i440FX-pcihost", "short_root_bus", "0" },
371     { "q35-pcihost", "short_root_bus", "0" },
372 };
373 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
374 
375 GlobalProperty pc_compat_1_4[] = {
376     PC_CPU_MODEL_IDS("1.4.0")
377     { "scsi-hd", "discard_granularity", "0" },
378     { "scsi-cd", "discard_granularity", "0" },
379     { "ide-hd", "discard_granularity", "0" },
380     { "ide-cd", "discard_granularity", "0" },
381     { "virtio-blk-pci", "discard_granularity", "0" },
382     /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
383     { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
384     { "virtio-net-pci", "ctrl_guest_offloads", "off" },
385     { "e1000", "romfile", "pxe-e1000.rom" },
386     { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
387     { "pcnet", "romfile", "pxe-pcnet.rom" },
388     { "rtl8139", "romfile", "pxe-rtl8139.rom" },
389     { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
390     { "486-" TYPE_X86_CPU, "model", "0" },
391     { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
392     { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
393 };
394 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
395 
396 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
397 {
398     GSIState *s;
399 
400     s = g_new0(GSIState, 1);
401     if (kvm_ioapic_in_kernel()) {
402         kvm_pc_setup_irq_routing(pci_enabled);
403     }
404     *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
405 
406     return s;
407 }
408 
409 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
410                            unsigned size)
411 {
412 }
413 
414 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
415 {
416     return 0xffffffffffffffffULL;
417 }
418 
419 /* MSDOS compatibility mode FPU exception support */
420 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
421                            unsigned size)
422 {
423     if (tcg_enabled()) {
424         cpu_set_ignne();
425     }
426 }
427 
428 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
429 {
430     return 0xffffffffffffffffULL;
431 }
432 
433 /* PC cmos mappings */
434 
435 #define REG_EQUIPMENT_BYTE          0x14
436 
437 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
438                          int16_t cylinders, int8_t heads, int8_t sectors)
439 {
440     rtc_set_memory(s, type_ofs, 47);
441     rtc_set_memory(s, info_ofs, cylinders);
442     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
443     rtc_set_memory(s, info_ofs + 2, heads);
444     rtc_set_memory(s, info_ofs + 3, 0xff);
445     rtc_set_memory(s, info_ofs + 4, 0xff);
446     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
447     rtc_set_memory(s, info_ofs + 6, cylinders);
448     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
449     rtc_set_memory(s, info_ofs + 8, sectors);
450 }
451 
452 /* convert boot_device letter to something recognizable by the bios */
453 static int boot_device2nibble(char boot_device)
454 {
455     switch(boot_device) {
456     case 'a':
457     case 'b':
458         return 0x01; /* floppy boot */
459     case 'c':
460         return 0x02; /* hard drive boot */
461     case 'd':
462         return 0x03; /* CD-ROM boot */
463     case 'n':
464         return 0x04; /* Network boot */
465     }
466     return 0;
467 }
468 
469 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
470 {
471 #define PC_MAX_BOOT_DEVICES 3
472     int nbds, bds[3] = { 0, };
473     int i;
474 
475     nbds = strlen(boot_device);
476     if (nbds > PC_MAX_BOOT_DEVICES) {
477         error_setg(errp, "Too many boot devices for PC");
478         return;
479     }
480     for (i = 0; i < nbds; i++) {
481         bds[i] = boot_device2nibble(boot_device[i]);
482         if (bds[i] == 0) {
483             error_setg(errp, "Invalid boot device for PC: '%c'",
484                        boot_device[i]);
485             return;
486         }
487     }
488     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
489     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
490 }
491 
492 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
493 {
494     set_boot_dev(opaque, boot_device, errp);
495 }
496 
497 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
498 {
499     int val, nb, i;
500     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
501                                    FLOPPY_DRIVE_TYPE_NONE };
502 
503     /* floppy type */
504     if (floppy) {
505         for (i = 0; i < 2; i++) {
506             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
507         }
508     }
509     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
510         cmos_get_fd_drive_type(fd_type[1]);
511     rtc_set_memory(rtc_state, 0x10, val);
512 
513     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
514     nb = 0;
515     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
516         nb++;
517     }
518     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
519         nb++;
520     }
521     switch (nb) {
522     case 0:
523         break;
524     case 1:
525         val |= 0x01; /* 1 drive, ready for boot */
526         break;
527     case 2:
528         val |= 0x41; /* 2 drives, ready for boot */
529         break;
530     }
531     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
532 }
533 
534 typedef struct pc_cmos_init_late_arg {
535     ISADevice *rtc_state;
536     BusState *idebus[2];
537 } pc_cmos_init_late_arg;
538 
539 typedef struct check_fdc_state {
540     ISADevice *floppy;
541     bool multiple;
542 } CheckFdcState;
543 
544 static int check_fdc(Object *obj, void *opaque)
545 {
546     CheckFdcState *state = opaque;
547     Object *fdc;
548     uint32_t iobase;
549     Error *local_err = NULL;
550 
551     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
552     if (!fdc) {
553         return 0;
554     }
555 
556     iobase = object_property_get_uint(obj, "iobase", &local_err);
557     if (local_err || iobase != 0x3f0) {
558         error_free(local_err);
559         return 0;
560     }
561 
562     if (state->floppy) {
563         state->multiple = true;
564     } else {
565         state->floppy = ISA_DEVICE(obj);
566     }
567     return 0;
568 }
569 
570 static const char * const fdc_container_path[] = {
571     "/unattached", "/peripheral", "/peripheral-anon"
572 };
573 
574 /*
575  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
576  * and ACPI objects.
577  */
578 static ISADevice *pc_find_fdc0(void)
579 {
580     int i;
581     Object *container;
582     CheckFdcState state = { 0 };
583 
584     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
585         container = container_get(qdev_get_machine(), fdc_container_path[i]);
586         object_child_foreach(container, check_fdc, &state);
587     }
588 
589     if (state.multiple) {
590         warn_report("multiple floppy disk controllers with "
591                     "iobase=0x3f0 have been found");
592         error_printf("the one being picked for CMOS setup might not reflect "
593                      "your intent");
594     }
595 
596     return state.floppy;
597 }
598 
599 static void pc_cmos_init_late(void *opaque)
600 {
601     pc_cmos_init_late_arg *arg = opaque;
602     ISADevice *s = arg->rtc_state;
603     int16_t cylinders;
604     int8_t heads, sectors;
605     int val;
606     int i, trans;
607 
608     val = 0;
609     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
610                                            &cylinders, &heads, &sectors) >= 0) {
611         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
612         val |= 0xf0;
613     }
614     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
615                                            &cylinders, &heads, &sectors) >= 0) {
616         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
617         val |= 0x0f;
618     }
619     rtc_set_memory(s, 0x12, val);
620 
621     val = 0;
622     for (i = 0; i < 4; i++) {
623         /* NOTE: ide_get_geometry() returns the physical
624            geometry.  It is always such that: 1 <= sects <= 63, 1
625            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
626            geometry can be different if a translation is done. */
627         if (arg->idebus[i / 2] &&
628             ide_get_geometry(arg->idebus[i / 2], i % 2,
629                              &cylinders, &heads, &sectors) >= 0) {
630             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
631             assert((trans & ~3) == 0);
632             val |= trans << (i * 2);
633         }
634     }
635     rtc_set_memory(s, 0x39, val);
636 
637     pc_cmos_init_floppy(s, pc_find_fdc0());
638 
639     qemu_unregister_reset(pc_cmos_init_late, opaque);
640 }
641 
642 void pc_cmos_init(PCMachineState *pcms,
643                   BusState *idebus0, BusState *idebus1,
644                   ISADevice *s)
645 {
646     int val;
647     static pc_cmos_init_late_arg arg;
648     X86MachineState *x86ms = X86_MACHINE(pcms);
649 
650     /* various important CMOS locations needed by PC/Bochs bios */
651 
652     /* memory size */
653     /* base memory (first MiB) */
654     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
655     rtc_set_memory(s, 0x15, val);
656     rtc_set_memory(s, 0x16, val >> 8);
657     /* extended memory (next 64MiB) */
658     if (x86ms->below_4g_mem_size > 1 * MiB) {
659         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
660     } else {
661         val = 0;
662     }
663     if (val > 65535)
664         val = 65535;
665     rtc_set_memory(s, 0x17, val);
666     rtc_set_memory(s, 0x18, val >> 8);
667     rtc_set_memory(s, 0x30, val);
668     rtc_set_memory(s, 0x31, val >> 8);
669     /* memory between 16MiB and 4GiB */
670     if (x86ms->below_4g_mem_size > 16 * MiB) {
671         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
672     } else {
673         val = 0;
674     }
675     if (val > 65535)
676         val = 65535;
677     rtc_set_memory(s, 0x34, val);
678     rtc_set_memory(s, 0x35, val >> 8);
679     /* memory above 4GiB */
680     val = x86ms->above_4g_mem_size / 65536;
681     rtc_set_memory(s, 0x5b, val);
682     rtc_set_memory(s, 0x5c, val >> 8);
683     rtc_set_memory(s, 0x5d, val >> 16);
684 
685     object_property_add_link(OBJECT(pcms), "rtc_state",
686                              TYPE_ISA_DEVICE,
687                              (Object **)&x86ms->rtc,
688                              object_property_allow_set_link,
689                              OBJ_PROP_LINK_STRONG);
690     object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
691                              &error_abort);
692 
693     set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
694 
695     val = 0;
696     val |= 0x02; /* FPU is there */
697     val |= 0x04; /* PS/2 mouse installed */
698     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
699 
700     /* hard drives and FDC */
701     arg.rtc_state = s;
702     arg.idebus[0] = idebus0;
703     arg.idebus[1] = idebus1;
704     qemu_register_reset(pc_cmos_init_late, &arg);
705 }
706 
707 static void handle_a20_line_change(void *opaque, int irq, int level)
708 {
709     X86CPU *cpu = opaque;
710 
711     /* XXX: send to all CPUs ? */
712     /* XXX: add logic to handle multiple A20 line sources */
713     x86_cpu_set_a20(cpu, level);
714 }
715 
716 #define NE2000_NB_MAX 6
717 
718 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
719                                               0x280, 0x380 };
720 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
721 
722 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
723 {
724     static int nb_ne2k = 0;
725 
726     if (nb_ne2k == NE2000_NB_MAX)
727         return;
728     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
729                     ne2000_irq[nb_ne2k], nd);
730     nb_ne2k++;
731 }
732 
733 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
734 {
735     X86CPU *cpu = opaque;
736 
737     if (level) {
738         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
739     }
740 }
741 
742 static
743 void pc_machine_done(Notifier *notifier, void *data)
744 {
745     PCMachineState *pcms = container_of(notifier,
746                                         PCMachineState, machine_done);
747     X86MachineState *x86ms = X86_MACHINE(pcms);
748 
749     cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
750                               &error_fatal);
751 
752     if (pcms->cxl_devices_state.is_enabled) {
753         cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
754     }
755 
756     /* set the number of CPUs */
757     x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
758 
759     fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
760 
761     acpi_setup();
762     if (x86ms->fw_cfg) {
763         fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
764         fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
765         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
766         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
767     }
768 }
769 
770 void pc_guest_info_init(PCMachineState *pcms)
771 {
772     X86MachineState *x86ms = X86_MACHINE(pcms);
773 
774     x86ms->apic_xrupt_override = true;
775     pcms->machine_done.notify = pc_machine_done;
776     qemu_add_machine_init_done_notifier(&pcms->machine_done);
777 }
778 
779 /* setup pci memory address space mapping into system address space */
780 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
781                             MemoryRegion *pci_address_space)
782 {
783     /* Set to lower priority than RAM */
784     memory_region_add_subregion_overlap(system_memory, 0x0,
785                                         pci_address_space, -1);
786 }
787 
788 void xen_load_linux(PCMachineState *pcms)
789 {
790     int i;
791     FWCfgState *fw_cfg;
792     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
793     X86MachineState *x86ms = X86_MACHINE(pcms);
794 
795     assert(MACHINE(pcms)->kernel_filename != NULL);
796 
797     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
798     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
799     rom_set_fw(fw_cfg);
800 
801     x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
802                    pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
803     for (i = 0; i < nb_option_roms; i++) {
804         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
805                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
806                !strcmp(option_rom[i].name, "pvh.bin") ||
807                !strcmp(option_rom[i].name, "multiboot.bin") ||
808                !strcmp(option_rom[i].name, "multiboot_dma.bin"));
809         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
810     }
811     x86ms->fw_cfg = fw_cfg;
812 }
813 
814 #define PC_ROM_MIN_VGA     0xc0000
815 #define PC_ROM_MIN_OPTION  0xc8000
816 #define PC_ROM_MAX         0xe0000
817 #define PC_ROM_ALIGN       0x800
818 #define PC_ROM_SIZE        (PC_ROM_MAX - PC_ROM_MIN_VGA)
819 
820 static hwaddr pc_above_4g_end(PCMachineState *pcms)
821 {
822     X86MachineState *x86ms = X86_MACHINE(pcms);
823 
824     if (pcms->sgx_epc.size != 0) {
825         return sgx_epc_above_4g_end(&pcms->sgx_epc);
826     }
827 
828     return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
829 }
830 
831 static void pc_get_device_memory_range(PCMachineState *pcms,
832                                        hwaddr *base,
833                                        ram_addr_t *device_mem_size)
834 {
835     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
836     MachineState *machine = MACHINE(pcms);
837     ram_addr_t size;
838     hwaddr addr;
839 
840     size = machine->maxram_size - machine->ram_size;
841     addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
842 
843     if (pcmc->enforce_aligned_dimm) {
844         /* size device region assuming 1G page max alignment per slot */
845         size += (1 * GiB) * machine->ram_slots;
846     }
847 
848     *base = addr;
849     *device_mem_size = size;
850 }
851 
852 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
853 {
854     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
855     hwaddr cxl_base;
856     ram_addr_t size;
857 
858     if (pcmc->has_reserved_memory) {
859         pc_get_device_memory_range(pcms, &cxl_base, &size);
860         cxl_base += size;
861     } else {
862         cxl_base = pc_above_4g_end(pcms);
863     }
864 
865     return cxl_base;
866 }
867 
868 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
869 {
870     uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
871 
872     if (pcms->cxl_devices_state.fixed_windows) {
873         GList *it;
874 
875         start = ROUND_UP(start, 256 * MiB);
876         for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
877             CXLFixedWindow *fw = it->data;
878             start += fw->size;
879         }
880     }
881 
882     return start;
883 }
884 
885 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
886 {
887     X86CPU *cpu = X86_CPU(first_cpu);
888 
889     /* 32-bit systems don't have hole64 thus return max CPU address */
890     if (cpu->phys_bits <= 32) {
891         return ((hwaddr)1 << cpu->phys_bits) - 1;
892     }
893 
894     return pc_pci_hole64_start() + pci_hole64_size - 1;
895 }
896 
897 /*
898  * AMD systems with an IOMMU have an additional hole close to the
899  * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
900  * on kernel version, VFIO may or may not let you DMA map those ranges.
901  * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
902  * with certain memory sizes. It's also wrong to use those IOVA ranges
903  * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
904  * The ranges reserved for Hyper-Transport are:
905  *
906  * FD_0000_0000h - FF_FFFF_FFFFh
907  *
908  * The ranges represent the following:
909  *
910  * Base Address   Top Address  Use
911  *
912  * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
913  * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
914  * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
915  * FD_F910_0000h FD_F91F_FFFFh System Management
916  * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
917  * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
918  * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
919  * FD_FE00_0000h FD_FFFF_FFFFh Configuration
920  * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
921  * FE_2000_0000h FF_FFFF_FFFFh Reserved
922  *
923  * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
924  * Table 3: Special Address Controls (GPA) for more information.
925  */
926 #define AMD_HT_START         0xfd00000000UL
927 #define AMD_HT_END           0xffffffffffUL
928 #define AMD_ABOVE_1TB_START  (AMD_HT_END + 1)
929 #define AMD_HT_SIZE          (AMD_ABOVE_1TB_START - AMD_HT_START)
930 
931 void pc_memory_init(PCMachineState *pcms,
932                     MemoryRegion *system_memory,
933                     MemoryRegion *rom_memory,
934                     MemoryRegion **ram_memory,
935                     uint64_t pci_hole64_size)
936 {
937     int linux_boot, i;
938     MemoryRegion *option_rom_mr;
939     MemoryRegion *ram_below_4g, *ram_above_4g;
940     FWCfgState *fw_cfg;
941     MachineState *machine = MACHINE(pcms);
942     MachineClass *mc = MACHINE_GET_CLASS(machine);
943     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
944     X86MachineState *x86ms = X86_MACHINE(pcms);
945     hwaddr maxphysaddr, maxusedaddr;
946     hwaddr cxl_base, cxl_resv_end = 0;
947     X86CPU *cpu = X86_CPU(first_cpu);
948 
949     assert(machine->ram_size == x86ms->below_4g_mem_size +
950                                 x86ms->above_4g_mem_size);
951 
952     linux_boot = (machine->kernel_filename != NULL);
953 
954     /*
955      * The HyperTransport range close to the 1T boundary is unique to AMD
956      * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
957      * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
958      * older machine types (<= 7.0) for compatibility purposes.
959      */
960     if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
961         /* Bail out if max possible address does not cross HT range */
962         if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
963             x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
964         }
965 
966         /*
967          * Advertise the HT region if address space covers the reserved
968          * region or if we relocate.
969          */
970         if (cpu->phys_bits >= 40) {
971             e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
972         }
973     }
974 
975     /*
976      * phys-bits is required to be appropriately configured
977      * to make sure max used GPA is reachable.
978      */
979     maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
980     maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
981     if (maxphysaddr < maxusedaddr) {
982         error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
983                      " phys-bits too low (%u)",
984                      maxphysaddr, maxusedaddr, cpu->phys_bits);
985         exit(EXIT_FAILURE);
986     }
987 
988     /*
989      * Split single memory region and use aliases to address portions of it,
990      * done for backwards compatibility with older qemus.
991      */
992     *ram_memory = machine->ram;
993     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
994     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
995                              0, x86ms->below_4g_mem_size);
996     memory_region_add_subregion(system_memory, 0, ram_below_4g);
997     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
998     if (x86ms->above_4g_mem_size > 0) {
999         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1000         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1001                                  machine->ram,
1002                                  x86ms->below_4g_mem_size,
1003                                  x86ms->above_4g_mem_size);
1004         memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1005                                     ram_above_4g);
1006         e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1007                        E820_RAM);
1008     }
1009 
1010     if (pcms->sgx_epc.size != 0) {
1011         e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1012     }
1013 
1014     if (!pcmc->has_reserved_memory &&
1015         (machine->ram_slots ||
1016          (machine->maxram_size > machine->ram_size))) {
1017 
1018         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1019                      mc->name);
1020         exit(EXIT_FAILURE);
1021     }
1022 
1023     /* always allocate the device memory information */
1024     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1025 
1026     /* initialize device memory address space */
1027     if (pcmc->has_reserved_memory &&
1028         (machine->ram_size < machine->maxram_size)) {
1029         ram_addr_t device_mem_size;
1030 
1031         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1032             error_report("unsupported amount of memory slots: %"PRIu64,
1033                          machine->ram_slots);
1034             exit(EXIT_FAILURE);
1035         }
1036 
1037         if (QEMU_ALIGN_UP(machine->maxram_size,
1038                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1039             error_report("maximum memory size must by aligned to multiple of "
1040                          "%d bytes", TARGET_PAGE_SIZE);
1041             exit(EXIT_FAILURE);
1042         }
1043 
1044         pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
1045 
1046         if ((machine->device_memory->base + device_mem_size) <
1047             device_mem_size) {
1048             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1049                          machine->maxram_size);
1050             exit(EXIT_FAILURE);
1051         }
1052 
1053         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1054                            "device-memory", device_mem_size);
1055         memory_region_add_subregion(system_memory, machine->device_memory->base,
1056                                     &machine->device_memory->mr);
1057     }
1058 
1059     if (pcms->cxl_devices_state.is_enabled) {
1060         MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1061         hwaddr cxl_size = MiB;
1062 
1063         cxl_base = pc_get_cxl_range_start(pcms);
1064         e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
1065         memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1066         memory_region_add_subregion(system_memory, cxl_base, mr);
1067         cxl_resv_end = cxl_base + cxl_size;
1068         if (pcms->cxl_devices_state.fixed_windows) {
1069             hwaddr cxl_fmw_base;
1070             GList *it;
1071 
1072             cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1073             for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1074                 CXLFixedWindow *fw = it->data;
1075 
1076                 fw->base = cxl_fmw_base;
1077                 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1078                                       "cxl-fixed-memory-region", fw->size);
1079                 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1080                 e820_add_entry(fw->base, fw->size, E820_RESERVED);
1081                 cxl_fmw_base += fw->size;
1082                 cxl_resv_end = cxl_fmw_base;
1083             }
1084         }
1085     }
1086 
1087     /* Initialize PC system firmware */
1088     pc_system_firmware_init(pcms, rom_memory);
1089 
1090     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1091     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1092                            &error_fatal);
1093     if (pcmc->pci_enabled) {
1094         memory_region_set_readonly(option_rom_mr, true);
1095     }
1096     memory_region_add_subregion_overlap(rom_memory,
1097                                         PC_ROM_MIN_VGA,
1098                                         option_rom_mr,
1099                                         1);
1100 
1101     fw_cfg = fw_cfg_arch_create(machine,
1102                                 x86ms->boot_cpus, x86ms->apic_id_limit);
1103 
1104     rom_set_fw(fw_cfg);
1105 
1106     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1107         uint64_t *val = g_malloc(sizeof(*val));
1108         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1109         uint64_t res_mem_end = machine->device_memory->base;
1110 
1111         if (!pcmc->broken_reserved_end) {
1112             res_mem_end += memory_region_size(&machine->device_memory->mr);
1113         }
1114 
1115         if (pcms->cxl_devices_state.is_enabled) {
1116             res_mem_end = cxl_resv_end;
1117         }
1118         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1119         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1120     }
1121 
1122     if (linux_boot) {
1123         x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1124                        pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
1125     }
1126 
1127     for (i = 0; i < nb_option_roms; i++) {
1128         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1129     }
1130     x86ms->fw_cfg = fw_cfg;
1131 
1132     /* Init default IOAPIC address space */
1133     x86ms->ioapic_as = &address_space_memory;
1134 
1135     /* Init ACPI memory hotplug IO base address */
1136     pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1137 }
1138 
1139 /*
1140  * The 64bit pci hole starts after "above 4G RAM" and
1141  * potentially the space reserved for memory hotplug.
1142  */
1143 uint64_t pc_pci_hole64_start(void)
1144 {
1145     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1146     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1147     MachineState *ms = MACHINE(pcms);
1148     uint64_t hole64_start = 0;
1149     ram_addr_t size = 0;
1150 
1151     if (pcms->cxl_devices_state.is_enabled) {
1152         hole64_start = pc_get_cxl_range_end(pcms);
1153     } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1154         pc_get_device_memory_range(pcms, &hole64_start, &size);
1155         if (!pcmc->broken_reserved_end) {
1156             hole64_start += size;
1157         }
1158     } else {
1159         hole64_start = pc_above_4g_end(pcms);
1160     }
1161 
1162     return ROUND_UP(hole64_start, 1 * GiB);
1163 }
1164 
1165 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1166 {
1167     DeviceState *dev = NULL;
1168 
1169     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1170     if (pci_bus) {
1171         PCIDevice *pcidev = pci_vga_init(pci_bus);
1172         dev = pcidev ? &pcidev->qdev : NULL;
1173     } else if (isa_bus) {
1174         ISADevice *isadev = isa_vga_init(isa_bus);
1175         dev = isadev ? DEVICE(isadev) : NULL;
1176     }
1177     rom_reset_order_override();
1178     return dev;
1179 }
1180 
1181 static const MemoryRegionOps ioport80_io_ops = {
1182     .write = ioport80_write,
1183     .read = ioport80_read,
1184     .endianness = DEVICE_NATIVE_ENDIAN,
1185     .impl = {
1186         .min_access_size = 1,
1187         .max_access_size = 1,
1188     },
1189 };
1190 
1191 static const MemoryRegionOps ioportF0_io_ops = {
1192     .write = ioportF0_write,
1193     .read = ioportF0_read,
1194     .endianness = DEVICE_NATIVE_ENDIAN,
1195     .impl = {
1196         .min_access_size = 1,
1197         .max_access_size = 1,
1198     },
1199 };
1200 
1201 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1202                             bool create_i8042, bool no_vmport)
1203 {
1204     int i;
1205     DriveInfo *fd[MAX_FD];
1206     qemu_irq *a20_line;
1207     ISADevice *fdc, *i8042, *port92, *vmmouse;
1208 
1209     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1210     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1211 
1212     for (i = 0; i < MAX_FD; i++) {
1213         fd[i] = drive_get(IF_FLOPPY, 0, i);
1214         create_fdctrl |= !!fd[i];
1215     }
1216     if (create_fdctrl) {
1217         fdc = isa_new(TYPE_ISA_FDC);
1218         if (fdc) {
1219             isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1220             isa_fdc_init_drives(fdc, fd);
1221         }
1222     }
1223 
1224     if (!create_i8042) {
1225         return;
1226     }
1227 
1228     i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1229     if (!no_vmport) {
1230         isa_create_simple(isa_bus, TYPE_VMPORT);
1231         vmmouse = isa_try_new("vmmouse");
1232     } else {
1233         vmmouse = NULL;
1234     }
1235     if (vmmouse) {
1236         object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1237                                  &error_abort);
1238         isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1239     }
1240     port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1241 
1242     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1243     i8042_setup_a20_line(i8042, a20_line[0]);
1244     qdev_connect_gpio_out_named(DEVICE(port92),
1245                                 PORT92_A20_LINE, 0, a20_line[1]);
1246     g_free(a20_line);
1247 }
1248 
1249 void pc_basic_device_init(struct PCMachineState *pcms,
1250                           ISABus *isa_bus, qemu_irq *gsi,
1251                           ISADevice **rtc_state,
1252                           bool create_fdctrl,
1253                           uint32_t hpet_irqs)
1254 {
1255     int i;
1256     DeviceState *hpet = NULL;
1257     int pit_isa_irq = 0;
1258     qemu_irq pit_alt_irq = NULL;
1259     qemu_irq rtc_irq = NULL;
1260     ISADevice *pit = NULL;
1261     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1262     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1263     X86MachineState *x86ms = X86_MACHINE(pcms);
1264 
1265     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1266     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1267 
1268     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1269     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1270 
1271     /*
1272      * Check if an HPET shall be created.
1273      *
1274      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1275      * when the HPET wants to take over. Thus we have to disable the latter.
1276      */
1277     if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1278                                kvm_has_pit_state2())) {
1279         hpet = qdev_try_new(TYPE_HPET);
1280         if (!hpet) {
1281             error_report("couldn't create HPET device");
1282             exit(1);
1283         }
1284         /*
1285          * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1286          * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1287          * IRQ2.
1288          */
1289         uint8_t compat = object_property_get_uint(OBJECT(hpet),
1290                 HPET_INTCAP, NULL);
1291         if (!compat) {
1292             qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1293         }
1294         sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1295         sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1296 
1297         for (i = 0; i < GSI_NUM_PINS; i++) {
1298             sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1299         }
1300         pit_isa_irq = -1;
1301         pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1302         rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1303     }
1304     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1305 
1306     qemu_register_boot_set(pc_boot_set, *rtc_state);
1307 
1308     if (!xen_enabled() &&
1309         (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1310         if (kvm_pit_in_kernel()) {
1311             pit = kvm_pit_init(isa_bus, 0x40);
1312         } else {
1313             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1314         }
1315         if (hpet) {
1316             /* connect PIT to output control line of the HPET */
1317             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1318         }
1319         pcspk_init(pcms->pcspk, isa_bus, pit);
1320     }
1321 
1322     i8257_dma_init(isa_bus, 0);
1323 
1324     /* Super I/O */
1325     pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1326                     pcms->vmport != ON_OFF_AUTO_ON);
1327 }
1328 
1329 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1330 {
1331     int i;
1332 
1333     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1334     for (i = 0; i < nb_nics; i++) {
1335         NICInfo *nd = &nd_table[i];
1336         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1337 
1338         if (g_str_equal(model, "ne2k_isa")) {
1339             pc_init_ne2k_isa(isa_bus, nd);
1340         } else {
1341             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1342         }
1343     }
1344     rom_reset_order_override();
1345 }
1346 
1347 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1348 {
1349     qemu_irq *i8259;
1350 
1351     if (kvm_pic_in_kernel()) {
1352         i8259 = kvm_i8259_init(isa_bus);
1353     } else if (xen_enabled()) {
1354         i8259 = xen_interrupt_controller_init();
1355     } else {
1356         i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1357     }
1358 
1359     for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1360         i8259_irqs[i] = i8259[i];
1361     }
1362 
1363     g_free(i8259);
1364 }
1365 
1366 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1367                                Error **errp)
1368 {
1369     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1370     const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1371     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1372     const MachineState *ms = MACHINE(hotplug_dev);
1373     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1374     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1375     Error *local_err = NULL;
1376 
1377     /*
1378      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1379      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1380      * addition to cover this case.
1381      */
1382     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1383         error_setg(errp,
1384                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1385         return;
1386     }
1387 
1388     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1389         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1390         return;
1391     }
1392 
1393     hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1394     if (local_err) {
1395         error_propagate(errp, local_err);
1396         return;
1397     }
1398 
1399     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1400                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1401 }
1402 
1403 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1404                            DeviceState *dev, Error **errp)
1405 {
1406     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1407     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1408     MachineState *ms = MACHINE(hotplug_dev);
1409     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1410 
1411     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1412 
1413     if (is_nvdimm) {
1414         nvdimm_plug(ms->nvdimms_state);
1415     }
1416 
1417     hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1418 }
1419 
1420 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1421                                      DeviceState *dev, Error **errp)
1422 {
1423     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1424 
1425     /*
1426      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1427      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1428      * addition to cover this case.
1429      */
1430     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1431         error_setg(errp,
1432                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1433         return;
1434     }
1435 
1436     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1437         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1438         return;
1439     }
1440 
1441     hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1442                                    errp);
1443 }
1444 
1445 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1446                              DeviceState *dev, Error **errp)
1447 {
1448     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1449     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1450     Error *local_err = NULL;
1451 
1452     hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1453     if (local_err) {
1454         goto out;
1455     }
1456 
1457     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1458     qdev_unrealize(dev);
1459  out:
1460     error_propagate(errp, local_err);
1461 }
1462 
1463 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1464                                       DeviceState *dev, Error **errp)
1465 {
1466     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1467     Error *local_err = NULL;
1468 
1469     if (!hotplug_dev2 && dev->hotplugged) {
1470         /*
1471          * Without a bus hotplug handler, we cannot control the plug/unplug
1472          * order. We should never reach this point when hotplugging on x86,
1473          * however, better add a safety net.
1474          */
1475         error_setg(errp, "hotplug of virtio based memory devices not supported"
1476                    " on this bus.");
1477         return;
1478     }
1479     /*
1480      * First, see if we can plug this memory device at all. If that
1481      * succeeds, branch of to the actual hotplug handler.
1482      */
1483     memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1484                            &local_err);
1485     if (!local_err && hotplug_dev2) {
1486         hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1487     }
1488     error_propagate(errp, local_err);
1489 }
1490 
1491 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1492                                   DeviceState *dev, Error **errp)
1493 {
1494     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1495     Error *local_err = NULL;
1496 
1497     /*
1498      * Plug the memory device first and then branch off to the actual
1499      * hotplug handler. If that one fails, we can easily undo the memory
1500      * device bits.
1501      */
1502     memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1503     if (hotplug_dev2) {
1504         hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1505         if (local_err) {
1506             memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1507         }
1508     }
1509     error_propagate(errp, local_err);
1510 }
1511 
1512 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1513                                             DeviceState *dev, Error **errp)
1514 {
1515     /* We don't support hot unplug of virtio based memory devices */
1516     error_setg(errp, "virtio based memory devices cannot be unplugged.");
1517 }
1518 
1519 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1520                                     DeviceState *dev, Error **errp)
1521 {
1522     /* We don't support hot unplug of virtio based memory devices */
1523 }
1524 
1525 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1526                                           DeviceState *dev, Error **errp)
1527 {
1528     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1529         pc_memory_pre_plug(hotplug_dev, dev, errp);
1530     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1531         x86_cpu_pre_plug(hotplug_dev, dev, errp);
1532     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1533                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1534         pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1535     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1536         /* Declare the APIC range as the reserved MSI region */
1537         char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1538                                               VIRTIO_IOMMU_RESV_MEM_T_MSI);
1539 
1540         object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1541         object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1542                                 resv_prop_str, errp);
1543         g_free(resv_prop_str);
1544     }
1545 
1546     if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1547         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1548         PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1549 
1550         if (pcms->iommu) {
1551             error_setg(errp, "QEMU does not support multiple vIOMMUs "
1552                        "for x86 yet.");
1553             return;
1554         }
1555         pcms->iommu = dev;
1556     }
1557 }
1558 
1559 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1560                                       DeviceState *dev, Error **errp)
1561 {
1562     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1563         pc_memory_plug(hotplug_dev, dev, errp);
1564     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1565         x86_cpu_plug(hotplug_dev, dev, errp);
1566     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1567                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1568         pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1569     }
1570 }
1571 
1572 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1573                                                 DeviceState *dev, Error **errp)
1574 {
1575     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1576         pc_memory_unplug_request(hotplug_dev, dev, errp);
1577     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1578         x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1579     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1580                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1581         pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1582     } else {
1583         error_setg(errp, "acpi: device unplug request for not supported device"
1584                    " type: %s", object_get_typename(OBJECT(dev)));
1585     }
1586 }
1587 
1588 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1589                                         DeviceState *dev, Error **errp)
1590 {
1591     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1592         pc_memory_unplug(hotplug_dev, dev, errp);
1593     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1594         x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1595     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1596                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1597         pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1598     } else {
1599         error_setg(errp, "acpi: device unplug for not supported device"
1600                    " type: %s", object_get_typename(OBJECT(dev)));
1601     }
1602 }
1603 
1604 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1605                                              DeviceState *dev)
1606 {
1607     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1608         object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1609         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1610         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1611         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1612         object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1613         return HOTPLUG_HANDLER(machine);
1614     }
1615 
1616     return NULL;
1617 }
1618 
1619 static void
1620 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1621                                          const char *name, void *opaque,
1622                                          Error **errp)
1623 {
1624     MachineState *ms = MACHINE(obj);
1625     int64_t value = 0;
1626 
1627     if (ms->device_memory) {
1628         value = memory_region_size(&ms->device_memory->mr);
1629     }
1630 
1631     visit_type_int(v, name, &value, errp);
1632 }
1633 
1634 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1635                                   void *opaque, Error **errp)
1636 {
1637     PCMachineState *pcms = PC_MACHINE(obj);
1638     OnOffAuto vmport = pcms->vmport;
1639 
1640     visit_type_OnOffAuto(v, name, &vmport, errp);
1641 }
1642 
1643 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1644                                   void *opaque, Error **errp)
1645 {
1646     PCMachineState *pcms = PC_MACHINE(obj);
1647 
1648     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1649 }
1650 
1651 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1652 {
1653     PCMachineState *pcms = PC_MACHINE(obj);
1654 
1655     return pcms->smbus_enabled;
1656 }
1657 
1658 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1659 {
1660     PCMachineState *pcms = PC_MACHINE(obj);
1661 
1662     pcms->smbus_enabled = value;
1663 }
1664 
1665 static bool pc_machine_get_sata(Object *obj, Error **errp)
1666 {
1667     PCMachineState *pcms = PC_MACHINE(obj);
1668 
1669     return pcms->sata_enabled;
1670 }
1671 
1672 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1673 {
1674     PCMachineState *pcms = PC_MACHINE(obj);
1675 
1676     pcms->sata_enabled = value;
1677 }
1678 
1679 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1680 {
1681     PCMachineState *pcms = PC_MACHINE(obj);
1682 
1683     return pcms->hpet_enabled;
1684 }
1685 
1686 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1687 {
1688     PCMachineState *pcms = PC_MACHINE(obj);
1689 
1690     pcms->hpet_enabled = value;
1691 }
1692 
1693 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1694 {
1695     PCMachineState *pcms = PC_MACHINE(obj);
1696 
1697     return pcms->i8042_enabled;
1698 }
1699 
1700 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1701 {
1702     PCMachineState *pcms = PC_MACHINE(obj);
1703 
1704     pcms->i8042_enabled = value;
1705 }
1706 
1707 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1708 {
1709     PCMachineState *pcms = PC_MACHINE(obj);
1710 
1711     return pcms->default_bus_bypass_iommu;
1712 }
1713 
1714 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1715                                                     Error **errp)
1716 {
1717     PCMachineState *pcms = PC_MACHINE(obj);
1718 
1719     pcms->default_bus_bypass_iommu = value;
1720 }
1721 
1722 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1723                                      void *opaque, Error **errp)
1724 {
1725     PCMachineState *pcms = PC_MACHINE(obj);
1726     SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1727 
1728     visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1729 }
1730 
1731 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1732                                      void *opaque, Error **errp)
1733 {
1734     PCMachineState *pcms = PC_MACHINE(obj);
1735 
1736     visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1737 }
1738 
1739 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1740                                             const char *name, void *opaque,
1741                                             Error **errp)
1742 {
1743     PCMachineState *pcms = PC_MACHINE(obj);
1744     uint64_t value = pcms->max_ram_below_4g;
1745 
1746     visit_type_size(v, name, &value, errp);
1747 }
1748 
1749 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1750                                             const char *name, void *opaque,
1751                                             Error **errp)
1752 {
1753     PCMachineState *pcms = PC_MACHINE(obj);
1754     uint64_t value;
1755 
1756     if (!visit_type_size(v, name, &value, errp)) {
1757         return;
1758     }
1759     if (value > 4 * GiB) {
1760         error_setg(errp,
1761                    "Machine option 'max-ram-below-4g=%"PRIu64
1762                    "' expects size less than or equal to 4G", value);
1763         return;
1764     }
1765 
1766     if (value < 1 * MiB) {
1767         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1768                     "BIOS may not work with less than 1MiB", value);
1769     }
1770 
1771     pcms->max_ram_below_4g = value;
1772 }
1773 
1774 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1775                                        const char *name, void *opaque,
1776                                        Error **errp)
1777 {
1778     PCMachineState *pcms = PC_MACHINE(obj);
1779     uint64_t value = pcms->max_fw_size;
1780 
1781     visit_type_size(v, name, &value, errp);
1782 }
1783 
1784 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1785                                        const char *name, void *opaque,
1786                                        Error **errp)
1787 {
1788     PCMachineState *pcms = PC_MACHINE(obj);
1789     Error *error = NULL;
1790     uint64_t value;
1791 
1792     visit_type_size(v, name, &value, &error);
1793     if (error) {
1794         error_propagate(errp, error);
1795         return;
1796     }
1797 
1798     /*
1799     * We don't have a theoretically justifiable exact lower bound on the base
1800     * address of any flash mapping. In practice, the IO-APIC MMIO range is
1801     * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1802     * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1803     * size.
1804     */
1805     if (value > 16 * MiB) {
1806         error_setg(errp,
1807                    "User specified max allowed firmware size %" PRIu64 " is "
1808                    "greater than 16MiB. If combined firwmare size exceeds "
1809                    "16MiB the system may not boot, or experience intermittent"
1810                    "stability issues.",
1811                    value);
1812         return;
1813     }
1814 
1815     pcms->max_fw_size = value;
1816 }
1817 
1818 
1819 static void pc_machine_initfn(Object *obj)
1820 {
1821     PCMachineState *pcms = PC_MACHINE(obj);
1822 
1823 #ifdef CONFIG_VMPORT
1824     pcms->vmport = ON_OFF_AUTO_AUTO;
1825 #else
1826     pcms->vmport = ON_OFF_AUTO_OFF;
1827 #endif /* CONFIG_VMPORT */
1828     pcms->max_ram_below_4g = 0; /* use default */
1829     pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1830 
1831     /* acpi build is enabled by default if machine supports it */
1832     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1833     pcms->smbus_enabled = true;
1834     pcms->sata_enabled = true;
1835     pcms->i8042_enabled = true;
1836     pcms->max_fw_size = 8 * MiB;
1837 #ifdef CONFIG_HPET
1838     pcms->hpet_enabled = true;
1839 #endif
1840     pcms->default_bus_bypass_iommu = false;
1841 
1842     pc_system_flash_create(pcms);
1843     pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1844     object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1845                               OBJECT(pcms->pcspk), "audiodev");
1846     cxl_machine_init(obj, &pcms->cxl_devices_state);
1847 }
1848 
1849 static void pc_machine_reset(MachineState *machine)
1850 {
1851     CPUState *cs;
1852     X86CPU *cpu;
1853 
1854     qemu_devices_reset();
1855 
1856     /* Reset APIC after devices have been reset to cancel
1857      * any changes that qemu_devices_reset() might have done.
1858      */
1859     CPU_FOREACH(cs) {
1860         cpu = X86_CPU(cs);
1861 
1862         if (cpu->apic_state) {
1863             device_legacy_reset(cpu->apic_state);
1864         }
1865     }
1866 }
1867 
1868 static void pc_machine_wakeup(MachineState *machine)
1869 {
1870     cpu_synchronize_all_states();
1871     pc_machine_reset(machine);
1872     cpu_synchronize_all_post_reset();
1873 }
1874 
1875 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1876 {
1877     X86IOMMUState *iommu = x86_iommu_get_default();
1878     IntelIOMMUState *intel_iommu;
1879 
1880     if (iommu &&
1881         object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1882         object_dynamic_cast((Object *)dev, "vfio-pci")) {
1883         intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1884         if (!intel_iommu->caching_mode) {
1885             error_setg(errp, "Device assignment is not allowed without "
1886                        "enabling caching-mode=on for Intel IOMMU.");
1887             return false;
1888         }
1889     }
1890 
1891     return true;
1892 }
1893 
1894 static void pc_machine_class_init(ObjectClass *oc, void *data)
1895 {
1896     MachineClass *mc = MACHINE_CLASS(oc);
1897     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1898     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1899 
1900     pcmc->pci_enabled = true;
1901     pcmc->has_acpi_build = true;
1902     pcmc->rsdp_in_ram = true;
1903     pcmc->smbios_defaults = true;
1904     pcmc->smbios_uuid_encoded = true;
1905     pcmc->gigabyte_align = true;
1906     pcmc->has_reserved_memory = true;
1907     pcmc->kvmclock_enabled = true;
1908     pcmc->enforce_aligned_dimm = true;
1909     pcmc->enforce_amd_1tb_hole = true;
1910     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1911      * to be used at the moment, 32K should be enough for a while.  */
1912     pcmc->acpi_data_size = 0x20000 + 0x8000;
1913     pcmc->pvh_enabled = true;
1914     pcmc->kvmclock_create_always = true;
1915     assert(!mc->get_hotplug_handler);
1916     mc->get_hotplug_handler = pc_get_hotplug_handler;
1917     mc->hotplug_allowed = pc_hotplug_allowed;
1918     mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1919     mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1920     mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1921     mc->auto_enable_numa_with_memhp = true;
1922     mc->auto_enable_numa_with_memdev = true;
1923     mc->has_hotpluggable_cpus = true;
1924     mc->default_boot_order = "cad";
1925     mc->block_default_type = IF_IDE;
1926     mc->max_cpus = 255;
1927     mc->reset = pc_machine_reset;
1928     mc->wakeup = pc_machine_wakeup;
1929     hc->pre_plug = pc_machine_device_pre_plug_cb;
1930     hc->plug = pc_machine_device_plug_cb;
1931     hc->unplug_request = pc_machine_device_unplug_request_cb;
1932     hc->unplug = pc_machine_device_unplug_cb;
1933     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1934     mc->nvdimm_supported = true;
1935     mc->smp_props.dies_supported = true;
1936     mc->default_ram_id = "pc.ram";
1937 
1938     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1939         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1940         NULL, NULL);
1941     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1942         "Maximum ram below the 4G boundary (32bit boundary)");
1943 
1944     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1945         pc_machine_get_device_memory_region_size, NULL,
1946         NULL, NULL);
1947 
1948     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1949         pc_machine_get_vmport, pc_machine_set_vmport,
1950         NULL, NULL);
1951     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1952         "Enable vmport (pc & q35)");
1953 
1954     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1955         pc_machine_get_smbus, pc_machine_set_smbus);
1956     object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1957         "Enable/disable system management bus");
1958 
1959     object_class_property_add_bool(oc, PC_MACHINE_SATA,
1960         pc_machine_get_sata, pc_machine_set_sata);
1961     object_class_property_set_description(oc, PC_MACHINE_SATA,
1962         "Enable/disable Serial ATA bus");
1963 
1964     object_class_property_add_bool(oc, "hpet",
1965         pc_machine_get_hpet, pc_machine_set_hpet);
1966     object_class_property_set_description(oc, "hpet",
1967         "Enable/disable high precision event timer emulation");
1968 
1969     object_class_property_add_bool(oc, PC_MACHINE_I8042,
1970         pc_machine_get_i8042, pc_machine_set_i8042);
1971 
1972     object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1973         pc_machine_get_default_bus_bypass_iommu,
1974         pc_machine_set_default_bus_bypass_iommu);
1975 
1976     object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1977         pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1978         NULL, NULL);
1979     object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1980         "Maximum combined firmware size");
1981 
1982     object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1983         pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1984         NULL, NULL);
1985     object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1986         "SMBIOS Entry Point type [32, 64]");
1987 }
1988 
1989 static const TypeInfo pc_machine_info = {
1990     .name = TYPE_PC_MACHINE,
1991     .parent = TYPE_X86_MACHINE,
1992     .abstract = true,
1993     .instance_size = sizeof(PCMachineState),
1994     .instance_init = pc_machine_initfn,
1995     .class_size = sizeof(PCMachineClass),
1996     .class_init = pc_machine_class_init,
1997     .interfaces = (InterfaceInfo[]) {
1998          { TYPE_HOTPLUG_HANDLER },
1999          { }
2000     },
2001 };
2002 
2003 static void pc_machine_register_types(void)
2004 {
2005     type_register_static(&pc_machine_info);
2006 }
2007 
2008 type_init(pc_machine_register_types)
2009