1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/i386/apic.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "sysemu/cpus.h" 34 #include "hw/block/fdc.h" 35 #include "hw/ide.h" 36 #include "hw/pci/pci.h" 37 #include "hw/pci/pci_bus.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/timer/hpet.h" 40 #include "hw/firmware/smbios.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "migration/vmstate.h" 44 #include "multiboot.h" 45 #include "hw/timer/mc146818rtc.h" 46 #include "hw/dma/i8257.h" 47 #include "hw/timer/i8254.h" 48 #include "hw/input/i8042.h" 49 #include "hw/irq.h" 50 #include "hw/audio/pcspk.h" 51 #include "hw/pci/msi.h" 52 #include "hw/sysbus.h" 53 #include "sysemu/sysemu.h" 54 #include "sysemu/tcg.h" 55 #include "sysemu/numa.h" 56 #include "sysemu/kvm.h" 57 #include "sysemu/qtest.h" 58 #include "sysemu/reset.h" 59 #include "sysemu/runstate.h" 60 #include "kvm_i386.h" 61 #include "hw/xen/xen.h" 62 #include "hw/xen/start_info.h" 63 #include "ui/qemu-spice.h" 64 #include "exec/memory.h" 65 #include "exec/address-spaces.h" 66 #include "sysemu/arch_init.h" 67 #include "qemu/bitmap.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "qemu/option.h" 71 #include "hw/acpi/acpi.h" 72 #include "hw/acpi/cpu_hotplug.h" 73 #include "hw/boards.h" 74 #include "acpi-build.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "qapi/error.h" 77 #include "qapi/qapi-visit-common.h" 78 #include "qapi/visitor.h" 79 #include "qom/cpu.h" 80 #include "hw/nmi.h" 81 #include "hw/usb.h" 82 #include "hw/i386/intel_iommu.h" 83 #include "hw/net/ne2000-isa.h" 84 #include "standard-headers/asm-x86/bootparam.h" 85 #include "hw/virtio/virtio-pmem-pci.h" 86 #include "hw/mem/memory-device.h" 87 #include "sysemu/replay.h" 88 #include "qapi/qmp/qerror.h" 89 #include "config-devices.h" 90 91 /* debug PC/ISA interrupts */ 92 //#define DEBUG_IRQ 93 94 #ifdef DEBUG_IRQ 95 #define DPRINTF(fmt, ...) \ 96 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 97 #else 98 #define DPRINTF(fmt, ...) 99 #endif 100 101 #define E820_NR_ENTRIES 16 102 103 struct e820_entry { 104 uint64_t address; 105 uint64_t length; 106 uint32_t type; 107 } QEMU_PACKED __attribute((__aligned__(4))); 108 109 struct e820_table { 110 uint32_t count; 111 struct e820_entry entry[E820_NR_ENTRIES]; 112 } QEMU_PACKED __attribute((__aligned__(4))); 113 114 static struct e820_table e820_reserve; 115 static struct e820_entry *e820_table; 116 static unsigned e820_entries; 117 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 118 119 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 120 static size_t pvh_start_addr; 121 122 GlobalProperty pc_compat_4_0[] = {}; 123 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 124 125 GlobalProperty pc_compat_3_1[] = { 126 { "intel-iommu", "dma-drain", "off" }, 127 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 128 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 129 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 130 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 131 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 132 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 133 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 134 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 135 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 136 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 137 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 138 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 139 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 140 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 141 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 142 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 143 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 144 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 145 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 146 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 147 }; 148 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 149 150 GlobalProperty pc_compat_3_0[] = { 151 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 152 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 153 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 154 }; 155 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 156 157 GlobalProperty pc_compat_2_12[] = { 158 { TYPE_X86_CPU, "legacy-cache", "on" }, 159 { TYPE_X86_CPU, "topoext", "off" }, 160 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 161 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 162 }; 163 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 164 165 GlobalProperty pc_compat_2_11[] = { 166 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 168 }; 169 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 170 171 GlobalProperty pc_compat_2_10[] = { 172 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 173 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 174 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 175 }; 176 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 177 178 GlobalProperty pc_compat_2_9[] = { 179 { "mch", "extended-tseg-mbytes", "0" }, 180 }; 181 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 182 183 GlobalProperty pc_compat_2_8[] = { 184 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 185 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 186 { "ICH9-LPC", "x-smi-broadcast", "off" }, 187 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 188 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 189 }; 190 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 191 192 GlobalProperty pc_compat_2_7[] = { 193 { TYPE_X86_CPU, "l3-cache", "off" }, 194 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 195 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 196 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 197 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 198 { "isa-pcspk", "migrate", "off" }, 199 }; 200 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 201 202 GlobalProperty pc_compat_2_6[] = { 203 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 204 { "vmxnet3", "romfile", "" }, 205 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 206 { "apic-common", "legacy-instance-id", "on", } 207 }; 208 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 209 210 GlobalProperty pc_compat_2_5[] = {}; 211 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 212 213 GlobalProperty pc_compat_2_4[] = { 214 PC_CPU_MODEL_IDS("2.4.0") 215 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 216 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 217 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 218 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 219 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 220 { TYPE_X86_CPU, "check", "off" }, 221 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 222 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 223 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 224 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 225 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 226 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 227 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 228 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 229 }; 230 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 231 232 GlobalProperty pc_compat_2_3[] = { 233 PC_CPU_MODEL_IDS("2.3.0") 234 { TYPE_X86_CPU, "arat", "off" }, 235 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 236 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 237 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 238 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 239 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 240 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 241 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 242 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 254 }; 255 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 256 257 GlobalProperty pc_compat_2_2[] = { 258 PC_CPU_MODEL_IDS("2.2.0") 259 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 274 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 275 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 276 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 277 }; 278 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 279 280 GlobalProperty pc_compat_2_1[] = { 281 PC_CPU_MODEL_IDS("2.1.0") 282 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 283 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 284 }; 285 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 286 287 GlobalProperty pc_compat_2_0[] = { 288 PC_CPU_MODEL_IDS("2.0.0") 289 { "virtio-scsi-pci", "any_layout", "off" }, 290 { "PIIX4_PM", "memory-hotplug-support", "off" }, 291 { "apic", "version", "0x11" }, 292 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 293 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 294 { "pci-serial", "prog_if", "0" }, 295 { "pci-serial-2x", "prog_if", "0" }, 296 { "pci-serial-4x", "prog_if", "0" }, 297 { "virtio-net-pci", "guest_announce", "off" }, 298 { "ICH9-LPC", "memory-hotplug-support", "off" }, 299 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 300 { "ioh3420", COMPAT_PROP_PCP, "off" }, 301 }; 302 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 303 304 GlobalProperty pc_compat_1_7[] = { 305 PC_CPU_MODEL_IDS("1.7.0") 306 { TYPE_USB_DEVICE, "msos-desc", "no" }, 307 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 308 { "hpet", HPET_INTCAP, "4" }, 309 }; 310 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 311 312 GlobalProperty pc_compat_1_6[] = { 313 PC_CPU_MODEL_IDS("1.6.0") 314 { "e1000", "mitigation", "off" }, 315 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 316 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 317 { "i440FX-pcihost", "short_root_bus", "1" }, 318 { "q35-pcihost", "short_root_bus", "1" }, 319 }; 320 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 321 322 GlobalProperty pc_compat_1_5[] = { 323 PC_CPU_MODEL_IDS("1.5.0") 324 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 325 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 326 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 327 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 328 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 329 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 330 { "virtio-net-pci", "any_layout", "off" }, 331 { TYPE_X86_CPU, "pmu", "on" }, 332 { "i440FX-pcihost", "short_root_bus", "0" }, 333 { "q35-pcihost", "short_root_bus", "0" }, 334 }; 335 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 336 337 GlobalProperty pc_compat_1_4[] = { 338 PC_CPU_MODEL_IDS("1.4.0") 339 { "scsi-hd", "discard_granularity", "0" }, 340 { "scsi-cd", "discard_granularity", "0" }, 341 { "scsi-disk", "discard_granularity", "0" }, 342 { "ide-hd", "discard_granularity", "0" }, 343 { "ide-cd", "discard_granularity", "0" }, 344 { "ide-drive", "discard_granularity", "0" }, 345 { "virtio-blk-pci", "discard_granularity", "0" }, 346 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 347 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 348 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 349 { "e1000", "romfile", "pxe-e1000.rom" }, 350 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 351 { "pcnet", "romfile", "pxe-pcnet.rom" }, 352 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 353 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 354 { "486-" TYPE_X86_CPU, "model", "0" }, 355 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 356 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 357 }; 358 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 359 360 void gsi_handler(void *opaque, int n, int level) 361 { 362 GSIState *s = opaque; 363 364 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 365 if (n < ISA_NUM_IRQS) { 366 qemu_set_irq(s->i8259_irq[n], level); 367 } 368 qemu_set_irq(s->ioapic_irq[n], level); 369 } 370 371 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 372 unsigned size) 373 { 374 } 375 376 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 377 { 378 return 0xffffffffffffffffULL; 379 } 380 381 /* MSDOS compatibility mode FPU exception support */ 382 static qemu_irq ferr_irq; 383 384 void pc_register_ferr_irq(qemu_irq irq) 385 { 386 ferr_irq = irq; 387 } 388 389 /* XXX: add IGNNE support */ 390 void cpu_set_ferr(CPUX86State *s) 391 { 392 qemu_irq_raise(ferr_irq); 393 } 394 395 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 396 unsigned size) 397 { 398 qemu_irq_lower(ferr_irq); 399 } 400 401 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 402 { 403 return 0xffffffffffffffffULL; 404 } 405 406 /* TSC handling */ 407 uint64_t cpu_get_tsc(CPUX86State *env) 408 { 409 return cpu_get_ticks(); 410 } 411 412 /* IRQ handling */ 413 int cpu_get_pic_interrupt(CPUX86State *env) 414 { 415 X86CPU *cpu = env_archcpu(env); 416 int intno; 417 418 if (!kvm_irqchip_in_kernel()) { 419 intno = apic_get_interrupt(cpu->apic_state); 420 if (intno >= 0) { 421 return intno; 422 } 423 /* read the irq from the PIC */ 424 if (!apic_accept_pic_intr(cpu->apic_state)) { 425 return -1; 426 } 427 } 428 429 intno = pic_read_irq(isa_pic); 430 return intno; 431 } 432 433 static void pic_irq_request(void *opaque, int irq, int level) 434 { 435 CPUState *cs = first_cpu; 436 X86CPU *cpu = X86_CPU(cs); 437 438 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 439 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 440 CPU_FOREACH(cs) { 441 cpu = X86_CPU(cs); 442 if (apic_accept_pic_intr(cpu->apic_state)) { 443 apic_deliver_pic_intr(cpu->apic_state, level); 444 } 445 } 446 } else { 447 if (level) { 448 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 449 } else { 450 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 451 } 452 } 453 } 454 455 /* PC cmos mappings */ 456 457 #define REG_EQUIPMENT_BYTE 0x14 458 459 int cmos_get_fd_drive_type(FloppyDriveType fd0) 460 { 461 int val; 462 463 switch (fd0) { 464 case FLOPPY_DRIVE_TYPE_144: 465 /* 1.44 Mb 3"5 drive */ 466 val = 4; 467 break; 468 case FLOPPY_DRIVE_TYPE_288: 469 /* 2.88 Mb 3"5 drive */ 470 val = 5; 471 break; 472 case FLOPPY_DRIVE_TYPE_120: 473 /* 1.2 Mb 5"5 drive */ 474 val = 2; 475 break; 476 case FLOPPY_DRIVE_TYPE_NONE: 477 default: 478 val = 0; 479 break; 480 } 481 return val; 482 } 483 484 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 485 int16_t cylinders, int8_t heads, int8_t sectors) 486 { 487 rtc_set_memory(s, type_ofs, 47); 488 rtc_set_memory(s, info_ofs, cylinders); 489 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 490 rtc_set_memory(s, info_ofs + 2, heads); 491 rtc_set_memory(s, info_ofs + 3, 0xff); 492 rtc_set_memory(s, info_ofs + 4, 0xff); 493 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 494 rtc_set_memory(s, info_ofs + 6, cylinders); 495 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 496 rtc_set_memory(s, info_ofs + 8, sectors); 497 } 498 499 /* convert boot_device letter to something recognizable by the bios */ 500 static int boot_device2nibble(char boot_device) 501 { 502 switch(boot_device) { 503 case 'a': 504 case 'b': 505 return 0x01; /* floppy boot */ 506 case 'c': 507 return 0x02; /* hard drive boot */ 508 case 'd': 509 return 0x03; /* CD-ROM boot */ 510 case 'n': 511 return 0x04; /* Network boot */ 512 } 513 return 0; 514 } 515 516 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 517 { 518 #define PC_MAX_BOOT_DEVICES 3 519 int nbds, bds[3] = { 0, }; 520 int i; 521 522 nbds = strlen(boot_device); 523 if (nbds > PC_MAX_BOOT_DEVICES) { 524 error_setg(errp, "Too many boot devices for PC"); 525 return; 526 } 527 for (i = 0; i < nbds; i++) { 528 bds[i] = boot_device2nibble(boot_device[i]); 529 if (bds[i] == 0) { 530 error_setg(errp, "Invalid boot device for PC: '%c'", 531 boot_device[i]); 532 return; 533 } 534 } 535 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 536 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 537 } 538 539 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 540 { 541 set_boot_dev(opaque, boot_device, errp); 542 } 543 544 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 545 { 546 int val, nb, i; 547 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 548 FLOPPY_DRIVE_TYPE_NONE }; 549 550 /* floppy type */ 551 if (floppy) { 552 for (i = 0; i < 2; i++) { 553 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 554 } 555 } 556 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 557 cmos_get_fd_drive_type(fd_type[1]); 558 rtc_set_memory(rtc_state, 0x10, val); 559 560 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 561 nb = 0; 562 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 563 nb++; 564 } 565 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 566 nb++; 567 } 568 switch (nb) { 569 case 0: 570 break; 571 case 1: 572 val |= 0x01; /* 1 drive, ready for boot */ 573 break; 574 case 2: 575 val |= 0x41; /* 2 drives, ready for boot */ 576 break; 577 } 578 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 579 } 580 581 typedef struct pc_cmos_init_late_arg { 582 ISADevice *rtc_state; 583 BusState *idebus[2]; 584 } pc_cmos_init_late_arg; 585 586 typedef struct check_fdc_state { 587 ISADevice *floppy; 588 bool multiple; 589 } CheckFdcState; 590 591 static int check_fdc(Object *obj, void *opaque) 592 { 593 CheckFdcState *state = opaque; 594 Object *fdc; 595 uint32_t iobase; 596 Error *local_err = NULL; 597 598 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 599 if (!fdc) { 600 return 0; 601 } 602 603 iobase = object_property_get_uint(obj, "iobase", &local_err); 604 if (local_err || iobase != 0x3f0) { 605 error_free(local_err); 606 return 0; 607 } 608 609 if (state->floppy) { 610 state->multiple = true; 611 } else { 612 state->floppy = ISA_DEVICE(obj); 613 } 614 return 0; 615 } 616 617 static const char * const fdc_container_path[] = { 618 "/unattached", "/peripheral", "/peripheral-anon" 619 }; 620 621 /* 622 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 623 * and ACPI objects. 624 */ 625 ISADevice *pc_find_fdc0(void) 626 { 627 int i; 628 Object *container; 629 CheckFdcState state = { 0 }; 630 631 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 632 container = container_get(qdev_get_machine(), fdc_container_path[i]); 633 object_child_foreach(container, check_fdc, &state); 634 } 635 636 if (state.multiple) { 637 warn_report("multiple floppy disk controllers with " 638 "iobase=0x3f0 have been found"); 639 error_printf("the one being picked for CMOS setup might not reflect " 640 "your intent"); 641 } 642 643 return state.floppy; 644 } 645 646 static void pc_cmos_init_late(void *opaque) 647 { 648 pc_cmos_init_late_arg *arg = opaque; 649 ISADevice *s = arg->rtc_state; 650 int16_t cylinders; 651 int8_t heads, sectors; 652 int val; 653 int i, trans; 654 655 val = 0; 656 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 657 &cylinders, &heads, §ors) >= 0) { 658 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 659 val |= 0xf0; 660 } 661 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 662 &cylinders, &heads, §ors) >= 0) { 663 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 664 val |= 0x0f; 665 } 666 rtc_set_memory(s, 0x12, val); 667 668 val = 0; 669 for (i = 0; i < 4; i++) { 670 /* NOTE: ide_get_geometry() returns the physical 671 geometry. It is always such that: 1 <= sects <= 63, 1 672 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 673 geometry can be different if a translation is done. */ 674 if (arg->idebus[i / 2] && 675 ide_get_geometry(arg->idebus[i / 2], i % 2, 676 &cylinders, &heads, §ors) >= 0) { 677 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 678 assert((trans & ~3) == 0); 679 val |= trans << (i * 2); 680 } 681 } 682 rtc_set_memory(s, 0x39, val); 683 684 pc_cmos_init_floppy(s, pc_find_fdc0()); 685 686 qemu_unregister_reset(pc_cmos_init_late, opaque); 687 } 688 689 void pc_cmos_init(PCMachineState *pcms, 690 BusState *idebus0, BusState *idebus1, 691 ISADevice *s) 692 { 693 int val; 694 static pc_cmos_init_late_arg arg; 695 696 /* various important CMOS locations needed by PC/Bochs bios */ 697 698 /* memory size */ 699 /* base memory (first MiB) */ 700 val = MIN(pcms->below_4g_mem_size / KiB, 640); 701 rtc_set_memory(s, 0x15, val); 702 rtc_set_memory(s, 0x16, val >> 8); 703 /* extended memory (next 64MiB) */ 704 if (pcms->below_4g_mem_size > 1 * MiB) { 705 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 706 } else { 707 val = 0; 708 } 709 if (val > 65535) 710 val = 65535; 711 rtc_set_memory(s, 0x17, val); 712 rtc_set_memory(s, 0x18, val >> 8); 713 rtc_set_memory(s, 0x30, val); 714 rtc_set_memory(s, 0x31, val >> 8); 715 /* memory between 16MiB and 4GiB */ 716 if (pcms->below_4g_mem_size > 16 * MiB) { 717 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 718 } else { 719 val = 0; 720 } 721 if (val > 65535) 722 val = 65535; 723 rtc_set_memory(s, 0x34, val); 724 rtc_set_memory(s, 0x35, val >> 8); 725 /* memory above 4GiB */ 726 val = pcms->above_4g_mem_size / 65536; 727 rtc_set_memory(s, 0x5b, val); 728 rtc_set_memory(s, 0x5c, val >> 8); 729 rtc_set_memory(s, 0x5d, val >> 16); 730 731 object_property_add_link(OBJECT(pcms), "rtc_state", 732 TYPE_ISA_DEVICE, 733 (Object **)&pcms->rtc, 734 object_property_allow_set_link, 735 OBJ_PROP_LINK_STRONG, &error_abort); 736 object_property_set_link(OBJECT(pcms), OBJECT(s), 737 "rtc_state", &error_abort); 738 739 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 740 741 val = 0; 742 val |= 0x02; /* FPU is there */ 743 val |= 0x04; /* PS/2 mouse installed */ 744 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 745 746 /* hard drives and FDC */ 747 arg.rtc_state = s; 748 arg.idebus[0] = idebus0; 749 arg.idebus[1] = idebus1; 750 qemu_register_reset(pc_cmos_init_late, &arg); 751 } 752 753 #define TYPE_PORT92 "port92" 754 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 755 756 /* port 92 stuff: could be split off */ 757 typedef struct Port92State { 758 ISADevice parent_obj; 759 760 MemoryRegion io; 761 uint8_t outport; 762 qemu_irq a20_out; 763 } Port92State; 764 765 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 766 unsigned size) 767 { 768 Port92State *s = opaque; 769 int oldval = s->outport; 770 771 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 772 s->outport = val; 773 qemu_set_irq(s->a20_out, (val >> 1) & 1); 774 if ((val & 1) && !(oldval & 1)) { 775 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 776 } 777 } 778 779 static uint64_t port92_read(void *opaque, hwaddr addr, 780 unsigned size) 781 { 782 Port92State *s = opaque; 783 uint32_t ret; 784 785 ret = s->outport; 786 DPRINTF("port92: read 0x%02x\n", ret); 787 return ret; 788 } 789 790 static void port92_init(ISADevice *dev, qemu_irq a20_out) 791 { 792 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 793 } 794 795 static const VMStateDescription vmstate_port92_isa = { 796 .name = "port92", 797 .version_id = 1, 798 .minimum_version_id = 1, 799 .fields = (VMStateField[]) { 800 VMSTATE_UINT8(outport, Port92State), 801 VMSTATE_END_OF_LIST() 802 } 803 }; 804 805 static void port92_reset(DeviceState *d) 806 { 807 Port92State *s = PORT92(d); 808 809 s->outport &= ~1; 810 } 811 812 static const MemoryRegionOps port92_ops = { 813 .read = port92_read, 814 .write = port92_write, 815 .impl = { 816 .min_access_size = 1, 817 .max_access_size = 1, 818 }, 819 .endianness = DEVICE_LITTLE_ENDIAN, 820 }; 821 822 static void port92_initfn(Object *obj) 823 { 824 Port92State *s = PORT92(obj); 825 826 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 827 828 s->outport = 0; 829 830 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 831 } 832 833 static void port92_realizefn(DeviceState *dev, Error **errp) 834 { 835 ISADevice *isadev = ISA_DEVICE(dev); 836 Port92State *s = PORT92(dev); 837 838 isa_register_ioport(isadev, &s->io, 0x92); 839 } 840 841 static void port92_class_initfn(ObjectClass *klass, void *data) 842 { 843 DeviceClass *dc = DEVICE_CLASS(klass); 844 845 dc->realize = port92_realizefn; 846 dc->reset = port92_reset; 847 dc->vmsd = &vmstate_port92_isa; 848 /* 849 * Reason: unlike ordinary ISA devices, this one needs additional 850 * wiring: its A20 output line needs to be wired up by 851 * port92_init(). 852 */ 853 dc->user_creatable = false; 854 } 855 856 static const TypeInfo port92_info = { 857 .name = TYPE_PORT92, 858 .parent = TYPE_ISA_DEVICE, 859 .instance_size = sizeof(Port92State), 860 .instance_init = port92_initfn, 861 .class_init = port92_class_initfn, 862 }; 863 864 static void port92_register_types(void) 865 { 866 type_register_static(&port92_info); 867 } 868 869 type_init(port92_register_types) 870 871 static void handle_a20_line_change(void *opaque, int irq, int level) 872 { 873 X86CPU *cpu = opaque; 874 875 /* XXX: send to all CPUs ? */ 876 /* XXX: add logic to handle multiple A20 line sources */ 877 x86_cpu_set_a20(cpu, level); 878 } 879 880 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 881 { 882 int index = le32_to_cpu(e820_reserve.count); 883 struct e820_entry *entry; 884 885 if (type != E820_RAM) { 886 /* old FW_CFG_E820_TABLE entry -- reservations only */ 887 if (index >= E820_NR_ENTRIES) { 888 return -EBUSY; 889 } 890 entry = &e820_reserve.entry[index++]; 891 892 entry->address = cpu_to_le64(address); 893 entry->length = cpu_to_le64(length); 894 entry->type = cpu_to_le32(type); 895 896 e820_reserve.count = cpu_to_le32(index); 897 } 898 899 /* new "etc/e820" file -- include ram too */ 900 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 901 e820_table[e820_entries].address = cpu_to_le64(address); 902 e820_table[e820_entries].length = cpu_to_le64(length); 903 e820_table[e820_entries].type = cpu_to_le32(type); 904 e820_entries++; 905 906 return e820_entries; 907 } 908 909 int e820_get_num_entries(void) 910 { 911 return e820_entries; 912 } 913 914 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 915 { 916 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 917 *address = le64_to_cpu(e820_table[idx].address); 918 *length = le64_to_cpu(e820_table[idx].length); 919 return true; 920 } 921 return false; 922 } 923 924 /* Calculates initial APIC ID for a specific CPU index 925 * 926 * Currently we need to be able to calculate the APIC ID from the CPU index 927 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 928 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 929 * all CPUs up to max_cpus. 930 */ 931 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, 932 unsigned int cpu_index) 933 { 934 MachineState *ms = MACHINE(pcms); 935 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 936 uint32_t correct_id; 937 static bool warned; 938 939 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, 940 ms->smp.threads, cpu_index); 941 if (pcmc->compat_apic_id_mode) { 942 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 943 error_report("APIC IDs set in compatibility mode, " 944 "CPU topology won't match the configuration"); 945 warned = true; 946 } 947 return cpu_index; 948 } else { 949 return correct_id; 950 } 951 } 952 953 static void pc_build_smbios(PCMachineState *pcms) 954 { 955 uint8_t *smbios_tables, *smbios_anchor; 956 size_t smbios_tables_len, smbios_anchor_len; 957 struct smbios_phys_mem_area *mem_array; 958 unsigned i, array_count; 959 MachineState *ms = MACHINE(pcms); 960 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 961 962 /* tell smbios about cpuid version and features */ 963 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 964 965 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); 966 if (smbios_tables) { 967 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 968 smbios_tables, smbios_tables_len); 969 } 970 971 /* build the array of physical mem area from e820 table */ 972 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 973 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 974 uint64_t addr, len; 975 976 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 977 mem_array[array_count].address = addr; 978 mem_array[array_count].length = len; 979 array_count++; 980 } 981 } 982 smbios_get_tables(ms, mem_array, array_count, 983 &smbios_tables, &smbios_tables_len, 984 &smbios_anchor, &smbios_anchor_len); 985 g_free(mem_array); 986 987 if (smbios_anchor) { 988 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 989 smbios_tables, smbios_tables_len); 990 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 991 smbios_anchor, smbios_anchor_len); 992 } 993 } 994 995 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 996 { 997 FWCfgState *fw_cfg; 998 uint64_t *numa_fw_cfg; 999 int i; 1000 const CPUArchIdList *cpus; 1001 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1002 1003 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 1004 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1005 1006 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1007 * 1008 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1009 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1010 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1011 * for CPU hotplug also uses APIC ID and not "CPU index". 1012 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1013 * but the "limit to the APIC ID values SeaBIOS may see". 1014 * 1015 * So for compatibility reasons with old BIOSes we are stuck with 1016 * "etc/max-cpus" actually being apic_id_limit 1017 */ 1018 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1019 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1020 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1021 acpi_tables, acpi_tables_len); 1022 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1023 1024 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1025 &e820_reserve, sizeof(e820_reserve)); 1026 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1027 sizeof(struct e820_entry) * e820_entries); 1028 1029 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1030 /* allocate memory for the NUMA channel: one (64bit) word for the number 1031 * of nodes, one word for each VCPU->node and one word for each node to 1032 * hold the amount of memory. 1033 */ 1034 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1035 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1036 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1037 for (i = 0; i < cpus->len; i++) { 1038 unsigned int apic_id = cpus->cpus[i].arch_id; 1039 assert(apic_id < pcms->apic_id_limit); 1040 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1041 } 1042 for (i = 0; i < nb_numa_nodes; i++) { 1043 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1044 cpu_to_le64(numa_info[i].node_mem); 1045 } 1046 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1047 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1048 sizeof(*numa_fw_cfg)); 1049 1050 return fw_cfg; 1051 } 1052 1053 static long get_file_size(FILE *f) 1054 { 1055 long where, size; 1056 1057 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1058 1059 where = ftell(f); 1060 fseek(f, 0, SEEK_END); 1061 size = ftell(f); 1062 fseek(f, where, SEEK_SET); 1063 1064 return size; 1065 } 1066 1067 struct setup_data { 1068 uint64_t next; 1069 uint32_t type; 1070 uint32_t len; 1071 uint8_t data[0]; 1072 } __attribute__((packed)); 1073 1074 1075 /* 1076 * The entry point into the kernel for PVH boot is different from 1077 * the native entry point. The PVH entry is defined by the x86/HVM 1078 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 1079 * 1080 * This function is passed to load_elf() when it is called from 1081 * load_elfboot() which then additionally checks for an ELF Note of 1082 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 1083 * parse the PVH entry address from the ELF Note. 1084 * 1085 * Due to trickery in elf_opts.h, load_elf() is actually available as 1086 * load_elf32() or load_elf64() and this routine needs to be able 1087 * to deal with being called as 32 or 64 bit. 1088 * 1089 * The address of the PVH entry point is saved to the 'pvh_start_addr' 1090 * global variable. (although the entry point is 32-bit, the kernel 1091 * binary can be either 32-bit or 64-bit). 1092 */ 1093 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 1094 { 1095 size_t *elf_note_data_addr; 1096 1097 /* Check if ELF Note header passed in is valid */ 1098 if (arg1 == NULL) { 1099 return 0; 1100 } 1101 1102 if (is64) { 1103 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 1104 uint64_t nhdr_size64 = sizeof(struct elf64_note); 1105 uint64_t phdr_align = *(uint64_t *)arg2; 1106 uint64_t nhdr_namesz = nhdr64->n_namesz; 1107 1108 elf_note_data_addr = 1109 ((void *)nhdr64) + nhdr_size64 + 1110 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1111 } else { 1112 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 1113 uint32_t nhdr_size32 = sizeof(struct elf32_note); 1114 uint32_t phdr_align = *(uint32_t *)arg2; 1115 uint32_t nhdr_namesz = nhdr32->n_namesz; 1116 1117 elf_note_data_addr = 1118 ((void *)nhdr32) + nhdr_size32 + 1119 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1120 } 1121 1122 pvh_start_addr = *elf_note_data_addr; 1123 1124 return pvh_start_addr; 1125 } 1126 1127 static bool load_elfboot(const char *kernel_filename, 1128 int kernel_file_size, 1129 uint8_t *header, 1130 size_t pvh_xen_start_addr, 1131 FWCfgState *fw_cfg) 1132 { 1133 uint32_t flags = 0; 1134 uint32_t mh_load_addr = 0; 1135 uint32_t elf_kernel_size = 0; 1136 uint64_t elf_entry; 1137 uint64_t elf_low, elf_high; 1138 int kernel_size; 1139 1140 if (ldl_p(header) != 0x464c457f) { 1141 return false; /* no elfboot */ 1142 } 1143 1144 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 1145 flags = elf_is64 ? 1146 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 1147 1148 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 1149 error_report("elfboot unsupported flags = %x", flags); 1150 exit(1); 1151 } 1152 1153 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 1154 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1155 NULL, &elf_note_type, &elf_entry, 1156 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1157 0, 0); 1158 1159 if (kernel_size < 0) { 1160 error_report("Error while loading elf kernel"); 1161 exit(1); 1162 } 1163 mh_load_addr = elf_low; 1164 elf_kernel_size = elf_high - elf_low; 1165 1166 if (pvh_start_addr == 0) { 1167 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1168 exit(1); 1169 } 1170 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1171 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1172 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1173 1174 return true; 1175 } 1176 1177 static void load_linux(PCMachineState *pcms, 1178 FWCfgState *fw_cfg) 1179 { 1180 uint16_t protocol; 1181 int setup_size, kernel_size, cmdline_size; 1182 int dtb_size, setup_data_offset; 1183 uint32_t initrd_max; 1184 uint8_t header[8192], *setup, *kernel; 1185 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1186 FILE *f; 1187 char *vmode; 1188 MachineState *machine = MACHINE(pcms); 1189 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1190 struct setup_data *setup_data; 1191 const char *kernel_filename = machine->kernel_filename; 1192 const char *initrd_filename = machine->initrd_filename; 1193 const char *dtb_filename = machine->dtb; 1194 const char *kernel_cmdline = machine->kernel_cmdline; 1195 1196 /* Align to 16 bytes as a paranoia measure */ 1197 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1198 1199 /* load the kernel header */ 1200 f = fopen(kernel_filename, "rb"); 1201 if (!f || !(kernel_size = get_file_size(f)) || 1202 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1203 MIN(ARRAY_SIZE(header), kernel_size)) { 1204 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1205 kernel_filename, strerror(errno)); 1206 exit(1); 1207 } 1208 1209 /* kernel protocol version */ 1210 #if 0 1211 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1212 #endif 1213 if (ldl_p(header+0x202) == 0x53726448) { 1214 protocol = lduw_p(header+0x206); 1215 } else { 1216 /* 1217 * This could be a multiboot kernel. If it is, let's stop treating it 1218 * like a Linux kernel. 1219 * Note: some multiboot images could be in the ELF format (the same of 1220 * PVH), so we try multiboot first since we check the multiboot magic 1221 * header before to load it. 1222 */ 1223 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1224 kernel_cmdline, kernel_size, header)) { 1225 return; 1226 } 1227 /* 1228 * Check if the file is an uncompressed kernel file (ELF) and load it, 1229 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1230 * If load_elfboot() is successful, populate the fw_cfg info. 1231 */ 1232 if (pcmc->pvh_enabled && 1233 load_elfboot(kernel_filename, kernel_size, 1234 header, pvh_start_addr, fw_cfg)) { 1235 fclose(f); 1236 1237 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1238 strlen(kernel_cmdline) + 1); 1239 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1240 1241 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1242 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1243 header, sizeof(header)); 1244 1245 /* load initrd */ 1246 if (initrd_filename) { 1247 GMappedFile *mapped_file; 1248 gsize initrd_size; 1249 gchar *initrd_data; 1250 GError *gerr = NULL; 1251 1252 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1253 if (!mapped_file) { 1254 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1255 initrd_filename, gerr->message); 1256 exit(1); 1257 } 1258 pcms->initrd_mapped_file = mapped_file; 1259 1260 initrd_data = g_mapped_file_get_contents(mapped_file); 1261 initrd_size = g_mapped_file_get_length(mapped_file); 1262 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1263 if (initrd_size >= initrd_max) { 1264 fprintf(stderr, "qemu: initrd is too large, cannot support." 1265 "(max: %"PRIu32", need %"PRId64")\n", 1266 initrd_max, (uint64_t)initrd_size); 1267 exit(1); 1268 } 1269 1270 initrd_addr = (initrd_max - initrd_size) & ~4095; 1271 1272 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1273 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1274 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1275 initrd_size); 1276 } 1277 1278 option_rom[nb_option_roms].bootindex = 0; 1279 option_rom[nb_option_roms].name = "pvh.bin"; 1280 nb_option_roms++; 1281 1282 return; 1283 } 1284 protocol = 0; 1285 } 1286 1287 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1288 /* Low kernel */ 1289 real_addr = 0x90000; 1290 cmdline_addr = 0x9a000 - cmdline_size; 1291 prot_addr = 0x10000; 1292 } else if (protocol < 0x202) { 1293 /* High but ancient kernel */ 1294 real_addr = 0x90000; 1295 cmdline_addr = 0x9a000 - cmdline_size; 1296 prot_addr = 0x100000; 1297 } else { 1298 /* High and recent kernel */ 1299 real_addr = 0x10000; 1300 cmdline_addr = 0x20000; 1301 prot_addr = 0x100000; 1302 } 1303 1304 #if 0 1305 fprintf(stderr, 1306 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1307 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1308 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1309 real_addr, 1310 cmdline_addr, 1311 prot_addr); 1312 #endif 1313 1314 /* highest address for loading the initrd */ 1315 if (protocol >= 0x20c && 1316 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1317 /* 1318 * Linux has supported initrd up to 4 GB for a very long time (2007, 1319 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1320 * though it only sets initrd_max to 2 GB to "work around bootloader 1321 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1322 * has supported this. 1323 * 1324 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1325 * be loaded into any address. 1326 * 1327 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1328 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1329 * field). 1330 * 1331 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1332 */ 1333 initrd_max = UINT32_MAX; 1334 } else if (protocol >= 0x203) { 1335 initrd_max = ldl_p(header+0x22c); 1336 } else { 1337 initrd_max = 0x37ffffff; 1338 } 1339 1340 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1341 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1342 } 1343 1344 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1345 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1346 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1347 1348 if (protocol >= 0x202) { 1349 stl_p(header+0x228, cmdline_addr); 1350 } else { 1351 stw_p(header+0x20, 0xA33F); 1352 stw_p(header+0x22, cmdline_addr-real_addr); 1353 } 1354 1355 /* handle vga= parameter */ 1356 vmode = strstr(kernel_cmdline, "vga="); 1357 if (vmode) { 1358 unsigned int video_mode; 1359 /* skip "vga=" */ 1360 vmode += 4; 1361 if (!strncmp(vmode, "normal", 6)) { 1362 video_mode = 0xffff; 1363 } else if (!strncmp(vmode, "ext", 3)) { 1364 video_mode = 0xfffe; 1365 } else if (!strncmp(vmode, "ask", 3)) { 1366 video_mode = 0xfffd; 1367 } else { 1368 video_mode = strtol(vmode, NULL, 0); 1369 } 1370 stw_p(header+0x1fa, video_mode); 1371 } 1372 1373 /* loader type */ 1374 /* High nybble = B reserved for QEMU; low nybble is revision number. 1375 If this code is substantially changed, you may want to consider 1376 incrementing the revision. */ 1377 if (protocol >= 0x200) { 1378 header[0x210] = 0xB0; 1379 } 1380 /* heap */ 1381 if (protocol >= 0x201) { 1382 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1383 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1384 } 1385 1386 /* load initrd */ 1387 if (initrd_filename) { 1388 GMappedFile *mapped_file; 1389 gsize initrd_size; 1390 gchar *initrd_data; 1391 GError *gerr = NULL; 1392 1393 if (protocol < 0x200) { 1394 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1395 exit(1); 1396 } 1397 1398 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1399 if (!mapped_file) { 1400 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1401 initrd_filename, gerr->message); 1402 exit(1); 1403 } 1404 pcms->initrd_mapped_file = mapped_file; 1405 1406 initrd_data = g_mapped_file_get_contents(mapped_file); 1407 initrd_size = g_mapped_file_get_length(mapped_file); 1408 if (initrd_size >= initrd_max) { 1409 fprintf(stderr, "qemu: initrd is too large, cannot support." 1410 "(max: %"PRIu32", need %"PRId64")\n", 1411 initrd_max, (uint64_t)initrd_size); 1412 exit(1); 1413 } 1414 1415 initrd_addr = (initrd_max-initrd_size) & ~4095; 1416 1417 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1418 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1419 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1420 1421 stl_p(header+0x218, initrd_addr); 1422 stl_p(header+0x21c, initrd_size); 1423 } 1424 1425 /* load kernel and setup */ 1426 setup_size = header[0x1f1]; 1427 if (setup_size == 0) { 1428 setup_size = 4; 1429 } 1430 setup_size = (setup_size+1)*512; 1431 if (setup_size > kernel_size) { 1432 fprintf(stderr, "qemu: invalid kernel header\n"); 1433 exit(1); 1434 } 1435 kernel_size -= setup_size; 1436 1437 setup = g_malloc(setup_size); 1438 kernel = g_malloc(kernel_size); 1439 fseek(f, 0, SEEK_SET); 1440 if (fread(setup, 1, setup_size, f) != setup_size) { 1441 fprintf(stderr, "fread() failed\n"); 1442 exit(1); 1443 } 1444 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1445 fprintf(stderr, "fread() failed\n"); 1446 exit(1); 1447 } 1448 fclose(f); 1449 1450 /* append dtb to kernel */ 1451 if (dtb_filename) { 1452 if (protocol < 0x209) { 1453 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1454 exit(1); 1455 } 1456 1457 dtb_size = get_image_size(dtb_filename); 1458 if (dtb_size <= 0) { 1459 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1460 dtb_filename, strerror(errno)); 1461 exit(1); 1462 } 1463 1464 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1465 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1466 kernel = g_realloc(kernel, kernel_size); 1467 1468 stq_p(header+0x250, prot_addr + setup_data_offset); 1469 1470 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1471 setup_data->next = 0; 1472 setup_data->type = cpu_to_le32(SETUP_DTB); 1473 setup_data->len = cpu_to_le32(dtb_size); 1474 1475 load_image_size(dtb_filename, setup_data->data, dtb_size); 1476 } 1477 1478 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1479 1480 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1481 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1482 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1483 1484 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1485 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1486 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1487 1488 option_rom[nb_option_roms].bootindex = 0; 1489 option_rom[nb_option_roms].name = "linuxboot.bin"; 1490 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1491 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1492 } 1493 nb_option_roms++; 1494 } 1495 1496 #define NE2000_NB_MAX 6 1497 1498 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1499 0x280, 0x380 }; 1500 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1501 1502 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1503 { 1504 static int nb_ne2k = 0; 1505 1506 if (nb_ne2k == NE2000_NB_MAX) 1507 return; 1508 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1509 ne2000_irq[nb_ne2k], nd); 1510 nb_ne2k++; 1511 } 1512 1513 DeviceState *cpu_get_current_apic(void) 1514 { 1515 if (current_cpu) { 1516 X86CPU *cpu = X86_CPU(current_cpu); 1517 return cpu->apic_state; 1518 } else { 1519 return NULL; 1520 } 1521 } 1522 1523 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1524 { 1525 X86CPU *cpu = opaque; 1526 1527 if (level) { 1528 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1529 } 1530 } 1531 1532 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) 1533 { 1534 Object *cpu = NULL; 1535 Error *local_err = NULL; 1536 CPUX86State *env = NULL; 1537 1538 cpu = object_new(MACHINE(pcms)->cpu_type); 1539 1540 env = &X86_CPU(cpu)->env; 1541 env->nr_dies = pcms->smp_dies; 1542 1543 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1544 object_property_set_bool(cpu, true, "realized", &local_err); 1545 1546 object_unref(cpu); 1547 error_propagate(errp, local_err); 1548 } 1549 1550 /* 1551 * This function is very similar to smp_parse() 1552 * in hw/core/machine.c but includes CPU die support. 1553 */ 1554 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(ms); 1557 1558 if (opts) { 1559 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 1560 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 1561 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 1562 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 1563 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 1564 1565 /* compute missing values, prefer sockets over cores over threads */ 1566 if (cpus == 0 || sockets == 0) { 1567 cores = cores > 0 ? cores : 1; 1568 threads = threads > 0 ? threads : 1; 1569 if (cpus == 0) { 1570 sockets = sockets > 0 ? sockets : 1; 1571 cpus = cores * threads * dies * sockets; 1572 } else { 1573 ms->smp.max_cpus = 1574 qemu_opt_get_number(opts, "maxcpus", cpus); 1575 sockets = ms->smp.max_cpus / (cores * threads * dies); 1576 } 1577 } else if (cores == 0) { 1578 threads = threads > 0 ? threads : 1; 1579 cores = cpus / (sockets * dies * threads); 1580 cores = cores > 0 ? cores : 1; 1581 } else if (threads == 0) { 1582 threads = cpus / (cores * dies * sockets); 1583 threads = threads > 0 ? threads : 1; 1584 } else if (sockets * dies * cores * threads < cpus) { 1585 error_report("cpu topology: " 1586 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 1587 "smp_cpus (%u)", 1588 sockets, dies, cores, threads, cpus); 1589 exit(1); 1590 } 1591 1592 ms->smp.max_cpus = 1593 qemu_opt_get_number(opts, "maxcpus", cpus); 1594 1595 if (ms->smp.max_cpus < cpus) { 1596 error_report("maxcpus must be equal to or greater than smp"); 1597 exit(1); 1598 } 1599 1600 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 1601 error_report("cpu topology: " 1602 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 1603 "maxcpus (%u)", 1604 sockets, dies, cores, threads, 1605 ms->smp.max_cpus); 1606 exit(1); 1607 } 1608 1609 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 1610 warn_report("Invalid CPU topology deprecated: " 1611 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 1612 "!= maxcpus (%u)", 1613 sockets, dies, cores, threads, 1614 ms->smp.max_cpus); 1615 } 1616 1617 ms->smp.cpus = cpus; 1618 ms->smp.cores = cores; 1619 ms->smp.threads = threads; 1620 pcms->smp_dies = dies; 1621 } 1622 1623 if (ms->smp.cpus > 1) { 1624 Error *blocker = NULL; 1625 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 1626 replay_add_blocker(blocker); 1627 } 1628 } 1629 1630 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 1631 { 1632 PCMachineState *pcms = PC_MACHINE(ms); 1633 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); 1634 Error *local_err = NULL; 1635 1636 if (id < 0) { 1637 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1638 return; 1639 } 1640 1641 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1642 error_setg(errp, "Unable to add CPU: %" PRIi64 1643 ", resulting APIC ID (%" PRIi64 ") is too large", 1644 id, apic_id); 1645 return; 1646 } 1647 1648 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err); 1649 if (local_err) { 1650 error_propagate(errp, local_err); 1651 return; 1652 } 1653 } 1654 1655 void pc_cpus_init(PCMachineState *pcms) 1656 { 1657 int i; 1658 const CPUArchIdList *possible_cpus; 1659 MachineState *ms = MACHINE(pcms); 1660 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1661 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc); 1662 1663 x86_cpu_set_default_version(pcmc->default_cpu_version); 1664 1665 /* Calculates the limit to CPU APIC ID values 1666 * 1667 * Limit for the APIC ID value, so that all 1668 * CPU APIC IDs are < pcms->apic_id_limit. 1669 * 1670 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1671 */ 1672 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, 1673 ms->smp.max_cpus - 1) + 1; 1674 possible_cpus = mc->possible_cpu_arch_ids(ms); 1675 for (i = 0; i < ms->smp.cpus; i++) { 1676 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal); 1677 } 1678 } 1679 1680 static void pc_build_feature_control_file(PCMachineState *pcms) 1681 { 1682 MachineState *ms = MACHINE(pcms); 1683 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1684 CPUX86State *env = &cpu->env; 1685 uint32_t unused, ecx, edx; 1686 uint64_t feature_control_bits = 0; 1687 uint64_t *val; 1688 1689 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1690 if (ecx & CPUID_EXT_VMX) { 1691 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1692 } 1693 1694 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1695 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1696 (env->mcg_cap & MCG_LMCE_P)) { 1697 feature_control_bits |= FEATURE_CONTROL_LMCE; 1698 } 1699 1700 if (!feature_control_bits) { 1701 return; 1702 } 1703 1704 val = g_malloc(sizeof(*val)); 1705 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1706 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1707 } 1708 1709 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1710 { 1711 if (cpus_count > 0xff) { 1712 /* If the number of CPUs can't be represented in 8 bits, the 1713 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1714 * to make old BIOSes fail more predictably. 1715 */ 1716 rtc_set_memory(rtc, 0x5f, 0); 1717 } else { 1718 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1719 } 1720 } 1721 1722 static 1723 void pc_machine_done(Notifier *notifier, void *data) 1724 { 1725 PCMachineState *pcms = container_of(notifier, 1726 PCMachineState, machine_done); 1727 PCIBus *bus = pcms->bus; 1728 1729 /* set the number of CPUs */ 1730 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1731 1732 if (bus) { 1733 int extra_hosts = 0; 1734 1735 QLIST_FOREACH(bus, &bus->child, sibling) { 1736 /* look for expander root buses */ 1737 if (pci_bus_is_root(bus)) { 1738 extra_hosts++; 1739 } 1740 } 1741 if (extra_hosts && pcms->fw_cfg) { 1742 uint64_t *val = g_malloc(sizeof(*val)); 1743 *val = cpu_to_le64(extra_hosts); 1744 fw_cfg_add_file(pcms->fw_cfg, 1745 "etc/extra-pci-roots", val, sizeof(*val)); 1746 } 1747 } 1748 1749 acpi_setup(); 1750 if (pcms->fw_cfg) { 1751 pc_build_smbios(pcms); 1752 pc_build_feature_control_file(pcms); 1753 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1754 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1755 } 1756 1757 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1758 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1759 1760 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1761 iommu->intr_eim != ON_OFF_AUTO_ON) { 1762 error_report("current -smp configuration requires " 1763 "Extended Interrupt Mode enabled. " 1764 "You can add an IOMMU using: " 1765 "-device intel-iommu,intremap=on,eim=on"); 1766 exit(EXIT_FAILURE); 1767 } 1768 } 1769 } 1770 1771 void pc_guest_info_init(PCMachineState *pcms) 1772 { 1773 int i; 1774 1775 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1776 pcms->numa_nodes = nb_numa_nodes; 1777 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1778 sizeof *pcms->node_mem); 1779 for (i = 0; i < nb_numa_nodes; i++) { 1780 pcms->node_mem[i] = numa_info[i].node_mem; 1781 } 1782 1783 pcms->machine_done.notify = pc_machine_done; 1784 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1785 } 1786 1787 /* setup pci memory address space mapping into system address space */ 1788 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1789 MemoryRegion *pci_address_space) 1790 { 1791 /* Set to lower priority than RAM */ 1792 memory_region_add_subregion_overlap(system_memory, 0x0, 1793 pci_address_space, -1); 1794 } 1795 1796 void xen_load_linux(PCMachineState *pcms) 1797 { 1798 int i; 1799 FWCfgState *fw_cfg; 1800 1801 assert(MACHINE(pcms)->kernel_filename != NULL); 1802 1803 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1804 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1805 rom_set_fw(fw_cfg); 1806 1807 load_linux(pcms, fw_cfg); 1808 for (i = 0; i < nb_option_roms; i++) { 1809 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1810 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1811 !strcmp(option_rom[i].name, "pvh.bin") || 1812 !strcmp(option_rom[i].name, "multiboot.bin")); 1813 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1814 } 1815 pcms->fw_cfg = fw_cfg; 1816 } 1817 1818 void pc_memory_init(PCMachineState *pcms, 1819 MemoryRegion *system_memory, 1820 MemoryRegion *rom_memory, 1821 MemoryRegion **ram_memory) 1822 { 1823 int linux_boot, i; 1824 MemoryRegion *ram, *option_rom_mr; 1825 MemoryRegion *ram_below_4g, *ram_above_4g; 1826 FWCfgState *fw_cfg; 1827 MachineState *machine = MACHINE(pcms); 1828 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1829 1830 assert(machine->ram_size == pcms->below_4g_mem_size + 1831 pcms->above_4g_mem_size); 1832 1833 linux_boot = (machine->kernel_filename != NULL); 1834 1835 /* Allocate RAM. We allocate it as a single memory region and use 1836 * aliases to address portions of it, mostly for backwards compatibility 1837 * with older qemus that used qemu_ram_alloc(). 1838 */ 1839 ram = g_malloc(sizeof(*ram)); 1840 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1841 machine->ram_size); 1842 *ram_memory = ram; 1843 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1844 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1845 0, pcms->below_4g_mem_size); 1846 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1847 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1848 if (pcms->above_4g_mem_size > 0) { 1849 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1850 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1851 pcms->below_4g_mem_size, 1852 pcms->above_4g_mem_size); 1853 memory_region_add_subregion(system_memory, 0x100000000ULL, 1854 ram_above_4g); 1855 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1856 } 1857 1858 if (!pcmc->has_reserved_memory && 1859 (machine->ram_slots || 1860 (machine->maxram_size > machine->ram_size))) { 1861 MachineClass *mc = MACHINE_GET_CLASS(machine); 1862 1863 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1864 mc->name); 1865 exit(EXIT_FAILURE); 1866 } 1867 1868 /* always allocate the device memory information */ 1869 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1870 1871 /* initialize device memory address space */ 1872 if (pcmc->has_reserved_memory && 1873 (machine->ram_size < machine->maxram_size)) { 1874 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1875 1876 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1877 error_report("unsupported amount of memory slots: %"PRIu64, 1878 machine->ram_slots); 1879 exit(EXIT_FAILURE); 1880 } 1881 1882 if (QEMU_ALIGN_UP(machine->maxram_size, 1883 TARGET_PAGE_SIZE) != machine->maxram_size) { 1884 error_report("maximum memory size must by aligned to multiple of " 1885 "%d bytes", TARGET_PAGE_SIZE); 1886 exit(EXIT_FAILURE); 1887 } 1888 1889 machine->device_memory->base = 1890 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1891 1892 if (pcmc->enforce_aligned_dimm) { 1893 /* size device region assuming 1G page max alignment per slot */ 1894 device_mem_size += (1 * GiB) * machine->ram_slots; 1895 } 1896 1897 if ((machine->device_memory->base + device_mem_size) < 1898 device_mem_size) { 1899 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1900 machine->maxram_size); 1901 exit(EXIT_FAILURE); 1902 } 1903 1904 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1905 "device-memory", device_mem_size); 1906 memory_region_add_subregion(system_memory, machine->device_memory->base, 1907 &machine->device_memory->mr); 1908 } 1909 1910 /* Initialize PC system firmware */ 1911 pc_system_firmware_init(pcms, rom_memory); 1912 1913 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1914 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1915 &error_fatal); 1916 if (pcmc->pci_enabled) { 1917 memory_region_set_readonly(option_rom_mr, true); 1918 } 1919 memory_region_add_subregion_overlap(rom_memory, 1920 PC_ROM_MIN_VGA, 1921 option_rom_mr, 1922 1); 1923 1924 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1925 1926 rom_set_fw(fw_cfg); 1927 1928 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1929 uint64_t *val = g_malloc(sizeof(*val)); 1930 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1931 uint64_t res_mem_end = machine->device_memory->base; 1932 1933 if (!pcmc->broken_reserved_end) { 1934 res_mem_end += memory_region_size(&machine->device_memory->mr); 1935 } 1936 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1937 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1938 } 1939 1940 if (linux_boot) { 1941 load_linux(pcms, fw_cfg); 1942 } 1943 1944 for (i = 0; i < nb_option_roms; i++) { 1945 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1946 } 1947 pcms->fw_cfg = fw_cfg; 1948 1949 /* Init default IOAPIC address space */ 1950 pcms->ioapic_as = &address_space_memory; 1951 } 1952 1953 /* 1954 * The 64bit pci hole starts after "above 4G RAM" and 1955 * potentially the space reserved for memory hotplug. 1956 */ 1957 uint64_t pc_pci_hole64_start(void) 1958 { 1959 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1960 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1961 MachineState *ms = MACHINE(pcms); 1962 uint64_t hole64_start = 0; 1963 1964 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1965 hole64_start = ms->device_memory->base; 1966 if (!pcmc->broken_reserved_end) { 1967 hole64_start += memory_region_size(&ms->device_memory->mr); 1968 } 1969 } else { 1970 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1971 } 1972 1973 return ROUND_UP(hole64_start, 1 * GiB); 1974 } 1975 1976 qemu_irq pc_allocate_cpu_irq(void) 1977 { 1978 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1979 } 1980 1981 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1982 { 1983 DeviceState *dev = NULL; 1984 1985 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1986 if (pci_bus) { 1987 PCIDevice *pcidev = pci_vga_init(pci_bus); 1988 dev = pcidev ? &pcidev->qdev : NULL; 1989 } else if (isa_bus) { 1990 ISADevice *isadev = isa_vga_init(isa_bus); 1991 dev = isadev ? DEVICE(isadev) : NULL; 1992 } 1993 rom_reset_order_override(); 1994 return dev; 1995 } 1996 1997 static const MemoryRegionOps ioport80_io_ops = { 1998 .write = ioport80_write, 1999 .read = ioport80_read, 2000 .endianness = DEVICE_NATIVE_ENDIAN, 2001 .impl = { 2002 .min_access_size = 1, 2003 .max_access_size = 1, 2004 }, 2005 }; 2006 2007 static const MemoryRegionOps ioportF0_io_ops = { 2008 .write = ioportF0_write, 2009 .read = ioportF0_read, 2010 .endianness = DEVICE_NATIVE_ENDIAN, 2011 .impl = { 2012 .min_access_size = 1, 2013 .max_access_size = 1, 2014 }, 2015 }; 2016 2017 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 2018 { 2019 int i; 2020 DriveInfo *fd[MAX_FD]; 2021 qemu_irq *a20_line; 2022 ISADevice *i8042, *port92, *vmmouse; 2023 2024 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 2025 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 2026 2027 for (i = 0; i < MAX_FD; i++) { 2028 fd[i] = drive_get(IF_FLOPPY, 0, i); 2029 create_fdctrl |= !!fd[i]; 2030 } 2031 if (create_fdctrl) { 2032 fdctrl_init_isa(isa_bus, fd); 2033 } 2034 2035 i8042 = isa_create_simple(isa_bus, "i8042"); 2036 if (!no_vmport) { 2037 vmport_init(isa_bus); 2038 vmmouse = isa_try_create(isa_bus, "vmmouse"); 2039 } else { 2040 vmmouse = NULL; 2041 } 2042 if (vmmouse) { 2043 DeviceState *dev = DEVICE(vmmouse); 2044 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 2045 qdev_init_nofail(dev); 2046 } 2047 port92 = isa_create_simple(isa_bus, "port92"); 2048 2049 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 2050 i8042_setup_a20_line(i8042, a20_line[0]); 2051 port92_init(port92, a20_line[1]); 2052 g_free(a20_line); 2053 } 2054 2055 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 2056 ISADevice **rtc_state, 2057 bool create_fdctrl, 2058 bool no_vmport, 2059 bool has_pit, 2060 uint32_t hpet_irqs) 2061 { 2062 int i; 2063 DeviceState *hpet = NULL; 2064 int pit_isa_irq = 0; 2065 qemu_irq pit_alt_irq = NULL; 2066 qemu_irq rtc_irq = NULL; 2067 ISADevice *pit = NULL; 2068 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 2069 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 2070 2071 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 2072 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 2073 2074 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 2075 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 2076 2077 /* 2078 * Check if an HPET shall be created. 2079 * 2080 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 2081 * when the HPET wants to take over. Thus we have to disable the latter. 2082 */ 2083 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 2084 /* In order to set property, here not using sysbus_try_create_simple */ 2085 hpet = qdev_try_create(NULL, TYPE_HPET); 2086 if (hpet) { 2087 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 2088 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 2089 * IRQ8 and IRQ2. 2090 */ 2091 uint8_t compat = object_property_get_uint(OBJECT(hpet), 2092 HPET_INTCAP, NULL); 2093 if (!compat) { 2094 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 2095 } 2096 qdev_init_nofail(hpet); 2097 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 2098 2099 for (i = 0; i < GSI_NUM_PINS; i++) { 2100 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 2101 } 2102 pit_isa_irq = -1; 2103 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 2104 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 2105 } 2106 } 2107 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 2108 2109 qemu_register_boot_set(pc_boot_set, *rtc_state); 2110 2111 if (!xen_enabled() && has_pit) { 2112 if (kvm_pit_in_kernel()) { 2113 pit = kvm_pit_init(isa_bus, 0x40); 2114 } else { 2115 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 2116 } 2117 if (hpet) { 2118 /* connect PIT to output control line of the HPET */ 2119 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 2120 } 2121 pcspk_init(isa_bus, pit); 2122 } 2123 2124 i8257_dma_init(isa_bus, 0); 2125 2126 /* Super I/O */ 2127 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 2128 } 2129 2130 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 2131 { 2132 int i; 2133 2134 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 2135 for (i = 0; i < nb_nics; i++) { 2136 NICInfo *nd = &nd_table[i]; 2137 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 2138 2139 if (g_str_equal(model, "ne2k_isa")) { 2140 pc_init_ne2k_isa(isa_bus, nd); 2141 } else { 2142 pci_nic_init_nofail(nd, pci_bus, model, NULL); 2143 } 2144 } 2145 rom_reset_order_override(); 2146 } 2147 2148 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 2149 { 2150 DeviceState *dev; 2151 SysBusDevice *d; 2152 unsigned int i; 2153 2154 if (kvm_ioapic_in_kernel()) { 2155 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 2156 } else { 2157 dev = qdev_create(NULL, TYPE_IOAPIC); 2158 } 2159 if (parent_name) { 2160 object_property_add_child(object_resolve_path(parent_name, NULL), 2161 "ioapic", OBJECT(dev), NULL); 2162 } 2163 qdev_init_nofail(dev); 2164 d = SYS_BUS_DEVICE(dev); 2165 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2166 2167 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2168 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2169 } 2170 } 2171 2172 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2173 Error **errp) 2174 { 2175 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2176 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2177 const MachineState *ms = MACHINE(hotplug_dev); 2178 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2179 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2180 Error *local_err = NULL; 2181 2182 /* 2183 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2184 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2185 * addition to cover this case. 2186 */ 2187 if (!pcms->acpi_dev || !acpi_enabled) { 2188 error_setg(errp, 2189 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2190 return; 2191 } 2192 2193 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2194 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2195 return; 2196 } 2197 2198 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 2199 if (local_err) { 2200 error_propagate(errp, local_err); 2201 return; 2202 } 2203 2204 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2205 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2206 } 2207 2208 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2209 DeviceState *dev, Error **errp) 2210 { 2211 Error *local_err = NULL; 2212 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2213 MachineState *ms = MACHINE(hotplug_dev); 2214 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2215 2216 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2217 if (local_err) { 2218 goto out; 2219 } 2220 2221 if (is_nvdimm) { 2222 nvdimm_plug(ms->nvdimms_state); 2223 } 2224 2225 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2226 out: 2227 error_propagate(errp, local_err); 2228 } 2229 2230 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2231 DeviceState *dev, Error **errp) 2232 { 2233 Error *local_err = NULL; 2234 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2235 2236 /* 2237 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2238 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2239 * addition to cover this case. 2240 */ 2241 if (!pcms->acpi_dev || !acpi_enabled) { 2242 error_setg(&local_err, 2243 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2244 goto out; 2245 } 2246 2247 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2248 error_setg(&local_err, 2249 "nvdimm device hot unplug is not supported yet."); 2250 goto out; 2251 } 2252 2253 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2254 &local_err); 2255 out: 2256 error_propagate(errp, local_err); 2257 } 2258 2259 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2260 DeviceState *dev, Error **errp) 2261 { 2262 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2263 Error *local_err = NULL; 2264 2265 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2266 if (local_err) { 2267 goto out; 2268 } 2269 2270 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2271 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2272 out: 2273 error_propagate(errp, local_err); 2274 } 2275 2276 static int pc_apic_cmp(const void *a, const void *b) 2277 { 2278 CPUArchId *apic_a = (CPUArchId *)a; 2279 CPUArchId *apic_b = (CPUArchId *)b; 2280 2281 return apic_a->arch_id - apic_b->arch_id; 2282 } 2283 2284 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2285 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2286 * entry corresponding to CPU's apic_id returns NULL. 2287 */ 2288 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2289 { 2290 CPUArchId apic_id, *found_cpu; 2291 2292 apic_id.arch_id = id; 2293 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2294 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2295 pc_apic_cmp); 2296 if (found_cpu && idx) { 2297 *idx = found_cpu - ms->possible_cpus->cpus; 2298 } 2299 return found_cpu; 2300 } 2301 2302 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2303 DeviceState *dev, Error **errp) 2304 { 2305 CPUArchId *found_cpu; 2306 Error *local_err = NULL; 2307 X86CPU *cpu = X86_CPU(dev); 2308 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2309 2310 if (pcms->acpi_dev) { 2311 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2312 if (local_err) { 2313 goto out; 2314 } 2315 } 2316 2317 /* increment the number of CPUs */ 2318 pcms->boot_cpus++; 2319 if (pcms->rtc) { 2320 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2321 } 2322 if (pcms->fw_cfg) { 2323 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2324 } 2325 2326 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2327 found_cpu->cpu = OBJECT(dev); 2328 out: 2329 error_propagate(errp, local_err); 2330 } 2331 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2332 DeviceState *dev, Error **errp) 2333 { 2334 int idx = -1; 2335 Error *local_err = NULL; 2336 X86CPU *cpu = X86_CPU(dev); 2337 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2338 2339 if (!pcms->acpi_dev) { 2340 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2341 goto out; 2342 } 2343 2344 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2345 assert(idx != -1); 2346 if (idx == 0) { 2347 error_setg(&local_err, "Boot CPU is unpluggable"); 2348 goto out; 2349 } 2350 2351 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2352 &local_err); 2353 if (local_err) { 2354 goto out; 2355 } 2356 2357 out: 2358 error_propagate(errp, local_err); 2359 2360 } 2361 2362 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2363 DeviceState *dev, Error **errp) 2364 { 2365 CPUArchId *found_cpu; 2366 Error *local_err = NULL; 2367 X86CPU *cpu = X86_CPU(dev); 2368 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2369 2370 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2371 if (local_err) { 2372 goto out; 2373 } 2374 2375 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2376 found_cpu->cpu = NULL; 2377 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2378 2379 /* decrement the number of CPUs */ 2380 pcms->boot_cpus--; 2381 /* Update the number of CPUs in CMOS */ 2382 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2383 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2384 out: 2385 error_propagate(errp, local_err); 2386 } 2387 2388 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2389 DeviceState *dev, Error **errp) 2390 { 2391 int idx; 2392 CPUState *cs; 2393 CPUArchId *cpu_slot; 2394 X86CPUTopoInfo topo; 2395 X86CPU *cpu = X86_CPU(dev); 2396 CPUX86State *env = &cpu->env; 2397 MachineState *ms = MACHINE(hotplug_dev); 2398 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2399 unsigned int smp_cores = ms->smp.cores; 2400 unsigned int smp_threads = ms->smp.threads; 2401 2402 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2403 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2404 ms->cpu_type); 2405 return; 2406 } 2407 2408 env->nr_dies = pcms->smp_dies; 2409 2410 /* 2411 * If APIC ID is not set, 2412 * set it based on socket/die/core/thread properties. 2413 */ 2414 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2415 int max_socket = (ms->smp.max_cpus - 1) / 2416 smp_threads / smp_cores / pcms->smp_dies; 2417 2418 if (cpu->socket_id < 0) { 2419 error_setg(errp, "CPU socket-id is not set"); 2420 return; 2421 } else if (cpu->socket_id > max_socket) { 2422 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2423 cpu->socket_id, max_socket); 2424 return; 2425 } else if (cpu->die_id > pcms->smp_dies - 1) { 2426 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 2427 cpu->die_id, max_socket); 2428 return; 2429 } 2430 if (cpu->core_id < 0) { 2431 error_setg(errp, "CPU core-id is not set"); 2432 return; 2433 } else if (cpu->core_id > (smp_cores - 1)) { 2434 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2435 cpu->core_id, smp_cores - 1); 2436 return; 2437 } 2438 if (cpu->thread_id < 0) { 2439 error_setg(errp, "CPU thread-id is not set"); 2440 return; 2441 } else if (cpu->thread_id > (smp_threads - 1)) { 2442 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2443 cpu->thread_id, smp_threads - 1); 2444 return; 2445 } 2446 2447 topo.pkg_id = cpu->socket_id; 2448 topo.die_id = cpu->die_id; 2449 topo.core_id = cpu->core_id; 2450 topo.smt_id = cpu->thread_id; 2451 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, 2452 smp_threads, &topo); 2453 } 2454 2455 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2456 if (!cpu_slot) { 2457 MachineState *ms = MACHINE(pcms); 2458 2459 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2460 smp_cores, smp_threads, &topo); 2461 error_setg(errp, 2462 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 2463 " APIC ID %" PRIu32 ", valid index range 0:%d", 2464 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 2465 cpu->apic_id, ms->possible_cpus->len - 1); 2466 return; 2467 } 2468 2469 if (cpu_slot->cpu) { 2470 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2471 idx, cpu->apic_id); 2472 return; 2473 } 2474 2475 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2476 * so that machine_query_hotpluggable_cpus would show correct values 2477 */ 2478 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2479 * once -smp refactoring is complete and there will be CPU private 2480 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2481 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2482 smp_cores, smp_threads, &topo); 2483 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2484 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2485 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2486 return; 2487 } 2488 cpu->socket_id = topo.pkg_id; 2489 2490 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 2491 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 2492 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 2493 return; 2494 } 2495 cpu->die_id = topo.die_id; 2496 2497 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2498 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2499 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2500 return; 2501 } 2502 cpu->core_id = topo.core_id; 2503 2504 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2505 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2506 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2507 return; 2508 } 2509 cpu->thread_id = topo.smt_id; 2510 2511 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 2512 !kvm_hv_vpindex_settable()) { 2513 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2514 return; 2515 } 2516 2517 cs = CPU(cpu); 2518 cs->cpu_index = idx; 2519 2520 numa_cpu_pre_plug(cpu_slot, dev, errp); 2521 } 2522 2523 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 2524 DeviceState *dev, Error **errp) 2525 { 2526 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2527 Error *local_err = NULL; 2528 2529 if (!hotplug_dev2) { 2530 /* 2531 * Without a bus hotplug handler, we cannot control the plug/unplug 2532 * order. This should never be the case on x86, however better add 2533 * a safety net. 2534 */ 2535 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 2536 return; 2537 } 2538 /* 2539 * First, see if we can plug this memory device at all. If that 2540 * succeeds, branch of to the actual hotplug handler. 2541 */ 2542 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2543 &local_err); 2544 if (!local_err) { 2545 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2546 } 2547 error_propagate(errp, local_err); 2548 } 2549 2550 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 2551 DeviceState *dev, Error **errp) 2552 { 2553 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2554 Error *local_err = NULL; 2555 2556 /* 2557 * Plug the memory device first and then branch off to the actual 2558 * hotplug handler. If that one fails, we can easily undo the memory 2559 * device bits. 2560 */ 2561 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2562 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2563 if (local_err) { 2564 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2565 } 2566 error_propagate(errp, local_err); 2567 } 2568 2569 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 2570 DeviceState *dev, Error **errp) 2571 { 2572 /* We don't support virtio pmem hot unplug */ 2573 error_setg(errp, "virtio pmem device unplug not supported."); 2574 } 2575 2576 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 2577 DeviceState *dev, Error **errp) 2578 { 2579 /* We don't support virtio pmem hot unplug */ 2580 } 2581 2582 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2583 DeviceState *dev, Error **errp) 2584 { 2585 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2586 pc_memory_pre_plug(hotplug_dev, dev, errp); 2587 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2588 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2590 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 2591 } 2592 } 2593 2594 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2595 DeviceState *dev, Error **errp) 2596 { 2597 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2598 pc_memory_plug(hotplug_dev, dev, errp); 2599 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2600 pc_cpu_plug(hotplug_dev, dev, errp); 2601 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2602 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 2603 } 2604 } 2605 2606 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2607 DeviceState *dev, Error **errp) 2608 { 2609 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2610 pc_memory_unplug_request(hotplug_dev, dev, errp); 2611 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2612 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2613 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2614 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 2615 } else { 2616 error_setg(errp, "acpi: device unplug request for not supported device" 2617 " type: %s", object_get_typename(OBJECT(dev))); 2618 } 2619 } 2620 2621 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2622 DeviceState *dev, Error **errp) 2623 { 2624 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2625 pc_memory_unplug(hotplug_dev, dev, errp); 2626 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2627 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2628 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2629 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 2630 } else { 2631 error_setg(errp, "acpi: device unplug for not supported device" 2632 " type: %s", object_get_typename(OBJECT(dev))); 2633 } 2634 } 2635 2636 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2637 DeviceState *dev) 2638 { 2639 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2640 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 2641 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2642 return HOTPLUG_HANDLER(machine); 2643 } 2644 2645 return NULL; 2646 } 2647 2648 static void 2649 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2650 const char *name, void *opaque, 2651 Error **errp) 2652 { 2653 MachineState *ms = MACHINE(obj); 2654 int64_t value = 0; 2655 2656 if (ms->device_memory) { 2657 value = memory_region_size(&ms->device_memory->mr); 2658 } 2659 2660 visit_type_int(v, name, &value, errp); 2661 } 2662 2663 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2664 const char *name, void *opaque, 2665 Error **errp) 2666 { 2667 PCMachineState *pcms = PC_MACHINE(obj); 2668 uint64_t value = pcms->max_ram_below_4g; 2669 2670 visit_type_size(v, name, &value, errp); 2671 } 2672 2673 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2674 const char *name, void *opaque, 2675 Error **errp) 2676 { 2677 PCMachineState *pcms = PC_MACHINE(obj); 2678 Error *error = NULL; 2679 uint64_t value; 2680 2681 visit_type_size(v, name, &value, &error); 2682 if (error) { 2683 error_propagate(errp, error); 2684 return; 2685 } 2686 if (value > 4 * GiB) { 2687 error_setg(&error, 2688 "Machine option 'max-ram-below-4g=%"PRIu64 2689 "' expects size less than or equal to 4G", value); 2690 error_propagate(errp, error); 2691 return; 2692 } 2693 2694 if (value < 1 * MiB) { 2695 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2696 "BIOS may not work with less than 1MiB", value); 2697 } 2698 2699 pcms->max_ram_below_4g = value; 2700 } 2701 2702 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2703 void *opaque, Error **errp) 2704 { 2705 PCMachineState *pcms = PC_MACHINE(obj); 2706 OnOffAuto vmport = pcms->vmport; 2707 2708 visit_type_OnOffAuto(v, name, &vmport, errp); 2709 } 2710 2711 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2712 void *opaque, Error **errp) 2713 { 2714 PCMachineState *pcms = PC_MACHINE(obj); 2715 2716 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2717 } 2718 2719 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2720 { 2721 bool smm_available = false; 2722 2723 if (pcms->smm == ON_OFF_AUTO_OFF) { 2724 return false; 2725 } 2726 2727 if (tcg_enabled() || qtest_enabled()) { 2728 smm_available = true; 2729 } else if (kvm_enabled()) { 2730 smm_available = kvm_has_smm(); 2731 } 2732 2733 if (smm_available) { 2734 return true; 2735 } 2736 2737 if (pcms->smm == ON_OFF_AUTO_ON) { 2738 error_report("System Management Mode not supported by this hypervisor."); 2739 exit(1); 2740 } 2741 return false; 2742 } 2743 2744 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2745 void *opaque, Error **errp) 2746 { 2747 PCMachineState *pcms = PC_MACHINE(obj); 2748 OnOffAuto smm = pcms->smm; 2749 2750 visit_type_OnOffAuto(v, name, &smm, errp); 2751 } 2752 2753 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2754 void *opaque, Error **errp) 2755 { 2756 PCMachineState *pcms = PC_MACHINE(obj); 2757 2758 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2759 } 2760 2761 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2762 { 2763 PCMachineState *pcms = PC_MACHINE(obj); 2764 2765 return pcms->smbus_enabled; 2766 } 2767 2768 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2769 { 2770 PCMachineState *pcms = PC_MACHINE(obj); 2771 2772 pcms->smbus_enabled = value; 2773 } 2774 2775 static bool pc_machine_get_sata(Object *obj, Error **errp) 2776 { 2777 PCMachineState *pcms = PC_MACHINE(obj); 2778 2779 return pcms->sata_enabled; 2780 } 2781 2782 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2783 { 2784 PCMachineState *pcms = PC_MACHINE(obj); 2785 2786 pcms->sata_enabled = value; 2787 } 2788 2789 static bool pc_machine_get_pit(Object *obj, Error **errp) 2790 { 2791 PCMachineState *pcms = PC_MACHINE(obj); 2792 2793 return pcms->pit_enabled; 2794 } 2795 2796 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2797 { 2798 PCMachineState *pcms = PC_MACHINE(obj); 2799 2800 pcms->pit_enabled = value; 2801 } 2802 2803 static void pc_machine_initfn(Object *obj) 2804 { 2805 PCMachineState *pcms = PC_MACHINE(obj); 2806 2807 pcms->max_ram_below_4g = 0; /* use default */ 2808 pcms->smm = ON_OFF_AUTO_AUTO; 2809 #ifdef CONFIG_VMPORT 2810 pcms->vmport = ON_OFF_AUTO_AUTO; 2811 #else 2812 pcms->vmport = ON_OFF_AUTO_OFF; 2813 #endif /* CONFIG_VMPORT */ 2814 /* acpi build is enabled by default if machine supports it */ 2815 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2816 pcms->smbus_enabled = true; 2817 pcms->sata_enabled = true; 2818 pcms->pit_enabled = true; 2819 pcms->smp_dies = 1; 2820 2821 pc_system_flash_create(pcms); 2822 } 2823 2824 static void pc_machine_reset(MachineState *machine) 2825 { 2826 CPUState *cs; 2827 X86CPU *cpu; 2828 2829 qemu_devices_reset(); 2830 2831 /* Reset APIC after devices have been reset to cancel 2832 * any changes that qemu_devices_reset() might have done. 2833 */ 2834 CPU_FOREACH(cs) { 2835 cpu = X86_CPU(cs); 2836 2837 if (cpu->apic_state) { 2838 device_reset(cpu->apic_state); 2839 } 2840 } 2841 } 2842 2843 static CpuInstanceProperties 2844 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2845 { 2846 MachineClass *mc = MACHINE_GET_CLASS(ms); 2847 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2848 2849 assert(cpu_index < possible_cpus->len); 2850 return possible_cpus->cpus[cpu_index].props; 2851 } 2852 2853 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2854 { 2855 X86CPUTopoInfo topo; 2856 PCMachineState *pcms = PC_MACHINE(ms); 2857 2858 assert(idx < ms->possible_cpus->len); 2859 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2860 pcms->smp_dies, ms->smp.cores, 2861 ms->smp.threads, &topo); 2862 return topo.pkg_id % nb_numa_nodes; 2863 } 2864 2865 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2866 { 2867 PCMachineState *pcms = PC_MACHINE(ms); 2868 int i; 2869 unsigned int max_cpus = ms->smp.max_cpus; 2870 2871 if (ms->possible_cpus) { 2872 /* 2873 * make sure that max_cpus hasn't changed since the first use, i.e. 2874 * -smp hasn't been parsed after it 2875 */ 2876 assert(ms->possible_cpus->len == max_cpus); 2877 return ms->possible_cpus; 2878 } 2879 2880 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2881 sizeof(CPUArchId) * max_cpus); 2882 ms->possible_cpus->len = max_cpus; 2883 for (i = 0; i < ms->possible_cpus->len; i++) { 2884 X86CPUTopoInfo topo; 2885 2886 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2887 ms->possible_cpus->cpus[i].vcpus_count = 1; 2888 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); 2889 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2890 pcms->smp_dies, ms->smp.cores, 2891 ms->smp.threads, &topo); 2892 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2893 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2894 ms->possible_cpus->cpus[i].props.has_die_id = true; 2895 ms->possible_cpus->cpus[i].props.die_id = topo.die_id; 2896 ms->possible_cpus->cpus[i].props.has_core_id = true; 2897 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2898 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2899 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2900 } 2901 return ms->possible_cpus; 2902 } 2903 2904 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2905 { 2906 /* cpu index isn't used */ 2907 CPUState *cs; 2908 2909 CPU_FOREACH(cs) { 2910 X86CPU *cpu = X86_CPU(cs); 2911 2912 if (!cpu->apic_state) { 2913 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2914 } else { 2915 apic_deliver_nmi(cpu->apic_state); 2916 } 2917 } 2918 } 2919 2920 static void pc_machine_class_init(ObjectClass *oc, void *data) 2921 { 2922 MachineClass *mc = MACHINE_CLASS(oc); 2923 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2924 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2925 NMIClass *nc = NMI_CLASS(oc); 2926 2927 pcmc->pci_enabled = true; 2928 pcmc->has_acpi_build = true; 2929 pcmc->rsdp_in_ram = true; 2930 pcmc->smbios_defaults = true; 2931 pcmc->smbios_uuid_encoded = true; 2932 pcmc->gigabyte_align = true; 2933 pcmc->has_reserved_memory = true; 2934 pcmc->kvmclock_enabled = true; 2935 pcmc->enforce_aligned_dimm = true; 2936 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2937 * to be used at the moment, 32K should be enough for a while. */ 2938 pcmc->acpi_data_size = 0x20000 + 0x8000; 2939 pcmc->save_tsc_khz = true; 2940 pcmc->linuxboot_dma_enabled = true; 2941 pcmc->pvh_enabled = true; 2942 assert(!mc->get_hotplug_handler); 2943 mc->get_hotplug_handler = pc_get_hotplug_handler; 2944 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2945 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2946 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2947 mc->auto_enable_numa_with_memhp = true; 2948 mc->has_hotpluggable_cpus = true; 2949 mc->default_boot_order = "cad"; 2950 mc->hot_add_cpu = pc_hot_add_cpu; 2951 mc->smp_parse = pc_smp_parse; 2952 mc->block_default_type = IF_IDE; 2953 mc->max_cpus = 255; 2954 mc->reset = pc_machine_reset; 2955 hc->pre_plug = pc_machine_device_pre_plug_cb; 2956 hc->plug = pc_machine_device_plug_cb; 2957 hc->unplug_request = pc_machine_device_unplug_request_cb; 2958 hc->unplug = pc_machine_device_unplug_cb; 2959 nc->nmi_monitor_handler = x86_nmi; 2960 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2961 mc->nvdimm_supported = true; 2962 mc->numa_mem_supported = true; 2963 2964 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2965 pc_machine_get_device_memory_region_size, NULL, 2966 NULL, NULL, &error_abort); 2967 2968 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2969 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2970 NULL, NULL, &error_abort); 2971 2972 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2973 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2974 2975 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2976 pc_machine_get_smm, pc_machine_set_smm, 2977 NULL, NULL, &error_abort); 2978 object_class_property_set_description(oc, PC_MACHINE_SMM, 2979 "Enable SMM (pc & q35)", &error_abort); 2980 2981 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2982 pc_machine_get_vmport, pc_machine_set_vmport, 2983 NULL, NULL, &error_abort); 2984 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2985 "Enable vmport (pc & q35)", &error_abort); 2986 2987 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2988 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2989 2990 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2991 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2992 2993 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2994 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2995 } 2996 2997 static const TypeInfo pc_machine_info = { 2998 .name = TYPE_PC_MACHINE, 2999 .parent = TYPE_MACHINE, 3000 .abstract = true, 3001 .instance_size = sizeof(PCMachineState), 3002 .instance_init = pc_machine_initfn, 3003 .class_size = sizeof(PCMachineClass), 3004 .class_init = pc_machine_class_init, 3005 .interfaces = (InterfaceInfo[]) { 3006 { TYPE_HOTPLUG_HANDLER }, 3007 { TYPE_NMI }, 3008 { } 3009 }, 3010 }; 3011 3012 static void pc_machine_register_types(void) 3013 { 3014 type_register_static(&pc_machine_info); 3015 } 3016 3017 type_init(pc_machine_register_types) 3018