1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/internal.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include CONFIG_DEVICES 66 67 #ifdef CONFIG_XEN_EMU 68 #include "hw/xen/xen-legacy-backend.h" 69 #include "hw/xen/xen-bus.h" 70 #endif 71 72 /* 73 * Helper for setting model-id for CPU models that changed model-id 74 * depending on QEMU versions up to QEMU 2.4. 75 */ 76 #define PC_CPU_MODEL_IDS(v) \ 77 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 78 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 80 81 GlobalProperty pc_compat_8_2[] = {}; 82 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 83 84 GlobalProperty pc_compat_8_1[] = {}; 85 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 86 87 GlobalProperty pc_compat_8_0[] = { 88 { "virtio-mem", "unplugged-inaccessible", "auto" }, 89 }; 90 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 91 92 GlobalProperty pc_compat_7_2[] = { 93 { "ICH9-LPC", "noreboot", "true" }, 94 }; 95 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 96 97 GlobalProperty pc_compat_7_1[] = {}; 98 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 99 100 GlobalProperty pc_compat_7_0[] = {}; 101 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 102 103 GlobalProperty pc_compat_6_2[] = { 104 { "virtio-mem", "unplugged-inaccessible", "off" }, 105 }; 106 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 107 108 GlobalProperty pc_compat_6_1[] = { 109 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 110 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 111 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 112 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 113 }; 114 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 115 116 GlobalProperty pc_compat_6_0[] = { 117 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 118 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 119 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 120 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 121 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 123 }; 124 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 125 126 GlobalProperty pc_compat_5_2[] = { 127 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 128 }; 129 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 130 131 GlobalProperty pc_compat_5_1[] = { 132 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 133 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 134 }; 135 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 136 137 GlobalProperty pc_compat_5_0[] = { 138 }; 139 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 140 141 GlobalProperty pc_compat_4_2[] = { 142 { "mch", "smbase-smram", "off" }, 143 }; 144 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 145 146 GlobalProperty pc_compat_4_1[] = {}; 147 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 148 149 GlobalProperty pc_compat_4_0[] = {}; 150 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 151 152 GlobalProperty pc_compat_3_1[] = { 153 { "intel-iommu", "dma-drain", "off" }, 154 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 155 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 156 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 157 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 158 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 159 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 160 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 161 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 162 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 163 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 164 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 165 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 166 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 167 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 168 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 169 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 170 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 171 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 172 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 173 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 174 }; 175 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 176 177 GlobalProperty pc_compat_3_0[] = { 178 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 179 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 180 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 181 }; 182 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 183 184 GlobalProperty pc_compat_2_12[] = { 185 { TYPE_X86_CPU, "legacy-cache", "on" }, 186 { TYPE_X86_CPU, "topoext", "off" }, 187 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 188 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 189 }; 190 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 191 192 GlobalProperty pc_compat_2_11[] = { 193 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 194 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 195 }; 196 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 197 198 GlobalProperty pc_compat_2_10[] = { 199 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 200 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 201 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 202 }; 203 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 204 205 GlobalProperty pc_compat_2_9[] = { 206 { "mch", "extended-tseg-mbytes", "0" }, 207 }; 208 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 209 210 GlobalProperty pc_compat_2_8[] = { 211 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 212 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 213 { "ICH9-LPC", "x-smi-broadcast", "off" }, 214 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 215 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 216 }; 217 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 218 219 GlobalProperty pc_compat_2_7[] = { 220 { TYPE_X86_CPU, "l3-cache", "off" }, 221 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 223 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 224 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 225 { "isa-pcspk", "migrate", "off" }, 226 }; 227 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 228 229 GlobalProperty pc_compat_2_6[] = { 230 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 231 { "vmxnet3", "romfile", "" }, 232 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 233 { "apic-common", "legacy-instance-id", "on", } 234 }; 235 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 236 237 GlobalProperty pc_compat_2_5[] = {}; 238 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 239 240 GlobalProperty pc_compat_2_4[] = { 241 PC_CPU_MODEL_IDS("2.4.0") 242 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 243 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 244 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 245 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 246 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 247 { TYPE_X86_CPU, "check", "off" }, 248 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 249 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 250 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 251 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 252 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 254 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 255 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 256 }; 257 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 258 259 GlobalProperty pc_compat_2_3[] = { 260 PC_CPU_MODEL_IDS("2.3.0") 261 { TYPE_X86_CPU, "arat", "off" }, 262 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 263 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 264 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 265 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 266 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 267 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 269 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 270 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 271 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 272 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 273 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 274 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 275 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 276 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 277 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 278 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 279 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 280 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 281 }; 282 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 283 284 GlobalProperty pc_compat_2_2[] = { 285 PC_CPU_MODEL_IDS("2.2.0") 286 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 290 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 291 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 292 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 293 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 294 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 295 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 296 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 297 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 298 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 299 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 300 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 301 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 302 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 303 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 304 }; 305 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 306 307 GlobalProperty pc_compat_2_1[] = { 308 PC_CPU_MODEL_IDS("2.1.0") 309 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 310 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 311 }; 312 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 313 314 GlobalProperty pc_compat_2_0[] = { 315 PC_CPU_MODEL_IDS("2.0.0") 316 { "virtio-scsi-pci", "any_layout", "off" }, 317 { "PIIX4_PM", "memory-hotplug-support", "off" }, 318 { "apic", "version", "0x11" }, 319 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 320 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 321 { "pci-serial", "prog_if", "0" }, 322 { "pci-serial-2x", "prog_if", "0" }, 323 { "pci-serial-4x", "prog_if", "0" }, 324 { "virtio-net-pci", "guest_announce", "off" }, 325 { "ICH9-LPC", "memory-hotplug-support", "off" }, 326 }; 327 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 328 329 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 330 { 331 GSIState *s; 332 333 s = g_new0(GSIState, 1); 334 if (kvm_ioapic_in_kernel()) { 335 kvm_pc_setup_irq_routing(pci_enabled); 336 } 337 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 338 339 return s; 340 } 341 342 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 343 unsigned size) 344 { 345 } 346 347 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 348 { 349 return 0xffffffffffffffffULL; 350 } 351 352 /* MS-DOS compatibility mode FPU exception support */ 353 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 354 unsigned size) 355 { 356 if (tcg_enabled()) { 357 cpu_set_ignne(); 358 } 359 } 360 361 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 362 { 363 return 0xffffffffffffffffULL; 364 } 365 366 /* PC cmos mappings */ 367 368 #define REG_EQUIPMENT_BYTE 0x14 369 370 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 371 int16_t cylinders, int8_t heads, int8_t sectors) 372 { 373 mc146818rtc_set_cmos_data(s, type_ofs, 47); 374 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 375 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 376 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 377 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 378 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 379 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 380 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 381 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 382 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 383 } 384 385 /* convert boot_device letter to something recognizable by the bios */ 386 static int boot_device2nibble(char boot_device) 387 { 388 switch(boot_device) { 389 case 'a': 390 case 'b': 391 return 0x01; /* floppy boot */ 392 case 'c': 393 return 0x02; /* hard drive boot */ 394 case 'd': 395 return 0x03; /* CD-ROM boot */ 396 case 'n': 397 return 0x04; /* Network boot */ 398 } 399 return 0; 400 } 401 402 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 403 Error **errp) 404 { 405 #define PC_MAX_BOOT_DEVICES 3 406 int nbds, bds[3] = { 0, }; 407 int i; 408 409 nbds = strlen(boot_device); 410 if (nbds > PC_MAX_BOOT_DEVICES) { 411 error_setg(errp, "Too many boot devices for PC"); 412 return; 413 } 414 for (i = 0; i < nbds; i++) { 415 bds[i] = boot_device2nibble(boot_device[i]); 416 if (bds[i] == 0) { 417 error_setg(errp, "Invalid boot device for PC: '%c'", 418 boot_device[i]); 419 return; 420 } 421 } 422 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 423 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 424 } 425 426 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 427 { 428 set_boot_dev(opaque, boot_device, errp); 429 } 430 431 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 432 { 433 int val, nb, i; 434 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 435 FLOPPY_DRIVE_TYPE_NONE }; 436 437 /* floppy type */ 438 if (floppy) { 439 for (i = 0; i < 2; i++) { 440 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 441 } 442 } 443 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 444 cmos_get_fd_drive_type(fd_type[1]); 445 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 446 447 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 448 nb = 0; 449 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 450 nb++; 451 } 452 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 453 nb++; 454 } 455 switch (nb) { 456 case 0: 457 break; 458 case 1: 459 val |= 0x01; /* 1 drive, ready for boot */ 460 break; 461 case 2: 462 val |= 0x41; /* 2 drives, ready for boot */ 463 break; 464 } 465 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 466 } 467 468 typedef struct pc_cmos_init_late_arg { 469 MC146818RtcState *rtc_state; 470 BusState *idebus[2]; 471 } pc_cmos_init_late_arg; 472 473 typedef struct check_fdc_state { 474 ISADevice *floppy; 475 bool multiple; 476 } CheckFdcState; 477 478 static int check_fdc(Object *obj, void *opaque) 479 { 480 CheckFdcState *state = opaque; 481 Object *fdc; 482 uint32_t iobase; 483 Error *local_err = NULL; 484 485 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 486 if (!fdc) { 487 return 0; 488 } 489 490 iobase = object_property_get_uint(obj, "iobase", &local_err); 491 if (local_err || iobase != 0x3f0) { 492 error_free(local_err); 493 return 0; 494 } 495 496 if (state->floppy) { 497 state->multiple = true; 498 } else { 499 state->floppy = ISA_DEVICE(obj); 500 } 501 return 0; 502 } 503 504 static const char * const fdc_container_path[] = { 505 "/unattached", "/peripheral", "/peripheral-anon" 506 }; 507 508 /* 509 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 510 * and ACPI objects. 511 */ 512 static ISADevice *pc_find_fdc0(void) 513 { 514 int i; 515 Object *container; 516 CheckFdcState state = { 0 }; 517 518 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 519 container = container_get(qdev_get_machine(), fdc_container_path[i]); 520 object_child_foreach(container, check_fdc, &state); 521 } 522 523 if (state.multiple) { 524 warn_report("multiple floppy disk controllers with " 525 "iobase=0x3f0 have been found"); 526 error_printf("the one being picked for CMOS setup might not reflect " 527 "your intent"); 528 } 529 530 return state.floppy; 531 } 532 533 static void pc_cmos_init_late(void *opaque) 534 { 535 pc_cmos_init_late_arg *arg = opaque; 536 MC146818RtcState *s = arg->rtc_state; 537 int16_t cylinders; 538 int8_t heads, sectors; 539 int val; 540 int i, trans; 541 542 val = 0; 543 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 544 &cylinders, &heads, §ors) >= 0) { 545 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 546 val |= 0xf0; 547 } 548 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 549 &cylinders, &heads, §ors) >= 0) { 550 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 551 val |= 0x0f; 552 } 553 mc146818rtc_set_cmos_data(s, 0x12, val); 554 555 val = 0; 556 for (i = 0; i < 4; i++) { 557 /* NOTE: ide_get_geometry() returns the physical 558 geometry. It is always such that: 1 <= sects <= 63, 1 559 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 560 geometry can be different if a translation is done. */ 561 if (arg->idebus[i / 2] && 562 ide_get_geometry(arg->idebus[i / 2], i % 2, 563 &cylinders, &heads, §ors) >= 0) { 564 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 565 assert((trans & ~3) == 0); 566 val |= trans << (i * 2); 567 } 568 } 569 mc146818rtc_set_cmos_data(s, 0x39, val); 570 571 pc_cmos_init_floppy(s, pc_find_fdc0()); 572 573 qemu_unregister_reset(pc_cmos_init_late, opaque); 574 } 575 576 void pc_cmos_init(PCMachineState *pcms, 577 BusState *idebus0, BusState *idebus1, 578 ISADevice *rtc) 579 { 580 int val; 581 static pc_cmos_init_late_arg arg; 582 X86MachineState *x86ms = X86_MACHINE(pcms); 583 MC146818RtcState *s = MC146818_RTC(rtc); 584 585 /* various important CMOS locations needed by PC/Bochs bios */ 586 587 /* memory size */ 588 /* base memory (first MiB) */ 589 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 590 mc146818rtc_set_cmos_data(s, 0x15, val); 591 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 592 /* extended memory (next 64MiB) */ 593 if (x86ms->below_4g_mem_size > 1 * MiB) { 594 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 595 } else { 596 val = 0; 597 } 598 if (val > 65535) 599 val = 65535; 600 mc146818rtc_set_cmos_data(s, 0x17, val); 601 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 602 mc146818rtc_set_cmos_data(s, 0x30, val); 603 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 604 /* memory between 16MiB and 4GiB */ 605 if (x86ms->below_4g_mem_size > 16 * MiB) { 606 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 607 } else { 608 val = 0; 609 } 610 if (val > 65535) 611 val = 65535; 612 mc146818rtc_set_cmos_data(s, 0x34, val); 613 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 614 /* memory above 4GiB */ 615 val = x86ms->above_4g_mem_size / 65536; 616 mc146818rtc_set_cmos_data(s, 0x5b, val); 617 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 618 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 619 620 object_property_add_link(OBJECT(pcms), "rtc_state", 621 TYPE_ISA_DEVICE, 622 (Object **)&x86ms->rtc, 623 object_property_allow_set_link, 624 OBJ_PROP_LINK_STRONG); 625 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 626 &error_abort); 627 628 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 629 630 val = 0; 631 val |= 0x02; /* FPU is there */ 632 val |= 0x04; /* PS/2 mouse installed */ 633 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 634 635 /* hard drives and FDC */ 636 arg.rtc_state = s; 637 arg.idebus[0] = idebus0; 638 arg.idebus[1] = idebus1; 639 qemu_register_reset(pc_cmos_init_late, &arg); 640 } 641 642 static void handle_a20_line_change(void *opaque, int irq, int level) 643 { 644 X86CPU *cpu = opaque; 645 646 /* XXX: send to all CPUs ? */ 647 /* XXX: add logic to handle multiple A20 line sources */ 648 x86_cpu_set_a20(cpu, level); 649 } 650 651 #define NE2000_NB_MAX 6 652 653 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 654 0x280, 0x380 }; 655 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 656 657 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 658 { 659 static int nb_ne2k = 0; 660 661 if (nb_ne2k == NE2000_NB_MAX) 662 return; 663 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 664 ne2000_irq[nb_ne2k], nd); 665 nb_ne2k++; 666 } 667 668 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 669 { 670 X86CPU *cpu = opaque; 671 672 if (level) { 673 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 674 } 675 } 676 677 static 678 void pc_machine_done(Notifier *notifier, void *data) 679 { 680 PCMachineState *pcms = container_of(notifier, 681 PCMachineState, machine_done); 682 X86MachineState *x86ms = X86_MACHINE(pcms); 683 684 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 685 &error_fatal); 686 687 if (pcms->cxl_devices_state.is_enabled) { 688 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 689 } 690 691 /* set the number of CPUs */ 692 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 693 694 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 695 696 acpi_setup(); 697 if (x86ms->fw_cfg) { 698 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 699 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 700 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 701 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 702 } 703 } 704 705 void pc_guest_info_init(PCMachineState *pcms) 706 { 707 X86MachineState *x86ms = X86_MACHINE(pcms); 708 709 x86ms->apic_xrupt_override = true; 710 pcms->machine_done.notify = pc_machine_done; 711 qemu_add_machine_init_done_notifier(&pcms->machine_done); 712 } 713 714 /* setup pci memory address space mapping into system address space */ 715 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 716 MemoryRegion *pci_address_space) 717 { 718 /* Set to lower priority than RAM */ 719 memory_region_add_subregion_overlap(system_memory, 0x0, 720 pci_address_space, -1); 721 } 722 723 void xen_load_linux(PCMachineState *pcms) 724 { 725 int i; 726 FWCfgState *fw_cfg; 727 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 728 X86MachineState *x86ms = X86_MACHINE(pcms); 729 730 assert(MACHINE(pcms)->kernel_filename != NULL); 731 732 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 733 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 734 rom_set_fw(fw_cfg); 735 736 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 737 pcmc->pvh_enabled); 738 for (i = 0; i < nb_option_roms; i++) { 739 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 740 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 741 !strcmp(option_rom[i].name, "pvh.bin") || 742 !strcmp(option_rom[i].name, "multiboot.bin") || 743 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 744 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 745 } 746 x86ms->fw_cfg = fw_cfg; 747 } 748 749 #define PC_ROM_MIN_VGA 0xc0000 750 #define PC_ROM_MIN_OPTION 0xc8000 751 #define PC_ROM_MAX 0xe0000 752 #define PC_ROM_ALIGN 0x800 753 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 754 755 static hwaddr pc_above_4g_end(PCMachineState *pcms) 756 { 757 X86MachineState *x86ms = X86_MACHINE(pcms); 758 759 if (pcms->sgx_epc.size != 0) { 760 return sgx_epc_above_4g_end(&pcms->sgx_epc); 761 } 762 763 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 764 } 765 766 static void pc_get_device_memory_range(PCMachineState *pcms, 767 hwaddr *base, 768 ram_addr_t *device_mem_size) 769 { 770 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 771 MachineState *machine = MACHINE(pcms); 772 ram_addr_t size; 773 hwaddr addr; 774 775 size = machine->maxram_size - machine->ram_size; 776 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 777 778 if (pcmc->enforce_aligned_dimm) { 779 /* size device region assuming 1G page max alignment per slot */ 780 size += (1 * GiB) * machine->ram_slots; 781 } 782 783 *base = addr; 784 *device_mem_size = size; 785 } 786 787 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 788 { 789 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 790 MachineState *ms = MACHINE(pcms); 791 hwaddr cxl_base; 792 ram_addr_t size; 793 794 if (pcmc->has_reserved_memory && 795 (ms->ram_size < ms->maxram_size)) { 796 pc_get_device_memory_range(pcms, &cxl_base, &size); 797 cxl_base += size; 798 } else { 799 cxl_base = pc_above_4g_end(pcms); 800 } 801 802 return cxl_base; 803 } 804 805 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 806 { 807 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 808 809 if (pcms->cxl_devices_state.fixed_windows) { 810 GList *it; 811 812 start = ROUND_UP(start, 256 * MiB); 813 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 814 CXLFixedWindow *fw = it->data; 815 start += fw->size; 816 } 817 } 818 819 return start; 820 } 821 822 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 823 { 824 X86CPU *cpu = X86_CPU(first_cpu); 825 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 826 MachineState *ms = MACHINE(pcms); 827 828 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 829 /* 64-bit systems */ 830 return pc_pci_hole64_start() + pci_hole64_size - 1; 831 } 832 833 /* 32-bit systems */ 834 if (pcmc->broken_32bit_mem_addr_check) { 835 /* old value for compatibility reasons */ 836 return ((hwaddr)1 << cpu->phys_bits) - 1; 837 } 838 839 /* 840 * 32-bit systems don't have hole64 but they might have a region for 841 * memory devices. Even if additional hotplugged memory devices might 842 * not be usable by most guest OSes, we need to still consider them for 843 * calculating the highest possible GPA so that we can properly report 844 * if someone configures them on a CPU that cannot possibly address them. 845 */ 846 if (pcmc->has_reserved_memory && 847 (ms->ram_size < ms->maxram_size)) { 848 hwaddr devmem_start; 849 ram_addr_t devmem_size; 850 851 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 852 devmem_start += devmem_size; 853 return devmem_start - 1; 854 } 855 856 /* configuration without any memory hotplug */ 857 return pc_above_4g_end(pcms) - 1; 858 } 859 860 /* 861 * AMD systems with an IOMMU have an additional hole close to the 862 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 863 * on kernel version, VFIO may or may not let you DMA map those ranges. 864 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 865 * with certain memory sizes. It's also wrong to use those IOVA ranges 866 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 867 * The ranges reserved for Hyper-Transport are: 868 * 869 * FD_0000_0000h - FF_FFFF_FFFFh 870 * 871 * The ranges represent the following: 872 * 873 * Base Address Top Address Use 874 * 875 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 876 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 877 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 878 * FD_F910_0000h FD_F91F_FFFFh System Management 879 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 880 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 881 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 882 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 883 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 884 * FE_2000_0000h FF_FFFF_FFFFh Reserved 885 * 886 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 887 * Table 3: Special Address Controls (GPA) for more information. 888 */ 889 #define AMD_HT_START 0xfd00000000UL 890 #define AMD_HT_END 0xffffffffffUL 891 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 892 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 893 894 void pc_memory_init(PCMachineState *pcms, 895 MemoryRegion *system_memory, 896 MemoryRegion *rom_memory, 897 uint64_t pci_hole64_size) 898 { 899 int linux_boot, i; 900 MemoryRegion *option_rom_mr; 901 MemoryRegion *ram_below_4g, *ram_above_4g; 902 FWCfgState *fw_cfg; 903 MachineState *machine = MACHINE(pcms); 904 MachineClass *mc = MACHINE_GET_CLASS(machine); 905 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 906 X86MachineState *x86ms = X86_MACHINE(pcms); 907 hwaddr maxphysaddr, maxusedaddr; 908 hwaddr cxl_base, cxl_resv_end = 0; 909 X86CPU *cpu = X86_CPU(first_cpu); 910 911 assert(machine->ram_size == x86ms->below_4g_mem_size + 912 x86ms->above_4g_mem_size); 913 914 linux_boot = (machine->kernel_filename != NULL); 915 916 /* 917 * The HyperTransport range close to the 1T boundary is unique to AMD 918 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 919 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 920 * older machine types (<= 7.0) for compatibility purposes. 921 */ 922 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 923 /* Bail out if max possible address does not cross HT range */ 924 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 925 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 926 } 927 928 /* 929 * Advertise the HT region if address space covers the reserved 930 * region or if we relocate. 931 */ 932 if (cpu->phys_bits >= 40) { 933 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 934 } 935 } 936 937 /* 938 * phys-bits is required to be appropriately configured 939 * to make sure max used GPA is reachable. 940 */ 941 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 942 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 943 if (maxphysaddr < maxusedaddr) { 944 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 945 " phys-bits too low (%u)", 946 maxphysaddr, maxusedaddr, cpu->phys_bits); 947 exit(EXIT_FAILURE); 948 } 949 950 /* 951 * Split single memory region and use aliases to address portions of it, 952 * done for backwards compatibility with older qemus. 953 */ 954 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 955 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 956 0, x86ms->below_4g_mem_size); 957 memory_region_add_subregion(system_memory, 0, ram_below_4g); 958 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 959 if (x86ms->above_4g_mem_size > 0) { 960 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 961 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 962 machine->ram, 963 x86ms->below_4g_mem_size, 964 x86ms->above_4g_mem_size); 965 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 966 ram_above_4g); 967 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 968 E820_RAM); 969 } 970 971 if (pcms->sgx_epc.size != 0) { 972 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 973 } 974 975 if (!pcmc->has_reserved_memory && 976 (machine->ram_slots || 977 (machine->maxram_size > machine->ram_size))) { 978 979 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 980 mc->name); 981 exit(EXIT_FAILURE); 982 } 983 984 /* initialize device memory address space */ 985 if (pcmc->has_reserved_memory && 986 (machine->ram_size < machine->maxram_size)) { 987 ram_addr_t device_mem_size; 988 hwaddr device_mem_base; 989 990 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 991 error_report("unsupported amount of memory slots: %"PRIu64, 992 machine->ram_slots); 993 exit(EXIT_FAILURE); 994 } 995 996 if (QEMU_ALIGN_UP(machine->maxram_size, 997 TARGET_PAGE_SIZE) != machine->maxram_size) { 998 error_report("maximum memory size must by aligned to multiple of " 999 "%d bytes", TARGET_PAGE_SIZE); 1000 exit(EXIT_FAILURE); 1001 } 1002 1003 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 1004 1005 if (device_mem_base + device_mem_size < device_mem_size) { 1006 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1007 machine->maxram_size); 1008 exit(EXIT_FAILURE); 1009 } 1010 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 1011 } 1012 1013 if (pcms->cxl_devices_state.is_enabled) { 1014 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1015 hwaddr cxl_size = MiB; 1016 1017 cxl_base = pc_get_cxl_range_start(pcms); 1018 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1019 memory_region_add_subregion(system_memory, cxl_base, mr); 1020 cxl_resv_end = cxl_base + cxl_size; 1021 if (pcms->cxl_devices_state.fixed_windows) { 1022 hwaddr cxl_fmw_base; 1023 GList *it; 1024 1025 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1026 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1027 CXLFixedWindow *fw = it->data; 1028 1029 fw->base = cxl_fmw_base; 1030 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1031 "cxl-fixed-memory-region", fw->size); 1032 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1033 cxl_fmw_base += fw->size; 1034 cxl_resv_end = cxl_fmw_base; 1035 } 1036 } 1037 } 1038 1039 /* Initialize PC system firmware */ 1040 pc_system_firmware_init(pcms, rom_memory); 1041 1042 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1043 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1044 &error_fatal); 1045 if (pcmc->pci_enabled) { 1046 memory_region_set_readonly(option_rom_mr, true); 1047 } 1048 memory_region_add_subregion_overlap(rom_memory, 1049 PC_ROM_MIN_VGA, 1050 option_rom_mr, 1051 1); 1052 1053 fw_cfg = fw_cfg_arch_create(machine, 1054 x86ms->boot_cpus, x86ms->apic_id_limit); 1055 1056 rom_set_fw(fw_cfg); 1057 1058 if (machine->device_memory) { 1059 uint64_t *val = g_malloc(sizeof(*val)); 1060 uint64_t res_mem_end = machine->device_memory->base; 1061 1062 if (!pcmc->broken_reserved_end) { 1063 res_mem_end += memory_region_size(&machine->device_memory->mr); 1064 } 1065 1066 if (pcms->cxl_devices_state.is_enabled) { 1067 res_mem_end = cxl_resv_end; 1068 } 1069 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1070 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1071 } 1072 1073 if (linux_boot) { 1074 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1075 pcmc->pvh_enabled); 1076 } 1077 1078 for (i = 0; i < nb_option_roms; i++) { 1079 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1080 } 1081 x86ms->fw_cfg = fw_cfg; 1082 1083 /* Init default IOAPIC address space */ 1084 x86ms->ioapic_as = &address_space_memory; 1085 1086 /* Init ACPI memory hotplug IO base address */ 1087 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1088 } 1089 1090 /* 1091 * The 64bit pci hole starts after "above 4G RAM" and 1092 * potentially the space reserved for memory hotplug. 1093 */ 1094 uint64_t pc_pci_hole64_start(void) 1095 { 1096 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1097 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1098 MachineState *ms = MACHINE(pcms); 1099 uint64_t hole64_start = 0; 1100 ram_addr_t size = 0; 1101 1102 if (pcms->cxl_devices_state.is_enabled) { 1103 hole64_start = pc_get_cxl_range_end(pcms); 1104 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1105 pc_get_device_memory_range(pcms, &hole64_start, &size); 1106 if (!pcmc->broken_reserved_end) { 1107 hole64_start += size; 1108 } 1109 } else { 1110 hole64_start = pc_above_4g_end(pcms); 1111 } 1112 1113 return ROUND_UP(hole64_start, 1 * GiB); 1114 } 1115 1116 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1117 { 1118 DeviceState *dev = NULL; 1119 1120 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1121 if (pci_bus) { 1122 PCIDevice *pcidev = pci_vga_init(pci_bus); 1123 dev = pcidev ? &pcidev->qdev : NULL; 1124 } else if (isa_bus) { 1125 ISADevice *isadev = isa_vga_init(isa_bus); 1126 dev = isadev ? DEVICE(isadev) : NULL; 1127 } 1128 rom_reset_order_override(); 1129 return dev; 1130 } 1131 1132 static const MemoryRegionOps ioport80_io_ops = { 1133 .write = ioport80_write, 1134 .read = ioport80_read, 1135 .endianness = DEVICE_NATIVE_ENDIAN, 1136 .impl = { 1137 .min_access_size = 1, 1138 .max_access_size = 1, 1139 }, 1140 }; 1141 1142 static const MemoryRegionOps ioportF0_io_ops = { 1143 .write = ioportF0_write, 1144 .read = ioportF0_read, 1145 .endianness = DEVICE_NATIVE_ENDIAN, 1146 .impl = { 1147 .min_access_size = 1, 1148 .max_access_size = 1, 1149 }, 1150 }; 1151 1152 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1153 bool create_i8042, bool no_vmport) 1154 { 1155 int i; 1156 DriveInfo *fd[MAX_FD]; 1157 qemu_irq *a20_line; 1158 ISADevice *fdc, *i8042, *port92, *vmmouse; 1159 1160 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1161 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1162 1163 for (i = 0; i < MAX_FD; i++) { 1164 fd[i] = drive_get(IF_FLOPPY, 0, i); 1165 create_fdctrl |= !!fd[i]; 1166 } 1167 if (create_fdctrl) { 1168 fdc = isa_new(TYPE_ISA_FDC); 1169 if (fdc) { 1170 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1171 isa_fdc_init_drives(fdc, fd); 1172 } 1173 } 1174 1175 if (!create_i8042) { 1176 return; 1177 } 1178 1179 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1180 if (!no_vmport) { 1181 isa_create_simple(isa_bus, TYPE_VMPORT); 1182 vmmouse = isa_try_new("vmmouse"); 1183 } else { 1184 vmmouse = NULL; 1185 } 1186 if (vmmouse) { 1187 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1188 &error_abort); 1189 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1190 } 1191 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1192 1193 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1194 i8042_setup_a20_line(i8042, a20_line[0]); 1195 qdev_connect_gpio_out_named(DEVICE(port92), 1196 PORT92_A20_LINE, 0, a20_line[1]); 1197 g_free(a20_line); 1198 } 1199 1200 void pc_basic_device_init(struct PCMachineState *pcms, 1201 ISABus *isa_bus, qemu_irq *gsi, 1202 ISADevice *rtc_state, 1203 bool create_fdctrl, 1204 uint32_t hpet_irqs) 1205 { 1206 int i; 1207 DeviceState *hpet = NULL; 1208 int pit_isa_irq = 0; 1209 qemu_irq pit_alt_irq = NULL; 1210 ISADevice *pit = NULL; 1211 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1212 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1213 X86MachineState *x86ms = X86_MACHINE(pcms); 1214 1215 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1216 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1217 1218 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1219 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1220 1221 /* 1222 * Check if an HPET shall be created. 1223 */ 1224 if (pcms->hpet_enabled) { 1225 qemu_irq rtc_irq; 1226 1227 hpet = qdev_try_new(TYPE_HPET); 1228 if (!hpet) { 1229 error_report("couldn't create HPET device"); 1230 exit(1); 1231 } 1232 /* 1233 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1234 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1235 * the property, use whatever mask they specified. 1236 */ 1237 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1238 HPET_INTCAP, NULL); 1239 if (!compat) { 1240 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1241 } 1242 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1243 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1244 1245 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1246 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1247 } 1248 pit_isa_irq = -1; 1249 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1250 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1251 1252 /* overwrite connection created by south bridge */ 1253 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1254 } 1255 1256 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1257 "date"); 1258 1259 #ifdef CONFIG_XEN_EMU 1260 if (xen_mode == XEN_EMULATE) { 1261 xen_overlay_create(); 1262 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1263 xen_gnttab_create(); 1264 xen_xenstore_create(); 1265 if (pcms->bus) { 1266 pci_create_simple(pcms->bus, -1, "xen-platform"); 1267 } 1268 pcms->xenbus = xen_bus_init(); 1269 xen_be_init(); 1270 } 1271 #endif 1272 1273 qemu_register_boot_set(pc_boot_set, rtc_state); 1274 1275 if (!xen_enabled() && 1276 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1277 if (kvm_pit_in_kernel()) { 1278 pit = kvm_pit_init(isa_bus, 0x40); 1279 } else { 1280 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1281 } 1282 if (hpet) { 1283 /* connect PIT to output control line of the HPET */ 1284 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1285 } 1286 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1287 OBJECT(pit), &error_fatal); 1288 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1289 } 1290 1291 /* Super I/O */ 1292 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1293 pcms->vmport != ON_OFF_AUTO_ON); 1294 } 1295 1296 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus, 1297 BusState *xen_bus) 1298 { 1299 MachineClass *mc = MACHINE_CLASS(pcmc); 1300 int i; 1301 1302 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1303 for (i = 0; i < nb_nics; i++) { 1304 NICInfo *nd = &nd_table[i]; 1305 const char *model = nd->model ? nd->model : mc->default_nic; 1306 1307 if (xen_bus && (!nd->model || g_str_equal(model, "xen-net-device"))) { 1308 DeviceState *dev = qdev_new("xen-net-device"); 1309 qdev_set_nic_properties(dev, nd); 1310 qdev_realize_and_unref(dev, xen_bus, &error_fatal); 1311 } else if (g_str_equal(model, "ne2k_isa")) { 1312 pc_init_ne2k_isa(isa_bus, nd); 1313 } else { 1314 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1315 } 1316 } 1317 rom_reset_order_override(); 1318 } 1319 1320 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1321 { 1322 qemu_irq *i8259; 1323 1324 if (kvm_pic_in_kernel()) { 1325 i8259 = kvm_i8259_init(isa_bus); 1326 } else if (xen_enabled()) { 1327 i8259 = xen_interrupt_controller_init(); 1328 } else { 1329 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1330 } 1331 1332 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1333 i8259_irqs[i] = i8259[i]; 1334 } 1335 1336 g_free(i8259); 1337 } 1338 1339 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1340 Error **errp) 1341 { 1342 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1343 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1344 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1345 const MachineState *ms = MACHINE(hotplug_dev); 1346 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1347 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1348 Error *local_err = NULL; 1349 1350 /* 1351 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1352 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1353 * addition to cover this case. 1354 */ 1355 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1356 error_setg(errp, 1357 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1358 return; 1359 } 1360 1361 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1362 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1363 return; 1364 } 1365 1366 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1367 if (local_err) { 1368 error_propagate(errp, local_err); 1369 return; 1370 } 1371 1372 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1373 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1374 } 1375 1376 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1377 DeviceState *dev, Error **errp) 1378 { 1379 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1380 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1381 MachineState *ms = MACHINE(hotplug_dev); 1382 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1383 1384 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1385 1386 if (is_nvdimm) { 1387 nvdimm_plug(ms->nvdimms_state); 1388 } 1389 1390 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1391 } 1392 1393 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1394 DeviceState *dev, Error **errp) 1395 { 1396 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1397 1398 /* 1399 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1400 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1401 * addition to cover this case. 1402 */ 1403 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1404 error_setg(errp, 1405 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1406 return; 1407 } 1408 1409 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1410 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1411 return; 1412 } 1413 1414 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1415 errp); 1416 } 1417 1418 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1419 DeviceState *dev, Error **errp) 1420 { 1421 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1422 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1423 Error *local_err = NULL; 1424 1425 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1426 if (local_err) { 1427 goto out; 1428 } 1429 1430 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1431 qdev_unrealize(dev); 1432 out: 1433 error_propagate(errp, local_err); 1434 } 1435 1436 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1437 DeviceState *dev, Error **errp) 1438 { 1439 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1440 g_assert(!dev->hotplugged); 1441 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1442 errp); 1443 } 1444 1445 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1446 DeviceState *dev, Error **errp) 1447 { 1448 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1449 } 1450 1451 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1452 DeviceState *dev, Error **errp) 1453 { 1454 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1455 pc_memory_pre_plug(hotplug_dev, dev, errp); 1456 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1457 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1458 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1459 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1460 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1461 /* Declare the APIC range as the reserved MSI region */ 1462 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1463 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1464 QList *reserved_regions = qlist_new(); 1465 1466 qlist_append_str(reserved_regions, resv_prop_str); 1467 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1468 1469 g_free(resv_prop_str); 1470 } 1471 1472 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1473 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1474 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1475 1476 if (pcms->iommu) { 1477 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1478 "for x86 yet."); 1479 return; 1480 } 1481 pcms->iommu = dev; 1482 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1483 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1484 } 1485 } 1486 1487 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1488 DeviceState *dev, Error **errp) 1489 { 1490 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1491 pc_memory_plug(hotplug_dev, dev, errp); 1492 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1493 x86_cpu_plug(hotplug_dev, dev, errp); 1494 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1495 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1496 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1497 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1498 } 1499 } 1500 1501 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1502 DeviceState *dev, Error **errp) 1503 { 1504 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1505 pc_memory_unplug_request(hotplug_dev, dev, errp); 1506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1507 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1508 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1509 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1510 errp); 1511 } else { 1512 error_setg(errp, "acpi: device unplug request for not supported device" 1513 " type: %s", object_get_typename(OBJECT(dev))); 1514 } 1515 } 1516 1517 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1518 DeviceState *dev, Error **errp) 1519 { 1520 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1521 pc_memory_unplug(hotplug_dev, dev, errp); 1522 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1523 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1524 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1525 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1526 } else { 1527 error_setg(errp, "acpi: device unplug for not supported device" 1528 " type: %s", object_get_typename(OBJECT(dev))); 1529 } 1530 } 1531 1532 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1533 DeviceState *dev) 1534 { 1535 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1536 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1537 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1538 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1539 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1540 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1541 return HOTPLUG_HANDLER(machine); 1542 } 1543 1544 return NULL; 1545 } 1546 1547 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1548 void *opaque, Error **errp) 1549 { 1550 PCMachineState *pcms = PC_MACHINE(obj); 1551 OnOffAuto vmport = pcms->vmport; 1552 1553 visit_type_OnOffAuto(v, name, &vmport, errp); 1554 } 1555 1556 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1557 void *opaque, Error **errp) 1558 { 1559 PCMachineState *pcms = PC_MACHINE(obj); 1560 1561 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1562 } 1563 1564 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1565 { 1566 PCMachineState *pcms = PC_MACHINE(obj); 1567 1568 return pcms->smbus_enabled; 1569 } 1570 1571 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1572 { 1573 PCMachineState *pcms = PC_MACHINE(obj); 1574 1575 pcms->smbus_enabled = value; 1576 } 1577 1578 static bool pc_machine_get_sata(Object *obj, Error **errp) 1579 { 1580 PCMachineState *pcms = PC_MACHINE(obj); 1581 1582 return pcms->sata_enabled; 1583 } 1584 1585 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1586 { 1587 PCMachineState *pcms = PC_MACHINE(obj); 1588 1589 pcms->sata_enabled = value; 1590 } 1591 1592 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1593 { 1594 PCMachineState *pcms = PC_MACHINE(obj); 1595 1596 return pcms->hpet_enabled; 1597 } 1598 1599 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1600 { 1601 PCMachineState *pcms = PC_MACHINE(obj); 1602 1603 pcms->hpet_enabled = value; 1604 } 1605 1606 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1607 { 1608 PCMachineState *pcms = PC_MACHINE(obj); 1609 1610 return pcms->i8042_enabled; 1611 } 1612 1613 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1614 { 1615 PCMachineState *pcms = PC_MACHINE(obj); 1616 1617 pcms->i8042_enabled = value; 1618 } 1619 1620 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1621 { 1622 PCMachineState *pcms = PC_MACHINE(obj); 1623 1624 return pcms->default_bus_bypass_iommu; 1625 } 1626 1627 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1628 Error **errp) 1629 { 1630 PCMachineState *pcms = PC_MACHINE(obj); 1631 1632 pcms->default_bus_bypass_iommu = value; 1633 } 1634 1635 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1636 void *opaque, Error **errp) 1637 { 1638 PCMachineState *pcms = PC_MACHINE(obj); 1639 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1640 1641 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1642 } 1643 1644 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1645 void *opaque, Error **errp) 1646 { 1647 PCMachineState *pcms = PC_MACHINE(obj); 1648 1649 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1650 } 1651 1652 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1653 const char *name, void *opaque, 1654 Error **errp) 1655 { 1656 PCMachineState *pcms = PC_MACHINE(obj); 1657 uint64_t value = pcms->max_ram_below_4g; 1658 1659 visit_type_size(v, name, &value, errp); 1660 } 1661 1662 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1663 const char *name, void *opaque, 1664 Error **errp) 1665 { 1666 PCMachineState *pcms = PC_MACHINE(obj); 1667 uint64_t value; 1668 1669 if (!visit_type_size(v, name, &value, errp)) { 1670 return; 1671 } 1672 if (value > 4 * GiB) { 1673 error_setg(errp, 1674 "Machine option 'max-ram-below-4g=%"PRIu64 1675 "' expects size less than or equal to 4G", value); 1676 return; 1677 } 1678 1679 if (value < 1 * MiB) { 1680 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1681 "BIOS may not work with less than 1MiB", value); 1682 } 1683 1684 pcms->max_ram_below_4g = value; 1685 } 1686 1687 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1688 const char *name, void *opaque, 1689 Error **errp) 1690 { 1691 PCMachineState *pcms = PC_MACHINE(obj); 1692 uint64_t value = pcms->max_fw_size; 1693 1694 visit_type_size(v, name, &value, errp); 1695 } 1696 1697 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1698 const char *name, void *opaque, 1699 Error **errp) 1700 { 1701 PCMachineState *pcms = PC_MACHINE(obj); 1702 uint64_t value; 1703 1704 if (!visit_type_size(v, name, &value, errp)) { 1705 return; 1706 } 1707 1708 /* 1709 * We don't have a theoretically justifiable exact lower bound on the base 1710 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1711 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1712 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1713 * 16MiB in size. 1714 */ 1715 if (value > 16 * MiB) { 1716 error_setg(errp, 1717 "User specified max allowed firmware size %" PRIu64 " is " 1718 "greater than 16MiB. If combined firmware size exceeds " 1719 "16MiB the system may not boot, or experience intermittent" 1720 "stability issues.", 1721 value); 1722 return; 1723 } 1724 1725 pcms->max_fw_size = value; 1726 } 1727 1728 1729 static void pc_machine_initfn(Object *obj) 1730 { 1731 PCMachineState *pcms = PC_MACHINE(obj); 1732 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1733 1734 #ifdef CONFIG_VMPORT 1735 pcms->vmport = ON_OFF_AUTO_AUTO; 1736 #else 1737 pcms->vmport = ON_OFF_AUTO_OFF; 1738 #endif /* CONFIG_VMPORT */ 1739 pcms->max_ram_below_4g = 0; /* use default */ 1740 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1741 pcms->south_bridge = pcmc->default_south_bridge; 1742 1743 /* acpi build is enabled by default if machine supports it */ 1744 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1745 pcms->smbus_enabled = true; 1746 pcms->sata_enabled = true; 1747 pcms->i8042_enabled = true; 1748 pcms->max_fw_size = 8 * MiB; 1749 #ifdef CONFIG_HPET 1750 pcms->hpet_enabled = true; 1751 #endif 1752 pcms->default_bus_bypass_iommu = false; 1753 1754 pc_system_flash_create(pcms); 1755 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1756 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1757 OBJECT(pcms->pcspk), "audiodev"); 1758 cxl_machine_init(obj, &pcms->cxl_devices_state); 1759 } 1760 1761 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) 1762 { 1763 return 0; 1764 } 1765 1766 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1767 { 1768 CPUState *cs; 1769 X86CPU *cpu; 1770 1771 qemu_devices_reset(reason); 1772 1773 /* Reset APIC after devices have been reset to cancel 1774 * any changes that qemu_devices_reset() might have done. 1775 */ 1776 CPU_FOREACH(cs) { 1777 cpu = X86_CPU(cs); 1778 1779 x86_cpu_after_reset(cpu); 1780 } 1781 } 1782 1783 static void pc_machine_wakeup(MachineState *machine) 1784 { 1785 cpu_synchronize_all_states(); 1786 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1787 cpu_synchronize_all_post_reset(); 1788 } 1789 1790 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1791 { 1792 X86IOMMUState *iommu = x86_iommu_get_default(); 1793 IntelIOMMUState *intel_iommu; 1794 1795 if (iommu && 1796 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1797 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1798 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1799 if (!intel_iommu->caching_mode) { 1800 error_setg(errp, "Device assignment is not allowed without " 1801 "enabling caching-mode=on for Intel IOMMU."); 1802 return false; 1803 } 1804 } 1805 1806 return true; 1807 } 1808 1809 static void pc_machine_class_init(ObjectClass *oc, void *data) 1810 { 1811 MachineClass *mc = MACHINE_CLASS(oc); 1812 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1813 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1814 1815 pcmc->pci_enabled = true; 1816 pcmc->has_acpi_build = true; 1817 pcmc->rsdp_in_ram = true; 1818 pcmc->smbios_defaults = true; 1819 pcmc->smbios_uuid_encoded = true; 1820 pcmc->gigabyte_align = true; 1821 pcmc->has_reserved_memory = true; 1822 pcmc->kvmclock_enabled = true; 1823 pcmc->enforce_aligned_dimm = true; 1824 pcmc->enforce_amd_1tb_hole = true; 1825 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1826 * to be used at the moment, 32K should be enough for a while. */ 1827 pcmc->acpi_data_size = 0x20000 + 0x8000; 1828 pcmc->pvh_enabled = true; 1829 pcmc->kvmclock_create_always = true; 1830 pcmc->resizable_acpi_blob = true; 1831 assert(!mc->get_hotplug_handler); 1832 mc->get_hotplug_handler = pc_get_hotplug_handler; 1833 mc->hotplug_allowed = pc_hotplug_allowed; 1834 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1835 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1836 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1837 mc->auto_enable_numa_with_memhp = true; 1838 mc->auto_enable_numa_with_memdev = true; 1839 mc->has_hotpluggable_cpus = true; 1840 mc->default_boot_order = "cad"; 1841 mc->block_default_type = IF_IDE; 1842 mc->max_cpus = 255; 1843 mc->reset = pc_machine_reset; 1844 mc->wakeup = pc_machine_wakeup; 1845 hc->pre_plug = pc_machine_device_pre_plug_cb; 1846 hc->plug = pc_machine_device_plug_cb; 1847 hc->unplug_request = pc_machine_device_unplug_request_cb; 1848 hc->unplug = pc_machine_device_unplug_cb; 1849 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1850 mc->nvdimm_supported = true; 1851 mc->smp_props.dies_supported = true; 1852 mc->default_ram_id = "pc.ram"; 1853 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_64; 1854 1855 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1856 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1857 NULL, NULL); 1858 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1859 "Maximum ram below the 4G boundary (32bit boundary)"); 1860 1861 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1862 pc_machine_get_vmport, pc_machine_set_vmport, 1863 NULL, NULL); 1864 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1865 "Enable vmport (pc & q35)"); 1866 1867 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1868 pc_machine_get_smbus, pc_machine_set_smbus); 1869 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1870 "Enable/disable system management bus"); 1871 1872 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1873 pc_machine_get_sata, pc_machine_set_sata); 1874 object_class_property_set_description(oc, PC_MACHINE_SATA, 1875 "Enable/disable Serial ATA bus"); 1876 1877 object_class_property_add_bool(oc, "hpet", 1878 pc_machine_get_hpet, pc_machine_set_hpet); 1879 object_class_property_set_description(oc, "hpet", 1880 "Enable/disable high precision event timer emulation"); 1881 1882 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1883 pc_machine_get_i8042, pc_machine_set_i8042); 1884 1885 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1886 pc_machine_get_default_bus_bypass_iommu, 1887 pc_machine_set_default_bus_bypass_iommu); 1888 1889 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1890 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1891 NULL, NULL); 1892 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1893 "Maximum combined firmware size"); 1894 1895 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1896 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1897 NULL, NULL); 1898 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1899 "SMBIOS Entry Point type [32, 64]"); 1900 } 1901 1902 static const TypeInfo pc_machine_info = { 1903 .name = TYPE_PC_MACHINE, 1904 .parent = TYPE_X86_MACHINE, 1905 .abstract = true, 1906 .instance_size = sizeof(PCMachineState), 1907 .instance_init = pc_machine_initfn, 1908 .class_size = sizeof(PCMachineClass), 1909 .class_init = pc_machine_class_init, 1910 .interfaces = (InterfaceInfo[]) { 1911 { TYPE_HOTPLUG_HANDLER }, 1912 { } 1913 }, 1914 }; 1915 1916 static void pc_machine_register_types(void) 1917 { 1918 type_register_static(&pc_machine_info); 1919 } 1920 1921 type_init(pc_machine_register_types) 1922