1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/smbios/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/boards.h" 63 #include "hw/pci/pci_host.h" 64 #include "acpi-build.h" 65 #include "hw/mem/pc-dimm.h" 66 #include "qapi/visitor.h" 67 #include "qapi-visit.h" 68 #include "qom/cpu.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 #define BIOS_CFG_IOPORT 0x510 81 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 82 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 83 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 84 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 85 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 86 87 #define E820_NR_ENTRIES 16 88 89 struct e820_entry { 90 uint64_t address; 91 uint64_t length; 92 uint32_t type; 93 } QEMU_PACKED __attribute((__aligned__(4))); 94 95 struct e820_table { 96 uint32_t count; 97 struct e820_entry entry[E820_NR_ENTRIES]; 98 } QEMU_PACKED __attribute((__aligned__(4))); 99 100 static struct e820_table e820_reserve; 101 static struct e820_entry *e820_table; 102 static unsigned e820_entries; 103 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 104 105 void gsi_handler(void *opaque, int n, int level) 106 { 107 GSIState *s = opaque; 108 109 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 110 if (n < ISA_NUM_IRQS) { 111 qemu_set_irq(s->i8259_irq[n], level); 112 } 113 qemu_set_irq(s->ioapic_irq[n], level); 114 } 115 116 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 117 unsigned size) 118 { 119 } 120 121 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 122 { 123 return 0xffffffffffffffffULL; 124 } 125 126 /* MSDOS compatibility mode FPU exception support */ 127 static qemu_irq ferr_irq; 128 129 void pc_register_ferr_irq(qemu_irq irq) 130 { 131 ferr_irq = irq; 132 } 133 134 /* XXX: add IGNNE support */ 135 void cpu_set_ferr(CPUX86State *s) 136 { 137 qemu_irq_raise(ferr_irq); 138 } 139 140 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 141 unsigned size) 142 { 143 qemu_irq_lower(ferr_irq); 144 } 145 146 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 147 { 148 return 0xffffffffffffffffULL; 149 } 150 151 /* TSC handling */ 152 uint64_t cpu_get_tsc(CPUX86State *env) 153 { 154 return cpu_get_ticks(); 155 } 156 157 /* IRQ handling */ 158 int cpu_get_pic_interrupt(CPUX86State *env) 159 { 160 X86CPU *cpu = x86_env_get_cpu(env); 161 int intno; 162 163 intno = apic_get_interrupt(cpu->apic_state); 164 if (intno >= 0) { 165 return intno; 166 } 167 /* read the irq from the PIC */ 168 if (!apic_accept_pic_intr(cpu->apic_state)) { 169 return -1; 170 } 171 172 intno = pic_read_irq(isa_pic); 173 return intno; 174 } 175 176 static void pic_irq_request(void *opaque, int irq, int level) 177 { 178 CPUState *cs = first_cpu; 179 X86CPU *cpu = X86_CPU(cs); 180 181 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 182 if (cpu->apic_state) { 183 CPU_FOREACH(cs) { 184 cpu = X86_CPU(cs); 185 if (apic_accept_pic_intr(cpu->apic_state)) { 186 apic_deliver_pic_intr(cpu->apic_state, level); 187 } 188 } 189 } else { 190 if (level) { 191 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 192 } else { 193 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 194 } 195 } 196 } 197 198 /* PC cmos mappings */ 199 200 #define REG_EQUIPMENT_BYTE 0x14 201 202 static int cmos_get_fd_drive_type(FDriveType fd0) 203 { 204 int val; 205 206 switch (fd0) { 207 case FDRIVE_DRV_144: 208 /* 1.44 Mb 3"5 drive */ 209 val = 4; 210 break; 211 case FDRIVE_DRV_288: 212 /* 2.88 Mb 3"5 drive */ 213 val = 5; 214 break; 215 case FDRIVE_DRV_120: 216 /* 1.2 Mb 5"5 drive */ 217 val = 2; 218 break; 219 case FDRIVE_DRV_NONE: 220 default: 221 val = 0; 222 break; 223 } 224 return val; 225 } 226 227 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 228 int16_t cylinders, int8_t heads, int8_t sectors) 229 { 230 rtc_set_memory(s, type_ofs, 47); 231 rtc_set_memory(s, info_ofs, cylinders); 232 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 233 rtc_set_memory(s, info_ofs + 2, heads); 234 rtc_set_memory(s, info_ofs + 3, 0xff); 235 rtc_set_memory(s, info_ofs + 4, 0xff); 236 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 237 rtc_set_memory(s, info_ofs + 6, cylinders); 238 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 239 rtc_set_memory(s, info_ofs + 8, sectors); 240 } 241 242 /* convert boot_device letter to something recognizable by the bios */ 243 static int boot_device2nibble(char boot_device) 244 { 245 switch(boot_device) { 246 case 'a': 247 case 'b': 248 return 0x01; /* floppy boot */ 249 case 'c': 250 return 0x02; /* hard drive boot */ 251 case 'd': 252 return 0x03; /* CD-ROM boot */ 253 case 'n': 254 return 0x04; /* Network boot */ 255 } 256 return 0; 257 } 258 259 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 260 { 261 #define PC_MAX_BOOT_DEVICES 3 262 int nbds, bds[3] = { 0, }; 263 int i; 264 265 nbds = strlen(boot_device); 266 if (nbds > PC_MAX_BOOT_DEVICES) { 267 error_setg(errp, "Too many boot devices for PC"); 268 return; 269 } 270 for (i = 0; i < nbds; i++) { 271 bds[i] = boot_device2nibble(boot_device[i]); 272 if (bds[i] == 0) { 273 error_setg(errp, "Invalid boot device for PC: '%c'", 274 boot_device[i]); 275 return; 276 } 277 } 278 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 279 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 280 } 281 282 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 283 { 284 set_boot_dev(opaque, boot_device, errp); 285 } 286 287 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 288 { 289 int val, nb, i; 290 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 291 292 /* floppy type */ 293 if (floppy) { 294 for (i = 0; i < 2; i++) { 295 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 296 } 297 } 298 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 299 cmos_get_fd_drive_type(fd_type[1]); 300 rtc_set_memory(rtc_state, 0x10, val); 301 302 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 303 nb = 0; 304 if (fd_type[0] < FDRIVE_DRV_NONE) { 305 nb++; 306 } 307 if (fd_type[1] < FDRIVE_DRV_NONE) { 308 nb++; 309 } 310 switch (nb) { 311 case 0: 312 break; 313 case 1: 314 val |= 0x01; /* 1 drive, ready for boot */ 315 break; 316 case 2: 317 val |= 0x41; /* 2 drives, ready for boot */ 318 break; 319 } 320 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 321 } 322 323 typedef struct pc_cmos_init_late_arg { 324 ISADevice *rtc_state; 325 BusState *idebus[2]; 326 } pc_cmos_init_late_arg; 327 328 typedef struct check_fdc_state { 329 ISADevice *floppy; 330 bool multiple; 331 } CheckFdcState; 332 333 static int check_fdc(Object *obj, void *opaque) 334 { 335 CheckFdcState *state = opaque; 336 Object *fdc; 337 uint32_t iobase; 338 Error *local_err = NULL; 339 340 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 341 if (!fdc) { 342 return 0; 343 } 344 345 iobase = object_property_get_int(obj, "iobase", &local_err); 346 if (local_err || iobase != 0x3f0) { 347 error_free(local_err); 348 return 0; 349 } 350 351 if (state->floppy) { 352 state->multiple = true; 353 } else { 354 state->floppy = ISA_DEVICE(obj); 355 } 356 return 0; 357 } 358 359 static const char * const fdc_container_path[] = { 360 "/unattached", "/peripheral", "/peripheral-anon" 361 }; 362 363 static void pc_cmos_init_late(void *opaque) 364 { 365 pc_cmos_init_late_arg *arg = opaque; 366 ISADevice *s = arg->rtc_state; 367 int16_t cylinders; 368 int8_t heads, sectors; 369 int val; 370 int i, trans; 371 Object *container; 372 CheckFdcState state = { 0 }; 373 374 val = 0; 375 if (ide_get_geometry(arg->idebus[0], 0, 376 &cylinders, &heads, §ors) >= 0) { 377 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 378 val |= 0xf0; 379 } 380 if (ide_get_geometry(arg->idebus[0], 1, 381 &cylinders, &heads, §ors) >= 0) { 382 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 383 val |= 0x0f; 384 } 385 rtc_set_memory(s, 0x12, val); 386 387 val = 0; 388 for (i = 0; i < 4; i++) { 389 /* NOTE: ide_get_geometry() returns the physical 390 geometry. It is always such that: 1 <= sects <= 63, 1 391 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 392 geometry can be different if a translation is done. */ 393 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 394 &cylinders, &heads, §ors) >= 0) { 395 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 396 assert((trans & ~3) == 0); 397 val |= trans << (i * 2); 398 } 399 } 400 rtc_set_memory(s, 0x39, val); 401 402 /* 403 * Locate the FDC at IO address 0x3f0, and configure the CMOS registers 404 * accordingly. 405 */ 406 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 407 container = container_get(qdev_get_machine(), fdc_container_path[i]); 408 object_child_foreach(container, check_fdc, &state); 409 } 410 411 if (state.multiple) { 412 error_report("warning: multiple floppy disk controllers with " 413 "iobase=0x3f0 have been found;\n" 414 "the one being picked for CMOS setup might not reflect " 415 "your intent"); 416 } 417 pc_cmos_init_floppy(s, state.floppy); 418 419 qemu_unregister_reset(pc_cmos_init_late, opaque); 420 } 421 422 void pc_cmos_init(PCMachineState *pcms, 423 BusState *idebus0, BusState *idebus1, 424 ISADevice *s) 425 { 426 int val; 427 static pc_cmos_init_late_arg arg; 428 Error *local_err = NULL; 429 430 /* various important CMOS locations needed by PC/Bochs bios */ 431 432 /* memory size */ 433 /* base memory (first MiB) */ 434 val = MIN(pcms->below_4g_mem_size / 1024, 640); 435 rtc_set_memory(s, 0x15, val); 436 rtc_set_memory(s, 0x16, val >> 8); 437 /* extended memory (next 64MiB) */ 438 if (pcms->below_4g_mem_size > 1024 * 1024) { 439 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 440 } else { 441 val = 0; 442 } 443 if (val > 65535) 444 val = 65535; 445 rtc_set_memory(s, 0x17, val); 446 rtc_set_memory(s, 0x18, val >> 8); 447 rtc_set_memory(s, 0x30, val); 448 rtc_set_memory(s, 0x31, val >> 8); 449 /* memory between 16MiB and 4GiB */ 450 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 451 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 452 } else { 453 val = 0; 454 } 455 if (val > 65535) 456 val = 65535; 457 rtc_set_memory(s, 0x34, val); 458 rtc_set_memory(s, 0x35, val >> 8); 459 /* memory above 4GiB */ 460 val = pcms->above_4g_mem_size / 65536; 461 rtc_set_memory(s, 0x5b, val); 462 rtc_set_memory(s, 0x5c, val >> 8); 463 rtc_set_memory(s, 0x5d, val >> 16); 464 465 /* set the number of CPU */ 466 rtc_set_memory(s, 0x5f, smp_cpus - 1); 467 468 object_property_add_link(OBJECT(pcms), "rtc_state", 469 TYPE_ISA_DEVICE, 470 (Object **)&pcms->rtc, 471 object_property_allow_set_link, 472 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 473 object_property_set_link(OBJECT(pcms), OBJECT(s), 474 "rtc_state", &error_abort); 475 476 set_boot_dev(s, MACHINE(pcms)->boot_order, &local_err); 477 if (local_err) { 478 error_report_err(local_err); 479 exit(1); 480 } 481 482 val = 0; 483 val |= 0x02; /* FPU is there */ 484 val |= 0x04; /* PS/2 mouse installed */ 485 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 486 487 /* hard drives and FDC */ 488 arg.rtc_state = s; 489 arg.idebus[0] = idebus0; 490 arg.idebus[1] = idebus1; 491 qemu_register_reset(pc_cmos_init_late, &arg); 492 } 493 494 #define TYPE_PORT92 "port92" 495 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 496 497 /* port 92 stuff: could be split off */ 498 typedef struct Port92State { 499 ISADevice parent_obj; 500 501 MemoryRegion io; 502 uint8_t outport; 503 qemu_irq *a20_out; 504 } Port92State; 505 506 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 507 unsigned size) 508 { 509 Port92State *s = opaque; 510 int oldval = s->outport; 511 512 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 513 s->outport = val; 514 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 515 if ((val & 1) && !(oldval & 1)) { 516 qemu_system_reset_request(); 517 } 518 } 519 520 static uint64_t port92_read(void *opaque, hwaddr addr, 521 unsigned size) 522 { 523 Port92State *s = opaque; 524 uint32_t ret; 525 526 ret = s->outport; 527 DPRINTF("port92: read 0x%02x\n", ret); 528 return ret; 529 } 530 531 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 532 { 533 Port92State *s = PORT92(dev); 534 535 s->a20_out = a20_out; 536 } 537 538 static const VMStateDescription vmstate_port92_isa = { 539 .name = "port92", 540 .version_id = 1, 541 .minimum_version_id = 1, 542 .fields = (VMStateField[]) { 543 VMSTATE_UINT8(outport, Port92State), 544 VMSTATE_END_OF_LIST() 545 } 546 }; 547 548 static void port92_reset(DeviceState *d) 549 { 550 Port92State *s = PORT92(d); 551 552 s->outport &= ~1; 553 } 554 555 static const MemoryRegionOps port92_ops = { 556 .read = port92_read, 557 .write = port92_write, 558 .impl = { 559 .min_access_size = 1, 560 .max_access_size = 1, 561 }, 562 .endianness = DEVICE_LITTLE_ENDIAN, 563 }; 564 565 static void port92_initfn(Object *obj) 566 { 567 Port92State *s = PORT92(obj); 568 569 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 570 571 s->outport = 0; 572 } 573 574 static void port92_realizefn(DeviceState *dev, Error **errp) 575 { 576 ISADevice *isadev = ISA_DEVICE(dev); 577 Port92State *s = PORT92(dev); 578 579 isa_register_ioport(isadev, &s->io, 0x92); 580 } 581 582 static void port92_class_initfn(ObjectClass *klass, void *data) 583 { 584 DeviceClass *dc = DEVICE_CLASS(klass); 585 586 dc->realize = port92_realizefn; 587 dc->reset = port92_reset; 588 dc->vmsd = &vmstate_port92_isa; 589 /* 590 * Reason: unlike ordinary ISA devices, this one needs additional 591 * wiring: its A20 output line needs to be wired up by 592 * port92_init(). 593 */ 594 dc->cannot_instantiate_with_device_add_yet = true; 595 } 596 597 static const TypeInfo port92_info = { 598 .name = TYPE_PORT92, 599 .parent = TYPE_ISA_DEVICE, 600 .instance_size = sizeof(Port92State), 601 .instance_init = port92_initfn, 602 .class_init = port92_class_initfn, 603 }; 604 605 static void port92_register_types(void) 606 { 607 type_register_static(&port92_info); 608 } 609 610 type_init(port92_register_types) 611 612 static void handle_a20_line_change(void *opaque, int irq, int level) 613 { 614 X86CPU *cpu = opaque; 615 616 /* XXX: send to all CPUs ? */ 617 /* XXX: add logic to handle multiple A20 line sources */ 618 x86_cpu_set_a20(cpu, level); 619 } 620 621 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 622 { 623 int index = le32_to_cpu(e820_reserve.count); 624 struct e820_entry *entry; 625 626 if (type != E820_RAM) { 627 /* old FW_CFG_E820_TABLE entry -- reservations only */ 628 if (index >= E820_NR_ENTRIES) { 629 return -EBUSY; 630 } 631 entry = &e820_reserve.entry[index++]; 632 633 entry->address = cpu_to_le64(address); 634 entry->length = cpu_to_le64(length); 635 entry->type = cpu_to_le32(type); 636 637 e820_reserve.count = cpu_to_le32(index); 638 } 639 640 /* new "etc/e820" file -- include ram too */ 641 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 642 e820_table[e820_entries].address = cpu_to_le64(address); 643 e820_table[e820_entries].length = cpu_to_le64(length); 644 e820_table[e820_entries].type = cpu_to_le32(type); 645 e820_entries++; 646 647 return e820_entries; 648 } 649 650 int e820_get_num_entries(void) 651 { 652 return e820_entries; 653 } 654 655 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 656 { 657 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 658 *address = le64_to_cpu(e820_table[idx].address); 659 *length = le64_to_cpu(e820_table[idx].length); 660 return true; 661 } 662 return false; 663 } 664 665 /* Enables contiguous-apic-ID mode, for compatibility */ 666 static bool compat_apic_id_mode; 667 668 void enable_compat_apic_id_mode(void) 669 { 670 compat_apic_id_mode = true; 671 } 672 673 /* Calculates initial APIC ID for a specific CPU index 674 * 675 * Currently we need to be able to calculate the APIC ID from the CPU index 676 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 677 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 678 * all CPUs up to max_cpus. 679 */ 680 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 681 { 682 uint32_t correct_id; 683 static bool warned; 684 685 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 686 if (compat_apic_id_mode) { 687 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 688 error_report("APIC IDs set in compatibility mode, " 689 "CPU topology won't match the configuration"); 690 warned = true; 691 } 692 return cpu_index; 693 } else { 694 return correct_id; 695 } 696 } 697 698 /* Calculates the limit to CPU APIC ID values 699 * 700 * This function returns the limit for the APIC ID value, so that all 701 * CPU APIC IDs are < pc_apic_id_limit(). 702 * 703 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 704 */ 705 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 706 { 707 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 708 } 709 710 static void pc_build_smbios(FWCfgState *fw_cfg) 711 { 712 uint8_t *smbios_tables, *smbios_anchor; 713 size_t smbios_tables_len, smbios_anchor_len; 714 struct smbios_phys_mem_area *mem_array; 715 unsigned i, array_count; 716 717 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 718 if (smbios_tables) { 719 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 720 smbios_tables, smbios_tables_len); 721 } 722 723 /* build the array of physical mem area from e820 table */ 724 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 725 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 726 uint64_t addr, len; 727 728 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 729 mem_array[array_count].address = addr; 730 mem_array[array_count].length = len; 731 array_count++; 732 } 733 } 734 smbios_get_tables(mem_array, array_count, 735 &smbios_tables, &smbios_tables_len, 736 &smbios_anchor, &smbios_anchor_len); 737 g_free(mem_array); 738 739 if (smbios_anchor) { 740 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 741 smbios_tables, smbios_tables_len); 742 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 743 smbios_anchor, smbios_anchor_len); 744 } 745 } 746 747 static FWCfgState *bochs_bios_init(AddressSpace *as) 748 { 749 FWCfgState *fw_cfg; 750 uint64_t *numa_fw_cfg; 751 int i, j; 752 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 753 754 fw_cfg = fw_cfg_init_io_dma(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 4, as); 755 756 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 757 * 758 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 759 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 760 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 761 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 762 * may see". 763 * 764 * So, this means we must not use max_cpus, here, but the maximum possible 765 * APIC ID value, plus one. 766 * 767 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 768 * the APIC ID, not the "CPU index" 769 */ 770 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 771 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 772 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 773 acpi_tables, acpi_tables_len); 774 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 775 776 pc_build_smbios(fw_cfg); 777 778 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 779 &e820_reserve, sizeof(e820_reserve)); 780 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 781 sizeof(struct e820_entry) * e820_entries); 782 783 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 784 /* allocate memory for the NUMA channel: one (64bit) word for the number 785 * of nodes, one word for each VCPU->node and one word for each node to 786 * hold the amount of memory. 787 */ 788 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 789 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 790 for (i = 0; i < max_cpus; i++) { 791 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 792 assert(apic_id < apic_id_limit); 793 for (j = 0; j < nb_numa_nodes; j++) { 794 if (test_bit(i, numa_info[j].node_cpu)) { 795 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 796 break; 797 } 798 } 799 } 800 for (i = 0; i < nb_numa_nodes; i++) { 801 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 802 } 803 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 804 (1 + apic_id_limit + nb_numa_nodes) * 805 sizeof(*numa_fw_cfg)); 806 807 return fw_cfg; 808 } 809 810 static long get_file_size(FILE *f) 811 { 812 long where, size; 813 814 /* XXX: on Unix systems, using fstat() probably makes more sense */ 815 816 where = ftell(f); 817 fseek(f, 0, SEEK_END); 818 size = ftell(f); 819 fseek(f, where, SEEK_SET); 820 821 return size; 822 } 823 824 static void load_linux(PCMachineState *pcms, 825 FWCfgState *fw_cfg) 826 { 827 uint16_t protocol; 828 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 829 uint32_t initrd_max; 830 uint8_t header[8192], *setup, *kernel, *initrd_data; 831 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 832 FILE *f; 833 char *vmode; 834 MachineState *machine = MACHINE(pcms); 835 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 836 const char *kernel_filename = machine->kernel_filename; 837 const char *initrd_filename = machine->initrd_filename; 838 const char *kernel_cmdline = machine->kernel_cmdline; 839 840 /* Align to 16 bytes as a paranoia measure */ 841 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 842 843 /* load the kernel header */ 844 f = fopen(kernel_filename, "rb"); 845 if (!f || !(kernel_size = get_file_size(f)) || 846 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 847 MIN(ARRAY_SIZE(header), kernel_size)) { 848 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 849 kernel_filename, strerror(errno)); 850 exit(1); 851 } 852 853 /* kernel protocol version */ 854 #if 0 855 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 856 #endif 857 if (ldl_p(header+0x202) == 0x53726448) { 858 protocol = lduw_p(header+0x206); 859 } else { 860 /* This looks like a multiboot kernel. If it is, let's stop 861 treating it like a Linux kernel. */ 862 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 863 kernel_cmdline, kernel_size, header)) { 864 return; 865 } 866 protocol = 0; 867 } 868 869 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 870 /* Low kernel */ 871 real_addr = 0x90000; 872 cmdline_addr = 0x9a000 - cmdline_size; 873 prot_addr = 0x10000; 874 } else if (protocol < 0x202) { 875 /* High but ancient kernel */ 876 real_addr = 0x90000; 877 cmdline_addr = 0x9a000 - cmdline_size; 878 prot_addr = 0x100000; 879 } else { 880 /* High and recent kernel */ 881 real_addr = 0x10000; 882 cmdline_addr = 0x20000; 883 prot_addr = 0x100000; 884 } 885 886 #if 0 887 fprintf(stderr, 888 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 889 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 890 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 891 real_addr, 892 cmdline_addr, 893 prot_addr); 894 #endif 895 896 /* highest address for loading the initrd */ 897 if (protocol >= 0x203) { 898 initrd_max = ldl_p(header+0x22c); 899 } else { 900 initrd_max = 0x37ffffff; 901 } 902 903 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 904 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 905 } 906 907 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 908 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 909 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 910 911 if (protocol >= 0x202) { 912 stl_p(header+0x228, cmdline_addr); 913 } else { 914 stw_p(header+0x20, 0xA33F); 915 stw_p(header+0x22, cmdline_addr-real_addr); 916 } 917 918 /* handle vga= parameter */ 919 vmode = strstr(kernel_cmdline, "vga="); 920 if (vmode) { 921 unsigned int video_mode; 922 /* skip "vga=" */ 923 vmode += 4; 924 if (!strncmp(vmode, "normal", 6)) { 925 video_mode = 0xffff; 926 } else if (!strncmp(vmode, "ext", 3)) { 927 video_mode = 0xfffe; 928 } else if (!strncmp(vmode, "ask", 3)) { 929 video_mode = 0xfffd; 930 } else { 931 video_mode = strtol(vmode, NULL, 0); 932 } 933 stw_p(header+0x1fa, video_mode); 934 } 935 936 /* loader type */ 937 /* High nybble = B reserved for QEMU; low nybble is revision number. 938 If this code is substantially changed, you may want to consider 939 incrementing the revision. */ 940 if (protocol >= 0x200) { 941 header[0x210] = 0xB0; 942 } 943 /* heap */ 944 if (protocol >= 0x201) { 945 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 946 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 947 } 948 949 /* load initrd */ 950 if (initrd_filename) { 951 if (protocol < 0x200) { 952 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 953 exit(1); 954 } 955 956 initrd_size = get_image_size(initrd_filename); 957 if (initrd_size < 0) { 958 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 959 initrd_filename, strerror(errno)); 960 exit(1); 961 } 962 963 initrd_addr = (initrd_max-initrd_size) & ~4095; 964 965 initrd_data = g_malloc(initrd_size); 966 load_image(initrd_filename, initrd_data); 967 968 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 969 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 970 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 971 972 stl_p(header+0x218, initrd_addr); 973 stl_p(header+0x21c, initrd_size); 974 } 975 976 /* load kernel and setup */ 977 setup_size = header[0x1f1]; 978 if (setup_size == 0) { 979 setup_size = 4; 980 } 981 setup_size = (setup_size+1)*512; 982 if (setup_size > kernel_size) { 983 fprintf(stderr, "qemu: invalid kernel header\n"); 984 exit(1); 985 } 986 kernel_size -= setup_size; 987 988 setup = g_malloc(setup_size); 989 kernel = g_malloc(kernel_size); 990 fseek(f, 0, SEEK_SET); 991 if (fread(setup, 1, setup_size, f) != setup_size) { 992 fprintf(stderr, "fread() failed\n"); 993 exit(1); 994 } 995 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 996 fprintf(stderr, "fread() failed\n"); 997 exit(1); 998 } 999 fclose(f); 1000 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1001 1002 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1003 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1004 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1005 1006 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1007 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1008 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1009 1010 option_rom[nb_option_roms].name = "linuxboot.bin"; 1011 option_rom[nb_option_roms].bootindex = 0; 1012 nb_option_roms++; 1013 } 1014 1015 #define NE2000_NB_MAX 6 1016 1017 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1018 0x280, 0x380 }; 1019 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1020 1021 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1022 { 1023 static int nb_ne2k = 0; 1024 1025 if (nb_ne2k == NE2000_NB_MAX) 1026 return; 1027 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1028 ne2000_irq[nb_ne2k], nd); 1029 nb_ne2k++; 1030 } 1031 1032 DeviceState *cpu_get_current_apic(void) 1033 { 1034 if (current_cpu) { 1035 X86CPU *cpu = X86_CPU(current_cpu); 1036 return cpu->apic_state; 1037 } else { 1038 return NULL; 1039 } 1040 } 1041 1042 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1043 { 1044 X86CPU *cpu = opaque; 1045 1046 if (level) { 1047 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1048 } 1049 } 1050 1051 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1052 Error **errp) 1053 { 1054 X86CPU *cpu = NULL; 1055 Error *local_err = NULL; 1056 1057 cpu = cpu_x86_create(cpu_model, &local_err); 1058 if (local_err != NULL) { 1059 goto out; 1060 } 1061 1062 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1063 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1064 1065 out: 1066 if (local_err) { 1067 error_propagate(errp, local_err); 1068 object_unref(OBJECT(cpu)); 1069 cpu = NULL; 1070 } 1071 return cpu; 1072 } 1073 1074 void pc_hot_add_cpu(const int64_t id, Error **errp) 1075 { 1076 X86CPU *cpu; 1077 MachineState *machine = MACHINE(qdev_get_machine()); 1078 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1079 Error *local_err = NULL; 1080 1081 if (id < 0) { 1082 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1083 return; 1084 } 1085 1086 if (cpu_exists(apic_id)) { 1087 error_setg(errp, "Unable to add CPU: %" PRIi64 1088 ", it already exists", id); 1089 return; 1090 } 1091 1092 if (id >= max_cpus) { 1093 error_setg(errp, "Unable to add CPU: %" PRIi64 1094 ", max allowed: %d", id, max_cpus - 1); 1095 return; 1096 } 1097 1098 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1099 error_setg(errp, "Unable to add CPU: %" PRIi64 1100 ", resulting APIC ID (%" PRIi64 ") is too large", 1101 id, apic_id); 1102 return; 1103 } 1104 1105 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1106 if (local_err) { 1107 error_propagate(errp, local_err); 1108 return; 1109 } 1110 object_unref(OBJECT(cpu)); 1111 } 1112 1113 void pc_cpus_init(PCMachineState *pcms) 1114 { 1115 int i; 1116 X86CPU *cpu = NULL; 1117 MachineState *machine = MACHINE(pcms); 1118 Error *error = NULL; 1119 unsigned long apic_id_limit; 1120 1121 /* init CPUs */ 1122 if (machine->cpu_model == NULL) { 1123 #ifdef TARGET_X86_64 1124 machine->cpu_model = "qemu64"; 1125 #else 1126 machine->cpu_model = "qemu32"; 1127 #endif 1128 } 1129 1130 apic_id_limit = pc_apic_id_limit(max_cpus); 1131 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1132 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1133 apic_id_limit - 1); 1134 exit(1); 1135 } 1136 1137 for (i = 0; i < smp_cpus; i++) { 1138 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1139 &error); 1140 if (error) { 1141 error_report_err(error); 1142 exit(1); 1143 } 1144 object_unref(OBJECT(cpu)); 1145 } 1146 1147 /* tell smbios about cpuid version and features */ 1148 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1149 } 1150 1151 /* pci-info ROM file. Little endian format */ 1152 typedef struct PcRomPciInfo { 1153 uint64_t w32_min; 1154 uint64_t w32_max; 1155 uint64_t w64_min; 1156 uint64_t w64_max; 1157 } PcRomPciInfo; 1158 1159 typedef struct PcGuestInfoState { 1160 PcGuestInfo info; 1161 Notifier machine_done; 1162 } PcGuestInfoState; 1163 1164 static 1165 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1166 { 1167 PcGuestInfoState *guest_info_state = container_of(notifier, 1168 PcGuestInfoState, 1169 machine_done); 1170 PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; 1171 1172 if (bus) { 1173 int extra_hosts = 0; 1174 1175 QLIST_FOREACH(bus, &bus->child, sibling) { 1176 /* look for expander root buses */ 1177 if (pci_bus_is_root(bus)) { 1178 extra_hosts++; 1179 } 1180 } 1181 if (extra_hosts && guest_info_state->info.fw_cfg) { 1182 uint64_t *val = g_malloc(sizeof(*val)); 1183 *val = cpu_to_le64(extra_hosts); 1184 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1185 "etc/extra-pci-roots", val, sizeof(*val)); 1186 } 1187 } 1188 1189 acpi_setup(&guest_info_state->info); 1190 } 1191 1192 PcGuestInfo *pc_guest_info_init(PCMachineState *pcms) 1193 { 1194 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1195 PcGuestInfo *guest_info = &guest_info_state->info; 1196 int i, j; 1197 1198 guest_info->ram_size_below_4g = pcms->below_4g_mem_size; 1199 guest_info->ram_size = pcms->below_4g_mem_size + pcms->above_4g_mem_size; 1200 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1201 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1202 guest_info->numa_nodes = nb_numa_nodes; 1203 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1204 sizeof *guest_info->node_mem); 1205 for (i = 0; i < nb_numa_nodes; i++) { 1206 guest_info->node_mem[i] = numa_info[i].node_mem; 1207 } 1208 1209 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1210 sizeof *guest_info->node_cpu); 1211 1212 for (i = 0; i < max_cpus; i++) { 1213 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1214 assert(apic_id < guest_info->apic_id_limit); 1215 for (j = 0; j < nb_numa_nodes; j++) { 1216 if (test_bit(i, numa_info[j].node_cpu)) { 1217 guest_info->node_cpu[apic_id] = j; 1218 break; 1219 } 1220 } 1221 } 1222 1223 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1224 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1225 return guest_info; 1226 } 1227 1228 /* setup pci memory address space mapping into system address space */ 1229 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1230 MemoryRegion *pci_address_space) 1231 { 1232 /* Set to lower priority than RAM */ 1233 memory_region_add_subregion_overlap(system_memory, 0x0, 1234 pci_address_space, -1); 1235 } 1236 1237 void pc_acpi_init(const char *default_dsdt) 1238 { 1239 char *filename; 1240 1241 if (acpi_tables != NULL) { 1242 /* manually set via -acpitable, leave it alone */ 1243 return; 1244 } 1245 1246 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1247 if (filename == NULL) { 1248 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1249 } else { 1250 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1251 &error_abort); 1252 Error *err = NULL; 1253 1254 qemu_opt_set(opts, "file", filename, &error_abort); 1255 1256 acpi_table_add_builtin(opts, &err); 1257 if (err) { 1258 error_report("WARNING: failed to load %s: %s", filename, 1259 error_get_pretty(err)); 1260 error_free(err); 1261 } 1262 g_free(filename); 1263 } 1264 } 1265 1266 FWCfgState *xen_load_linux(PCMachineState *pcms, 1267 PcGuestInfo *guest_info) 1268 { 1269 int i; 1270 FWCfgState *fw_cfg; 1271 1272 assert(MACHINE(pcms)->kernel_filename != NULL); 1273 1274 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1275 rom_set_fw(fw_cfg); 1276 1277 load_linux(pcms, fw_cfg); 1278 for (i = 0; i < nb_option_roms; i++) { 1279 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1280 !strcmp(option_rom[i].name, "multiboot.bin")); 1281 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1282 } 1283 guest_info->fw_cfg = fw_cfg; 1284 return fw_cfg; 1285 } 1286 1287 FWCfgState *pc_memory_init(PCMachineState *pcms, 1288 MemoryRegion *system_memory, 1289 MemoryRegion *rom_memory, 1290 MemoryRegion **ram_memory, 1291 PcGuestInfo *guest_info) 1292 { 1293 int linux_boot, i; 1294 MemoryRegion *ram, *option_rom_mr; 1295 MemoryRegion *ram_below_4g, *ram_above_4g; 1296 FWCfgState *fw_cfg; 1297 MachineState *machine = MACHINE(pcms); 1298 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1299 1300 assert(machine->ram_size == pcms->below_4g_mem_size + 1301 pcms->above_4g_mem_size); 1302 1303 linux_boot = (machine->kernel_filename != NULL); 1304 1305 /* Allocate RAM. We allocate it as a single memory region and use 1306 * aliases to address portions of it, mostly for backwards compatibility 1307 * with older qemus that used qemu_ram_alloc(). 1308 */ 1309 ram = g_malloc(sizeof(*ram)); 1310 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1311 machine->ram_size); 1312 *ram_memory = ram; 1313 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1314 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1315 0, pcms->below_4g_mem_size); 1316 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1317 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1318 if (pcms->above_4g_mem_size > 0) { 1319 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1320 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1321 pcms->below_4g_mem_size, 1322 pcms->above_4g_mem_size); 1323 memory_region_add_subregion(system_memory, 0x100000000ULL, 1324 ram_above_4g); 1325 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1326 } 1327 1328 if (!guest_info->has_reserved_memory && 1329 (machine->ram_slots || 1330 (machine->maxram_size > machine->ram_size))) { 1331 MachineClass *mc = MACHINE_GET_CLASS(machine); 1332 1333 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1334 mc->name); 1335 exit(EXIT_FAILURE); 1336 } 1337 1338 /* initialize hotplug memory address space */ 1339 if (guest_info->has_reserved_memory && 1340 (machine->ram_size < machine->maxram_size)) { 1341 ram_addr_t hotplug_mem_size = 1342 machine->maxram_size - machine->ram_size; 1343 1344 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1345 error_report("unsupported amount of memory slots: %"PRIu64, 1346 machine->ram_slots); 1347 exit(EXIT_FAILURE); 1348 } 1349 1350 if (QEMU_ALIGN_UP(machine->maxram_size, 1351 TARGET_PAGE_SIZE) != machine->maxram_size) { 1352 error_report("maximum memory size must by aligned to multiple of " 1353 "%d bytes", TARGET_PAGE_SIZE); 1354 exit(EXIT_FAILURE); 1355 } 1356 1357 pcms->hotplug_memory.base = 1358 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1359 1360 if (pcmc->enforce_aligned_dimm) { 1361 /* size hotplug region assuming 1G page max alignment per slot */ 1362 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1363 } 1364 1365 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1366 hotplug_mem_size) { 1367 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1368 machine->maxram_size); 1369 exit(EXIT_FAILURE); 1370 } 1371 1372 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1373 "hotplug-memory", hotplug_mem_size); 1374 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1375 &pcms->hotplug_memory.mr); 1376 } 1377 1378 /* Initialize PC system firmware */ 1379 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1380 1381 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1382 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1383 &error_fatal); 1384 vmstate_register_ram_global(option_rom_mr); 1385 memory_region_add_subregion_overlap(rom_memory, 1386 PC_ROM_MIN_VGA, 1387 option_rom_mr, 1388 1); 1389 1390 fw_cfg = bochs_bios_init(&address_space_memory); 1391 1392 rom_set_fw(fw_cfg); 1393 1394 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1395 uint64_t *val = g_malloc(sizeof(*val)); 1396 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1397 uint64_t res_mem_end = pcms->hotplug_memory.base; 1398 1399 if (!pcmc->broken_reserved_end) { 1400 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1401 } 1402 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1403 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1404 } 1405 1406 if (linux_boot) { 1407 load_linux(pcms, fw_cfg); 1408 } 1409 1410 for (i = 0; i < nb_option_roms; i++) { 1411 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1412 } 1413 guest_info->fw_cfg = fw_cfg; 1414 return fw_cfg; 1415 } 1416 1417 qemu_irq pc_allocate_cpu_irq(void) 1418 { 1419 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1420 } 1421 1422 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1423 { 1424 DeviceState *dev = NULL; 1425 1426 if (pci_bus) { 1427 PCIDevice *pcidev = pci_vga_init(pci_bus); 1428 dev = pcidev ? &pcidev->qdev : NULL; 1429 } else if (isa_bus) { 1430 ISADevice *isadev = isa_vga_init(isa_bus); 1431 dev = isadev ? DEVICE(isadev) : NULL; 1432 } 1433 return dev; 1434 } 1435 1436 static const MemoryRegionOps ioport80_io_ops = { 1437 .write = ioport80_write, 1438 .read = ioport80_read, 1439 .endianness = DEVICE_NATIVE_ENDIAN, 1440 .impl = { 1441 .min_access_size = 1, 1442 .max_access_size = 1, 1443 }, 1444 }; 1445 1446 static const MemoryRegionOps ioportF0_io_ops = { 1447 .write = ioportF0_write, 1448 .read = ioportF0_read, 1449 .endianness = DEVICE_NATIVE_ENDIAN, 1450 .impl = { 1451 .min_access_size = 1, 1452 .max_access_size = 1, 1453 }, 1454 }; 1455 1456 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1457 ISADevice **rtc_state, 1458 bool create_fdctrl, 1459 bool no_vmport, 1460 uint32 hpet_irqs) 1461 { 1462 int i; 1463 DriveInfo *fd[MAX_FD]; 1464 DeviceState *hpet = NULL; 1465 int pit_isa_irq = 0; 1466 qemu_irq pit_alt_irq = NULL; 1467 qemu_irq rtc_irq = NULL; 1468 qemu_irq *a20_line; 1469 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1470 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1471 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1472 1473 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1474 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1475 1476 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1477 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1478 1479 /* 1480 * Check if an HPET shall be created. 1481 * 1482 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1483 * when the HPET wants to take over. Thus we have to disable the latter. 1484 */ 1485 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1486 /* In order to set property, here not using sysbus_try_create_simple */ 1487 hpet = qdev_try_create(NULL, TYPE_HPET); 1488 if (hpet) { 1489 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1490 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1491 * IRQ8 and IRQ2. 1492 */ 1493 uint8_t compat = object_property_get_int(OBJECT(hpet), 1494 HPET_INTCAP, NULL); 1495 if (!compat) { 1496 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1497 } 1498 qdev_init_nofail(hpet); 1499 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1500 1501 for (i = 0; i < GSI_NUM_PINS; i++) { 1502 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1503 } 1504 pit_isa_irq = -1; 1505 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1506 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1507 } 1508 } 1509 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1510 1511 qemu_register_boot_set(pc_boot_set, *rtc_state); 1512 1513 if (!xen_enabled()) { 1514 if (kvm_pit_in_kernel()) { 1515 pit = kvm_pit_init(isa_bus, 0x40); 1516 } else { 1517 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1518 } 1519 if (hpet) { 1520 /* connect PIT to output control line of the HPET */ 1521 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1522 } 1523 pcspk_init(isa_bus, pit); 1524 } 1525 1526 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1527 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1528 1529 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1530 i8042 = isa_create_simple(isa_bus, "i8042"); 1531 i8042_setup_a20_line(i8042, &a20_line[0]); 1532 if (!no_vmport) { 1533 vmport_init(isa_bus); 1534 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1535 } else { 1536 vmmouse = NULL; 1537 } 1538 if (vmmouse) { 1539 DeviceState *dev = DEVICE(vmmouse); 1540 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1541 qdev_init_nofail(dev); 1542 } 1543 port92 = isa_create_simple(isa_bus, "port92"); 1544 port92_init(port92, &a20_line[1]); 1545 1546 DMA_init(0); 1547 1548 for(i = 0; i < MAX_FD; i++) { 1549 fd[i] = drive_get(IF_FLOPPY, 0, i); 1550 create_fdctrl |= !!fd[i]; 1551 } 1552 if (create_fdctrl) { 1553 fdctrl_init_isa(isa_bus, fd); 1554 } 1555 } 1556 1557 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1558 { 1559 int i; 1560 1561 for (i = 0; i < nb_nics; i++) { 1562 NICInfo *nd = &nd_table[i]; 1563 1564 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1565 pc_init_ne2k_isa(isa_bus, nd); 1566 } else { 1567 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1568 } 1569 } 1570 } 1571 1572 void pc_pci_device_init(PCIBus *pci_bus) 1573 { 1574 int max_bus; 1575 int bus; 1576 1577 max_bus = drive_get_max_bus(IF_SCSI); 1578 for (bus = 0; bus <= max_bus; bus++) { 1579 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1580 } 1581 } 1582 1583 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1584 { 1585 DeviceState *dev; 1586 SysBusDevice *d; 1587 unsigned int i; 1588 1589 if (kvm_ioapic_in_kernel()) { 1590 dev = qdev_create(NULL, "kvm-ioapic"); 1591 } else { 1592 dev = qdev_create(NULL, "ioapic"); 1593 } 1594 if (parent_name) { 1595 object_property_add_child(object_resolve_path(parent_name, NULL), 1596 "ioapic", OBJECT(dev), NULL); 1597 } 1598 qdev_init_nofail(dev); 1599 d = SYS_BUS_DEVICE(dev); 1600 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1601 1602 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1603 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1604 } 1605 } 1606 1607 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1608 DeviceState *dev, Error **errp) 1609 { 1610 HotplugHandlerClass *hhc; 1611 Error *local_err = NULL; 1612 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1613 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1614 PCDIMMDevice *dimm = PC_DIMM(dev); 1615 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1616 MemoryRegion *mr = ddc->get_memory_region(dimm); 1617 uint64_t align = TARGET_PAGE_SIZE; 1618 1619 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1620 align = memory_region_get_alignment(mr); 1621 } 1622 1623 if (!pcms->acpi_dev) { 1624 error_setg(&local_err, 1625 "memory hotplug is not enabled: missing acpi device"); 1626 goto out; 1627 } 1628 1629 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1630 if (local_err) { 1631 goto out; 1632 } 1633 1634 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1635 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1636 out: 1637 error_propagate(errp, local_err); 1638 } 1639 1640 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1641 DeviceState *dev, Error **errp) 1642 { 1643 HotplugHandlerClass *hhc; 1644 Error *local_err = NULL; 1645 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1646 1647 if (!pcms->acpi_dev) { 1648 error_setg(&local_err, 1649 "memory hotplug is not enabled: missing acpi device"); 1650 goto out; 1651 } 1652 1653 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1654 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1655 1656 out: 1657 error_propagate(errp, local_err); 1658 } 1659 1660 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1661 DeviceState *dev, Error **errp) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1664 PCDIMMDevice *dimm = PC_DIMM(dev); 1665 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1666 MemoryRegion *mr = ddc->get_memory_region(dimm); 1667 HotplugHandlerClass *hhc; 1668 Error *local_err = NULL; 1669 1670 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1671 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1672 1673 if (local_err) { 1674 goto out; 1675 } 1676 1677 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1678 object_unparent(OBJECT(dev)); 1679 1680 out: 1681 error_propagate(errp, local_err); 1682 } 1683 1684 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1685 DeviceState *dev, Error **errp) 1686 { 1687 HotplugHandlerClass *hhc; 1688 Error *local_err = NULL; 1689 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1690 1691 if (!dev->hotplugged) { 1692 goto out; 1693 } 1694 1695 if (!pcms->acpi_dev) { 1696 error_setg(&local_err, 1697 "cpu hotplug is not enabled: missing acpi device"); 1698 goto out; 1699 } 1700 1701 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1702 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1703 if (local_err) { 1704 goto out; 1705 } 1706 1707 /* increment the number of CPUs */ 1708 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1709 out: 1710 error_propagate(errp, local_err); 1711 } 1712 1713 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1714 DeviceState *dev, Error **errp) 1715 { 1716 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1717 pc_dimm_plug(hotplug_dev, dev, errp); 1718 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1719 pc_cpu_plug(hotplug_dev, dev, errp); 1720 } 1721 } 1722 1723 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1724 DeviceState *dev, Error **errp) 1725 { 1726 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1727 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1728 } else { 1729 error_setg(errp, "acpi: device unplug request for not supported device" 1730 " type: %s", object_get_typename(OBJECT(dev))); 1731 } 1732 } 1733 1734 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1735 DeviceState *dev, Error **errp) 1736 { 1737 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1738 pc_dimm_unplug(hotplug_dev, dev, errp); 1739 } else { 1740 error_setg(errp, "acpi: device unplug for not supported device" 1741 " type: %s", object_get_typename(OBJECT(dev))); 1742 } 1743 } 1744 1745 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1746 DeviceState *dev) 1747 { 1748 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1749 1750 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1751 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1752 return HOTPLUG_HANDLER(machine); 1753 } 1754 1755 return pcmc->get_hotplug_handler ? 1756 pcmc->get_hotplug_handler(machine, dev) : NULL; 1757 } 1758 1759 static void 1760 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1761 const char *name, Error **errp) 1762 { 1763 PCMachineState *pcms = PC_MACHINE(obj); 1764 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1765 1766 visit_type_int(v, &value, name, errp); 1767 } 1768 1769 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1770 void *opaque, const char *name, 1771 Error **errp) 1772 { 1773 PCMachineState *pcms = PC_MACHINE(obj); 1774 uint64_t value = pcms->max_ram_below_4g; 1775 1776 visit_type_size(v, &value, name, errp); 1777 } 1778 1779 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1780 void *opaque, const char *name, 1781 Error **errp) 1782 { 1783 PCMachineState *pcms = PC_MACHINE(obj); 1784 Error *error = NULL; 1785 uint64_t value; 1786 1787 visit_type_size(v, &value, name, &error); 1788 if (error) { 1789 error_propagate(errp, error); 1790 return; 1791 } 1792 if (value > (1ULL << 32)) { 1793 error_setg(&error, 1794 "Machine option 'max-ram-below-4g=%"PRIu64 1795 "' expects size less than or equal to 4G", value); 1796 error_propagate(errp, error); 1797 return; 1798 } 1799 1800 if (value < (1ULL << 20)) { 1801 error_report("Warning: small max_ram_below_4g(%"PRIu64 1802 ") less than 1M. BIOS may not work..", 1803 value); 1804 } 1805 1806 pcms->max_ram_below_4g = value; 1807 } 1808 1809 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1810 const char *name, Error **errp) 1811 { 1812 PCMachineState *pcms = PC_MACHINE(obj); 1813 OnOffAuto vmport = pcms->vmport; 1814 1815 visit_type_OnOffAuto(v, &vmport, name, errp); 1816 } 1817 1818 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1819 const char *name, Error **errp) 1820 { 1821 PCMachineState *pcms = PC_MACHINE(obj); 1822 1823 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1824 } 1825 1826 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1827 { 1828 bool smm_available = false; 1829 1830 if (pcms->smm == ON_OFF_AUTO_OFF) { 1831 return false; 1832 } 1833 1834 if (tcg_enabled() || qtest_enabled()) { 1835 smm_available = true; 1836 } else if (kvm_enabled()) { 1837 smm_available = kvm_has_smm(); 1838 } 1839 1840 if (smm_available) { 1841 return true; 1842 } 1843 1844 if (pcms->smm == ON_OFF_AUTO_ON) { 1845 error_report("System Management Mode not supported by this hypervisor."); 1846 exit(1); 1847 } 1848 return false; 1849 } 1850 1851 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1852 const char *name, Error **errp) 1853 { 1854 PCMachineState *pcms = PC_MACHINE(obj); 1855 OnOffAuto smm = pcms->smm; 1856 1857 visit_type_OnOffAuto(v, &smm, name, errp); 1858 } 1859 1860 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1861 const char *name, Error **errp) 1862 { 1863 PCMachineState *pcms = PC_MACHINE(obj); 1864 1865 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1866 } 1867 1868 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 1869 { 1870 PCMachineState *pcms = PC_MACHINE(obj); 1871 1872 return pcms->nvdimm; 1873 } 1874 1875 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 1876 { 1877 PCMachineState *pcms = PC_MACHINE(obj); 1878 1879 pcms->nvdimm = value; 1880 } 1881 1882 static void pc_machine_initfn(Object *obj) 1883 { 1884 PCMachineState *pcms = PC_MACHINE(obj); 1885 1886 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1887 pc_machine_get_hotplug_memory_region_size, 1888 NULL, NULL, NULL, &error_abort); 1889 1890 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1891 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1892 pc_machine_get_max_ram_below_4g, 1893 pc_machine_set_max_ram_below_4g, 1894 NULL, NULL, &error_abort); 1895 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1896 "Maximum ram below the 4G boundary (32bit boundary)", 1897 &error_abort); 1898 1899 pcms->smm = ON_OFF_AUTO_AUTO; 1900 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1901 pc_machine_get_smm, 1902 pc_machine_set_smm, 1903 NULL, NULL, &error_abort); 1904 object_property_set_description(obj, PC_MACHINE_SMM, 1905 "Enable SMM (pc & q35)", 1906 &error_abort); 1907 1908 pcms->vmport = ON_OFF_AUTO_AUTO; 1909 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1910 pc_machine_get_vmport, 1911 pc_machine_set_vmport, 1912 NULL, NULL, &error_abort); 1913 object_property_set_description(obj, PC_MACHINE_VMPORT, 1914 "Enable vmport (pc & q35)", 1915 &error_abort); 1916 1917 /* nvdimm is disabled on default. */ 1918 pcms->nvdimm = false; 1919 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, 1920 pc_machine_set_nvdimm, &error_abort); 1921 } 1922 1923 static void pc_machine_reset(void) 1924 { 1925 CPUState *cs; 1926 X86CPU *cpu; 1927 1928 qemu_devices_reset(); 1929 1930 /* Reset APIC after devices have been reset to cancel 1931 * any changes that qemu_devices_reset() might have done. 1932 */ 1933 CPU_FOREACH(cs) { 1934 cpu = X86_CPU(cs); 1935 1936 if (cpu->apic_state) { 1937 device_reset(cpu->apic_state); 1938 } 1939 } 1940 } 1941 1942 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1943 { 1944 X86CPUTopoInfo topo; 1945 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1946 &topo); 1947 return topo.pkg_id; 1948 } 1949 1950 static void pc_machine_class_init(ObjectClass *oc, void *data) 1951 { 1952 MachineClass *mc = MACHINE_CLASS(oc); 1953 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1954 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1955 1956 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1957 pcmc->pci_enabled = true; 1958 pcmc->has_acpi_build = true; 1959 pcmc->rsdp_in_ram = true; 1960 pcmc->smbios_defaults = true; 1961 pcmc->smbios_uuid_encoded = true; 1962 pcmc->gigabyte_align = true; 1963 pcmc->has_reserved_memory = true; 1964 pcmc->kvmclock_enabled = true; 1965 pcmc->enforce_aligned_dimm = true; 1966 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1967 * to be used at the moment, 32K should be enough for a while. */ 1968 pcmc->acpi_data_size = 0x20000 + 0x8000; 1969 mc->get_hotplug_handler = pc_get_hotpug_handler; 1970 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1971 mc->default_boot_order = "cad"; 1972 mc->hot_add_cpu = pc_hot_add_cpu; 1973 mc->max_cpus = 255; 1974 mc->reset = pc_machine_reset; 1975 hc->plug = pc_machine_device_plug_cb; 1976 hc->unplug_request = pc_machine_device_unplug_request_cb; 1977 hc->unplug = pc_machine_device_unplug_cb; 1978 } 1979 1980 static const TypeInfo pc_machine_info = { 1981 .name = TYPE_PC_MACHINE, 1982 .parent = TYPE_MACHINE, 1983 .abstract = true, 1984 .instance_size = sizeof(PCMachineState), 1985 .instance_init = pc_machine_initfn, 1986 .class_size = sizeof(PCMachineClass), 1987 .class_init = pc_machine_class_init, 1988 .interfaces = (InterfaceInfo[]) { 1989 { TYPE_HOTPLUG_HANDLER }, 1990 { } 1991 }, 1992 }; 1993 1994 static void pc_machine_register_types(void) 1995 { 1996 type_register_static(&pc_machine_info); 1997 } 1998 1999 type_init(pc_machine_register_types) 2000