1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "monitor/monitor.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/i386/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "kvm_i386.h" 49 #include "hw/xen/xen.h" 50 #include "sysemu/block-backend.h" 51 #include "hw/block/block.h" 52 #include "ui/qemu-spice.h" 53 #include "exec/memory.h" 54 #include "exec/address-spaces.h" 55 #include "sysemu/arch_init.h" 56 #include "qemu/bitmap.h" 57 #include "qemu/config-file.h" 58 #include "hw/acpi/acpi.h" 59 #include "hw/acpi/cpu_hotplug.h" 60 #include "hw/cpu/icc_bus.h" 61 #include "hw/boards.h" 62 #include "hw/pci/pci_host.h" 63 #include "acpi-build.h" 64 #include "hw/mem/pc-dimm.h" 65 #include "trace.h" 66 #include "qapi/visitor.h" 67 #include "qapi-visit.h" 68 69 /* debug PC/ISA interrupts */ 70 //#define DEBUG_IRQ 71 72 #ifdef DEBUG_IRQ 73 #define DPRINTF(fmt, ...) \ 74 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 75 #else 76 #define DPRINTF(fmt, ...) 77 #endif 78 79 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 80 * (128K) and other BIOS datastructures (less than 4K reported to be used at 81 * the moment, 32K should be enough for a while). */ 82 static unsigned acpi_data_size = 0x20000 + 0x8000; 83 void pc_set_legacy_acpi_data_size(void) 84 { 85 acpi_data_size = 0x10000; 86 } 87 88 #define BIOS_CFG_IOPORT 0x510 89 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 90 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 91 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 92 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 93 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 94 95 #define E820_NR_ENTRIES 16 96 97 struct e820_entry { 98 uint64_t address; 99 uint64_t length; 100 uint32_t type; 101 } QEMU_PACKED __attribute((__aligned__(4))); 102 103 struct e820_table { 104 uint32_t count; 105 struct e820_entry entry[E820_NR_ENTRIES]; 106 } QEMU_PACKED __attribute((__aligned__(4))); 107 108 static struct e820_table e820_reserve; 109 static struct e820_entry *e820_table; 110 static unsigned e820_entries; 111 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 112 113 void gsi_handler(void *opaque, int n, int level) 114 { 115 GSIState *s = opaque; 116 117 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 118 if (n < ISA_NUM_IRQS) { 119 qemu_set_irq(s->i8259_irq[n], level); 120 } 121 qemu_set_irq(s->ioapic_irq[n], level); 122 } 123 124 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 125 unsigned size) 126 { 127 } 128 129 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 130 { 131 return 0xffffffffffffffffULL; 132 } 133 134 /* MSDOS compatibility mode FPU exception support */ 135 static qemu_irq ferr_irq; 136 137 void pc_register_ferr_irq(qemu_irq irq) 138 { 139 ferr_irq = irq; 140 } 141 142 /* XXX: add IGNNE support */ 143 void cpu_set_ferr(CPUX86State *s) 144 { 145 qemu_irq_raise(ferr_irq); 146 } 147 148 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 149 unsigned size) 150 { 151 qemu_irq_lower(ferr_irq); 152 } 153 154 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 155 { 156 return 0xffffffffffffffffULL; 157 } 158 159 /* TSC handling */ 160 uint64_t cpu_get_tsc(CPUX86State *env) 161 { 162 return cpu_get_ticks(); 163 } 164 165 /* SMM support */ 166 167 static cpu_set_smm_t smm_set; 168 static void *smm_arg; 169 170 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 171 { 172 assert(smm_set == NULL); 173 assert(smm_arg == NULL); 174 smm_set = callback; 175 smm_arg = arg; 176 } 177 178 void cpu_smm_update(CPUX86State *env) 179 { 180 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 181 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 182 } 183 } 184 185 186 /* IRQ handling */ 187 int cpu_get_pic_interrupt(CPUX86State *env) 188 { 189 X86CPU *cpu = x86_env_get_cpu(env); 190 int intno; 191 192 intno = apic_get_interrupt(cpu->apic_state); 193 if (intno >= 0) { 194 return intno; 195 } 196 /* read the irq from the PIC */ 197 if (!apic_accept_pic_intr(cpu->apic_state)) { 198 return -1; 199 } 200 201 intno = pic_read_irq(isa_pic); 202 return intno; 203 } 204 205 static void pic_irq_request(void *opaque, int irq, int level) 206 { 207 CPUState *cs = first_cpu; 208 X86CPU *cpu = X86_CPU(cs); 209 210 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 211 if (cpu->apic_state) { 212 CPU_FOREACH(cs) { 213 cpu = X86_CPU(cs); 214 if (apic_accept_pic_intr(cpu->apic_state)) { 215 apic_deliver_pic_intr(cpu->apic_state, level); 216 } 217 } 218 } else { 219 if (level) { 220 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 221 } else { 222 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 223 } 224 } 225 } 226 227 /* PC cmos mappings */ 228 229 #define REG_EQUIPMENT_BYTE 0x14 230 231 static int cmos_get_fd_drive_type(FDriveType fd0) 232 { 233 int val; 234 235 switch (fd0) { 236 case FDRIVE_DRV_144: 237 /* 1.44 Mb 3"5 drive */ 238 val = 4; 239 break; 240 case FDRIVE_DRV_288: 241 /* 2.88 Mb 3"5 drive */ 242 val = 5; 243 break; 244 case FDRIVE_DRV_120: 245 /* 1.2 Mb 5"5 drive */ 246 val = 2; 247 break; 248 case FDRIVE_DRV_NONE: 249 default: 250 val = 0; 251 break; 252 } 253 return val; 254 } 255 256 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 257 int16_t cylinders, int8_t heads, int8_t sectors) 258 { 259 rtc_set_memory(s, type_ofs, 47); 260 rtc_set_memory(s, info_ofs, cylinders); 261 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 262 rtc_set_memory(s, info_ofs + 2, heads); 263 rtc_set_memory(s, info_ofs + 3, 0xff); 264 rtc_set_memory(s, info_ofs + 4, 0xff); 265 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 266 rtc_set_memory(s, info_ofs + 6, cylinders); 267 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 268 rtc_set_memory(s, info_ofs + 8, sectors); 269 } 270 271 /* convert boot_device letter to something recognizable by the bios */ 272 static int boot_device2nibble(char boot_device) 273 { 274 switch(boot_device) { 275 case 'a': 276 case 'b': 277 return 0x01; /* floppy boot */ 278 case 'c': 279 return 0x02; /* hard drive boot */ 280 case 'd': 281 return 0x03; /* CD-ROM boot */ 282 case 'n': 283 return 0x04; /* Network boot */ 284 } 285 return 0; 286 } 287 288 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 289 { 290 #define PC_MAX_BOOT_DEVICES 3 291 int nbds, bds[3] = { 0, }; 292 int i; 293 294 nbds = strlen(boot_device); 295 if (nbds > PC_MAX_BOOT_DEVICES) { 296 error_setg(errp, "Too many boot devices for PC"); 297 return; 298 } 299 for (i = 0; i < nbds; i++) { 300 bds[i] = boot_device2nibble(boot_device[i]); 301 if (bds[i] == 0) { 302 error_setg(errp, "Invalid boot device for PC: '%c'", 303 boot_device[i]); 304 return; 305 } 306 } 307 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 308 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 309 } 310 311 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 312 { 313 set_boot_dev(opaque, boot_device, errp); 314 } 315 316 typedef struct pc_cmos_init_late_arg { 317 ISADevice *rtc_state; 318 BusState *idebus[2]; 319 } pc_cmos_init_late_arg; 320 321 static void pc_cmos_init_late(void *opaque) 322 { 323 pc_cmos_init_late_arg *arg = opaque; 324 ISADevice *s = arg->rtc_state; 325 int16_t cylinders; 326 int8_t heads, sectors; 327 int val; 328 int i, trans; 329 330 val = 0; 331 if (ide_get_geometry(arg->idebus[0], 0, 332 &cylinders, &heads, §ors) >= 0) { 333 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 334 val |= 0xf0; 335 } 336 if (ide_get_geometry(arg->idebus[0], 1, 337 &cylinders, &heads, §ors) >= 0) { 338 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 339 val |= 0x0f; 340 } 341 rtc_set_memory(s, 0x12, val); 342 343 val = 0; 344 for (i = 0; i < 4; i++) { 345 /* NOTE: ide_get_geometry() returns the physical 346 geometry. It is always such that: 1 <= sects <= 63, 1 347 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 348 geometry can be different if a translation is done. */ 349 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 350 &cylinders, &heads, §ors) >= 0) { 351 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 352 assert((trans & ~3) == 0); 353 val |= trans << (i * 2); 354 } 355 } 356 rtc_set_memory(s, 0x39, val); 357 358 qemu_unregister_reset(pc_cmos_init_late, opaque); 359 } 360 361 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 362 const char *boot_device, MachineState *machine, 363 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 364 ISADevice *s) 365 { 366 int val, nb, i; 367 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 368 static pc_cmos_init_late_arg arg; 369 PCMachineState *pc_machine = PC_MACHINE(machine); 370 Error *local_err = NULL; 371 372 /* various important CMOS locations needed by PC/Bochs bios */ 373 374 /* memory size */ 375 /* base memory (first MiB) */ 376 val = MIN(ram_size / 1024, 640); 377 rtc_set_memory(s, 0x15, val); 378 rtc_set_memory(s, 0x16, val >> 8); 379 /* extended memory (next 64MiB) */ 380 if (ram_size > 1024 * 1024) { 381 val = (ram_size - 1024 * 1024) / 1024; 382 } else { 383 val = 0; 384 } 385 if (val > 65535) 386 val = 65535; 387 rtc_set_memory(s, 0x17, val); 388 rtc_set_memory(s, 0x18, val >> 8); 389 rtc_set_memory(s, 0x30, val); 390 rtc_set_memory(s, 0x31, val >> 8); 391 /* memory between 16MiB and 4GiB */ 392 if (ram_size > 16 * 1024 * 1024) { 393 val = (ram_size - 16 * 1024 * 1024) / 65536; 394 } else { 395 val = 0; 396 } 397 if (val > 65535) 398 val = 65535; 399 rtc_set_memory(s, 0x34, val); 400 rtc_set_memory(s, 0x35, val >> 8); 401 /* memory above 4GiB */ 402 val = above_4g_mem_size / 65536; 403 rtc_set_memory(s, 0x5b, val); 404 rtc_set_memory(s, 0x5c, val >> 8); 405 rtc_set_memory(s, 0x5d, val >> 16); 406 407 /* set the number of CPU */ 408 rtc_set_memory(s, 0x5f, smp_cpus - 1); 409 410 object_property_add_link(OBJECT(machine), "rtc_state", 411 TYPE_ISA_DEVICE, 412 (Object **)&pc_machine->rtc, 413 object_property_allow_set_link, 414 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 415 object_property_set_link(OBJECT(machine), OBJECT(s), 416 "rtc_state", &error_abort); 417 418 set_boot_dev(s, boot_device, &local_err); 419 if (local_err) { 420 error_report_err(local_err); 421 exit(1); 422 } 423 424 /* floppy type */ 425 if (floppy) { 426 for (i = 0; i < 2; i++) { 427 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 428 } 429 } 430 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 431 cmos_get_fd_drive_type(fd_type[1]); 432 rtc_set_memory(s, 0x10, val); 433 434 val = 0; 435 nb = 0; 436 if (fd_type[0] < FDRIVE_DRV_NONE) { 437 nb++; 438 } 439 if (fd_type[1] < FDRIVE_DRV_NONE) { 440 nb++; 441 } 442 switch (nb) { 443 case 0: 444 break; 445 case 1: 446 val |= 0x01; /* 1 drive, ready for boot */ 447 break; 448 case 2: 449 val |= 0x41; /* 2 drives, ready for boot */ 450 break; 451 } 452 val |= 0x02; /* FPU is there */ 453 val |= 0x04; /* PS/2 mouse installed */ 454 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 455 456 /* hard drives */ 457 arg.rtc_state = s; 458 arg.idebus[0] = idebus0; 459 arg.idebus[1] = idebus1; 460 qemu_register_reset(pc_cmos_init_late, &arg); 461 } 462 463 #define TYPE_PORT92 "port92" 464 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 465 466 /* port 92 stuff: could be split off */ 467 typedef struct Port92State { 468 ISADevice parent_obj; 469 470 MemoryRegion io; 471 uint8_t outport; 472 qemu_irq *a20_out; 473 } Port92State; 474 475 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 476 unsigned size) 477 { 478 Port92State *s = opaque; 479 int oldval = s->outport; 480 481 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 482 s->outport = val; 483 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 484 if ((val & 1) && !(oldval & 1)) { 485 qemu_system_reset_request(); 486 } 487 } 488 489 static uint64_t port92_read(void *opaque, hwaddr addr, 490 unsigned size) 491 { 492 Port92State *s = opaque; 493 uint32_t ret; 494 495 ret = s->outport; 496 DPRINTF("port92: read 0x%02x\n", ret); 497 return ret; 498 } 499 500 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 501 { 502 Port92State *s = PORT92(dev); 503 504 s->a20_out = a20_out; 505 } 506 507 static const VMStateDescription vmstate_port92_isa = { 508 .name = "port92", 509 .version_id = 1, 510 .minimum_version_id = 1, 511 .fields = (VMStateField[]) { 512 VMSTATE_UINT8(outport, Port92State), 513 VMSTATE_END_OF_LIST() 514 } 515 }; 516 517 static void port92_reset(DeviceState *d) 518 { 519 Port92State *s = PORT92(d); 520 521 s->outport &= ~1; 522 } 523 524 static const MemoryRegionOps port92_ops = { 525 .read = port92_read, 526 .write = port92_write, 527 .impl = { 528 .min_access_size = 1, 529 .max_access_size = 1, 530 }, 531 .endianness = DEVICE_LITTLE_ENDIAN, 532 }; 533 534 static void port92_initfn(Object *obj) 535 { 536 Port92State *s = PORT92(obj); 537 538 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 539 540 s->outport = 0; 541 } 542 543 static void port92_realizefn(DeviceState *dev, Error **errp) 544 { 545 ISADevice *isadev = ISA_DEVICE(dev); 546 Port92State *s = PORT92(dev); 547 548 isa_register_ioport(isadev, &s->io, 0x92); 549 } 550 551 static void port92_class_initfn(ObjectClass *klass, void *data) 552 { 553 DeviceClass *dc = DEVICE_CLASS(klass); 554 555 dc->realize = port92_realizefn; 556 dc->reset = port92_reset; 557 dc->vmsd = &vmstate_port92_isa; 558 /* 559 * Reason: unlike ordinary ISA devices, this one needs additional 560 * wiring: its A20 output line needs to be wired up by 561 * port92_init(). 562 */ 563 dc->cannot_instantiate_with_device_add_yet = true; 564 } 565 566 static const TypeInfo port92_info = { 567 .name = TYPE_PORT92, 568 .parent = TYPE_ISA_DEVICE, 569 .instance_size = sizeof(Port92State), 570 .instance_init = port92_initfn, 571 .class_init = port92_class_initfn, 572 }; 573 574 static void port92_register_types(void) 575 { 576 type_register_static(&port92_info); 577 } 578 579 type_init(port92_register_types) 580 581 static void handle_a20_line_change(void *opaque, int irq, int level) 582 { 583 X86CPU *cpu = opaque; 584 585 /* XXX: send to all CPUs ? */ 586 /* XXX: add logic to handle multiple A20 line sources */ 587 x86_cpu_set_a20(cpu, level); 588 } 589 590 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 591 { 592 int index = le32_to_cpu(e820_reserve.count); 593 struct e820_entry *entry; 594 595 if (type != E820_RAM) { 596 /* old FW_CFG_E820_TABLE entry -- reservations only */ 597 if (index >= E820_NR_ENTRIES) { 598 return -EBUSY; 599 } 600 entry = &e820_reserve.entry[index++]; 601 602 entry->address = cpu_to_le64(address); 603 entry->length = cpu_to_le64(length); 604 entry->type = cpu_to_le32(type); 605 606 e820_reserve.count = cpu_to_le32(index); 607 } 608 609 /* new "etc/e820" file -- include ram too */ 610 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 611 e820_table[e820_entries].address = cpu_to_le64(address); 612 e820_table[e820_entries].length = cpu_to_le64(length); 613 e820_table[e820_entries].type = cpu_to_le32(type); 614 e820_entries++; 615 616 return e820_entries; 617 } 618 619 int e820_get_num_entries(void) 620 { 621 return e820_entries; 622 } 623 624 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 625 { 626 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 627 *address = le64_to_cpu(e820_table[idx].address); 628 *length = le64_to_cpu(e820_table[idx].length); 629 return true; 630 } 631 return false; 632 } 633 634 /* Enables contiguous-apic-ID mode, for compatibility */ 635 static bool compat_apic_id_mode; 636 637 void enable_compat_apic_id_mode(void) 638 { 639 compat_apic_id_mode = true; 640 } 641 642 /* Calculates initial APIC ID for a specific CPU index 643 * 644 * Currently we need to be able to calculate the APIC ID from the CPU index 645 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 646 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 647 * all CPUs up to max_cpus. 648 */ 649 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 650 { 651 uint32_t correct_id; 652 static bool warned; 653 654 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 655 if (compat_apic_id_mode) { 656 if (cpu_index != correct_id && !warned) { 657 error_report("APIC IDs set in compatibility mode, " 658 "CPU topology won't match the configuration"); 659 warned = true; 660 } 661 return cpu_index; 662 } else { 663 return correct_id; 664 } 665 } 666 667 /* Calculates the limit to CPU APIC ID values 668 * 669 * This function returns the limit for the APIC ID value, so that all 670 * CPU APIC IDs are < pc_apic_id_limit(). 671 * 672 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 673 */ 674 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 675 { 676 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 677 } 678 679 static FWCfgState *bochs_bios_init(void) 680 { 681 FWCfgState *fw_cfg; 682 uint8_t *smbios_tables, *smbios_anchor; 683 size_t smbios_tables_len, smbios_anchor_len; 684 uint64_t *numa_fw_cfg; 685 int i, j; 686 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 687 688 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 689 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 690 * 691 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 692 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 693 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 694 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 695 * may see". 696 * 697 * So, this means we must not use max_cpus, here, but the maximum possible 698 * APIC ID value, plus one. 699 * 700 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 701 * the APIC ID, not the "CPU index" 702 */ 703 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 704 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 705 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 706 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 707 acpi_tables, acpi_tables_len); 708 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 709 710 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 711 if (smbios_tables) { 712 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 713 smbios_tables, smbios_tables_len); 714 } 715 716 smbios_get_tables(&smbios_tables, &smbios_tables_len, 717 &smbios_anchor, &smbios_anchor_len); 718 if (smbios_anchor) { 719 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 720 smbios_tables, smbios_tables_len); 721 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 722 smbios_anchor, smbios_anchor_len); 723 } 724 725 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 726 &e820_reserve, sizeof(e820_reserve)); 727 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 728 sizeof(struct e820_entry) * e820_entries); 729 730 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 731 /* allocate memory for the NUMA channel: one (64bit) word for the number 732 * of nodes, one word for each VCPU->node and one word for each node to 733 * hold the amount of memory. 734 */ 735 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 736 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 737 for (i = 0; i < max_cpus; i++) { 738 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 739 assert(apic_id < apic_id_limit); 740 for (j = 0; j < nb_numa_nodes; j++) { 741 if (test_bit(i, numa_info[j].node_cpu)) { 742 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 743 break; 744 } 745 } 746 } 747 for (i = 0; i < nb_numa_nodes; i++) { 748 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 749 } 750 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 751 (1 + apic_id_limit + nb_numa_nodes) * 752 sizeof(*numa_fw_cfg)); 753 754 return fw_cfg; 755 } 756 757 static long get_file_size(FILE *f) 758 { 759 long where, size; 760 761 /* XXX: on Unix systems, using fstat() probably makes more sense */ 762 763 where = ftell(f); 764 fseek(f, 0, SEEK_END); 765 size = ftell(f); 766 fseek(f, where, SEEK_SET); 767 768 return size; 769 } 770 771 static void load_linux(FWCfgState *fw_cfg, 772 const char *kernel_filename, 773 const char *initrd_filename, 774 const char *kernel_cmdline, 775 hwaddr max_ram_size) 776 { 777 uint16_t protocol; 778 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 779 uint32_t initrd_max; 780 uint8_t header[8192], *setup, *kernel, *initrd_data; 781 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 782 FILE *f; 783 char *vmode; 784 785 /* Align to 16 bytes as a paranoia measure */ 786 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 787 788 /* load the kernel header */ 789 f = fopen(kernel_filename, "rb"); 790 if (!f || !(kernel_size = get_file_size(f)) || 791 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 792 MIN(ARRAY_SIZE(header), kernel_size)) { 793 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 794 kernel_filename, strerror(errno)); 795 exit(1); 796 } 797 798 /* kernel protocol version */ 799 #if 0 800 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 801 #endif 802 if (ldl_p(header+0x202) == 0x53726448) { 803 protocol = lduw_p(header+0x206); 804 } else { 805 /* This looks like a multiboot kernel. If it is, let's stop 806 treating it like a Linux kernel. */ 807 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 808 kernel_cmdline, kernel_size, header)) { 809 return; 810 } 811 protocol = 0; 812 } 813 814 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 815 /* Low kernel */ 816 real_addr = 0x90000; 817 cmdline_addr = 0x9a000 - cmdline_size; 818 prot_addr = 0x10000; 819 } else if (protocol < 0x202) { 820 /* High but ancient kernel */ 821 real_addr = 0x90000; 822 cmdline_addr = 0x9a000 - cmdline_size; 823 prot_addr = 0x100000; 824 } else { 825 /* High and recent kernel */ 826 real_addr = 0x10000; 827 cmdline_addr = 0x20000; 828 prot_addr = 0x100000; 829 } 830 831 #if 0 832 fprintf(stderr, 833 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 834 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 835 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 836 real_addr, 837 cmdline_addr, 838 prot_addr); 839 #endif 840 841 /* highest address for loading the initrd */ 842 if (protocol >= 0x203) { 843 initrd_max = ldl_p(header+0x22c); 844 } else { 845 initrd_max = 0x37ffffff; 846 } 847 848 if (initrd_max >= max_ram_size - acpi_data_size) { 849 initrd_max = max_ram_size - acpi_data_size - 1; 850 } 851 852 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 853 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 854 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 855 856 if (protocol >= 0x202) { 857 stl_p(header+0x228, cmdline_addr); 858 } else { 859 stw_p(header+0x20, 0xA33F); 860 stw_p(header+0x22, cmdline_addr-real_addr); 861 } 862 863 /* handle vga= parameter */ 864 vmode = strstr(kernel_cmdline, "vga="); 865 if (vmode) { 866 unsigned int video_mode; 867 /* skip "vga=" */ 868 vmode += 4; 869 if (!strncmp(vmode, "normal", 6)) { 870 video_mode = 0xffff; 871 } else if (!strncmp(vmode, "ext", 3)) { 872 video_mode = 0xfffe; 873 } else if (!strncmp(vmode, "ask", 3)) { 874 video_mode = 0xfffd; 875 } else { 876 video_mode = strtol(vmode, NULL, 0); 877 } 878 stw_p(header+0x1fa, video_mode); 879 } 880 881 /* loader type */ 882 /* High nybble = B reserved for QEMU; low nybble is revision number. 883 If this code is substantially changed, you may want to consider 884 incrementing the revision. */ 885 if (protocol >= 0x200) { 886 header[0x210] = 0xB0; 887 } 888 /* heap */ 889 if (protocol >= 0x201) { 890 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 891 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 892 } 893 894 /* load initrd */ 895 if (initrd_filename) { 896 if (protocol < 0x200) { 897 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 898 exit(1); 899 } 900 901 initrd_size = get_image_size(initrd_filename); 902 if (initrd_size < 0) { 903 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 904 initrd_filename, strerror(errno)); 905 exit(1); 906 } 907 908 initrd_addr = (initrd_max-initrd_size) & ~4095; 909 910 initrd_data = g_malloc(initrd_size); 911 load_image(initrd_filename, initrd_data); 912 913 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 914 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 915 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 916 917 stl_p(header+0x218, initrd_addr); 918 stl_p(header+0x21c, initrd_size); 919 } 920 921 /* load kernel and setup */ 922 setup_size = header[0x1f1]; 923 if (setup_size == 0) { 924 setup_size = 4; 925 } 926 setup_size = (setup_size+1)*512; 927 kernel_size -= setup_size; 928 929 setup = g_malloc(setup_size); 930 kernel = g_malloc(kernel_size); 931 fseek(f, 0, SEEK_SET); 932 if (fread(setup, 1, setup_size, f) != setup_size) { 933 fprintf(stderr, "fread() failed\n"); 934 exit(1); 935 } 936 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 937 fprintf(stderr, "fread() failed\n"); 938 exit(1); 939 } 940 fclose(f); 941 memcpy(setup, header, MIN(sizeof(header), setup_size)); 942 943 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 944 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 945 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 946 947 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 948 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 949 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 950 951 option_rom[nb_option_roms].name = "linuxboot.bin"; 952 option_rom[nb_option_roms].bootindex = 0; 953 nb_option_roms++; 954 } 955 956 #define NE2000_NB_MAX 6 957 958 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 959 0x280, 0x380 }; 960 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 961 962 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 963 { 964 static int nb_ne2k = 0; 965 966 if (nb_ne2k == NE2000_NB_MAX) 967 return; 968 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 969 ne2000_irq[nb_ne2k], nd); 970 nb_ne2k++; 971 } 972 973 DeviceState *cpu_get_current_apic(void) 974 { 975 if (current_cpu) { 976 X86CPU *cpu = X86_CPU(current_cpu); 977 return cpu->apic_state; 978 } else { 979 return NULL; 980 } 981 } 982 983 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 984 { 985 X86CPU *cpu = opaque; 986 987 if (level) { 988 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 989 } 990 } 991 992 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 993 DeviceState *icc_bridge, Error **errp) 994 { 995 X86CPU *cpu; 996 Error *local_err = NULL; 997 998 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 999 if (local_err != NULL) { 1000 error_propagate(errp, local_err); 1001 return NULL; 1002 } 1003 1004 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1005 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1006 1007 if (local_err) { 1008 error_propagate(errp, local_err); 1009 object_unref(OBJECT(cpu)); 1010 cpu = NULL; 1011 } 1012 return cpu; 1013 } 1014 1015 static const char *current_cpu_model; 1016 1017 void pc_hot_add_cpu(const int64_t id, Error **errp) 1018 { 1019 DeviceState *icc_bridge; 1020 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1021 1022 if (id < 0) { 1023 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1024 return; 1025 } 1026 1027 if (cpu_exists(apic_id)) { 1028 error_setg(errp, "Unable to add CPU: %" PRIi64 1029 ", it already exists", id); 1030 return; 1031 } 1032 1033 if (id >= max_cpus) { 1034 error_setg(errp, "Unable to add CPU: %" PRIi64 1035 ", max allowed: %d", id, max_cpus - 1); 1036 return; 1037 } 1038 1039 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1040 error_setg(errp, "Unable to add CPU: %" PRIi64 1041 ", resulting APIC ID (%" PRIi64 ") is too large", 1042 id, apic_id); 1043 return; 1044 } 1045 1046 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1047 TYPE_ICC_BRIDGE, NULL)); 1048 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1049 } 1050 1051 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1052 { 1053 int i; 1054 X86CPU *cpu = NULL; 1055 Error *error = NULL; 1056 unsigned long apic_id_limit; 1057 1058 /* init CPUs */ 1059 if (cpu_model == NULL) { 1060 #ifdef TARGET_X86_64 1061 cpu_model = "qemu64"; 1062 #else 1063 cpu_model = "qemu32"; 1064 #endif 1065 } 1066 current_cpu_model = cpu_model; 1067 1068 apic_id_limit = pc_apic_id_limit(max_cpus); 1069 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1070 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1071 apic_id_limit - 1); 1072 exit(1); 1073 } 1074 1075 for (i = 0; i < smp_cpus; i++) { 1076 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1077 icc_bridge, &error); 1078 if (error) { 1079 error_report_err(error); 1080 exit(1); 1081 } 1082 } 1083 1084 /* map APIC MMIO area if CPU has APIC */ 1085 if (cpu && cpu->apic_state) { 1086 /* XXX: what if the base changes? */ 1087 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1088 APIC_DEFAULT_ADDRESS, 0x1000); 1089 } 1090 1091 /* tell smbios about cpuid version and features */ 1092 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1093 } 1094 1095 /* pci-info ROM file. Little endian format */ 1096 typedef struct PcRomPciInfo { 1097 uint64_t w32_min; 1098 uint64_t w32_max; 1099 uint64_t w64_min; 1100 uint64_t w64_max; 1101 } PcRomPciInfo; 1102 1103 typedef struct PcGuestInfoState { 1104 PcGuestInfo info; 1105 Notifier machine_done; 1106 } PcGuestInfoState; 1107 1108 static 1109 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1110 { 1111 PcGuestInfoState *guest_info_state = container_of(notifier, 1112 PcGuestInfoState, 1113 machine_done); 1114 acpi_setup(&guest_info_state->info); 1115 } 1116 1117 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1118 ram_addr_t above_4g_mem_size) 1119 { 1120 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1121 PcGuestInfo *guest_info = &guest_info_state->info; 1122 int i, j; 1123 1124 guest_info->ram_size_below_4g = below_4g_mem_size; 1125 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1126 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1127 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1128 guest_info->numa_nodes = nb_numa_nodes; 1129 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1130 sizeof *guest_info->node_mem); 1131 for (i = 0; i < nb_numa_nodes; i++) { 1132 guest_info->node_mem[i] = numa_info[i].node_mem; 1133 } 1134 1135 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1136 sizeof *guest_info->node_cpu); 1137 1138 for (i = 0; i < max_cpus; i++) { 1139 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1140 assert(apic_id < guest_info->apic_id_limit); 1141 for (j = 0; j < nb_numa_nodes; j++) { 1142 if (test_bit(i, numa_info[j].node_cpu)) { 1143 guest_info->node_cpu[apic_id] = j; 1144 break; 1145 } 1146 } 1147 } 1148 1149 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1150 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1151 return guest_info; 1152 } 1153 1154 /* setup pci memory address space mapping into system address space */ 1155 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1156 MemoryRegion *pci_address_space) 1157 { 1158 /* Set to lower priority than RAM */ 1159 memory_region_add_subregion_overlap(system_memory, 0x0, 1160 pci_address_space, -1); 1161 } 1162 1163 void pc_acpi_init(const char *default_dsdt) 1164 { 1165 char *filename; 1166 1167 if (acpi_tables != NULL) { 1168 /* manually set via -acpitable, leave it alone */ 1169 return; 1170 } 1171 1172 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1173 if (filename == NULL) { 1174 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1175 } else { 1176 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1177 &error_abort); 1178 Error *err = NULL; 1179 1180 qemu_opt_set(opts, "file", filename, &error_abort); 1181 1182 acpi_table_add_builtin(opts, &err); 1183 if (err) { 1184 error_report("WARNING: failed to load %s: %s", filename, 1185 error_get_pretty(err)); 1186 error_free(err); 1187 } 1188 g_free(filename); 1189 } 1190 } 1191 1192 FWCfgState *xen_load_linux(const char *kernel_filename, 1193 const char *kernel_cmdline, 1194 const char *initrd_filename, 1195 ram_addr_t below_4g_mem_size, 1196 PcGuestInfo *guest_info) 1197 { 1198 int i; 1199 FWCfgState *fw_cfg; 1200 1201 assert(kernel_filename != NULL); 1202 1203 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1204 rom_set_fw(fw_cfg); 1205 1206 load_linux(fw_cfg, kernel_filename, initrd_filename, 1207 kernel_cmdline, below_4g_mem_size); 1208 for (i = 0; i < nb_option_roms; i++) { 1209 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1210 !strcmp(option_rom[i].name, "multiboot.bin")); 1211 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1212 } 1213 guest_info->fw_cfg = fw_cfg; 1214 return fw_cfg; 1215 } 1216 1217 FWCfgState *pc_memory_init(MachineState *machine, 1218 MemoryRegion *system_memory, 1219 ram_addr_t below_4g_mem_size, 1220 ram_addr_t above_4g_mem_size, 1221 MemoryRegion *rom_memory, 1222 MemoryRegion **ram_memory, 1223 PcGuestInfo *guest_info) 1224 { 1225 int linux_boot, i; 1226 MemoryRegion *ram, *option_rom_mr; 1227 MemoryRegion *ram_below_4g, *ram_above_4g; 1228 FWCfgState *fw_cfg; 1229 PCMachineState *pcms = PC_MACHINE(machine); 1230 1231 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1232 1233 linux_boot = (machine->kernel_filename != NULL); 1234 1235 /* Allocate RAM. We allocate it as a single memory region and use 1236 * aliases to address portions of it, mostly for backwards compatibility 1237 * with older qemus that used qemu_ram_alloc(). 1238 */ 1239 ram = g_malloc(sizeof(*ram)); 1240 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1241 machine->ram_size); 1242 *ram_memory = ram; 1243 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1244 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1245 0, below_4g_mem_size); 1246 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1247 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1248 if (above_4g_mem_size > 0) { 1249 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1250 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1251 below_4g_mem_size, above_4g_mem_size); 1252 memory_region_add_subregion(system_memory, 0x100000000ULL, 1253 ram_above_4g); 1254 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1255 } 1256 1257 if (!guest_info->has_reserved_memory && 1258 (machine->ram_slots || 1259 (machine->maxram_size > machine->ram_size))) { 1260 MachineClass *mc = MACHINE_GET_CLASS(machine); 1261 1262 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1263 mc->name); 1264 exit(EXIT_FAILURE); 1265 } 1266 1267 /* initialize hotplug memory address space */ 1268 if (guest_info->has_reserved_memory && 1269 (machine->ram_size < machine->maxram_size)) { 1270 ram_addr_t hotplug_mem_size = 1271 machine->maxram_size - machine->ram_size; 1272 1273 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1274 error_report("unsupported amount of memory slots: %"PRIu64, 1275 machine->ram_slots); 1276 exit(EXIT_FAILURE); 1277 } 1278 1279 if (QEMU_ALIGN_UP(machine->maxram_size, 1280 TARGET_PAGE_SIZE) != machine->maxram_size) { 1281 error_report("maximum memory size must by aligned to multiple of " 1282 "%d bytes", TARGET_PAGE_SIZE); 1283 exit(EXIT_FAILURE); 1284 } 1285 1286 pcms->hotplug_memory_base = 1287 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1288 1289 if (pcms->enforce_aligned_dimm) { 1290 /* size hotplug region assuming 1G page max alignment per slot */ 1291 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1292 } 1293 1294 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1295 hotplug_mem_size) { 1296 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1297 machine->maxram_size); 1298 exit(EXIT_FAILURE); 1299 } 1300 1301 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1302 "hotplug-memory", hotplug_mem_size); 1303 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1304 &pcms->hotplug_memory); 1305 } 1306 1307 /* Initialize PC system firmware */ 1308 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1309 1310 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1311 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1312 &error_abort); 1313 vmstate_register_ram_global(option_rom_mr); 1314 memory_region_add_subregion_overlap(rom_memory, 1315 PC_ROM_MIN_VGA, 1316 option_rom_mr, 1317 1); 1318 1319 fw_cfg = bochs_bios_init(); 1320 rom_set_fw(fw_cfg); 1321 1322 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1323 uint64_t *val = g_malloc(sizeof(*val)); 1324 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1325 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1326 } 1327 1328 if (linux_boot) { 1329 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1330 machine->kernel_cmdline, below_4g_mem_size); 1331 } 1332 1333 for (i = 0; i < nb_option_roms; i++) { 1334 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1335 } 1336 guest_info->fw_cfg = fw_cfg; 1337 return fw_cfg; 1338 } 1339 1340 qemu_irq *pc_allocate_cpu_irq(void) 1341 { 1342 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1343 } 1344 1345 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1346 { 1347 DeviceState *dev = NULL; 1348 1349 if (pci_bus) { 1350 PCIDevice *pcidev = pci_vga_init(pci_bus); 1351 dev = pcidev ? &pcidev->qdev : NULL; 1352 } else if (isa_bus) { 1353 ISADevice *isadev = isa_vga_init(isa_bus); 1354 dev = isadev ? DEVICE(isadev) : NULL; 1355 } 1356 return dev; 1357 } 1358 1359 static void cpu_request_exit(void *opaque, int irq, int level) 1360 { 1361 CPUState *cpu = current_cpu; 1362 1363 if (cpu && level) { 1364 cpu_exit(cpu); 1365 } 1366 } 1367 1368 static const MemoryRegionOps ioport80_io_ops = { 1369 .write = ioport80_write, 1370 .read = ioport80_read, 1371 .endianness = DEVICE_NATIVE_ENDIAN, 1372 .impl = { 1373 .min_access_size = 1, 1374 .max_access_size = 1, 1375 }, 1376 }; 1377 1378 static const MemoryRegionOps ioportF0_io_ops = { 1379 .write = ioportF0_write, 1380 .read = ioportF0_read, 1381 .endianness = DEVICE_NATIVE_ENDIAN, 1382 .impl = { 1383 .min_access_size = 1, 1384 .max_access_size = 1, 1385 }, 1386 }; 1387 1388 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1389 ISADevice **rtc_state, 1390 ISADevice **floppy, 1391 bool no_vmport, 1392 uint32 hpet_irqs) 1393 { 1394 int i; 1395 DriveInfo *fd[MAX_FD]; 1396 DeviceState *hpet = NULL; 1397 int pit_isa_irq = 0; 1398 qemu_irq pit_alt_irq = NULL; 1399 qemu_irq rtc_irq = NULL; 1400 qemu_irq *a20_line; 1401 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1402 qemu_irq *cpu_exit_irq; 1403 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1404 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1405 1406 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1407 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1408 1409 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1410 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1411 1412 /* 1413 * Check if an HPET shall be created. 1414 * 1415 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1416 * when the HPET wants to take over. Thus we have to disable the latter. 1417 */ 1418 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1419 /* In order to set property, here not using sysbus_try_create_simple */ 1420 hpet = qdev_try_create(NULL, TYPE_HPET); 1421 if (hpet) { 1422 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1423 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1424 * IRQ8 and IRQ2. 1425 */ 1426 uint8_t compat = object_property_get_int(OBJECT(hpet), 1427 HPET_INTCAP, NULL); 1428 if (!compat) { 1429 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1430 } 1431 qdev_init_nofail(hpet); 1432 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1433 1434 for (i = 0; i < GSI_NUM_PINS; i++) { 1435 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1436 } 1437 pit_isa_irq = -1; 1438 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1439 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1440 } 1441 } 1442 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1443 1444 qemu_register_boot_set(pc_boot_set, *rtc_state); 1445 1446 if (!xen_enabled()) { 1447 if (kvm_irqchip_in_kernel()) { 1448 pit = kvm_pit_init(isa_bus, 0x40); 1449 } else { 1450 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1451 } 1452 if (hpet) { 1453 /* connect PIT to output control line of the HPET */ 1454 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1455 } 1456 pcspk_init(isa_bus, pit); 1457 } 1458 1459 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1460 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1461 1462 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1463 i8042 = isa_create_simple(isa_bus, "i8042"); 1464 i8042_setup_a20_line(i8042, &a20_line[0]); 1465 if (!no_vmport) { 1466 vmport_init(isa_bus); 1467 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1468 } else { 1469 vmmouse = NULL; 1470 } 1471 if (vmmouse) { 1472 DeviceState *dev = DEVICE(vmmouse); 1473 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1474 qdev_init_nofail(dev); 1475 } 1476 port92 = isa_create_simple(isa_bus, "port92"); 1477 port92_init(port92, &a20_line[1]); 1478 1479 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1480 DMA_init(0, cpu_exit_irq); 1481 1482 for(i = 0; i < MAX_FD; i++) { 1483 fd[i] = drive_get(IF_FLOPPY, 0, i); 1484 } 1485 *floppy = fdctrl_init_isa(isa_bus, fd); 1486 } 1487 1488 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1489 { 1490 int i; 1491 1492 for (i = 0; i < nb_nics; i++) { 1493 NICInfo *nd = &nd_table[i]; 1494 1495 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1496 pc_init_ne2k_isa(isa_bus, nd); 1497 } else { 1498 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1499 } 1500 } 1501 } 1502 1503 void pc_pci_device_init(PCIBus *pci_bus) 1504 { 1505 int max_bus; 1506 int bus; 1507 1508 max_bus = drive_get_max_bus(IF_SCSI); 1509 for (bus = 0; bus <= max_bus; bus++) { 1510 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1511 } 1512 } 1513 1514 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1515 { 1516 DeviceState *dev; 1517 SysBusDevice *d; 1518 unsigned int i; 1519 1520 if (kvm_irqchip_in_kernel()) { 1521 dev = qdev_create(NULL, "kvm-ioapic"); 1522 } else { 1523 dev = qdev_create(NULL, "ioapic"); 1524 } 1525 if (parent_name) { 1526 object_property_add_child(object_resolve_path(parent_name, NULL), 1527 "ioapic", OBJECT(dev), NULL); 1528 } 1529 qdev_init_nofail(dev); 1530 d = SYS_BUS_DEVICE(dev); 1531 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1532 1533 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1534 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1535 } 1536 } 1537 1538 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1539 { 1540 MachineClass *mc = MACHINE_CLASS(oc); 1541 QEMUMachine *qm = data; 1542 1543 mc->family = qm->family; 1544 mc->name = qm->name; 1545 mc->alias = qm->alias; 1546 mc->desc = qm->desc; 1547 mc->init = qm->init; 1548 mc->reset = qm->reset; 1549 mc->hot_add_cpu = qm->hot_add_cpu; 1550 mc->kvm_type = qm->kvm_type; 1551 mc->block_default_type = qm->block_default_type; 1552 mc->units_per_default_bus = qm->units_per_default_bus; 1553 mc->max_cpus = qm->max_cpus; 1554 mc->no_serial = qm->no_serial; 1555 mc->no_parallel = qm->no_parallel; 1556 mc->use_virtcon = qm->use_virtcon; 1557 mc->use_sclp = qm->use_sclp; 1558 mc->no_floppy = qm->no_floppy; 1559 mc->no_cdrom = qm->no_cdrom; 1560 mc->no_sdcard = qm->no_sdcard; 1561 mc->is_default = qm->is_default; 1562 mc->default_machine_opts = qm->default_machine_opts; 1563 mc->default_boot_order = qm->default_boot_order; 1564 mc->default_display = qm->default_display; 1565 mc->compat_props = qm->compat_props; 1566 mc->hw_version = qm->hw_version; 1567 } 1568 1569 void qemu_register_pc_machine(QEMUMachine *m) 1570 { 1571 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1572 TypeInfo ti = { 1573 .name = name, 1574 .parent = TYPE_PC_MACHINE, 1575 .class_init = pc_generic_machine_class_init, 1576 .class_data = (void *)m, 1577 }; 1578 1579 type_register(&ti); 1580 g_free(name); 1581 } 1582 1583 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1584 DeviceState *dev, Error **errp) 1585 { 1586 int slot; 1587 HotplugHandlerClass *hhc; 1588 Error *local_err = NULL; 1589 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1590 MachineState *machine = MACHINE(hotplug_dev); 1591 PCDIMMDevice *dimm = PC_DIMM(dev); 1592 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1593 MemoryRegion *mr = ddc->get_memory_region(dimm); 1594 uint64_t existing_dimms_capacity = 0; 1595 uint64_t align = TARGET_PAGE_SIZE; 1596 uint64_t addr; 1597 1598 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 1599 if (local_err) { 1600 goto out; 1601 } 1602 1603 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1604 align = memory_region_get_alignment(mr); 1605 } 1606 1607 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1608 memory_region_size(&pcms->hotplug_memory), 1609 !addr ? NULL : &addr, align, 1610 memory_region_size(mr), &local_err); 1611 if (local_err) { 1612 goto out; 1613 } 1614 1615 existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); 1616 if (local_err) { 1617 goto out; 1618 } 1619 1620 if (existing_dimms_capacity + memory_region_size(mr) > 1621 machine->maxram_size - machine->ram_size) { 1622 error_setg(&local_err, "not enough space, currently 0x%" PRIx64 1623 " in use of total hot pluggable 0x" RAM_ADDR_FMT, 1624 existing_dimms_capacity, 1625 machine->maxram_size - machine->ram_size); 1626 goto out; 1627 } 1628 1629 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1630 if (local_err) { 1631 goto out; 1632 } 1633 trace_mhp_pc_dimm_assigned_address(addr); 1634 1635 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1636 if (local_err) { 1637 goto out; 1638 } 1639 1640 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1641 machine->ram_slots, &local_err); 1642 if (local_err) { 1643 goto out; 1644 } 1645 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1646 if (local_err) { 1647 goto out; 1648 } 1649 trace_mhp_pc_dimm_assigned_slot(slot); 1650 1651 if (!pcms->acpi_dev) { 1652 error_setg(&local_err, 1653 "memory hotplug is not enabled: missing acpi device"); 1654 goto out; 1655 } 1656 1657 if (kvm_enabled() && !kvm_has_free_slot(machine)) { 1658 error_setg(&local_err, "hypervisor has no free memory slots left"); 1659 goto out; 1660 } 1661 1662 memory_region_add_subregion(&pcms->hotplug_memory, 1663 addr - pcms->hotplug_memory_base, mr); 1664 vmstate_register_ram(mr, dev); 1665 1666 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1667 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1668 out: 1669 error_propagate(errp, local_err); 1670 } 1671 1672 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1673 DeviceState *dev, Error **errp) 1674 { 1675 HotplugHandlerClass *hhc; 1676 Error *local_err = NULL; 1677 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1678 1679 if (!dev->hotplugged) { 1680 goto out; 1681 } 1682 1683 if (!pcms->acpi_dev) { 1684 error_setg(&local_err, 1685 "cpu hotplug is not enabled: missing acpi device"); 1686 goto out; 1687 } 1688 1689 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1690 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1691 if (local_err) { 1692 goto out; 1693 } 1694 1695 /* increment the number of CPUs */ 1696 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1697 out: 1698 error_propagate(errp, local_err); 1699 } 1700 1701 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1702 DeviceState *dev, Error **errp) 1703 { 1704 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1705 pc_dimm_plug(hotplug_dev, dev, errp); 1706 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1707 pc_cpu_plug(hotplug_dev, dev, errp); 1708 } 1709 } 1710 1711 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1712 DeviceState *dev, Error **errp) 1713 { 1714 error_setg(errp, "acpi: device unplug request for not supported device" 1715 " type: %s", object_get_typename(OBJECT(dev))); 1716 } 1717 1718 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1719 DeviceState *dev, Error **errp) 1720 { 1721 error_setg(errp, "acpi: device unplug for not supported device" 1722 " type: %s", object_get_typename(OBJECT(dev))); 1723 } 1724 1725 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1726 DeviceState *dev) 1727 { 1728 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1729 1730 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1731 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1732 return HOTPLUG_HANDLER(machine); 1733 } 1734 1735 return pcmc->get_hotplug_handler ? 1736 pcmc->get_hotplug_handler(machine, dev) : NULL; 1737 } 1738 1739 static void 1740 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1741 const char *name, Error **errp) 1742 { 1743 PCMachineState *pcms = PC_MACHINE(obj); 1744 int64_t value = memory_region_size(&pcms->hotplug_memory); 1745 1746 visit_type_int(v, &value, name, errp); 1747 } 1748 1749 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1750 void *opaque, const char *name, 1751 Error **errp) 1752 { 1753 PCMachineState *pcms = PC_MACHINE(obj); 1754 uint64_t value = pcms->max_ram_below_4g; 1755 1756 visit_type_size(v, &value, name, errp); 1757 } 1758 1759 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1760 void *opaque, const char *name, 1761 Error **errp) 1762 { 1763 PCMachineState *pcms = PC_MACHINE(obj); 1764 Error *error = NULL; 1765 uint64_t value; 1766 1767 visit_type_size(v, &value, name, &error); 1768 if (error) { 1769 error_propagate(errp, error); 1770 return; 1771 } 1772 if (value > (1ULL << 32)) { 1773 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1774 "Machine option 'max-ram-below-4g=%"PRIu64 1775 "' expects size less than or equal to 4G", value); 1776 error_propagate(errp, error); 1777 return; 1778 } 1779 1780 if (value < (1ULL << 20)) { 1781 error_report("Warning: small max_ram_below_4g(%"PRIu64 1782 ") less than 1M. BIOS may not work..", 1783 value); 1784 } 1785 1786 pcms->max_ram_below_4g = value; 1787 } 1788 1789 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1790 const char *name, Error **errp) 1791 { 1792 PCMachineState *pcms = PC_MACHINE(obj); 1793 OnOffAuto vmport = pcms->vmport; 1794 1795 visit_type_OnOffAuto(v, &vmport, name, errp); 1796 } 1797 1798 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1799 const char *name, Error **errp) 1800 { 1801 PCMachineState *pcms = PC_MACHINE(obj); 1802 1803 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1804 } 1805 1806 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1807 { 1808 PCMachineState *pcms = PC_MACHINE(obj); 1809 1810 return pcms->enforce_aligned_dimm; 1811 } 1812 1813 static void pc_machine_initfn(Object *obj) 1814 { 1815 PCMachineState *pcms = PC_MACHINE(obj); 1816 1817 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1818 pc_machine_get_hotplug_memory_region_size, 1819 NULL, NULL, NULL, NULL); 1820 1821 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1822 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1823 pc_machine_get_max_ram_below_4g, 1824 pc_machine_set_max_ram_below_4g, 1825 NULL, NULL, NULL); 1826 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1827 "Maximum ram below the 4G boundary (32bit boundary)", 1828 NULL); 1829 1830 pcms->vmport = ON_OFF_AUTO_AUTO; 1831 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1832 pc_machine_get_vmport, 1833 pc_machine_set_vmport, 1834 NULL, NULL, NULL); 1835 object_property_set_description(obj, PC_MACHINE_VMPORT, 1836 "Enable vmport (pc & q35)", 1837 NULL); 1838 1839 pcms->enforce_aligned_dimm = true; 1840 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1841 pc_machine_get_aligned_dimm, 1842 NULL, NULL); 1843 } 1844 1845 static void pc_machine_class_init(ObjectClass *oc, void *data) 1846 { 1847 MachineClass *mc = MACHINE_CLASS(oc); 1848 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1849 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1850 1851 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1852 mc->get_hotplug_handler = pc_get_hotpug_handler; 1853 hc->plug = pc_machine_device_plug_cb; 1854 hc->unplug_request = pc_machine_device_unplug_request_cb; 1855 hc->unplug = pc_machine_device_unplug_cb; 1856 } 1857 1858 static const TypeInfo pc_machine_info = { 1859 .name = TYPE_PC_MACHINE, 1860 .parent = TYPE_MACHINE, 1861 .abstract = true, 1862 .instance_size = sizeof(PCMachineState), 1863 .instance_init = pc_machine_initfn, 1864 .class_size = sizeof(PCMachineClass), 1865 .class_init = pc_machine_class_init, 1866 .interfaces = (InterfaceInfo[]) { 1867 { TYPE_HOTPLUG_HANDLER }, 1868 { } 1869 }, 1870 }; 1871 1872 static void pc_machine_register_types(void) 1873 { 1874 type_register_static(&pc_machine_info); 1875 } 1876 1877 type_init(pc_machine_register_types) 1878