1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "monitor/monitor.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/i386/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "hw/acpi/acpi.h" 60 #include "hw/acpi/cpu_hotplug.h" 61 #include "hw/cpu/icc_bus.h" 62 #include "hw/boards.h" 63 #include "hw/pci/pci_host.h" 64 #include "acpi-build.h" 65 #include "hw/mem/pc-dimm.h" 66 #include "trace.h" 67 #include "qapi/visitor.h" 68 #include "qapi-visit.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 81 * (128K) and other BIOS datastructures (less than 4K reported to be used at 82 * the moment, 32K should be enough for a while). */ 83 static unsigned acpi_data_size = 0x20000 + 0x8000; 84 void pc_set_legacy_acpi_data_size(void) 85 { 86 acpi_data_size = 0x10000; 87 } 88 89 #define BIOS_CFG_IOPORT 0x510 90 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 91 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 92 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 93 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 94 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 95 96 #define E820_NR_ENTRIES 16 97 98 struct e820_entry { 99 uint64_t address; 100 uint64_t length; 101 uint32_t type; 102 } QEMU_PACKED __attribute((__aligned__(4))); 103 104 struct e820_table { 105 uint32_t count; 106 struct e820_entry entry[E820_NR_ENTRIES]; 107 } QEMU_PACKED __attribute((__aligned__(4))); 108 109 static struct e820_table e820_reserve; 110 static struct e820_entry *e820_table; 111 static unsigned e820_entries; 112 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 113 114 void gsi_handler(void *opaque, int n, int level) 115 { 116 GSIState *s = opaque; 117 118 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 119 if (n < ISA_NUM_IRQS) { 120 qemu_set_irq(s->i8259_irq[n], level); 121 } 122 qemu_set_irq(s->ioapic_irq[n], level); 123 } 124 125 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 126 unsigned size) 127 { 128 } 129 130 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 131 { 132 return 0xffffffffffffffffULL; 133 } 134 135 /* MSDOS compatibility mode FPU exception support */ 136 static qemu_irq ferr_irq; 137 138 void pc_register_ferr_irq(qemu_irq irq) 139 { 140 ferr_irq = irq; 141 } 142 143 /* XXX: add IGNNE support */ 144 void cpu_set_ferr(CPUX86State *s) 145 { 146 qemu_irq_raise(ferr_irq); 147 } 148 149 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 150 unsigned size) 151 { 152 qemu_irq_lower(ferr_irq); 153 } 154 155 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 156 { 157 return 0xffffffffffffffffULL; 158 } 159 160 /* TSC handling */ 161 uint64_t cpu_get_tsc(CPUX86State *env) 162 { 163 return cpu_get_ticks(); 164 } 165 166 /* SMM support */ 167 168 static cpu_set_smm_t smm_set; 169 static void *smm_arg; 170 171 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 172 { 173 assert(smm_set == NULL); 174 assert(smm_arg == NULL); 175 smm_set = callback; 176 smm_arg = arg; 177 } 178 179 void cpu_smm_update(CPUX86State *env) 180 { 181 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 182 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 183 } 184 } 185 186 187 /* IRQ handling */ 188 int cpu_get_pic_interrupt(CPUX86State *env) 189 { 190 X86CPU *cpu = x86_env_get_cpu(env); 191 int intno; 192 193 intno = apic_get_interrupt(cpu->apic_state); 194 if (intno >= 0) { 195 return intno; 196 } 197 /* read the irq from the PIC */ 198 if (!apic_accept_pic_intr(cpu->apic_state)) { 199 return -1; 200 } 201 202 intno = pic_read_irq(isa_pic); 203 return intno; 204 } 205 206 static void pic_irq_request(void *opaque, int irq, int level) 207 { 208 CPUState *cs = first_cpu; 209 X86CPU *cpu = X86_CPU(cs); 210 211 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 212 if (cpu->apic_state) { 213 CPU_FOREACH(cs) { 214 cpu = X86_CPU(cs); 215 if (apic_accept_pic_intr(cpu->apic_state)) { 216 apic_deliver_pic_intr(cpu->apic_state, level); 217 } 218 } 219 } else { 220 if (level) { 221 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 222 } else { 223 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 224 } 225 } 226 } 227 228 /* PC cmos mappings */ 229 230 #define REG_EQUIPMENT_BYTE 0x14 231 232 static int cmos_get_fd_drive_type(FDriveType fd0) 233 { 234 int val; 235 236 switch (fd0) { 237 case FDRIVE_DRV_144: 238 /* 1.44 Mb 3"5 drive */ 239 val = 4; 240 break; 241 case FDRIVE_DRV_288: 242 /* 2.88 Mb 3"5 drive */ 243 val = 5; 244 break; 245 case FDRIVE_DRV_120: 246 /* 1.2 Mb 5"5 drive */ 247 val = 2; 248 break; 249 case FDRIVE_DRV_NONE: 250 default: 251 val = 0; 252 break; 253 } 254 return val; 255 } 256 257 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 258 int16_t cylinders, int8_t heads, int8_t sectors) 259 { 260 rtc_set_memory(s, type_ofs, 47); 261 rtc_set_memory(s, info_ofs, cylinders); 262 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 263 rtc_set_memory(s, info_ofs + 2, heads); 264 rtc_set_memory(s, info_ofs + 3, 0xff); 265 rtc_set_memory(s, info_ofs + 4, 0xff); 266 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 267 rtc_set_memory(s, info_ofs + 6, cylinders); 268 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 269 rtc_set_memory(s, info_ofs + 8, sectors); 270 } 271 272 /* convert boot_device letter to something recognizable by the bios */ 273 static int boot_device2nibble(char boot_device) 274 { 275 switch(boot_device) { 276 case 'a': 277 case 'b': 278 return 0x01; /* floppy boot */ 279 case 'c': 280 return 0x02; /* hard drive boot */ 281 case 'd': 282 return 0x03; /* CD-ROM boot */ 283 case 'n': 284 return 0x04; /* Network boot */ 285 } 286 return 0; 287 } 288 289 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 290 { 291 #define PC_MAX_BOOT_DEVICES 3 292 int nbds, bds[3] = { 0, }; 293 int i; 294 295 nbds = strlen(boot_device); 296 if (nbds > PC_MAX_BOOT_DEVICES) { 297 error_setg(errp, "Too many boot devices for PC"); 298 return; 299 } 300 for (i = 0; i < nbds; i++) { 301 bds[i] = boot_device2nibble(boot_device[i]); 302 if (bds[i] == 0) { 303 error_setg(errp, "Invalid boot device for PC: '%c'", 304 boot_device[i]); 305 return; 306 } 307 } 308 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 309 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 310 } 311 312 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 313 { 314 set_boot_dev(opaque, boot_device, errp); 315 } 316 317 typedef struct pc_cmos_init_late_arg { 318 ISADevice *rtc_state; 319 BusState *idebus[2]; 320 } pc_cmos_init_late_arg; 321 322 static void pc_cmos_init_late(void *opaque) 323 { 324 pc_cmos_init_late_arg *arg = opaque; 325 ISADevice *s = arg->rtc_state; 326 int16_t cylinders; 327 int8_t heads, sectors; 328 int val; 329 int i, trans; 330 331 val = 0; 332 if (ide_get_geometry(arg->idebus[0], 0, 333 &cylinders, &heads, §ors) >= 0) { 334 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 335 val |= 0xf0; 336 } 337 if (ide_get_geometry(arg->idebus[0], 1, 338 &cylinders, &heads, §ors) >= 0) { 339 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 340 val |= 0x0f; 341 } 342 rtc_set_memory(s, 0x12, val); 343 344 val = 0; 345 for (i = 0; i < 4; i++) { 346 /* NOTE: ide_get_geometry() returns the physical 347 geometry. It is always such that: 1 <= sects <= 63, 1 348 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 349 geometry can be different if a translation is done. */ 350 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 351 &cylinders, &heads, §ors) >= 0) { 352 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 353 assert((trans & ~3) == 0); 354 val |= trans << (i * 2); 355 } 356 } 357 rtc_set_memory(s, 0x39, val); 358 359 qemu_unregister_reset(pc_cmos_init_late, opaque); 360 } 361 362 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 363 const char *boot_device, MachineState *machine, 364 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 365 ISADevice *s) 366 { 367 int val, nb, i; 368 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 369 static pc_cmos_init_late_arg arg; 370 PCMachineState *pc_machine = PC_MACHINE(machine); 371 Error *local_err = NULL; 372 373 /* various important CMOS locations needed by PC/Bochs bios */ 374 375 /* memory size */ 376 /* base memory (first MiB) */ 377 val = MIN(ram_size / 1024, 640); 378 rtc_set_memory(s, 0x15, val); 379 rtc_set_memory(s, 0x16, val >> 8); 380 /* extended memory (next 64MiB) */ 381 if (ram_size > 1024 * 1024) { 382 val = (ram_size - 1024 * 1024) / 1024; 383 } else { 384 val = 0; 385 } 386 if (val > 65535) 387 val = 65535; 388 rtc_set_memory(s, 0x17, val); 389 rtc_set_memory(s, 0x18, val >> 8); 390 rtc_set_memory(s, 0x30, val); 391 rtc_set_memory(s, 0x31, val >> 8); 392 /* memory between 16MiB and 4GiB */ 393 if (ram_size > 16 * 1024 * 1024) { 394 val = (ram_size - 16 * 1024 * 1024) / 65536; 395 } else { 396 val = 0; 397 } 398 if (val > 65535) 399 val = 65535; 400 rtc_set_memory(s, 0x34, val); 401 rtc_set_memory(s, 0x35, val >> 8); 402 /* memory above 4GiB */ 403 val = above_4g_mem_size / 65536; 404 rtc_set_memory(s, 0x5b, val); 405 rtc_set_memory(s, 0x5c, val >> 8); 406 rtc_set_memory(s, 0x5d, val >> 16); 407 408 /* set the number of CPU */ 409 rtc_set_memory(s, 0x5f, smp_cpus - 1); 410 411 object_property_add_link(OBJECT(machine), "rtc_state", 412 TYPE_ISA_DEVICE, 413 (Object **)&pc_machine->rtc, 414 object_property_allow_set_link, 415 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 416 object_property_set_link(OBJECT(machine), OBJECT(s), 417 "rtc_state", &error_abort); 418 419 set_boot_dev(s, boot_device, &local_err); 420 if (local_err) { 421 error_report_err(local_err); 422 exit(1); 423 } 424 425 /* floppy type */ 426 if (floppy) { 427 for (i = 0; i < 2; i++) { 428 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 429 } 430 } 431 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 432 cmos_get_fd_drive_type(fd_type[1]); 433 rtc_set_memory(s, 0x10, val); 434 435 val = 0; 436 nb = 0; 437 if (fd_type[0] < FDRIVE_DRV_NONE) { 438 nb++; 439 } 440 if (fd_type[1] < FDRIVE_DRV_NONE) { 441 nb++; 442 } 443 switch (nb) { 444 case 0: 445 break; 446 case 1: 447 val |= 0x01; /* 1 drive, ready for boot */ 448 break; 449 case 2: 450 val |= 0x41; /* 2 drives, ready for boot */ 451 break; 452 } 453 val |= 0x02; /* FPU is there */ 454 val |= 0x04; /* PS/2 mouse installed */ 455 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 456 457 /* hard drives */ 458 arg.rtc_state = s; 459 arg.idebus[0] = idebus0; 460 arg.idebus[1] = idebus1; 461 qemu_register_reset(pc_cmos_init_late, &arg); 462 } 463 464 #define TYPE_PORT92 "port92" 465 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 466 467 /* port 92 stuff: could be split off */ 468 typedef struct Port92State { 469 ISADevice parent_obj; 470 471 MemoryRegion io; 472 uint8_t outport; 473 qemu_irq *a20_out; 474 } Port92State; 475 476 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 477 unsigned size) 478 { 479 Port92State *s = opaque; 480 int oldval = s->outport; 481 482 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 483 s->outport = val; 484 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 485 if ((val & 1) && !(oldval & 1)) { 486 qemu_system_reset_request(); 487 } 488 } 489 490 static uint64_t port92_read(void *opaque, hwaddr addr, 491 unsigned size) 492 { 493 Port92State *s = opaque; 494 uint32_t ret; 495 496 ret = s->outport; 497 DPRINTF("port92: read 0x%02x\n", ret); 498 return ret; 499 } 500 501 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 502 { 503 Port92State *s = PORT92(dev); 504 505 s->a20_out = a20_out; 506 } 507 508 static const VMStateDescription vmstate_port92_isa = { 509 .name = "port92", 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .fields = (VMStateField[]) { 513 VMSTATE_UINT8(outport, Port92State), 514 VMSTATE_END_OF_LIST() 515 } 516 }; 517 518 static void port92_reset(DeviceState *d) 519 { 520 Port92State *s = PORT92(d); 521 522 s->outport &= ~1; 523 } 524 525 static const MemoryRegionOps port92_ops = { 526 .read = port92_read, 527 .write = port92_write, 528 .impl = { 529 .min_access_size = 1, 530 .max_access_size = 1, 531 }, 532 .endianness = DEVICE_LITTLE_ENDIAN, 533 }; 534 535 static void port92_initfn(Object *obj) 536 { 537 Port92State *s = PORT92(obj); 538 539 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 540 541 s->outport = 0; 542 } 543 544 static void port92_realizefn(DeviceState *dev, Error **errp) 545 { 546 ISADevice *isadev = ISA_DEVICE(dev); 547 Port92State *s = PORT92(dev); 548 549 isa_register_ioport(isadev, &s->io, 0x92); 550 } 551 552 static void port92_class_initfn(ObjectClass *klass, void *data) 553 { 554 DeviceClass *dc = DEVICE_CLASS(klass); 555 556 dc->realize = port92_realizefn; 557 dc->reset = port92_reset; 558 dc->vmsd = &vmstate_port92_isa; 559 /* 560 * Reason: unlike ordinary ISA devices, this one needs additional 561 * wiring: its A20 output line needs to be wired up by 562 * port92_init(). 563 */ 564 dc->cannot_instantiate_with_device_add_yet = true; 565 } 566 567 static const TypeInfo port92_info = { 568 .name = TYPE_PORT92, 569 .parent = TYPE_ISA_DEVICE, 570 .instance_size = sizeof(Port92State), 571 .instance_init = port92_initfn, 572 .class_init = port92_class_initfn, 573 }; 574 575 static void port92_register_types(void) 576 { 577 type_register_static(&port92_info); 578 } 579 580 type_init(port92_register_types) 581 582 static void handle_a20_line_change(void *opaque, int irq, int level) 583 { 584 X86CPU *cpu = opaque; 585 586 /* XXX: send to all CPUs ? */ 587 /* XXX: add logic to handle multiple A20 line sources */ 588 x86_cpu_set_a20(cpu, level); 589 } 590 591 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 592 { 593 int index = le32_to_cpu(e820_reserve.count); 594 struct e820_entry *entry; 595 596 if (type != E820_RAM) { 597 /* old FW_CFG_E820_TABLE entry -- reservations only */ 598 if (index >= E820_NR_ENTRIES) { 599 return -EBUSY; 600 } 601 entry = &e820_reserve.entry[index++]; 602 603 entry->address = cpu_to_le64(address); 604 entry->length = cpu_to_le64(length); 605 entry->type = cpu_to_le32(type); 606 607 e820_reserve.count = cpu_to_le32(index); 608 } 609 610 /* new "etc/e820" file -- include ram too */ 611 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 612 e820_table[e820_entries].address = cpu_to_le64(address); 613 e820_table[e820_entries].length = cpu_to_le64(length); 614 e820_table[e820_entries].type = cpu_to_le32(type); 615 e820_entries++; 616 617 return e820_entries; 618 } 619 620 int e820_get_num_entries(void) 621 { 622 return e820_entries; 623 } 624 625 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 626 { 627 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 628 *address = le64_to_cpu(e820_table[idx].address); 629 *length = le64_to_cpu(e820_table[idx].length); 630 return true; 631 } 632 return false; 633 } 634 635 /* Enables contiguous-apic-ID mode, for compatibility */ 636 static bool compat_apic_id_mode; 637 638 void enable_compat_apic_id_mode(void) 639 { 640 compat_apic_id_mode = true; 641 } 642 643 /* Calculates initial APIC ID for a specific CPU index 644 * 645 * Currently we need to be able to calculate the APIC ID from the CPU index 646 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 647 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 648 * all CPUs up to max_cpus. 649 */ 650 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 651 { 652 uint32_t correct_id; 653 static bool warned; 654 655 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 656 if (compat_apic_id_mode) { 657 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 658 error_report("APIC IDs set in compatibility mode, " 659 "CPU topology won't match the configuration"); 660 warned = true; 661 } 662 return cpu_index; 663 } else { 664 return correct_id; 665 } 666 } 667 668 /* Calculates the limit to CPU APIC ID values 669 * 670 * This function returns the limit for the APIC ID value, so that all 671 * CPU APIC IDs are < pc_apic_id_limit(). 672 * 673 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 674 */ 675 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 676 { 677 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 678 } 679 680 static FWCfgState *bochs_bios_init(void) 681 { 682 FWCfgState *fw_cfg; 683 uint8_t *smbios_tables, *smbios_anchor; 684 size_t smbios_tables_len, smbios_anchor_len; 685 uint64_t *numa_fw_cfg; 686 int i, j; 687 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 688 689 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 690 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 691 * 692 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 693 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 694 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 695 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 696 * may see". 697 * 698 * So, this means we must not use max_cpus, here, but the maximum possible 699 * APIC ID value, plus one. 700 * 701 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 702 * the APIC ID, not the "CPU index" 703 */ 704 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 705 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 706 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 707 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 708 acpi_tables, acpi_tables_len); 709 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 710 711 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 712 if (smbios_tables) { 713 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 714 smbios_tables, smbios_tables_len); 715 } 716 717 smbios_get_tables(&smbios_tables, &smbios_tables_len, 718 &smbios_anchor, &smbios_anchor_len); 719 if (smbios_anchor) { 720 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 721 smbios_tables, smbios_tables_len); 722 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 723 smbios_anchor, smbios_anchor_len); 724 } 725 726 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 727 &e820_reserve, sizeof(e820_reserve)); 728 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 729 sizeof(struct e820_entry) * e820_entries); 730 731 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 732 /* allocate memory for the NUMA channel: one (64bit) word for the number 733 * of nodes, one word for each VCPU->node and one word for each node to 734 * hold the amount of memory. 735 */ 736 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 737 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 738 for (i = 0; i < max_cpus; i++) { 739 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 740 assert(apic_id < apic_id_limit); 741 for (j = 0; j < nb_numa_nodes; j++) { 742 if (test_bit(i, numa_info[j].node_cpu)) { 743 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 744 break; 745 } 746 } 747 } 748 for (i = 0; i < nb_numa_nodes; i++) { 749 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 750 } 751 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 752 (1 + apic_id_limit + nb_numa_nodes) * 753 sizeof(*numa_fw_cfg)); 754 755 return fw_cfg; 756 } 757 758 static long get_file_size(FILE *f) 759 { 760 long where, size; 761 762 /* XXX: on Unix systems, using fstat() probably makes more sense */ 763 764 where = ftell(f); 765 fseek(f, 0, SEEK_END); 766 size = ftell(f); 767 fseek(f, where, SEEK_SET); 768 769 return size; 770 } 771 772 static void load_linux(FWCfgState *fw_cfg, 773 const char *kernel_filename, 774 const char *initrd_filename, 775 const char *kernel_cmdline, 776 hwaddr max_ram_size) 777 { 778 uint16_t protocol; 779 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 780 uint32_t initrd_max; 781 uint8_t header[8192], *setup, *kernel, *initrd_data; 782 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 783 FILE *f; 784 char *vmode; 785 786 /* Align to 16 bytes as a paranoia measure */ 787 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 788 789 /* load the kernel header */ 790 f = fopen(kernel_filename, "rb"); 791 if (!f || !(kernel_size = get_file_size(f)) || 792 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 793 MIN(ARRAY_SIZE(header), kernel_size)) { 794 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 795 kernel_filename, strerror(errno)); 796 exit(1); 797 } 798 799 /* kernel protocol version */ 800 #if 0 801 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 802 #endif 803 if (ldl_p(header+0x202) == 0x53726448) { 804 protocol = lduw_p(header+0x206); 805 } else { 806 /* This looks like a multiboot kernel. If it is, let's stop 807 treating it like a Linux kernel. */ 808 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 809 kernel_cmdline, kernel_size, header)) { 810 return; 811 } 812 protocol = 0; 813 } 814 815 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 816 /* Low kernel */ 817 real_addr = 0x90000; 818 cmdline_addr = 0x9a000 - cmdline_size; 819 prot_addr = 0x10000; 820 } else if (protocol < 0x202) { 821 /* High but ancient kernel */ 822 real_addr = 0x90000; 823 cmdline_addr = 0x9a000 - cmdline_size; 824 prot_addr = 0x100000; 825 } else { 826 /* High and recent kernel */ 827 real_addr = 0x10000; 828 cmdline_addr = 0x20000; 829 prot_addr = 0x100000; 830 } 831 832 #if 0 833 fprintf(stderr, 834 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 835 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 836 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 837 real_addr, 838 cmdline_addr, 839 prot_addr); 840 #endif 841 842 /* highest address for loading the initrd */ 843 if (protocol >= 0x203) { 844 initrd_max = ldl_p(header+0x22c); 845 } else { 846 initrd_max = 0x37ffffff; 847 } 848 849 if (initrd_max >= max_ram_size - acpi_data_size) { 850 initrd_max = max_ram_size - acpi_data_size - 1; 851 } 852 853 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 854 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 855 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 856 857 if (protocol >= 0x202) { 858 stl_p(header+0x228, cmdline_addr); 859 } else { 860 stw_p(header+0x20, 0xA33F); 861 stw_p(header+0x22, cmdline_addr-real_addr); 862 } 863 864 /* handle vga= parameter */ 865 vmode = strstr(kernel_cmdline, "vga="); 866 if (vmode) { 867 unsigned int video_mode; 868 /* skip "vga=" */ 869 vmode += 4; 870 if (!strncmp(vmode, "normal", 6)) { 871 video_mode = 0xffff; 872 } else if (!strncmp(vmode, "ext", 3)) { 873 video_mode = 0xfffe; 874 } else if (!strncmp(vmode, "ask", 3)) { 875 video_mode = 0xfffd; 876 } else { 877 video_mode = strtol(vmode, NULL, 0); 878 } 879 stw_p(header+0x1fa, video_mode); 880 } 881 882 /* loader type */ 883 /* High nybble = B reserved for QEMU; low nybble is revision number. 884 If this code is substantially changed, you may want to consider 885 incrementing the revision. */ 886 if (protocol >= 0x200) { 887 header[0x210] = 0xB0; 888 } 889 /* heap */ 890 if (protocol >= 0x201) { 891 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 892 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 893 } 894 895 /* load initrd */ 896 if (initrd_filename) { 897 if (protocol < 0x200) { 898 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 899 exit(1); 900 } 901 902 initrd_size = get_image_size(initrd_filename); 903 if (initrd_size < 0) { 904 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 905 initrd_filename, strerror(errno)); 906 exit(1); 907 } 908 909 initrd_addr = (initrd_max-initrd_size) & ~4095; 910 911 initrd_data = g_malloc(initrd_size); 912 load_image(initrd_filename, initrd_data); 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 916 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 917 918 stl_p(header+0x218, initrd_addr); 919 stl_p(header+0x21c, initrd_size); 920 } 921 922 /* load kernel and setup */ 923 setup_size = header[0x1f1]; 924 if (setup_size == 0) { 925 setup_size = 4; 926 } 927 setup_size = (setup_size+1)*512; 928 kernel_size -= setup_size; 929 930 setup = g_malloc(setup_size); 931 kernel = g_malloc(kernel_size); 932 fseek(f, 0, SEEK_SET); 933 if (fread(setup, 1, setup_size, f) != setup_size) { 934 fprintf(stderr, "fread() failed\n"); 935 exit(1); 936 } 937 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 938 fprintf(stderr, "fread() failed\n"); 939 exit(1); 940 } 941 fclose(f); 942 memcpy(setup, header, MIN(sizeof(header), setup_size)); 943 944 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 945 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 946 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 947 948 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 949 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 950 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 951 952 option_rom[nb_option_roms].name = "linuxboot.bin"; 953 option_rom[nb_option_roms].bootindex = 0; 954 nb_option_roms++; 955 } 956 957 #define NE2000_NB_MAX 6 958 959 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 960 0x280, 0x380 }; 961 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 962 963 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 964 { 965 static int nb_ne2k = 0; 966 967 if (nb_ne2k == NE2000_NB_MAX) 968 return; 969 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 970 ne2000_irq[nb_ne2k], nd); 971 nb_ne2k++; 972 } 973 974 DeviceState *cpu_get_current_apic(void) 975 { 976 if (current_cpu) { 977 X86CPU *cpu = X86_CPU(current_cpu); 978 return cpu->apic_state; 979 } else { 980 return NULL; 981 } 982 } 983 984 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 985 { 986 X86CPU *cpu = opaque; 987 988 if (level) { 989 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 990 } 991 } 992 993 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 994 DeviceState *icc_bridge, Error **errp) 995 { 996 X86CPU *cpu = NULL; 997 Error *local_err = NULL; 998 999 if (icc_bridge == NULL) { 1000 error_setg(&local_err, "Invalid icc-bridge value"); 1001 goto out; 1002 } 1003 1004 cpu = cpu_x86_create(cpu_model, &local_err); 1005 if (local_err != NULL) { 1006 goto out; 1007 } 1008 1009 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); 1010 object_unref(OBJECT(cpu)); 1011 1012 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1013 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1014 1015 out: 1016 if (local_err) { 1017 error_propagate(errp, local_err); 1018 object_unref(OBJECT(cpu)); 1019 cpu = NULL; 1020 } 1021 return cpu; 1022 } 1023 1024 static const char *current_cpu_model; 1025 1026 void pc_hot_add_cpu(const int64_t id, Error **errp) 1027 { 1028 DeviceState *icc_bridge; 1029 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1030 1031 if (id < 0) { 1032 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1033 return; 1034 } 1035 1036 if (cpu_exists(apic_id)) { 1037 error_setg(errp, "Unable to add CPU: %" PRIi64 1038 ", it already exists", id); 1039 return; 1040 } 1041 1042 if (id >= max_cpus) { 1043 error_setg(errp, "Unable to add CPU: %" PRIi64 1044 ", max allowed: %d", id, max_cpus - 1); 1045 return; 1046 } 1047 1048 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1049 error_setg(errp, "Unable to add CPU: %" PRIi64 1050 ", resulting APIC ID (%" PRIi64 ") is too large", 1051 id, apic_id); 1052 return; 1053 } 1054 1055 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1056 TYPE_ICC_BRIDGE, NULL)); 1057 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1058 } 1059 1060 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1061 { 1062 int i; 1063 X86CPU *cpu = NULL; 1064 Error *error = NULL; 1065 unsigned long apic_id_limit; 1066 1067 /* init CPUs */ 1068 if (cpu_model == NULL) { 1069 #ifdef TARGET_X86_64 1070 cpu_model = "qemu64"; 1071 #else 1072 cpu_model = "qemu32"; 1073 #endif 1074 } 1075 current_cpu_model = cpu_model; 1076 1077 apic_id_limit = pc_apic_id_limit(max_cpus); 1078 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1079 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1080 apic_id_limit - 1); 1081 exit(1); 1082 } 1083 1084 for (i = 0; i < smp_cpus; i++) { 1085 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1086 icc_bridge, &error); 1087 if (error) { 1088 error_report_err(error); 1089 exit(1); 1090 } 1091 } 1092 1093 /* map APIC MMIO area if CPU has APIC */ 1094 if (cpu && cpu->apic_state) { 1095 /* XXX: what if the base changes? */ 1096 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1097 APIC_DEFAULT_ADDRESS, 0x1000); 1098 } 1099 1100 /* tell smbios about cpuid version and features */ 1101 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1102 } 1103 1104 /* pci-info ROM file. Little endian format */ 1105 typedef struct PcRomPciInfo { 1106 uint64_t w32_min; 1107 uint64_t w32_max; 1108 uint64_t w64_min; 1109 uint64_t w64_max; 1110 } PcRomPciInfo; 1111 1112 typedef struct PcGuestInfoState { 1113 PcGuestInfo info; 1114 Notifier machine_done; 1115 } PcGuestInfoState; 1116 1117 static 1118 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1119 { 1120 PcGuestInfoState *guest_info_state = container_of(notifier, 1121 PcGuestInfoState, 1122 machine_done); 1123 acpi_setup(&guest_info_state->info); 1124 } 1125 1126 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1127 ram_addr_t above_4g_mem_size) 1128 { 1129 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1130 PcGuestInfo *guest_info = &guest_info_state->info; 1131 int i, j; 1132 1133 guest_info->ram_size_below_4g = below_4g_mem_size; 1134 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1135 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1136 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1137 guest_info->numa_nodes = nb_numa_nodes; 1138 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1139 sizeof *guest_info->node_mem); 1140 for (i = 0; i < nb_numa_nodes; i++) { 1141 guest_info->node_mem[i] = numa_info[i].node_mem; 1142 } 1143 1144 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1145 sizeof *guest_info->node_cpu); 1146 1147 for (i = 0; i < max_cpus; i++) { 1148 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1149 assert(apic_id < guest_info->apic_id_limit); 1150 for (j = 0; j < nb_numa_nodes; j++) { 1151 if (test_bit(i, numa_info[j].node_cpu)) { 1152 guest_info->node_cpu[apic_id] = j; 1153 break; 1154 } 1155 } 1156 } 1157 1158 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1159 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1160 return guest_info; 1161 } 1162 1163 /* setup pci memory address space mapping into system address space */ 1164 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1165 MemoryRegion *pci_address_space) 1166 { 1167 /* Set to lower priority than RAM */ 1168 memory_region_add_subregion_overlap(system_memory, 0x0, 1169 pci_address_space, -1); 1170 } 1171 1172 void pc_acpi_init(const char *default_dsdt) 1173 { 1174 char *filename; 1175 1176 if (acpi_tables != NULL) { 1177 /* manually set via -acpitable, leave it alone */ 1178 return; 1179 } 1180 1181 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1182 if (filename == NULL) { 1183 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1184 } else { 1185 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1186 &error_abort); 1187 Error *err = NULL; 1188 1189 qemu_opt_set(opts, "file", filename, &error_abort); 1190 1191 acpi_table_add_builtin(opts, &err); 1192 if (err) { 1193 error_report("WARNING: failed to load %s: %s", filename, 1194 error_get_pretty(err)); 1195 error_free(err); 1196 } 1197 g_free(filename); 1198 } 1199 } 1200 1201 FWCfgState *xen_load_linux(const char *kernel_filename, 1202 const char *kernel_cmdline, 1203 const char *initrd_filename, 1204 ram_addr_t below_4g_mem_size, 1205 PcGuestInfo *guest_info) 1206 { 1207 int i; 1208 FWCfgState *fw_cfg; 1209 1210 assert(kernel_filename != NULL); 1211 1212 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1213 rom_set_fw(fw_cfg); 1214 1215 load_linux(fw_cfg, kernel_filename, initrd_filename, 1216 kernel_cmdline, below_4g_mem_size); 1217 for (i = 0; i < nb_option_roms; i++) { 1218 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1219 !strcmp(option_rom[i].name, "multiboot.bin")); 1220 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1221 } 1222 guest_info->fw_cfg = fw_cfg; 1223 return fw_cfg; 1224 } 1225 1226 FWCfgState *pc_memory_init(MachineState *machine, 1227 MemoryRegion *system_memory, 1228 ram_addr_t below_4g_mem_size, 1229 ram_addr_t above_4g_mem_size, 1230 MemoryRegion *rom_memory, 1231 MemoryRegion **ram_memory, 1232 PcGuestInfo *guest_info) 1233 { 1234 int linux_boot, i; 1235 MemoryRegion *ram, *option_rom_mr; 1236 MemoryRegion *ram_below_4g, *ram_above_4g; 1237 FWCfgState *fw_cfg; 1238 PCMachineState *pcms = PC_MACHINE(machine); 1239 1240 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1241 1242 linux_boot = (machine->kernel_filename != NULL); 1243 1244 /* Allocate RAM. We allocate it as a single memory region and use 1245 * aliases to address portions of it, mostly for backwards compatibility 1246 * with older qemus that used qemu_ram_alloc(). 1247 */ 1248 ram = g_malloc(sizeof(*ram)); 1249 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1250 machine->ram_size); 1251 *ram_memory = ram; 1252 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1253 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1254 0, below_4g_mem_size); 1255 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1256 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1257 if (above_4g_mem_size > 0) { 1258 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1259 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1260 below_4g_mem_size, above_4g_mem_size); 1261 memory_region_add_subregion(system_memory, 0x100000000ULL, 1262 ram_above_4g); 1263 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1264 } 1265 1266 if (!guest_info->has_reserved_memory && 1267 (machine->ram_slots || 1268 (machine->maxram_size > machine->ram_size))) { 1269 MachineClass *mc = MACHINE_GET_CLASS(machine); 1270 1271 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1272 mc->name); 1273 exit(EXIT_FAILURE); 1274 } 1275 1276 /* initialize hotplug memory address space */ 1277 if (guest_info->has_reserved_memory && 1278 (machine->ram_size < machine->maxram_size)) { 1279 ram_addr_t hotplug_mem_size = 1280 machine->maxram_size - machine->ram_size; 1281 1282 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1283 error_report("unsupported amount of memory slots: %"PRIu64, 1284 machine->ram_slots); 1285 exit(EXIT_FAILURE); 1286 } 1287 1288 if (QEMU_ALIGN_UP(machine->maxram_size, 1289 TARGET_PAGE_SIZE) != machine->maxram_size) { 1290 error_report("maximum memory size must by aligned to multiple of " 1291 "%d bytes", TARGET_PAGE_SIZE); 1292 exit(EXIT_FAILURE); 1293 } 1294 1295 pcms->hotplug_memory_base = 1296 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1297 1298 if (pcms->enforce_aligned_dimm) { 1299 /* size hotplug region assuming 1G page max alignment per slot */ 1300 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1301 } 1302 1303 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1304 hotplug_mem_size) { 1305 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1306 machine->maxram_size); 1307 exit(EXIT_FAILURE); 1308 } 1309 1310 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1311 "hotplug-memory", hotplug_mem_size); 1312 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1313 &pcms->hotplug_memory); 1314 } 1315 1316 /* Initialize PC system firmware */ 1317 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1318 1319 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1320 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1321 &error_abort); 1322 vmstate_register_ram_global(option_rom_mr); 1323 memory_region_add_subregion_overlap(rom_memory, 1324 PC_ROM_MIN_VGA, 1325 option_rom_mr, 1326 1); 1327 1328 fw_cfg = bochs_bios_init(); 1329 rom_set_fw(fw_cfg); 1330 1331 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1332 uint64_t *val = g_malloc(sizeof(*val)); 1333 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1334 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1335 } 1336 1337 if (linux_boot) { 1338 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1339 machine->kernel_cmdline, below_4g_mem_size); 1340 } 1341 1342 for (i = 0; i < nb_option_roms; i++) { 1343 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1344 } 1345 guest_info->fw_cfg = fw_cfg; 1346 return fw_cfg; 1347 } 1348 1349 qemu_irq *pc_allocate_cpu_irq(void) 1350 { 1351 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1352 } 1353 1354 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1355 { 1356 DeviceState *dev = NULL; 1357 1358 if (pci_bus) { 1359 PCIDevice *pcidev = pci_vga_init(pci_bus); 1360 dev = pcidev ? &pcidev->qdev : NULL; 1361 } else if (isa_bus) { 1362 ISADevice *isadev = isa_vga_init(isa_bus); 1363 dev = isadev ? DEVICE(isadev) : NULL; 1364 } 1365 return dev; 1366 } 1367 1368 static void cpu_request_exit(void *opaque, int irq, int level) 1369 { 1370 CPUState *cpu = current_cpu; 1371 1372 if (cpu && level) { 1373 cpu_exit(cpu); 1374 } 1375 } 1376 1377 static const MemoryRegionOps ioport80_io_ops = { 1378 .write = ioport80_write, 1379 .read = ioport80_read, 1380 .endianness = DEVICE_NATIVE_ENDIAN, 1381 .impl = { 1382 .min_access_size = 1, 1383 .max_access_size = 1, 1384 }, 1385 }; 1386 1387 static const MemoryRegionOps ioportF0_io_ops = { 1388 .write = ioportF0_write, 1389 .read = ioportF0_read, 1390 .endianness = DEVICE_NATIVE_ENDIAN, 1391 .impl = { 1392 .min_access_size = 1, 1393 .max_access_size = 1, 1394 }, 1395 }; 1396 1397 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1398 ISADevice **rtc_state, 1399 ISADevice **floppy, 1400 bool no_vmport, 1401 uint32 hpet_irqs) 1402 { 1403 int i; 1404 DriveInfo *fd[MAX_FD]; 1405 DeviceState *hpet = NULL; 1406 int pit_isa_irq = 0; 1407 qemu_irq pit_alt_irq = NULL; 1408 qemu_irq rtc_irq = NULL; 1409 qemu_irq *a20_line; 1410 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1411 qemu_irq *cpu_exit_irq; 1412 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1413 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1414 1415 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1416 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1417 1418 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1419 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1420 1421 /* 1422 * Check if an HPET shall be created. 1423 * 1424 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1425 * when the HPET wants to take over. Thus we have to disable the latter. 1426 */ 1427 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1428 /* In order to set property, here not using sysbus_try_create_simple */ 1429 hpet = qdev_try_create(NULL, TYPE_HPET); 1430 if (hpet) { 1431 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1432 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1433 * IRQ8 and IRQ2. 1434 */ 1435 uint8_t compat = object_property_get_int(OBJECT(hpet), 1436 HPET_INTCAP, NULL); 1437 if (!compat) { 1438 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1439 } 1440 qdev_init_nofail(hpet); 1441 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1442 1443 for (i = 0; i < GSI_NUM_PINS; i++) { 1444 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1445 } 1446 pit_isa_irq = -1; 1447 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1448 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1449 } 1450 } 1451 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1452 1453 qemu_register_boot_set(pc_boot_set, *rtc_state); 1454 1455 if (!xen_enabled()) { 1456 if (kvm_irqchip_in_kernel()) { 1457 pit = kvm_pit_init(isa_bus, 0x40); 1458 } else { 1459 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1460 } 1461 if (hpet) { 1462 /* connect PIT to output control line of the HPET */ 1463 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1464 } 1465 pcspk_init(isa_bus, pit); 1466 } 1467 1468 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1469 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1470 1471 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1472 i8042 = isa_create_simple(isa_bus, "i8042"); 1473 i8042_setup_a20_line(i8042, &a20_line[0]); 1474 if (!no_vmport) { 1475 vmport_init(isa_bus); 1476 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1477 } else { 1478 vmmouse = NULL; 1479 } 1480 if (vmmouse) { 1481 DeviceState *dev = DEVICE(vmmouse); 1482 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1483 qdev_init_nofail(dev); 1484 } 1485 port92 = isa_create_simple(isa_bus, "port92"); 1486 port92_init(port92, &a20_line[1]); 1487 1488 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1489 DMA_init(0, cpu_exit_irq); 1490 1491 for(i = 0; i < MAX_FD; i++) { 1492 fd[i] = drive_get(IF_FLOPPY, 0, i); 1493 } 1494 *floppy = fdctrl_init_isa(isa_bus, fd); 1495 } 1496 1497 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1498 { 1499 int i; 1500 1501 for (i = 0; i < nb_nics; i++) { 1502 NICInfo *nd = &nd_table[i]; 1503 1504 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1505 pc_init_ne2k_isa(isa_bus, nd); 1506 } else { 1507 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1508 } 1509 } 1510 } 1511 1512 void pc_pci_device_init(PCIBus *pci_bus) 1513 { 1514 int max_bus; 1515 int bus; 1516 1517 max_bus = drive_get_max_bus(IF_SCSI); 1518 for (bus = 0; bus <= max_bus; bus++) { 1519 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1520 } 1521 } 1522 1523 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1524 { 1525 DeviceState *dev; 1526 SysBusDevice *d; 1527 unsigned int i; 1528 1529 if (kvm_irqchip_in_kernel()) { 1530 dev = qdev_create(NULL, "kvm-ioapic"); 1531 } else { 1532 dev = qdev_create(NULL, "ioapic"); 1533 } 1534 if (parent_name) { 1535 object_property_add_child(object_resolve_path(parent_name, NULL), 1536 "ioapic", OBJECT(dev), NULL); 1537 } 1538 qdev_init_nofail(dev); 1539 d = SYS_BUS_DEVICE(dev); 1540 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1541 1542 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1543 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1544 } 1545 } 1546 1547 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1548 { 1549 MachineClass *mc = MACHINE_CLASS(oc); 1550 QEMUMachine *qm = data; 1551 1552 mc->family = qm->family; 1553 mc->name = qm->name; 1554 mc->alias = qm->alias; 1555 mc->desc = qm->desc; 1556 mc->init = qm->init; 1557 mc->reset = qm->reset; 1558 mc->hot_add_cpu = qm->hot_add_cpu; 1559 mc->kvm_type = qm->kvm_type; 1560 mc->block_default_type = qm->block_default_type; 1561 mc->units_per_default_bus = qm->units_per_default_bus; 1562 mc->max_cpus = qm->max_cpus; 1563 mc->no_serial = qm->no_serial; 1564 mc->no_parallel = qm->no_parallel; 1565 mc->use_virtcon = qm->use_virtcon; 1566 mc->use_sclp = qm->use_sclp; 1567 mc->no_floppy = qm->no_floppy; 1568 mc->no_cdrom = qm->no_cdrom; 1569 mc->no_sdcard = qm->no_sdcard; 1570 mc->is_default = qm->is_default; 1571 mc->default_machine_opts = qm->default_machine_opts; 1572 mc->default_boot_order = qm->default_boot_order; 1573 mc->default_display = qm->default_display; 1574 mc->compat_props = qm->compat_props; 1575 mc->hw_version = qm->hw_version; 1576 } 1577 1578 void qemu_register_pc_machine(QEMUMachine *m) 1579 { 1580 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1581 TypeInfo ti = { 1582 .name = name, 1583 .parent = TYPE_PC_MACHINE, 1584 .class_init = pc_generic_machine_class_init, 1585 .class_data = (void *)m, 1586 }; 1587 1588 type_register(&ti); 1589 g_free(name); 1590 } 1591 1592 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1593 DeviceState *dev, Error **errp) 1594 { 1595 int slot; 1596 HotplugHandlerClass *hhc; 1597 Error *local_err = NULL; 1598 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1599 MachineState *machine = MACHINE(hotplug_dev); 1600 PCDIMMDevice *dimm = PC_DIMM(dev); 1601 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1602 MemoryRegion *mr = ddc->get_memory_region(dimm); 1603 uint64_t existing_dimms_capacity = 0; 1604 uint64_t align = TARGET_PAGE_SIZE; 1605 uint64_t addr; 1606 1607 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 1608 if (local_err) { 1609 goto out; 1610 } 1611 1612 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1613 align = memory_region_get_alignment(mr); 1614 } 1615 1616 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1617 memory_region_size(&pcms->hotplug_memory), 1618 !addr ? NULL : &addr, align, 1619 memory_region_size(mr), &local_err); 1620 if (local_err) { 1621 goto out; 1622 } 1623 1624 existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); 1625 if (local_err) { 1626 goto out; 1627 } 1628 1629 if (existing_dimms_capacity + memory_region_size(mr) > 1630 machine->maxram_size - machine->ram_size) { 1631 error_setg(&local_err, "not enough space, currently 0x%" PRIx64 1632 " in use of total hot pluggable 0x" RAM_ADDR_FMT, 1633 existing_dimms_capacity, 1634 machine->maxram_size - machine->ram_size); 1635 goto out; 1636 } 1637 1638 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1639 if (local_err) { 1640 goto out; 1641 } 1642 trace_mhp_pc_dimm_assigned_address(addr); 1643 1644 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1645 if (local_err) { 1646 goto out; 1647 } 1648 1649 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1650 machine->ram_slots, &local_err); 1651 if (local_err) { 1652 goto out; 1653 } 1654 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1655 if (local_err) { 1656 goto out; 1657 } 1658 trace_mhp_pc_dimm_assigned_slot(slot); 1659 1660 if (!pcms->acpi_dev) { 1661 error_setg(&local_err, 1662 "memory hotplug is not enabled: missing acpi device"); 1663 goto out; 1664 } 1665 1666 if (kvm_enabled() && !kvm_has_free_slot(machine)) { 1667 error_setg(&local_err, "hypervisor has no free memory slots left"); 1668 goto out; 1669 } 1670 1671 memory_region_add_subregion(&pcms->hotplug_memory, 1672 addr - pcms->hotplug_memory_base, mr); 1673 vmstate_register_ram(mr, dev); 1674 1675 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1676 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1677 out: 1678 error_propagate(errp, local_err); 1679 } 1680 1681 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1682 DeviceState *dev, Error **errp) 1683 { 1684 HotplugHandlerClass *hhc; 1685 Error *local_err = NULL; 1686 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1687 1688 if (!dev->hotplugged) { 1689 goto out; 1690 } 1691 1692 if (!pcms->acpi_dev) { 1693 error_setg(&local_err, 1694 "cpu hotplug is not enabled: missing acpi device"); 1695 goto out; 1696 } 1697 1698 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1699 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1700 if (local_err) { 1701 goto out; 1702 } 1703 1704 /* increment the number of CPUs */ 1705 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1706 out: 1707 error_propagate(errp, local_err); 1708 } 1709 1710 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1711 DeviceState *dev, Error **errp) 1712 { 1713 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1714 pc_dimm_plug(hotplug_dev, dev, errp); 1715 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1716 pc_cpu_plug(hotplug_dev, dev, errp); 1717 } 1718 } 1719 1720 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1721 DeviceState *dev, Error **errp) 1722 { 1723 error_setg(errp, "acpi: device unplug request for not supported device" 1724 " type: %s", object_get_typename(OBJECT(dev))); 1725 } 1726 1727 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1728 DeviceState *dev, Error **errp) 1729 { 1730 error_setg(errp, "acpi: device unplug for not supported device" 1731 " type: %s", object_get_typename(OBJECT(dev))); 1732 } 1733 1734 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1735 DeviceState *dev) 1736 { 1737 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1738 1739 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1740 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1741 return HOTPLUG_HANDLER(machine); 1742 } 1743 1744 return pcmc->get_hotplug_handler ? 1745 pcmc->get_hotplug_handler(machine, dev) : NULL; 1746 } 1747 1748 static void 1749 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1750 const char *name, Error **errp) 1751 { 1752 PCMachineState *pcms = PC_MACHINE(obj); 1753 int64_t value = memory_region_size(&pcms->hotplug_memory); 1754 1755 visit_type_int(v, &value, name, errp); 1756 } 1757 1758 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1759 void *opaque, const char *name, 1760 Error **errp) 1761 { 1762 PCMachineState *pcms = PC_MACHINE(obj); 1763 uint64_t value = pcms->max_ram_below_4g; 1764 1765 visit_type_size(v, &value, name, errp); 1766 } 1767 1768 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1769 void *opaque, const char *name, 1770 Error **errp) 1771 { 1772 PCMachineState *pcms = PC_MACHINE(obj); 1773 Error *error = NULL; 1774 uint64_t value; 1775 1776 visit_type_size(v, &value, name, &error); 1777 if (error) { 1778 error_propagate(errp, error); 1779 return; 1780 } 1781 if (value > (1ULL << 32)) { 1782 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1783 "Machine option 'max-ram-below-4g=%"PRIu64 1784 "' expects size less than or equal to 4G", value); 1785 error_propagate(errp, error); 1786 return; 1787 } 1788 1789 if (value < (1ULL << 20)) { 1790 error_report("Warning: small max_ram_below_4g(%"PRIu64 1791 ") less than 1M. BIOS may not work..", 1792 value); 1793 } 1794 1795 pcms->max_ram_below_4g = value; 1796 } 1797 1798 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1799 const char *name, Error **errp) 1800 { 1801 PCMachineState *pcms = PC_MACHINE(obj); 1802 OnOffAuto vmport = pcms->vmport; 1803 1804 visit_type_OnOffAuto(v, &vmport, name, errp); 1805 } 1806 1807 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1808 const char *name, Error **errp) 1809 { 1810 PCMachineState *pcms = PC_MACHINE(obj); 1811 1812 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1813 } 1814 1815 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1816 { 1817 PCMachineState *pcms = PC_MACHINE(obj); 1818 1819 return pcms->enforce_aligned_dimm; 1820 } 1821 1822 static void pc_machine_initfn(Object *obj) 1823 { 1824 PCMachineState *pcms = PC_MACHINE(obj); 1825 1826 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1827 pc_machine_get_hotplug_memory_region_size, 1828 NULL, NULL, NULL, NULL); 1829 1830 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1831 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1832 pc_machine_get_max_ram_below_4g, 1833 pc_machine_set_max_ram_below_4g, 1834 NULL, NULL, NULL); 1835 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1836 "Maximum ram below the 4G boundary (32bit boundary)", 1837 NULL); 1838 1839 pcms->vmport = ON_OFF_AUTO_AUTO; 1840 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1841 pc_machine_get_vmport, 1842 pc_machine_set_vmport, 1843 NULL, NULL, NULL); 1844 object_property_set_description(obj, PC_MACHINE_VMPORT, 1845 "Enable vmport (pc & q35)", 1846 NULL); 1847 1848 pcms->enforce_aligned_dimm = true; 1849 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1850 pc_machine_get_aligned_dimm, 1851 NULL, NULL); 1852 } 1853 1854 static void pc_machine_class_init(ObjectClass *oc, void *data) 1855 { 1856 MachineClass *mc = MACHINE_CLASS(oc); 1857 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1858 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1859 1860 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1861 mc->get_hotplug_handler = pc_get_hotpug_handler; 1862 hc->plug = pc_machine_device_plug_cb; 1863 hc->unplug_request = pc_machine_device_unplug_request_cb; 1864 hc->unplug = pc_machine_device_unplug_cb; 1865 } 1866 1867 static const TypeInfo pc_machine_info = { 1868 .name = TYPE_PC_MACHINE, 1869 .parent = TYPE_MACHINE, 1870 .abstract = true, 1871 .instance_size = sizeof(PCMachineState), 1872 .instance_init = pc_machine_initfn, 1873 .class_size = sizeof(PCMachineClass), 1874 .class_init = pc_machine_class_init, 1875 .interfaces = (InterfaceInfo[]) { 1876 { TYPE_HOTPLUG_HANDLER }, 1877 { } 1878 }, 1879 }; 1880 1881 static void pc_machine_register_types(void) 1882 { 1883 type_register_static(&pc_machine_info); 1884 } 1885 1886 type_init(pc_machine_register_types) 1887