1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/smbios/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/boards.h" 63 #include "hw/pci/pci_host.h" 64 #include "acpi-build.h" 65 #include "hw/mem/pc-dimm.h" 66 #include "qapi/visitor.h" 67 #include "qapi-visit.h" 68 69 /* debug PC/ISA interrupts */ 70 //#define DEBUG_IRQ 71 72 #ifdef DEBUG_IRQ 73 #define DPRINTF(fmt, ...) \ 74 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 75 #else 76 #define DPRINTF(fmt, ...) 77 #endif 78 79 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 80 * (128K) and other BIOS datastructures (less than 4K reported to be used at 81 * the moment, 32K should be enough for a while). */ 82 static unsigned acpi_data_size = 0x20000 + 0x8000; 83 void pc_set_legacy_acpi_data_size(void) 84 { 85 acpi_data_size = 0x10000; 86 } 87 88 #define BIOS_CFG_IOPORT 0x510 89 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 90 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 91 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 92 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 93 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 94 95 #define E820_NR_ENTRIES 16 96 97 struct e820_entry { 98 uint64_t address; 99 uint64_t length; 100 uint32_t type; 101 } QEMU_PACKED __attribute((__aligned__(4))); 102 103 struct e820_table { 104 uint32_t count; 105 struct e820_entry entry[E820_NR_ENTRIES]; 106 } QEMU_PACKED __attribute((__aligned__(4))); 107 108 static struct e820_table e820_reserve; 109 static struct e820_entry *e820_table; 110 static unsigned e820_entries; 111 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 112 113 void gsi_handler(void *opaque, int n, int level) 114 { 115 GSIState *s = opaque; 116 117 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 118 if (n < ISA_NUM_IRQS) { 119 qemu_set_irq(s->i8259_irq[n], level); 120 } 121 qemu_set_irq(s->ioapic_irq[n], level); 122 } 123 124 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 125 unsigned size) 126 { 127 } 128 129 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 130 { 131 return 0xffffffffffffffffULL; 132 } 133 134 /* MSDOS compatibility mode FPU exception support */ 135 static qemu_irq ferr_irq; 136 137 void pc_register_ferr_irq(qemu_irq irq) 138 { 139 ferr_irq = irq; 140 } 141 142 /* XXX: add IGNNE support */ 143 void cpu_set_ferr(CPUX86State *s) 144 { 145 qemu_irq_raise(ferr_irq); 146 } 147 148 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 149 unsigned size) 150 { 151 qemu_irq_lower(ferr_irq); 152 } 153 154 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 155 { 156 return 0xffffffffffffffffULL; 157 } 158 159 /* TSC handling */ 160 uint64_t cpu_get_tsc(CPUX86State *env) 161 { 162 return cpu_get_ticks(); 163 } 164 165 /* IRQ handling */ 166 int cpu_get_pic_interrupt(CPUX86State *env) 167 { 168 X86CPU *cpu = x86_env_get_cpu(env); 169 int intno; 170 171 intno = apic_get_interrupt(cpu->apic_state); 172 if (intno >= 0) { 173 return intno; 174 } 175 /* read the irq from the PIC */ 176 if (!apic_accept_pic_intr(cpu->apic_state)) { 177 return -1; 178 } 179 180 intno = pic_read_irq(isa_pic); 181 return intno; 182 } 183 184 static void pic_irq_request(void *opaque, int irq, int level) 185 { 186 CPUState *cs = first_cpu; 187 X86CPU *cpu = X86_CPU(cs); 188 189 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 190 if (cpu->apic_state) { 191 CPU_FOREACH(cs) { 192 cpu = X86_CPU(cs); 193 if (apic_accept_pic_intr(cpu->apic_state)) { 194 apic_deliver_pic_intr(cpu->apic_state, level); 195 } 196 } 197 } else { 198 if (level) { 199 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 200 } else { 201 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 202 } 203 } 204 } 205 206 /* PC cmos mappings */ 207 208 #define REG_EQUIPMENT_BYTE 0x14 209 210 static int cmos_get_fd_drive_type(FDriveType fd0) 211 { 212 int val; 213 214 switch (fd0) { 215 case FDRIVE_DRV_144: 216 /* 1.44 Mb 3"5 drive */ 217 val = 4; 218 break; 219 case FDRIVE_DRV_288: 220 /* 2.88 Mb 3"5 drive */ 221 val = 5; 222 break; 223 case FDRIVE_DRV_120: 224 /* 1.2 Mb 5"5 drive */ 225 val = 2; 226 break; 227 case FDRIVE_DRV_NONE: 228 default: 229 val = 0; 230 break; 231 } 232 return val; 233 } 234 235 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 236 int16_t cylinders, int8_t heads, int8_t sectors) 237 { 238 rtc_set_memory(s, type_ofs, 47); 239 rtc_set_memory(s, info_ofs, cylinders); 240 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 241 rtc_set_memory(s, info_ofs + 2, heads); 242 rtc_set_memory(s, info_ofs + 3, 0xff); 243 rtc_set_memory(s, info_ofs + 4, 0xff); 244 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 245 rtc_set_memory(s, info_ofs + 6, cylinders); 246 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 247 rtc_set_memory(s, info_ofs + 8, sectors); 248 } 249 250 /* convert boot_device letter to something recognizable by the bios */ 251 static int boot_device2nibble(char boot_device) 252 { 253 switch(boot_device) { 254 case 'a': 255 case 'b': 256 return 0x01; /* floppy boot */ 257 case 'c': 258 return 0x02; /* hard drive boot */ 259 case 'd': 260 return 0x03; /* CD-ROM boot */ 261 case 'n': 262 return 0x04; /* Network boot */ 263 } 264 return 0; 265 } 266 267 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 268 { 269 #define PC_MAX_BOOT_DEVICES 3 270 int nbds, bds[3] = { 0, }; 271 int i; 272 273 nbds = strlen(boot_device); 274 if (nbds > PC_MAX_BOOT_DEVICES) { 275 error_setg(errp, "Too many boot devices for PC"); 276 return; 277 } 278 for (i = 0; i < nbds; i++) { 279 bds[i] = boot_device2nibble(boot_device[i]); 280 if (bds[i] == 0) { 281 error_setg(errp, "Invalid boot device for PC: '%c'", 282 boot_device[i]); 283 return; 284 } 285 } 286 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 287 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 288 } 289 290 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 291 { 292 set_boot_dev(opaque, boot_device, errp); 293 } 294 295 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 296 { 297 int val, nb, i; 298 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 299 300 /* floppy type */ 301 if (floppy) { 302 for (i = 0; i < 2; i++) { 303 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 304 } 305 } 306 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 307 cmos_get_fd_drive_type(fd_type[1]); 308 rtc_set_memory(rtc_state, 0x10, val); 309 310 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 311 nb = 0; 312 if (fd_type[0] < FDRIVE_DRV_NONE) { 313 nb++; 314 } 315 if (fd_type[1] < FDRIVE_DRV_NONE) { 316 nb++; 317 } 318 switch (nb) { 319 case 0: 320 break; 321 case 1: 322 val |= 0x01; /* 1 drive, ready for boot */ 323 break; 324 case 2: 325 val |= 0x41; /* 2 drives, ready for boot */ 326 break; 327 } 328 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 329 } 330 331 typedef struct pc_cmos_init_late_arg { 332 ISADevice *rtc_state; 333 BusState *idebus[2]; 334 } pc_cmos_init_late_arg; 335 336 typedef struct check_fdc_state { 337 ISADevice *floppy; 338 bool multiple; 339 } CheckFdcState; 340 341 static int check_fdc(Object *obj, void *opaque) 342 { 343 CheckFdcState *state = opaque; 344 Object *fdc; 345 uint32_t iobase; 346 Error *local_err = NULL; 347 348 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 349 if (!fdc) { 350 return 0; 351 } 352 353 iobase = object_property_get_int(obj, "iobase", &local_err); 354 if (local_err || iobase != 0x3f0) { 355 error_free(local_err); 356 return 0; 357 } 358 359 if (state->floppy) { 360 state->multiple = true; 361 } else { 362 state->floppy = ISA_DEVICE(obj); 363 } 364 return 0; 365 } 366 367 static const char * const fdc_container_path[] = { 368 "/unattached", "/peripheral", "/peripheral-anon" 369 }; 370 371 static void pc_cmos_init_late(void *opaque) 372 { 373 pc_cmos_init_late_arg *arg = opaque; 374 ISADevice *s = arg->rtc_state; 375 int16_t cylinders; 376 int8_t heads, sectors; 377 int val; 378 int i, trans; 379 Object *container; 380 CheckFdcState state = { 0 }; 381 382 val = 0; 383 if (ide_get_geometry(arg->idebus[0], 0, 384 &cylinders, &heads, §ors) >= 0) { 385 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 386 val |= 0xf0; 387 } 388 if (ide_get_geometry(arg->idebus[0], 1, 389 &cylinders, &heads, §ors) >= 0) { 390 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 391 val |= 0x0f; 392 } 393 rtc_set_memory(s, 0x12, val); 394 395 val = 0; 396 for (i = 0; i < 4; i++) { 397 /* NOTE: ide_get_geometry() returns the physical 398 geometry. It is always such that: 1 <= sects <= 63, 1 399 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 400 geometry can be different if a translation is done. */ 401 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 402 &cylinders, &heads, §ors) >= 0) { 403 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 404 assert((trans & ~3) == 0); 405 val |= trans << (i * 2); 406 } 407 } 408 rtc_set_memory(s, 0x39, val); 409 410 /* 411 * Locate the FDC at IO address 0x3f0, and configure the CMOS registers 412 * accordingly. 413 */ 414 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 415 container = container_get(qdev_get_machine(), fdc_container_path[i]); 416 object_child_foreach(container, check_fdc, &state); 417 } 418 419 if (state.multiple) { 420 error_report("warning: multiple floppy disk controllers with " 421 "iobase=0x3f0 have been found;\n" 422 "the one being picked for CMOS setup might not reflect " 423 "your intent"); 424 } 425 pc_cmos_init_floppy(s, state.floppy); 426 427 qemu_unregister_reset(pc_cmos_init_late, opaque); 428 } 429 430 void pc_cmos_init(PCMachineState *pcms, 431 BusState *idebus0, BusState *idebus1, 432 ISADevice *s) 433 { 434 int val; 435 static pc_cmos_init_late_arg arg; 436 Error *local_err = NULL; 437 438 /* various important CMOS locations needed by PC/Bochs bios */ 439 440 /* memory size */ 441 /* base memory (first MiB) */ 442 val = MIN(pcms->below_4g_mem_size / 1024, 640); 443 rtc_set_memory(s, 0x15, val); 444 rtc_set_memory(s, 0x16, val >> 8); 445 /* extended memory (next 64MiB) */ 446 if (pcms->below_4g_mem_size > 1024 * 1024) { 447 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 448 } else { 449 val = 0; 450 } 451 if (val > 65535) 452 val = 65535; 453 rtc_set_memory(s, 0x17, val); 454 rtc_set_memory(s, 0x18, val >> 8); 455 rtc_set_memory(s, 0x30, val); 456 rtc_set_memory(s, 0x31, val >> 8); 457 /* memory between 16MiB and 4GiB */ 458 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 459 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 460 } else { 461 val = 0; 462 } 463 if (val > 65535) 464 val = 65535; 465 rtc_set_memory(s, 0x34, val); 466 rtc_set_memory(s, 0x35, val >> 8); 467 /* memory above 4GiB */ 468 val = pcms->above_4g_mem_size / 65536; 469 rtc_set_memory(s, 0x5b, val); 470 rtc_set_memory(s, 0x5c, val >> 8); 471 rtc_set_memory(s, 0x5d, val >> 16); 472 473 /* set the number of CPU */ 474 rtc_set_memory(s, 0x5f, smp_cpus - 1); 475 476 object_property_add_link(OBJECT(pcms), "rtc_state", 477 TYPE_ISA_DEVICE, 478 (Object **)&pcms->rtc, 479 object_property_allow_set_link, 480 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 481 object_property_set_link(OBJECT(pcms), OBJECT(s), 482 "rtc_state", &error_abort); 483 484 set_boot_dev(s, MACHINE(pcms)->boot_order, &local_err); 485 if (local_err) { 486 error_report_err(local_err); 487 exit(1); 488 } 489 490 val = 0; 491 val |= 0x02; /* FPU is there */ 492 val |= 0x04; /* PS/2 mouse installed */ 493 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 494 495 /* hard drives and FDC */ 496 arg.rtc_state = s; 497 arg.idebus[0] = idebus0; 498 arg.idebus[1] = idebus1; 499 qemu_register_reset(pc_cmos_init_late, &arg); 500 } 501 502 #define TYPE_PORT92 "port92" 503 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 504 505 /* port 92 stuff: could be split off */ 506 typedef struct Port92State { 507 ISADevice parent_obj; 508 509 MemoryRegion io; 510 uint8_t outport; 511 qemu_irq *a20_out; 512 } Port92State; 513 514 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 515 unsigned size) 516 { 517 Port92State *s = opaque; 518 int oldval = s->outport; 519 520 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 521 s->outport = val; 522 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 523 if ((val & 1) && !(oldval & 1)) { 524 qemu_system_reset_request(); 525 } 526 } 527 528 static uint64_t port92_read(void *opaque, hwaddr addr, 529 unsigned size) 530 { 531 Port92State *s = opaque; 532 uint32_t ret; 533 534 ret = s->outport; 535 DPRINTF("port92: read 0x%02x\n", ret); 536 return ret; 537 } 538 539 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 540 { 541 Port92State *s = PORT92(dev); 542 543 s->a20_out = a20_out; 544 } 545 546 static const VMStateDescription vmstate_port92_isa = { 547 .name = "port92", 548 .version_id = 1, 549 .minimum_version_id = 1, 550 .fields = (VMStateField[]) { 551 VMSTATE_UINT8(outport, Port92State), 552 VMSTATE_END_OF_LIST() 553 } 554 }; 555 556 static void port92_reset(DeviceState *d) 557 { 558 Port92State *s = PORT92(d); 559 560 s->outport &= ~1; 561 } 562 563 static const MemoryRegionOps port92_ops = { 564 .read = port92_read, 565 .write = port92_write, 566 .impl = { 567 .min_access_size = 1, 568 .max_access_size = 1, 569 }, 570 .endianness = DEVICE_LITTLE_ENDIAN, 571 }; 572 573 static void port92_initfn(Object *obj) 574 { 575 Port92State *s = PORT92(obj); 576 577 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 578 579 s->outport = 0; 580 } 581 582 static void port92_realizefn(DeviceState *dev, Error **errp) 583 { 584 ISADevice *isadev = ISA_DEVICE(dev); 585 Port92State *s = PORT92(dev); 586 587 isa_register_ioport(isadev, &s->io, 0x92); 588 } 589 590 static void port92_class_initfn(ObjectClass *klass, void *data) 591 { 592 DeviceClass *dc = DEVICE_CLASS(klass); 593 594 dc->realize = port92_realizefn; 595 dc->reset = port92_reset; 596 dc->vmsd = &vmstate_port92_isa; 597 /* 598 * Reason: unlike ordinary ISA devices, this one needs additional 599 * wiring: its A20 output line needs to be wired up by 600 * port92_init(). 601 */ 602 dc->cannot_instantiate_with_device_add_yet = true; 603 } 604 605 static const TypeInfo port92_info = { 606 .name = TYPE_PORT92, 607 .parent = TYPE_ISA_DEVICE, 608 .instance_size = sizeof(Port92State), 609 .instance_init = port92_initfn, 610 .class_init = port92_class_initfn, 611 }; 612 613 static void port92_register_types(void) 614 { 615 type_register_static(&port92_info); 616 } 617 618 type_init(port92_register_types) 619 620 static void handle_a20_line_change(void *opaque, int irq, int level) 621 { 622 X86CPU *cpu = opaque; 623 624 /* XXX: send to all CPUs ? */ 625 /* XXX: add logic to handle multiple A20 line sources */ 626 x86_cpu_set_a20(cpu, level); 627 } 628 629 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 630 { 631 int index = le32_to_cpu(e820_reserve.count); 632 struct e820_entry *entry; 633 634 if (type != E820_RAM) { 635 /* old FW_CFG_E820_TABLE entry -- reservations only */ 636 if (index >= E820_NR_ENTRIES) { 637 return -EBUSY; 638 } 639 entry = &e820_reserve.entry[index++]; 640 641 entry->address = cpu_to_le64(address); 642 entry->length = cpu_to_le64(length); 643 entry->type = cpu_to_le32(type); 644 645 e820_reserve.count = cpu_to_le32(index); 646 } 647 648 /* new "etc/e820" file -- include ram too */ 649 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 650 e820_table[e820_entries].address = cpu_to_le64(address); 651 e820_table[e820_entries].length = cpu_to_le64(length); 652 e820_table[e820_entries].type = cpu_to_le32(type); 653 e820_entries++; 654 655 return e820_entries; 656 } 657 658 int e820_get_num_entries(void) 659 { 660 return e820_entries; 661 } 662 663 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 664 { 665 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 666 *address = le64_to_cpu(e820_table[idx].address); 667 *length = le64_to_cpu(e820_table[idx].length); 668 return true; 669 } 670 return false; 671 } 672 673 /* Enables contiguous-apic-ID mode, for compatibility */ 674 static bool compat_apic_id_mode; 675 676 void enable_compat_apic_id_mode(void) 677 { 678 compat_apic_id_mode = true; 679 } 680 681 /* Calculates initial APIC ID for a specific CPU index 682 * 683 * Currently we need to be able to calculate the APIC ID from the CPU index 684 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 685 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 686 * all CPUs up to max_cpus. 687 */ 688 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 689 { 690 uint32_t correct_id; 691 static bool warned; 692 693 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 694 if (compat_apic_id_mode) { 695 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 696 error_report("APIC IDs set in compatibility mode, " 697 "CPU topology won't match the configuration"); 698 warned = true; 699 } 700 return cpu_index; 701 } else { 702 return correct_id; 703 } 704 } 705 706 /* Calculates the limit to CPU APIC ID values 707 * 708 * This function returns the limit for the APIC ID value, so that all 709 * CPU APIC IDs are < pc_apic_id_limit(). 710 * 711 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 712 */ 713 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 714 { 715 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 716 } 717 718 static void pc_build_smbios(FWCfgState *fw_cfg) 719 { 720 uint8_t *smbios_tables, *smbios_anchor; 721 size_t smbios_tables_len, smbios_anchor_len; 722 struct smbios_phys_mem_area *mem_array; 723 unsigned i, array_count; 724 725 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 726 if (smbios_tables) { 727 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 728 smbios_tables, smbios_tables_len); 729 } 730 731 /* build the array of physical mem area from e820 table */ 732 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 733 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 734 uint64_t addr, len; 735 736 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 737 mem_array[array_count].address = addr; 738 mem_array[array_count].length = len; 739 array_count++; 740 } 741 } 742 smbios_get_tables(mem_array, array_count, 743 &smbios_tables, &smbios_tables_len, 744 &smbios_anchor, &smbios_anchor_len); 745 g_free(mem_array); 746 747 if (smbios_anchor) { 748 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 749 smbios_tables, smbios_tables_len); 750 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 751 smbios_anchor, smbios_anchor_len); 752 } 753 } 754 755 static FWCfgState *bochs_bios_init(AddressSpace *as) 756 { 757 FWCfgState *fw_cfg; 758 uint64_t *numa_fw_cfg; 759 int i, j; 760 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 761 762 fw_cfg = fw_cfg_init_io_dma(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 4, as); 763 764 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 765 * 766 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 767 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 768 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 769 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 770 * may see". 771 * 772 * So, this means we must not use max_cpus, here, but the maximum possible 773 * APIC ID value, plus one. 774 * 775 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 776 * the APIC ID, not the "CPU index" 777 */ 778 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 779 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 780 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 781 acpi_tables, acpi_tables_len); 782 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 783 784 pc_build_smbios(fw_cfg); 785 786 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 787 &e820_reserve, sizeof(e820_reserve)); 788 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 789 sizeof(struct e820_entry) * e820_entries); 790 791 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 792 /* allocate memory for the NUMA channel: one (64bit) word for the number 793 * of nodes, one word for each VCPU->node and one word for each node to 794 * hold the amount of memory. 795 */ 796 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 797 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 798 for (i = 0; i < max_cpus; i++) { 799 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 800 assert(apic_id < apic_id_limit); 801 for (j = 0; j < nb_numa_nodes; j++) { 802 if (test_bit(i, numa_info[j].node_cpu)) { 803 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 804 break; 805 } 806 } 807 } 808 for (i = 0; i < nb_numa_nodes; i++) { 809 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 810 } 811 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 812 (1 + apic_id_limit + nb_numa_nodes) * 813 sizeof(*numa_fw_cfg)); 814 815 return fw_cfg; 816 } 817 818 static long get_file_size(FILE *f) 819 { 820 long where, size; 821 822 /* XXX: on Unix systems, using fstat() probably makes more sense */ 823 824 where = ftell(f); 825 fseek(f, 0, SEEK_END); 826 size = ftell(f); 827 fseek(f, where, SEEK_SET); 828 829 return size; 830 } 831 832 static void load_linux(PCMachineState *pcms, 833 FWCfgState *fw_cfg) 834 { 835 uint16_t protocol; 836 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 837 uint32_t initrd_max; 838 uint8_t header[8192], *setup, *kernel, *initrd_data; 839 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 840 FILE *f; 841 char *vmode; 842 MachineState *machine = MACHINE(pcms); 843 const char *kernel_filename = machine->kernel_filename; 844 const char *initrd_filename = machine->initrd_filename; 845 const char *kernel_cmdline = machine->kernel_cmdline; 846 847 /* Align to 16 bytes as a paranoia measure */ 848 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 849 850 /* load the kernel header */ 851 f = fopen(kernel_filename, "rb"); 852 if (!f || !(kernel_size = get_file_size(f)) || 853 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 854 MIN(ARRAY_SIZE(header), kernel_size)) { 855 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 856 kernel_filename, strerror(errno)); 857 exit(1); 858 } 859 860 /* kernel protocol version */ 861 #if 0 862 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 863 #endif 864 if (ldl_p(header+0x202) == 0x53726448) { 865 protocol = lduw_p(header+0x206); 866 } else { 867 /* This looks like a multiboot kernel. If it is, let's stop 868 treating it like a Linux kernel. */ 869 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 870 kernel_cmdline, kernel_size, header)) { 871 return; 872 } 873 protocol = 0; 874 } 875 876 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 877 /* Low kernel */ 878 real_addr = 0x90000; 879 cmdline_addr = 0x9a000 - cmdline_size; 880 prot_addr = 0x10000; 881 } else if (protocol < 0x202) { 882 /* High but ancient kernel */ 883 real_addr = 0x90000; 884 cmdline_addr = 0x9a000 - cmdline_size; 885 prot_addr = 0x100000; 886 } else { 887 /* High and recent kernel */ 888 real_addr = 0x10000; 889 cmdline_addr = 0x20000; 890 prot_addr = 0x100000; 891 } 892 893 #if 0 894 fprintf(stderr, 895 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 896 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 897 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 898 real_addr, 899 cmdline_addr, 900 prot_addr); 901 #endif 902 903 /* highest address for loading the initrd */ 904 if (protocol >= 0x203) { 905 initrd_max = ldl_p(header+0x22c); 906 } else { 907 initrd_max = 0x37ffffff; 908 } 909 910 if (initrd_max >= pcms->below_4g_mem_size - acpi_data_size) { 911 initrd_max = pcms->below_4g_mem_size - acpi_data_size - 1; 912 } 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 916 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 917 918 if (protocol >= 0x202) { 919 stl_p(header+0x228, cmdline_addr); 920 } else { 921 stw_p(header+0x20, 0xA33F); 922 stw_p(header+0x22, cmdline_addr-real_addr); 923 } 924 925 /* handle vga= parameter */ 926 vmode = strstr(kernel_cmdline, "vga="); 927 if (vmode) { 928 unsigned int video_mode; 929 /* skip "vga=" */ 930 vmode += 4; 931 if (!strncmp(vmode, "normal", 6)) { 932 video_mode = 0xffff; 933 } else if (!strncmp(vmode, "ext", 3)) { 934 video_mode = 0xfffe; 935 } else if (!strncmp(vmode, "ask", 3)) { 936 video_mode = 0xfffd; 937 } else { 938 video_mode = strtol(vmode, NULL, 0); 939 } 940 stw_p(header+0x1fa, video_mode); 941 } 942 943 /* loader type */ 944 /* High nybble = B reserved for QEMU; low nybble is revision number. 945 If this code is substantially changed, you may want to consider 946 incrementing the revision. */ 947 if (protocol >= 0x200) { 948 header[0x210] = 0xB0; 949 } 950 /* heap */ 951 if (protocol >= 0x201) { 952 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 953 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 954 } 955 956 /* load initrd */ 957 if (initrd_filename) { 958 if (protocol < 0x200) { 959 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 960 exit(1); 961 } 962 963 initrd_size = get_image_size(initrd_filename); 964 if (initrd_size < 0) { 965 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 966 initrd_filename, strerror(errno)); 967 exit(1); 968 } 969 970 initrd_addr = (initrd_max-initrd_size) & ~4095; 971 972 initrd_data = g_malloc(initrd_size); 973 load_image(initrd_filename, initrd_data); 974 975 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 976 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 977 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 978 979 stl_p(header+0x218, initrd_addr); 980 stl_p(header+0x21c, initrd_size); 981 } 982 983 /* load kernel and setup */ 984 setup_size = header[0x1f1]; 985 if (setup_size == 0) { 986 setup_size = 4; 987 } 988 setup_size = (setup_size+1)*512; 989 if (setup_size > kernel_size) { 990 fprintf(stderr, "qemu: invalid kernel header\n"); 991 exit(1); 992 } 993 kernel_size -= setup_size; 994 995 setup = g_malloc(setup_size); 996 kernel = g_malloc(kernel_size); 997 fseek(f, 0, SEEK_SET); 998 if (fread(setup, 1, setup_size, f) != setup_size) { 999 fprintf(stderr, "fread() failed\n"); 1000 exit(1); 1001 } 1002 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1003 fprintf(stderr, "fread() failed\n"); 1004 exit(1); 1005 } 1006 fclose(f); 1007 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1008 1009 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1010 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1011 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1012 1013 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1014 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1015 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1016 1017 option_rom[nb_option_roms].name = "linuxboot.bin"; 1018 option_rom[nb_option_roms].bootindex = 0; 1019 nb_option_roms++; 1020 } 1021 1022 #define NE2000_NB_MAX 6 1023 1024 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1025 0x280, 0x380 }; 1026 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1027 1028 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1029 { 1030 static int nb_ne2k = 0; 1031 1032 if (nb_ne2k == NE2000_NB_MAX) 1033 return; 1034 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1035 ne2000_irq[nb_ne2k], nd); 1036 nb_ne2k++; 1037 } 1038 1039 DeviceState *cpu_get_current_apic(void) 1040 { 1041 if (current_cpu) { 1042 X86CPU *cpu = X86_CPU(current_cpu); 1043 return cpu->apic_state; 1044 } else { 1045 return NULL; 1046 } 1047 } 1048 1049 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1050 { 1051 X86CPU *cpu = opaque; 1052 1053 if (level) { 1054 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1055 } 1056 } 1057 1058 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1059 Error **errp) 1060 { 1061 X86CPU *cpu = NULL; 1062 Error *local_err = NULL; 1063 1064 cpu = cpu_x86_create(cpu_model, &local_err); 1065 if (local_err != NULL) { 1066 goto out; 1067 } 1068 1069 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1070 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1071 1072 out: 1073 if (local_err) { 1074 error_propagate(errp, local_err); 1075 object_unref(OBJECT(cpu)); 1076 cpu = NULL; 1077 } 1078 return cpu; 1079 } 1080 1081 void pc_hot_add_cpu(const int64_t id, Error **errp) 1082 { 1083 X86CPU *cpu; 1084 MachineState *machine = MACHINE(qdev_get_machine()); 1085 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1086 Error *local_err = NULL; 1087 1088 if (id < 0) { 1089 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1090 return; 1091 } 1092 1093 if (cpu_exists(apic_id)) { 1094 error_setg(errp, "Unable to add CPU: %" PRIi64 1095 ", it already exists", id); 1096 return; 1097 } 1098 1099 if (id >= max_cpus) { 1100 error_setg(errp, "Unable to add CPU: %" PRIi64 1101 ", max allowed: %d", id, max_cpus - 1); 1102 return; 1103 } 1104 1105 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1106 error_setg(errp, "Unable to add CPU: %" PRIi64 1107 ", resulting APIC ID (%" PRIi64 ") is too large", 1108 id, apic_id); 1109 return; 1110 } 1111 1112 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1113 if (local_err) { 1114 error_propagate(errp, local_err); 1115 return; 1116 } 1117 object_unref(OBJECT(cpu)); 1118 } 1119 1120 void pc_cpus_init(PCMachineState *pcms) 1121 { 1122 int i; 1123 X86CPU *cpu = NULL; 1124 MachineState *machine = MACHINE(pcms); 1125 Error *error = NULL; 1126 unsigned long apic_id_limit; 1127 1128 /* init CPUs */ 1129 if (machine->cpu_model == NULL) { 1130 #ifdef TARGET_X86_64 1131 machine->cpu_model = "qemu64"; 1132 #else 1133 machine->cpu_model = "qemu32"; 1134 #endif 1135 } 1136 1137 apic_id_limit = pc_apic_id_limit(max_cpus); 1138 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1139 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1140 apic_id_limit - 1); 1141 exit(1); 1142 } 1143 1144 for (i = 0; i < smp_cpus; i++) { 1145 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1146 &error); 1147 if (error) { 1148 error_report_err(error); 1149 exit(1); 1150 } 1151 object_unref(OBJECT(cpu)); 1152 } 1153 1154 /* tell smbios about cpuid version and features */ 1155 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1156 } 1157 1158 /* pci-info ROM file. Little endian format */ 1159 typedef struct PcRomPciInfo { 1160 uint64_t w32_min; 1161 uint64_t w32_max; 1162 uint64_t w64_min; 1163 uint64_t w64_max; 1164 } PcRomPciInfo; 1165 1166 typedef struct PcGuestInfoState { 1167 PcGuestInfo info; 1168 Notifier machine_done; 1169 } PcGuestInfoState; 1170 1171 static 1172 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1173 { 1174 PcGuestInfoState *guest_info_state = container_of(notifier, 1175 PcGuestInfoState, 1176 machine_done); 1177 PCIBus *bus = find_i440fx(); 1178 1179 if (bus) { 1180 int extra_hosts = 0; 1181 1182 QLIST_FOREACH(bus, &bus->child, sibling) { 1183 /* look for expander root buses */ 1184 if (pci_bus_is_root(bus)) { 1185 extra_hosts++; 1186 } 1187 } 1188 if (extra_hosts && guest_info_state->info.fw_cfg) { 1189 uint64_t *val = g_malloc(sizeof(*val)); 1190 *val = cpu_to_le64(extra_hosts); 1191 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1192 "etc/extra-pci-roots", val, sizeof(*val)); 1193 } 1194 } 1195 1196 acpi_setup(&guest_info_state->info); 1197 } 1198 1199 PcGuestInfo *pc_guest_info_init(PCMachineState *pcms) 1200 { 1201 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1202 PcGuestInfo *guest_info = &guest_info_state->info; 1203 int i, j; 1204 1205 guest_info->ram_size_below_4g = pcms->below_4g_mem_size; 1206 guest_info->ram_size = pcms->below_4g_mem_size + pcms->above_4g_mem_size; 1207 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1208 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1209 guest_info->numa_nodes = nb_numa_nodes; 1210 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1211 sizeof *guest_info->node_mem); 1212 for (i = 0; i < nb_numa_nodes; i++) { 1213 guest_info->node_mem[i] = numa_info[i].node_mem; 1214 } 1215 1216 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1217 sizeof *guest_info->node_cpu); 1218 1219 for (i = 0; i < max_cpus; i++) { 1220 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1221 assert(apic_id < guest_info->apic_id_limit); 1222 for (j = 0; j < nb_numa_nodes; j++) { 1223 if (test_bit(i, numa_info[j].node_cpu)) { 1224 guest_info->node_cpu[apic_id] = j; 1225 break; 1226 } 1227 } 1228 } 1229 1230 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1231 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1232 return guest_info; 1233 } 1234 1235 /* setup pci memory address space mapping into system address space */ 1236 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1237 MemoryRegion *pci_address_space) 1238 { 1239 /* Set to lower priority than RAM */ 1240 memory_region_add_subregion_overlap(system_memory, 0x0, 1241 pci_address_space, -1); 1242 } 1243 1244 void pc_acpi_init(const char *default_dsdt) 1245 { 1246 char *filename; 1247 1248 if (acpi_tables != NULL) { 1249 /* manually set via -acpitable, leave it alone */ 1250 return; 1251 } 1252 1253 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1254 if (filename == NULL) { 1255 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1256 } else { 1257 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1258 &error_abort); 1259 Error *err = NULL; 1260 1261 qemu_opt_set(opts, "file", filename, &error_abort); 1262 1263 acpi_table_add_builtin(opts, &err); 1264 if (err) { 1265 error_report("WARNING: failed to load %s: %s", filename, 1266 error_get_pretty(err)); 1267 error_free(err); 1268 } 1269 g_free(filename); 1270 } 1271 } 1272 1273 FWCfgState *xen_load_linux(PCMachineState *pcms, 1274 PcGuestInfo *guest_info) 1275 { 1276 int i; 1277 FWCfgState *fw_cfg; 1278 1279 assert(MACHINE(pcms)->kernel_filename != NULL); 1280 1281 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1282 rom_set_fw(fw_cfg); 1283 1284 load_linux(pcms, fw_cfg); 1285 for (i = 0; i < nb_option_roms; i++) { 1286 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1287 !strcmp(option_rom[i].name, "multiboot.bin")); 1288 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1289 } 1290 guest_info->fw_cfg = fw_cfg; 1291 return fw_cfg; 1292 } 1293 1294 FWCfgState *pc_memory_init(PCMachineState *pcms, 1295 MemoryRegion *system_memory, 1296 MemoryRegion *rom_memory, 1297 MemoryRegion **ram_memory, 1298 PcGuestInfo *guest_info) 1299 { 1300 int linux_boot, i; 1301 MemoryRegion *ram, *option_rom_mr; 1302 MemoryRegion *ram_below_4g, *ram_above_4g; 1303 FWCfgState *fw_cfg; 1304 MachineState *machine = MACHINE(pcms); 1305 1306 assert(machine->ram_size == pcms->below_4g_mem_size + 1307 pcms->above_4g_mem_size); 1308 1309 linux_boot = (machine->kernel_filename != NULL); 1310 1311 /* Allocate RAM. We allocate it as a single memory region and use 1312 * aliases to address portions of it, mostly for backwards compatibility 1313 * with older qemus that used qemu_ram_alloc(). 1314 */ 1315 ram = g_malloc(sizeof(*ram)); 1316 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1317 machine->ram_size); 1318 *ram_memory = ram; 1319 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1320 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1321 0, pcms->below_4g_mem_size); 1322 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1323 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1324 if (pcms->above_4g_mem_size > 0) { 1325 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1326 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1327 pcms->below_4g_mem_size, 1328 pcms->above_4g_mem_size); 1329 memory_region_add_subregion(system_memory, 0x100000000ULL, 1330 ram_above_4g); 1331 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1332 } 1333 1334 if (!guest_info->has_reserved_memory && 1335 (machine->ram_slots || 1336 (machine->maxram_size > machine->ram_size))) { 1337 MachineClass *mc = MACHINE_GET_CLASS(machine); 1338 1339 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1340 mc->name); 1341 exit(EXIT_FAILURE); 1342 } 1343 1344 /* initialize hotplug memory address space */ 1345 if (guest_info->has_reserved_memory && 1346 (machine->ram_size < machine->maxram_size)) { 1347 ram_addr_t hotplug_mem_size = 1348 machine->maxram_size - machine->ram_size; 1349 1350 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1351 error_report("unsupported amount of memory slots: %"PRIu64, 1352 machine->ram_slots); 1353 exit(EXIT_FAILURE); 1354 } 1355 1356 if (QEMU_ALIGN_UP(machine->maxram_size, 1357 TARGET_PAGE_SIZE) != machine->maxram_size) { 1358 error_report("maximum memory size must by aligned to multiple of " 1359 "%d bytes", TARGET_PAGE_SIZE); 1360 exit(EXIT_FAILURE); 1361 } 1362 1363 pcms->hotplug_memory.base = 1364 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1365 1366 if (pcms->enforce_aligned_dimm) { 1367 /* size hotplug region assuming 1G page max alignment per slot */ 1368 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1369 } 1370 1371 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1372 hotplug_mem_size) { 1373 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1374 machine->maxram_size); 1375 exit(EXIT_FAILURE); 1376 } 1377 1378 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1379 "hotplug-memory", hotplug_mem_size); 1380 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1381 &pcms->hotplug_memory.mr); 1382 } 1383 1384 /* Initialize PC system firmware */ 1385 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1386 1387 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1388 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1389 &error_fatal); 1390 vmstate_register_ram_global(option_rom_mr); 1391 memory_region_add_subregion_overlap(rom_memory, 1392 PC_ROM_MIN_VGA, 1393 option_rom_mr, 1394 1); 1395 1396 fw_cfg = bochs_bios_init(&address_space_memory); 1397 1398 rom_set_fw(fw_cfg); 1399 1400 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1401 uint64_t *val = g_malloc(sizeof(*val)); 1402 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1403 uint64_t res_mem_end = pcms->hotplug_memory.base; 1404 1405 if (!pcmc->broken_reserved_end) { 1406 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1407 } 1408 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1409 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1410 } 1411 1412 if (linux_boot) { 1413 load_linux(pcms, fw_cfg); 1414 } 1415 1416 for (i = 0; i < nb_option_roms; i++) { 1417 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1418 } 1419 guest_info->fw_cfg = fw_cfg; 1420 return fw_cfg; 1421 } 1422 1423 qemu_irq pc_allocate_cpu_irq(void) 1424 { 1425 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1426 } 1427 1428 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1429 { 1430 DeviceState *dev = NULL; 1431 1432 if (pci_bus) { 1433 PCIDevice *pcidev = pci_vga_init(pci_bus); 1434 dev = pcidev ? &pcidev->qdev : NULL; 1435 } else if (isa_bus) { 1436 ISADevice *isadev = isa_vga_init(isa_bus); 1437 dev = isadev ? DEVICE(isadev) : NULL; 1438 } 1439 return dev; 1440 } 1441 1442 static const MemoryRegionOps ioport80_io_ops = { 1443 .write = ioport80_write, 1444 .read = ioport80_read, 1445 .endianness = DEVICE_NATIVE_ENDIAN, 1446 .impl = { 1447 .min_access_size = 1, 1448 .max_access_size = 1, 1449 }, 1450 }; 1451 1452 static const MemoryRegionOps ioportF0_io_ops = { 1453 .write = ioportF0_write, 1454 .read = ioportF0_read, 1455 .endianness = DEVICE_NATIVE_ENDIAN, 1456 .impl = { 1457 .min_access_size = 1, 1458 .max_access_size = 1, 1459 }, 1460 }; 1461 1462 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1463 ISADevice **rtc_state, 1464 bool create_fdctrl, 1465 bool no_vmport, 1466 uint32 hpet_irqs) 1467 { 1468 int i; 1469 DriveInfo *fd[MAX_FD]; 1470 DeviceState *hpet = NULL; 1471 int pit_isa_irq = 0; 1472 qemu_irq pit_alt_irq = NULL; 1473 qemu_irq rtc_irq = NULL; 1474 qemu_irq *a20_line; 1475 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1476 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1477 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1478 1479 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1480 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1481 1482 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1483 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1484 1485 /* 1486 * Check if an HPET shall be created. 1487 * 1488 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1489 * when the HPET wants to take over. Thus we have to disable the latter. 1490 */ 1491 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1492 /* In order to set property, here not using sysbus_try_create_simple */ 1493 hpet = qdev_try_create(NULL, TYPE_HPET); 1494 if (hpet) { 1495 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1496 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1497 * IRQ8 and IRQ2. 1498 */ 1499 uint8_t compat = object_property_get_int(OBJECT(hpet), 1500 HPET_INTCAP, NULL); 1501 if (!compat) { 1502 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1503 } 1504 qdev_init_nofail(hpet); 1505 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1506 1507 for (i = 0; i < GSI_NUM_PINS; i++) { 1508 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1509 } 1510 pit_isa_irq = -1; 1511 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1512 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1513 } 1514 } 1515 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1516 1517 qemu_register_boot_set(pc_boot_set, *rtc_state); 1518 1519 if (!xen_enabled()) { 1520 if (kvm_irqchip_in_kernel()) { 1521 pit = kvm_pit_init(isa_bus, 0x40); 1522 } else { 1523 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1524 } 1525 if (hpet) { 1526 /* connect PIT to output control line of the HPET */ 1527 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1528 } 1529 pcspk_init(isa_bus, pit); 1530 } 1531 1532 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1533 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1534 1535 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1536 i8042 = isa_create_simple(isa_bus, "i8042"); 1537 i8042_setup_a20_line(i8042, &a20_line[0]); 1538 if (!no_vmport) { 1539 vmport_init(isa_bus); 1540 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1541 } else { 1542 vmmouse = NULL; 1543 } 1544 if (vmmouse) { 1545 DeviceState *dev = DEVICE(vmmouse); 1546 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1547 qdev_init_nofail(dev); 1548 } 1549 port92 = isa_create_simple(isa_bus, "port92"); 1550 port92_init(port92, &a20_line[1]); 1551 1552 DMA_init(0); 1553 1554 for(i = 0; i < MAX_FD; i++) { 1555 fd[i] = drive_get(IF_FLOPPY, 0, i); 1556 create_fdctrl |= !!fd[i]; 1557 } 1558 if (create_fdctrl) { 1559 fdctrl_init_isa(isa_bus, fd); 1560 } 1561 } 1562 1563 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1564 { 1565 int i; 1566 1567 for (i = 0; i < nb_nics; i++) { 1568 NICInfo *nd = &nd_table[i]; 1569 1570 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1571 pc_init_ne2k_isa(isa_bus, nd); 1572 } else { 1573 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1574 } 1575 } 1576 } 1577 1578 void pc_pci_device_init(PCIBus *pci_bus) 1579 { 1580 int max_bus; 1581 int bus; 1582 1583 max_bus = drive_get_max_bus(IF_SCSI); 1584 for (bus = 0; bus <= max_bus; bus++) { 1585 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1586 } 1587 } 1588 1589 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1590 { 1591 DeviceState *dev; 1592 SysBusDevice *d; 1593 unsigned int i; 1594 1595 if (kvm_irqchip_in_kernel()) { 1596 dev = qdev_create(NULL, "kvm-ioapic"); 1597 } else { 1598 dev = qdev_create(NULL, "ioapic"); 1599 } 1600 if (parent_name) { 1601 object_property_add_child(object_resolve_path(parent_name, NULL), 1602 "ioapic", OBJECT(dev), NULL); 1603 } 1604 qdev_init_nofail(dev); 1605 d = SYS_BUS_DEVICE(dev); 1606 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1607 1608 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1609 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1610 } 1611 } 1612 1613 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1614 DeviceState *dev, Error **errp) 1615 { 1616 HotplugHandlerClass *hhc; 1617 Error *local_err = NULL; 1618 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1619 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1620 PCDIMMDevice *dimm = PC_DIMM(dev); 1621 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1622 MemoryRegion *mr = ddc->get_memory_region(dimm); 1623 uint64_t align = TARGET_PAGE_SIZE; 1624 1625 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1626 align = memory_region_get_alignment(mr); 1627 } 1628 1629 if (!pcms->acpi_dev) { 1630 error_setg(&local_err, 1631 "memory hotplug is not enabled: missing acpi device"); 1632 goto out; 1633 } 1634 1635 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, 1636 pcmc->inter_dimm_gap, &local_err); 1637 if (local_err) { 1638 goto out; 1639 } 1640 1641 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1642 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1643 out: 1644 error_propagate(errp, local_err); 1645 } 1646 1647 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1648 DeviceState *dev, Error **errp) 1649 { 1650 HotplugHandlerClass *hhc; 1651 Error *local_err = NULL; 1652 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1653 1654 if (!pcms->acpi_dev) { 1655 error_setg(&local_err, 1656 "memory hotplug is not enabled: missing acpi device"); 1657 goto out; 1658 } 1659 1660 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1661 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1662 1663 out: 1664 error_propagate(errp, local_err); 1665 } 1666 1667 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1668 DeviceState *dev, Error **errp) 1669 { 1670 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1671 PCDIMMDevice *dimm = PC_DIMM(dev); 1672 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1673 MemoryRegion *mr = ddc->get_memory_region(dimm); 1674 HotplugHandlerClass *hhc; 1675 Error *local_err = NULL; 1676 1677 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1678 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1679 1680 if (local_err) { 1681 goto out; 1682 } 1683 1684 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1685 object_unparent(OBJECT(dev)); 1686 1687 out: 1688 error_propagate(errp, local_err); 1689 } 1690 1691 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1692 DeviceState *dev, Error **errp) 1693 { 1694 HotplugHandlerClass *hhc; 1695 Error *local_err = NULL; 1696 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1697 1698 if (!dev->hotplugged) { 1699 goto out; 1700 } 1701 1702 if (!pcms->acpi_dev) { 1703 error_setg(&local_err, 1704 "cpu hotplug is not enabled: missing acpi device"); 1705 goto out; 1706 } 1707 1708 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1709 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1710 if (local_err) { 1711 goto out; 1712 } 1713 1714 /* increment the number of CPUs */ 1715 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1716 out: 1717 error_propagate(errp, local_err); 1718 } 1719 1720 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1721 DeviceState *dev, Error **errp) 1722 { 1723 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1724 pc_dimm_plug(hotplug_dev, dev, errp); 1725 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1726 pc_cpu_plug(hotplug_dev, dev, errp); 1727 } 1728 } 1729 1730 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1731 DeviceState *dev, Error **errp) 1732 { 1733 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1734 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1735 } else { 1736 error_setg(errp, "acpi: device unplug request for not supported device" 1737 " type: %s", object_get_typename(OBJECT(dev))); 1738 } 1739 } 1740 1741 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1742 DeviceState *dev, Error **errp) 1743 { 1744 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1745 pc_dimm_unplug(hotplug_dev, dev, errp); 1746 } else { 1747 error_setg(errp, "acpi: device unplug for not supported device" 1748 " type: %s", object_get_typename(OBJECT(dev))); 1749 } 1750 } 1751 1752 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1753 DeviceState *dev) 1754 { 1755 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1756 1757 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1758 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1759 return HOTPLUG_HANDLER(machine); 1760 } 1761 1762 return pcmc->get_hotplug_handler ? 1763 pcmc->get_hotplug_handler(machine, dev) : NULL; 1764 } 1765 1766 static void 1767 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1768 const char *name, Error **errp) 1769 { 1770 PCMachineState *pcms = PC_MACHINE(obj); 1771 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1772 1773 visit_type_int(v, &value, name, errp); 1774 } 1775 1776 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1777 void *opaque, const char *name, 1778 Error **errp) 1779 { 1780 PCMachineState *pcms = PC_MACHINE(obj); 1781 uint64_t value = pcms->max_ram_below_4g; 1782 1783 visit_type_size(v, &value, name, errp); 1784 } 1785 1786 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1787 void *opaque, const char *name, 1788 Error **errp) 1789 { 1790 PCMachineState *pcms = PC_MACHINE(obj); 1791 Error *error = NULL; 1792 uint64_t value; 1793 1794 visit_type_size(v, &value, name, &error); 1795 if (error) { 1796 error_propagate(errp, error); 1797 return; 1798 } 1799 if (value > (1ULL << 32)) { 1800 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1801 "Machine option 'max-ram-below-4g=%"PRIu64 1802 "' expects size less than or equal to 4G", value); 1803 error_propagate(errp, error); 1804 return; 1805 } 1806 1807 if (value < (1ULL << 20)) { 1808 error_report("Warning: small max_ram_below_4g(%"PRIu64 1809 ") less than 1M. BIOS may not work..", 1810 value); 1811 } 1812 1813 pcms->max_ram_below_4g = value; 1814 } 1815 1816 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1817 const char *name, Error **errp) 1818 { 1819 PCMachineState *pcms = PC_MACHINE(obj); 1820 OnOffAuto vmport = pcms->vmport; 1821 1822 visit_type_OnOffAuto(v, &vmport, name, errp); 1823 } 1824 1825 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1826 const char *name, Error **errp) 1827 { 1828 PCMachineState *pcms = PC_MACHINE(obj); 1829 1830 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1831 } 1832 1833 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1834 { 1835 bool smm_available = false; 1836 1837 if (pcms->smm == ON_OFF_AUTO_OFF) { 1838 return false; 1839 } 1840 1841 if (tcg_enabled() || qtest_enabled()) { 1842 smm_available = true; 1843 } else if (kvm_enabled()) { 1844 smm_available = kvm_has_smm(); 1845 } 1846 1847 if (smm_available) { 1848 return true; 1849 } 1850 1851 if (pcms->smm == ON_OFF_AUTO_ON) { 1852 error_report("System Management Mode not supported by this hypervisor."); 1853 exit(1); 1854 } 1855 return false; 1856 } 1857 1858 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1859 const char *name, Error **errp) 1860 { 1861 PCMachineState *pcms = PC_MACHINE(obj); 1862 OnOffAuto smm = pcms->smm; 1863 1864 visit_type_OnOffAuto(v, &smm, name, errp); 1865 } 1866 1867 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1868 const char *name, Error **errp) 1869 { 1870 PCMachineState *pcms = PC_MACHINE(obj); 1871 1872 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1873 } 1874 1875 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1876 { 1877 PCMachineState *pcms = PC_MACHINE(obj); 1878 1879 return pcms->enforce_aligned_dimm; 1880 } 1881 1882 static void pc_machine_initfn(Object *obj) 1883 { 1884 PCMachineState *pcms = PC_MACHINE(obj); 1885 1886 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1887 pc_machine_get_hotplug_memory_region_size, 1888 NULL, NULL, NULL, &error_abort); 1889 1890 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1891 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1892 pc_machine_get_max_ram_below_4g, 1893 pc_machine_set_max_ram_below_4g, 1894 NULL, NULL, &error_abort); 1895 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1896 "Maximum ram below the 4G boundary (32bit boundary)", 1897 &error_abort); 1898 1899 pcms->smm = ON_OFF_AUTO_AUTO; 1900 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1901 pc_machine_get_smm, 1902 pc_machine_set_smm, 1903 NULL, NULL, &error_abort); 1904 object_property_set_description(obj, PC_MACHINE_SMM, 1905 "Enable SMM (pc & q35)", 1906 &error_abort); 1907 1908 pcms->vmport = ON_OFF_AUTO_AUTO; 1909 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1910 pc_machine_get_vmport, 1911 pc_machine_set_vmport, 1912 NULL, NULL, &error_abort); 1913 object_property_set_description(obj, PC_MACHINE_VMPORT, 1914 "Enable vmport (pc & q35)", 1915 &error_abort); 1916 1917 pcms->enforce_aligned_dimm = true; 1918 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1919 pc_machine_get_aligned_dimm, 1920 NULL, &error_abort); 1921 } 1922 1923 static void pc_machine_reset(void) 1924 { 1925 CPUState *cs; 1926 X86CPU *cpu; 1927 1928 qemu_devices_reset(); 1929 1930 /* Reset APIC after devices have been reset to cancel 1931 * any changes that qemu_devices_reset() might have done. 1932 */ 1933 CPU_FOREACH(cs) { 1934 cpu = X86_CPU(cs); 1935 1936 if (cpu->apic_state) { 1937 device_reset(cpu->apic_state); 1938 } 1939 } 1940 } 1941 1942 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1943 { 1944 X86CPUTopoInfo topo; 1945 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1946 &topo); 1947 return topo.pkg_id; 1948 } 1949 1950 static void pc_machine_class_init(ObjectClass *oc, void *data) 1951 { 1952 MachineClass *mc = MACHINE_CLASS(oc); 1953 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1954 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1955 1956 pcmc->inter_dimm_gap = true; 1957 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1958 mc->get_hotplug_handler = pc_get_hotpug_handler; 1959 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1960 mc->default_boot_order = "cad"; 1961 mc->hot_add_cpu = pc_hot_add_cpu; 1962 mc->max_cpus = 255; 1963 mc->reset = pc_machine_reset; 1964 hc->plug = pc_machine_device_plug_cb; 1965 hc->unplug_request = pc_machine_device_unplug_request_cb; 1966 hc->unplug = pc_machine_device_unplug_cb; 1967 } 1968 1969 static const TypeInfo pc_machine_info = { 1970 .name = TYPE_PC_MACHINE, 1971 .parent = TYPE_MACHINE, 1972 .abstract = true, 1973 .instance_size = sizeof(PCMachineState), 1974 .instance_init = pc_machine_initfn, 1975 .class_size = sizeof(PCMachineClass), 1976 .class_init = pc_machine_class_init, 1977 .interfaces = (InterfaceInfo[]) { 1978 { TYPE_HOTPLUG_HANDLER }, 1979 { } 1980 }, 1981 }; 1982 1983 static void pc_machine_register_types(void) 1984 { 1985 type_register_static(&pc_machine_info); 1986 } 1987 1988 type_init(pc_machine_register_types) 1989