1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/i386/apic.h" 31 #include "hw/i386/topology.h" 32 #include "sysemu/cpus.h" 33 #include "hw/block/fdc.h" 34 #include "hw/ide.h" 35 #include "hw/pci/pci.h" 36 #include "hw/pci/pci_bus.h" 37 #include "hw/nvram/fw_cfg.h" 38 #include "hw/timer/hpet.h" 39 #include "hw/smbios/smbios.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "multiboot.h" 43 #include "hw/timer/mc146818rtc.h" 44 #include "hw/dma/i8257.h" 45 #include "hw/timer/i8254.h" 46 #include "hw/input/i8042.h" 47 #include "hw/audio/pcspk.h" 48 #include "hw/pci/msi.h" 49 #include "hw/sysbus.h" 50 #include "sysemu/sysemu.h" 51 #include "sysemu/numa.h" 52 #include "sysemu/kvm.h" 53 #include "sysemu/qtest.h" 54 #include "kvm_i386.h" 55 #include "hw/xen/xen.h" 56 #include "ui/qemu-spice.h" 57 #include "exec/memory.h" 58 #include "exec/address-spaces.h" 59 #include "sysemu/arch_init.h" 60 #include "qemu/bitmap.h" 61 #include "qemu/config-file.h" 62 #include "qemu/error-report.h" 63 #include "qemu/option.h" 64 #include "hw/acpi/acpi.h" 65 #include "hw/acpi/cpu_hotplug.h" 66 #include "hw/boards.h" 67 #include "acpi-build.h" 68 #include "hw/mem/pc-dimm.h" 69 #include "qapi/error.h" 70 #include "qapi/qapi-visit-common.h" 71 #include "qapi/visitor.h" 72 #include "qom/cpu.h" 73 #include "hw/nmi.h" 74 #include "hw/i386/intel_iommu.h" 75 #include "hw/net/ne2000-isa.h" 76 77 /* debug PC/ISA interrupts */ 78 //#define DEBUG_IRQ 79 80 #ifdef DEBUG_IRQ 81 #define DPRINTF(fmt, ...) \ 82 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 83 #else 84 #define DPRINTF(fmt, ...) 85 #endif 86 87 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 88 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 89 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 90 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 91 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 92 93 #define E820_NR_ENTRIES 16 94 95 struct e820_entry { 96 uint64_t address; 97 uint64_t length; 98 uint32_t type; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 struct e820_table { 102 uint32_t count; 103 struct e820_entry entry[E820_NR_ENTRIES]; 104 } QEMU_PACKED __attribute((__aligned__(4))); 105 106 static struct e820_table e820_reserve; 107 static struct e820_entry *e820_table; 108 static unsigned e820_entries; 109 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 110 111 void gsi_handler(void *opaque, int n, int level) 112 { 113 GSIState *s = opaque; 114 115 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 116 if (n < ISA_NUM_IRQS) { 117 qemu_set_irq(s->i8259_irq[n], level); 118 } 119 qemu_set_irq(s->ioapic_irq[n], level); 120 } 121 122 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 123 unsigned size) 124 { 125 } 126 127 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 128 { 129 return 0xffffffffffffffffULL; 130 } 131 132 /* MSDOS compatibility mode FPU exception support */ 133 static qemu_irq ferr_irq; 134 135 void pc_register_ferr_irq(qemu_irq irq) 136 { 137 ferr_irq = irq; 138 } 139 140 /* XXX: add IGNNE support */ 141 void cpu_set_ferr(CPUX86State *s) 142 { 143 qemu_irq_raise(ferr_irq); 144 } 145 146 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 147 unsigned size) 148 { 149 qemu_irq_lower(ferr_irq); 150 } 151 152 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 153 { 154 return 0xffffffffffffffffULL; 155 } 156 157 /* TSC handling */ 158 uint64_t cpu_get_tsc(CPUX86State *env) 159 { 160 return cpu_get_ticks(); 161 } 162 163 /* IRQ handling */ 164 int cpu_get_pic_interrupt(CPUX86State *env) 165 { 166 X86CPU *cpu = x86_env_get_cpu(env); 167 int intno; 168 169 if (!kvm_irqchip_in_kernel()) { 170 intno = apic_get_interrupt(cpu->apic_state); 171 if (intno >= 0) { 172 return intno; 173 } 174 /* read the irq from the PIC */ 175 if (!apic_accept_pic_intr(cpu->apic_state)) { 176 return -1; 177 } 178 } 179 180 intno = pic_read_irq(isa_pic); 181 return intno; 182 } 183 184 static void pic_irq_request(void *opaque, int irq, int level) 185 { 186 CPUState *cs = first_cpu; 187 X86CPU *cpu = X86_CPU(cs); 188 189 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 190 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 191 CPU_FOREACH(cs) { 192 cpu = X86_CPU(cs); 193 if (apic_accept_pic_intr(cpu->apic_state)) { 194 apic_deliver_pic_intr(cpu->apic_state, level); 195 } 196 } 197 } else { 198 if (level) { 199 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 200 } else { 201 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 202 } 203 } 204 } 205 206 /* PC cmos mappings */ 207 208 #define REG_EQUIPMENT_BYTE 0x14 209 210 int cmos_get_fd_drive_type(FloppyDriveType fd0) 211 { 212 int val; 213 214 switch (fd0) { 215 case FLOPPY_DRIVE_TYPE_144: 216 /* 1.44 Mb 3"5 drive */ 217 val = 4; 218 break; 219 case FLOPPY_DRIVE_TYPE_288: 220 /* 2.88 Mb 3"5 drive */ 221 val = 5; 222 break; 223 case FLOPPY_DRIVE_TYPE_120: 224 /* 1.2 Mb 5"5 drive */ 225 val = 2; 226 break; 227 case FLOPPY_DRIVE_TYPE_NONE: 228 default: 229 val = 0; 230 break; 231 } 232 return val; 233 } 234 235 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 236 int16_t cylinders, int8_t heads, int8_t sectors) 237 { 238 rtc_set_memory(s, type_ofs, 47); 239 rtc_set_memory(s, info_ofs, cylinders); 240 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 241 rtc_set_memory(s, info_ofs + 2, heads); 242 rtc_set_memory(s, info_ofs + 3, 0xff); 243 rtc_set_memory(s, info_ofs + 4, 0xff); 244 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 245 rtc_set_memory(s, info_ofs + 6, cylinders); 246 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 247 rtc_set_memory(s, info_ofs + 8, sectors); 248 } 249 250 /* convert boot_device letter to something recognizable by the bios */ 251 static int boot_device2nibble(char boot_device) 252 { 253 switch(boot_device) { 254 case 'a': 255 case 'b': 256 return 0x01; /* floppy boot */ 257 case 'c': 258 return 0x02; /* hard drive boot */ 259 case 'd': 260 return 0x03; /* CD-ROM boot */ 261 case 'n': 262 return 0x04; /* Network boot */ 263 } 264 return 0; 265 } 266 267 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 268 { 269 #define PC_MAX_BOOT_DEVICES 3 270 int nbds, bds[3] = { 0, }; 271 int i; 272 273 nbds = strlen(boot_device); 274 if (nbds > PC_MAX_BOOT_DEVICES) { 275 error_setg(errp, "Too many boot devices for PC"); 276 return; 277 } 278 for (i = 0; i < nbds; i++) { 279 bds[i] = boot_device2nibble(boot_device[i]); 280 if (bds[i] == 0) { 281 error_setg(errp, "Invalid boot device for PC: '%c'", 282 boot_device[i]); 283 return; 284 } 285 } 286 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 287 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 288 } 289 290 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 291 { 292 set_boot_dev(opaque, boot_device, errp); 293 } 294 295 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 296 { 297 int val, nb, i; 298 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 299 FLOPPY_DRIVE_TYPE_NONE }; 300 301 /* floppy type */ 302 if (floppy) { 303 for (i = 0; i < 2; i++) { 304 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 305 } 306 } 307 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 308 cmos_get_fd_drive_type(fd_type[1]); 309 rtc_set_memory(rtc_state, 0x10, val); 310 311 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 312 nb = 0; 313 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 314 nb++; 315 } 316 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 317 nb++; 318 } 319 switch (nb) { 320 case 0: 321 break; 322 case 1: 323 val |= 0x01; /* 1 drive, ready for boot */ 324 break; 325 case 2: 326 val |= 0x41; /* 2 drives, ready for boot */ 327 break; 328 } 329 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 330 } 331 332 typedef struct pc_cmos_init_late_arg { 333 ISADevice *rtc_state; 334 BusState *idebus[2]; 335 } pc_cmos_init_late_arg; 336 337 typedef struct check_fdc_state { 338 ISADevice *floppy; 339 bool multiple; 340 } CheckFdcState; 341 342 static int check_fdc(Object *obj, void *opaque) 343 { 344 CheckFdcState *state = opaque; 345 Object *fdc; 346 uint32_t iobase; 347 Error *local_err = NULL; 348 349 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 350 if (!fdc) { 351 return 0; 352 } 353 354 iobase = object_property_get_uint(obj, "iobase", &local_err); 355 if (local_err || iobase != 0x3f0) { 356 error_free(local_err); 357 return 0; 358 } 359 360 if (state->floppy) { 361 state->multiple = true; 362 } else { 363 state->floppy = ISA_DEVICE(obj); 364 } 365 return 0; 366 } 367 368 static const char * const fdc_container_path[] = { 369 "/unattached", "/peripheral", "/peripheral-anon" 370 }; 371 372 /* 373 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 374 * and ACPI objects. 375 */ 376 ISADevice *pc_find_fdc0(void) 377 { 378 int i; 379 Object *container; 380 CheckFdcState state = { 0 }; 381 382 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 383 container = container_get(qdev_get_machine(), fdc_container_path[i]); 384 object_child_foreach(container, check_fdc, &state); 385 } 386 387 if (state.multiple) { 388 warn_report("multiple floppy disk controllers with " 389 "iobase=0x3f0 have been found"); 390 error_printf("the one being picked for CMOS setup might not reflect " 391 "your intent"); 392 } 393 394 return state.floppy; 395 } 396 397 static void pc_cmos_init_late(void *opaque) 398 { 399 pc_cmos_init_late_arg *arg = opaque; 400 ISADevice *s = arg->rtc_state; 401 int16_t cylinders; 402 int8_t heads, sectors; 403 int val; 404 int i, trans; 405 406 val = 0; 407 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 408 &cylinders, &heads, §ors) >= 0) { 409 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 410 val |= 0xf0; 411 } 412 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 413 &cylinders, &heads, §ors) >= 0) { 414 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 415 val |= 0x0f; 416 } 417 rtc_set_memory(s, 0x12, val); 418 419 val = 0; 420 for (i = 0; i < 4; i++) { 421 /* NOTE: ide_get_geometry() returns the physical 422 geometry. It is always such that: 1 <= sects <= 63, 1 423 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 424 geometry can be different if a translation is done. */ 425 if (arg->idebus[i / 2] && 426 ide_get_geometry(arg->idebus[i / 2], i % 2, 427 &cylinders, &heads, §ors) >= 0) { 428 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 429 assert((trans & ~3) == 0); 430 val |= trans << (i * 2); 431 } 432 } 433 rtc_set_memory(s, 0x39, val); 434 435 pc_cmos_init_floppy(s, pc_find_fdc0()); 436 437 qemu_unregister_reset(pc_cmos_init_late, opaque); 438 } 439 440 void pc_cmos_init(PCMachineState *pcms, 441 BusState *idebus0, BusState *idebus1, 442 ISADevice *s) 443 { 444 int val; 445 static pc_cmos_init_late_arg arg; 446 447 /* various important CMOS locations needed by PC/Bochs bios */ 448 449 /* memory size */ 450 /* base memory (first MiB) */ 451 val = MIN(pcms->below_4g_mem_size / 1024, 640); 452 rtc_set_memory(s, 0x15, val); 453 rtc_set_memory(s, 0x16, val >> 8); 454 /* extended memory (next 64MiB) */ 455 if (pcms->below_4g_mem_size > 1024 * 1024) { 456 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 457 } else { 458 val = 0; 459 } 460 if (val > 65535) 461 val = 65535; 462 rtc_set_memory(s, 0x17, val); 463 rtc_set_memory(s, 0x18, val >> 8); 464 rtc_set_memory(s, 0x30, val); 465 rtc_set_memory(s, 0x31, val >> 8); 466 /* memory between 16MiB and 4GiB */ 467 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 468 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 469 } else { 470 val = 0; 471 } 472 if (val > 65535) 473 val = 65535; 474 rtc_set_memory(s, 0x34, val); 475 rtc_set_memory(s, 0x35, val >> 8); 476 /* memory above 4GiB */ 477 val = pcms->above_4g_mem_size / 65536; 478 rtc_set_memory(s, 0x5b, val); 479 rtc_set_memory(s, 0x5c, val >> 8); 480 rtc_set_memory(s, 0x5d, val >> 16); 481 482 object_property_add_link(OBJECT(pcms), "rtc_state", 483 TYPE_ISA_DEVICE, 484 (Object **)&pcms->rtc, 485 object_property_allow_set_link, 486 OBJ_PROP_LINK_STRONG, &error_abort); 487 object_property_set_link(OBJECT(pcms), OBJECT(s), 488 "rtc_state", &error_abort); 489 490 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 491 492 val = 0; 493 val |= 0x02; /* FPU is there */ 494 val |= 0x04; /* PS/2 mouse installed */ 495 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 496 497 /* hard drives and FDC */ 498 arg.rtc_state = s; 499 arg.idebus[0] = idebus0; 500 arg.idebus[1] = idebus1; 501 qemu_register_reset(pc_cmos_init_late, &arg); 502 } 503 504 #define TYPE_PORT92 "port92" 505 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 506 507 /* port 92 stuff: could be split off */ 508 typedef struct Port92State { 509 ISADevice parent_obj; 510 511 MemoryRegion io; 512 uint8_t outport; 513 qemu_irq a20_out; 514 } Port92State; 515 516 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 517 unsigned size) 518 { 519 Port92State *s = opaque; 520 int oldval = s->outport; 521 522 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 523 s->outport = val; 524 qemu_set_irq(s->a20_out, (val >> 1) & 1); 525 if ((val & 1) && !(oldval & 1)) { 526 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 527 } 528 } 529 530 static uint64_t port92_read(void *opaque, hwaddr addr, 531 unsigned size) 532 { 533 Port92State *s = opaque; 534 uint32_t ret; 535 536 ret = s->outport; 537 DPRINTF("port92: read 0x%02x\n", ret); 538 return ret; 539 } 540 541 static void port92_init(ISADevice *dev, qemu_irq a20_out) 542 { 543 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 544 } 545 546 static const VMStateDescription vmstate_port92_isa = { 547 .name = "port92", 548 .version_id = 1, 549 .minimum_version_id = 1, 550 .fields = (VMStateField[]) { 551 VMSTATE_UINT8(outport, Port92State), 552 VMSTATE_END_OF_LIST() 553 } 554 }; 555 556 static void port92_reset(DeviceState *d) 557 { 558 Port92State *s = PORT92(d); 559 560 s->outport &= ~1; 561 } 562 563 static const MemoryRegionOps port92_ops = { 564 .read = port92_read, 565 .write = port92_write, 566 .impl = { 567 .min_access_size = 1, 568 .max_access_size = 1, 569 }, 570 .endianness = DEVICE_LITTLE_ENDIAN, 571 }; 572 573 static void port92_initfn(Object *obj) 574 { 575 Port92State *s = PORT92(obj); 576 577 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 578 579 s->outport = 0; 580 581 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 582 } 583 584 static void port92_realizefn(DeviceState *dev, Error **errp) 585 { 586 ISADevice *isadev = ISA_DEVICE(dev); 587 Port92State *s = PORT92(dev); 588 589 isa_register_ioport(isadev, &s->io, 0x92); 590 } 591 592 static void port92_class_initfn(ObjectClass *klass, void *data) 593 { 594 DeviceClass *dc = DEVICE_CLASS(klass); 595 596 dc->realize = port92_realizefn; 597 dc->reset = port92_reset; 598 dc->vmsd = &vmstate_port92_isa; 599 /* 600 * Reason: unlike ordinary ISA devices, this one needs additional 601 * wiring: its A20 output line needs to be wired up by 602 * port92_init(). 603 */ 604 dc->user_creatable = false; 605 } 606 607 static const TypeInfo port92_info = { 608 .name = TYPE_PORT92, 609 .parent = TYPE_ISA_DEVICE, 610 .instance_size = sizeof(Port92State), 611 .instance_init = port92_initfn, 612 .class_init = port92_class_initfn, 613 }; 614 615 static void port92_register_types(void) 616 { 617 type_register_static(&port92_info); 618 } 619 620 type_init(port92_register_types) 621 622 static void handle_a20_line_change(void *opaque, int irq, int level) 623 { 624 X86CPU *cpu = opaque; 625 626 /* XXX: send to all CPUs ? */ 627 /* XXX: add logic to handle multiple A20 line sources */ 628 x86_cpu_set_a20(cpu, level); 629 } 630 631 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 632 { 633 int index = le32_to_cpu(e820_reserve.count); 634 struct e820_entry *entry; 635 636 if (type != E820_RAM) { 637 /* old FW_CFG_E820_TABLE entry -- reservations only */ 638 if (index >= E820_NR_ENTRIES) { 639 return -EBUSY; 640 } 641 entry = &e820_reserve.entry[index++]; 642 643 entry->address = cpu_to_le64(address); 644 entry->length = cpu_to_le64(length); 645 entry->type = cpu_to_le32(type); 646 647 e820_reserve.count = cpu_to_le32(index); 648 } 649 650 /* new "etc/e820" file -- include ram too */ 651 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 652 e820_table[e820_entries].address = cpu_to_le64(address); 653 e820_table[e820_entries].length = cpu_to_le64(length); 654 e820_table[e820_entries].type = cpu_to_le32(type); 655 e820_entries++; 656 657 return e820_entries; 658 } 659 660 int e820_get_num_entries(void) 661 { 662 return e820_entries; 663 } 664 665 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 666 { 667 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 668 *address = le64_to_cpu(e820_table[idx].address); 669 *length = le64_to_cpu(e820_table[idx].length); 670 return true; 671 } 672 return false; 673 } 674 675 /* Enables contiguous-apic-ID mode, for compatibility */ 676 static bool compat_apic_id_mode; 677 678 void enable_compat_apic_id_mode(void) 679 { 680 compat_apic_id_mode = true; 681 } 682 683 /* Calculates initial APIC ID for a specific CPU index 684 * 685 * Currently we need to be able to calculate the APIC ID from the CPU index 686 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 687 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 688 * all CPUs up to max_cpus. 689 */ 690 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 691 { 692 uint32_t correct_id; 693 static bool warned; 694 695 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 696 if (compat_apic_id_mode) { 697 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 698 error_report("APIC IDs set in compatibility mode, " 699 "CPU topology won't match the configuration"); 700 warned = true; 701 } 702 return cpu_index; 703 } else { 704 return correct_id; 705 } 706 } 707 708 static void pc_build_smbios(PCMachineState *pcms) 709 { 710 uint8_t *smbios_tables, *smbios_anchor; 711 size_t smbios_tables_len, smbios_anchor_len; 712 struct smbios_phys_mem_area *mem_array; 713 unsigned i, array_count; 714 MachineState *ms = MACHINE(pcms); 715 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 716 717 /* tell smbios about cpuid version and features */ 718 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 719 720 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 721 if (smbios_tables) { 722 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 723 smbios_tables, smbios_tables_len); 724 } 725 726 /* build the array of physical mem area from e820 table */ 727 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 728 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 729 uint64_t addr, len; 730 731 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 732 mem_array[array_count].address = addr; 733 mem_array[array_count].length = len; 734 array_count++; 735 } 736 } 737 smbios_get_tables(mem_array, array_count, 738 &smbios_tables, &smbios_tables_len, 739 &smbios_anchor, &smbios_anchor_len); 740 g_free(mem_array); 741 742 if (smbios_anchor) { 743 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 744 smbios_tables, smbios_tables_len); 745 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 746 smbios_anchor, smbios_anchor_len); 747 } 748 } 749 750 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 751 { 752 FWCfgState *fw_cfg; 753 uint64_t *numa_fw_cfg; 754 int i; 755 const CPUArchIdList *cpus; 756 MachineClass *mc = MACHINE_GET_CLASS(pcms); 757 758 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 759 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 760 761 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 762 * 763 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 764 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 765 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 766 * for CPU hotplug also uses APIC ID and not "CPU index". 767 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 768 * but the "limit to the APIC ID values SeaBIOS may see". 769 * 770 * So for compatibility reasons with old BIOSes we are stuck with 771 * "etc/max-cpus" actually being apic_id_limit 772 */ 773 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 774 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 775 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 776 acpi_tables, acpi_tables_len); 777 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 778 779 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 780 &e820_reserve, sizeof(e820_reserve)); 781 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 782 sizeof(struct e820_entry) * e820_entries); 783 784 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 785 /* allocate memory for the NUMA channel: one (64bit) word for the number 786 * of nodes, one word for each VCPU->node and one word for each node to 787 * hold the amount of memory. 788 */ 789 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 790 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 791 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 792 for (i = 0; i < cpus->len; i++) { 793 unsigned int apic_id = cpus->cpus[i].arch_id; 794 assert(apic_id < pcms->apic_id_limit); 795 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 796 } 797 for (i = 0; i < nb_numa_nodes; i++) { 798 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 799 cpu_to_le64(numa_info[i].node_mem); 800 } 801 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 802 (1 + pcms->apic_id_limit + nb_numa_nodes) * 803 sizeof(*numa_fw_cfg)); 804 805 return fw_cfg; 806 } 807 808 static long get_file_size(FILE *f) 809 { 810 long where, size; 811 812 /* XXX: on Unix systems, using fstat() probably makes more sense */ 813 814 where = ftell(f); 815 fseek(f, 0, SEEK_END); 816 size = ftell(f); 817 fseek(f, where, SEEK_SET); 818 819 return size; 820 } 821 822 /* setup_data types */ 823 #define SETUP_NONE 0 824 #define SETUP_E820_EXT 1 825 #define SETUP_DTB 2 826 #define SETUP_PCI 3 827 #define SETUP_EFI 4 828 829 struct setup_data { 830 uint64_t next; 831 uint32_t type; 832 uint32_t len; 833 uint8_t data[0]; 834 } __attribute__((packed)); 835 836 static void load_linux(PCMachineState *pcms, 837 FWCfgState *fw_cfg) 838 { 839 uint16_t protocol; 840 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 841 int dtb_size, setup_data_offset; 842 uint32_t initrd_max; 843 uint8_t header[8192], *setup, *kernel, *initrd_data; 844 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 845 FILE *f; 846 char *vmode; 847 MachineState *machine = MACHINE(pcms); 848 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 849 struct setup_data *setup_data; 850 const char *kernel_filename = machine->kernel_filename; 851 const char *initrd_filename = machine->initrd_filename; 852 const char *dtb_filename = machine->dtb; 853 const char *kernel_cmdline = machine->kernel_cmdline; 854 855 /* Align to 16 bytes as a paranoia measure */ 856 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 857 858 /* load the kernel header */ 859 f = fopen(kernel_filename, "rb"); 860 if (!f || !(kernel_size = get_file_size(f)) || 861 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 862 MIN(ARRAY_SIZE(header), kernel_size)) { 863 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 864 kernel_filename, strerror(errno)); 865 exit(1); 866 } 867 868 /* kernel protocol version */ 869 #if 0 870 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 871 #endif 872 if (ldl_p(header+0x202) == 0x53726448) { 873 protocol = lduw_p(header+0x206); 874 } else { 875 /* This looks like a multiboot kernel. If it is, let's stop 876 treating it like a Linux kernel. */ 877 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 878 kernel_cmdline, kernel_size, header)) { 879 return; 880 } 881 protocol = 0; 882 } 883 884 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 885 /* Low kernel */ 886 real_addr = 0x90000; 887 cmdline_addr = 0x9a000 - cmdline_size; 888 prot_addr = 0x10000; 889 } else if (protocol < 0x202) { 890 /* High but ancient kernel */ 891 real_addr = 0x90000; 892 cmdline_addr = 0x9a000 - cmdline_size; 893 prot_addr = 0x100000; 894 } else { 895 /* High and recent kernel */ 896 real_addr = 0x10000; 897 cmdline_addr = 0x20000; 898 prot_addr = 0x100000; 899 } 900 901 #if 0 902 fprintf(stderr, 903 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 904 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 905 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 906 real_addr, 907 cmdline_addr, 908 prot_addr); 909 #endif 910 911 /* highest address for loading the initrd */ 912 if (protocol >= 0x203) { 913 initrd_max = ldl_p(header+0x22c); 914 } else { 915 initrd_max = 0x37ffffff; 916 } 917 918 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 919 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 920 } 921 922 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 923 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 924 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 925 926 if (protocol >= 0x202) { 927 stl_p(header+0x228, cmdline_addr); 928 } else { 929 stw_p(header+0x20, 0xA33F); 930 stw_p(header+0x22, cmdline_addr-real_addr); 931 } 932 933 /* handle vga= parameter */ 934 vmode = strstr(kernel_cmdline, "vga="); 935 if (vmode) { 936 unsigned int video_mode; 937 /* skip "vga=" */ 938 vmode += 4; 939 if (!strncmp(vmode, "normal", 6)) { 940 video_mode = 0xffff; 941 } else if (!strncmp(vmode, "ext", 3)) { 942 video_mode = 0xfffe; 943 } else if (!strncmp(vmode, "ask", 3)) { 944 video_mode = 0xfffd; 945 } else { 946 video_mode = strtol(vmode, NULL, 0); 947 } 948 stw_p(header+0x1fa, video_mode); 949 } 950 951 /* loader type */ 952 /* High nybble = B reserved for QEMU; low nybble is revision number. 953 If this code is substantially changed, you may want to consider 954 incrementing the revision. */ 955 if (protocol >= 0x200) { 956 header[0x210] = 0xB0; 957 } 958 /* heap */ 959 if (protocol >= 0x201) { 960 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 961 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 962 } 963 964 /* load initrd */ 965 if (initrd_filename) { 966 if (protocol < 0x200) { 967 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 968 exit(1); 969 } 970 971 initrd_size = get_image_size(initrd_filename); 972 if (initrd_size < 0) { 973 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 974 initrd_filename, strerror(errno)); 975 exit(1); 976 } 977 978 initrd_addr = (initrd_max-initrd_size) & ~4095; 979 980 initrd_data = g_malloc(initrd_size); 981 load_image(initrd_filename, initrd_data); 982 983 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 984 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 985 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 986 987 stl_p(header+0x218, initrd_addr); 988 stl_p(header+0x21c, initrd_size); 989 } 990 991 /* load kernel and setup */ 992 setup_size = header[0x1f1]; 993 if (setup_size == 0) { 994 setup_size = 4; 995 } 996 setup_size = (setup_size+1)*512; 997 if (setup_size > kernel_size) { 998 fprintf(stderr, "qemu: invalid kernel header\n"); 999 exit(1); 1000 } 1001 kernel_size -= setup_size; 1002 1003 setup = g_malloc(setup_size); 1004 kernel = g_malloc(kernel_size); 1005 fseek(f, 0, SEEK_SET); 1006 if (fread(setup, 1, setup_size, f) != setup_size) { 1007 fprintf(stderr, "fread() failed\n"); 1008 exit(1); 1009 } 1010 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1011 fprintf(stderr, "fread() failed\n"); 1012 exit(1); 1013 } 1014 fclose(f); 1015 1016 /* append dtb to kernel */ 1017 if (dtb_filename) { 1018 if (protocol < 0x209) { 1019 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1020 exit(1); 1021 } 1022 1023 dtb_size = get_image_size(dtb_filename); 1024 if (dtb_size <= 0) { 1025 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1026 dtb_filename, strerror(errno)); 1027 exit(1); 1028 } 1029 1030 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1031 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1032 kernel = g_realloc(kernel, kernel_size); 1033 1034 stq_p(header+0x250, prot_addr + setup_data_offset); 1035 1036 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1037 setup_data->next = 0; 1038 setup_data->type = cpu_to_le32(SETUP_DTB); 1039 setup_data->len = cpu_to_le32(dtb_size); 1040 1041 load_image_size(dtb_filename, setup_data->data, dtb_size); 1042 } 1043 1044 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1045 1046 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1047 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1048 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1049 1050 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1051 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1052 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1053 1054 option_rom[nb_option_roms].bootindex = 0; 1055 option_rom[nb_option_roms].name = "linuxboot.bin"; 1056 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1057 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1058 } 1059 nb_option_roms++; 1060 } 1061 1062 #define NE2000_NB_MAX 6 1063 1064 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1065 0x280, 0x380 }; 1066 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1067 1068 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1069 { 1070 static int nb_ne2k = 0; 1071 1072 if (nb_ne2k == NE2000_NB_MAX) 1073 return; 1074 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1075 ne2000_irq[nb_ne2k], nd); 1076 nb_ne2k++; 1077 } 1078 1079 DeviceState *cpu_get_current_apic(void) 1080 { 1081 if (current_cpu) { 1082 X86CPU *cpu = X86_CPU(current_cpu); 1083 return cpu->apic_state; 1084 } else { 1085 return NULL; 1086 } 1087 } 1088 1089 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1090 { 1091 X86CPU *cpu = opaque; 1092 1093 if (level) { 1094 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1095 } 1096 } 1097 1098 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) 1099 { 1100 Object *cpu = NULL; 1101 Error *local_err = NULL; 1102 1103 cpu = object_new(typename); 1104 1105 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1106 object_property_set_bool(cpu, true, "realized", &local_err); 1107 1108 object_unref(cpu); 1109 error_propagate(errp, local_err); 1110 } 1111 1112 void pc_hot_add_cpu(const int64_t id, Error **errp) 1113 { 1114 MachineState *ms = MACHINE(qdev_get_machine()); 1115 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1116 Error *local_err = NULL; 1117 1118 if (id < 0) { 1119 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1120 return; 1121 } 1122 1123 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1124 error_setg(errp, "Unable to add CPU: %" PRIi64 1125 ", resulting APIC ID (%" PRIi64 ") is too large", 1126 id, apic_id); 1127 return; 1128 } 1129 1130 pc_new_cpu(ms->cpu_type, apic_id, &local_err); 1131 if (local_err) { 1132 error_propagate(errp, local_err); 1133 return; 1134 } 1135 } 1136 1137 void pc_cpus_init(PCMachineState *pcms) 1138 { 1139 int i; 1140 const CPUArchIdList *possible_cpus; 1141 MachineState *ms = MACHINE(pcms); 1142 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1143 1144 /* Calculates the limit to CPU APIC ID values 1145 * 1146 * Limit for the APIC ID value, so that all 1147 * CPU APIC IDs are < pcms->apic_id_limit. 1148 * 1149 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1150 */ 1151 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1152 possible_cpus = mc->possible_cpu_arch_ids(ms); 1153 for (i = 0; i < smp_cpus; i++) { 1154 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, 1155 &error_fatal); 1156 } 1157 } 1158 1159 static void pc_build_feature_control_file(PCMachineState *pcms) 1160 { 1161 MachineState *ms = MACHINE(pcms); 1162 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1163 CPUX86State *env = &cpu->env; 1164 uint32_t unused, ecx, edx; 1165 uint64_t feature_control_bits = 0; 1166 uint64_t *val; 1167 1168 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1169 if (ecx & CPUID_EXT_VMX) { 1170 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1171 } 1172 1173 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1174 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1175 (env->mcg_cap & MCG_LMCE_P)) { 1176 feature_control_bits |= FEATURE_CONTROL_LMCE; 1177 } 1178 1179 if (!feature_control_bits) { 1180 return; 1181 } 1182 1183 val = g_malloc(sizeof(*val)); 1184 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1185 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1186 } 1187 1188 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1189 { 1190 if (cpus_count > 0xff) { 1191 /* If the number of CPUs can't be represented in 8 bits, the 1192 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1193 * to make old BIOSes fail more predictably. 1194 */ 1195 rtc_set_memory(rtc, 0x5f, 0); 1196 } else { 1197 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1198 } 1199 } 1200 1201 static 1202 void pc_machine_done(Notifier *notifier, void *data) 1203 { 1204 PCMachineState *pcms = container_of(notifier, 1205 PCMachineState, machine_done); 1206 PCIBus *bus = pcms->bus; 1207 1208 /* set the number of CPUs */ 1209 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1210 1211 if (bus) { 1212 int extra_hosts = 0; 1213 1214 QLIST_FOREACH(bus, &bus->child, sibling) { 1215 /* look for expander root buses */ 1216 if (pci_bus_is_root(bus)) { 1217 extra_hosts++; 1218 } 1219 } 1220 if (extra_hosts && pcms->fw_cfg) { 1221 uint64_t *val = g_malloc(sizeof(*val)); 1222 *val = cpu_to_le64(extra_hosts); 1223 fw_cfg_add_file(pcms->fw_cfg, 1224 "etc/extra-pci-roots", val, sizeof(*val)); 1225 } 1226 } 1227 1228 acpi_setup(); 1229 if (pcms->fw_cfg) { 1230 pc_build_smbios(pcms); 1231 pc_build_feature_control_file(pcms); 1232 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1233 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1234 } 1235 1236 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1237 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1238 1239 if (!iommu || !iommu->x86_iommu.intr_supported || 1240 iommu->intr_eim != ON_OFF_AUTO_ON) { 1241 error_report("current -smp configuration requires " 1242 "Extended Interrupt Mode enabled. " 1243 "You can add an IOMMU using: " 1244 "-device intel-iommu,intremap=on,eim=on"); 1245 exit(EXIT_FAILURE); 1246 } 1247 } 1248 } 1249 1250 void pc_guest_info_init(PCMachineState *pcms) 1251 { 1252 int i; 1253 1254 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1255 pcms->numa_nodes = nb_numa_nodes; 1256 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1257 sizeof *pcms->node_mem); 1258 for (i = 0; i < nb_numa_nodes; i++) { 1259 pcms->node_mem[i] = numa_info[i].node_mem; 1260 } 1261 1262 pcms->machine_done.notify = pc_machine_done; 1263 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1264 } 1265 1266 /* setup pci memory address space mapping into system address space */ 1267 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1268 MemoryRegion *pci_address_space) 1269 { 1270 /* Set to lower priority than RAM */ 1271 memory_region_add_subregion_overlap(system_memory, 0x0, 1272 pci_address_space, -1); 1273 } 1274 1275 void pc_acpi_init(const char *default_dsdt) 1276 { 1277 char *filename; 1278 1279 if (acpi_tables != NULL) { 1280 /* manually set via -acpitable, leave it alone */ 1281 return; 1282 } 1283 1284 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1285 if (filename == NULL) { 1286 warn_report("failed to find %s", default_dsdt); 1287 } else { 1288 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1289 &error_abort); 1290 Error *err = NULL; 1291 1292 qemu_opt_set(opts, "file", filename, &error_abort); 1293 1294 acpi_table_add_builtin(opts, &err); 1295 if (err) { 1296 warn_reportf_err(err, "failed to load %s: ", filename); 1297 } 1298 g_free(filename); 1299 } 1300 } 1301 1302 void xen_load_linux(PCMachineState *pcms) 1303 { 1304 int i; 1305 FWCfgState *fw_cfg; 1306 1307 assert(MACHINE(pcms)->kernel_filename != NULL); 1308 1309 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1310 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1311 rom_set_fw(fw_cfg); 1312 1313 load_linux(pcms, fw_cfg); 1314 for (i = 0; i < nb_option_roms; i++) { 1315 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1316 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1317 !strcmp(option_rom[i].name, "multiboot.bin")); 1318 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1319 } 1320 pcms->fw_cfg = fw_cfg; 1321 } 1322 1323 void pc_memory_init(PCMachineState *pcms, 1324 MemoryRegion *system_memory, 1325 MemoryRegion *rom_memory, 1326 MemoryRegion **ram_memory) 1327 { 1328 int linux_boot, i; 1329 MemoryRegion *ram, *option_rom_mr; 1330 MemoryRegion *ram_below_4g, *ram_above_4g; 1331 FWCfgState *fw_cfg; 1332 MachineState *machine = MACHINE(pcms); 1333 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1334 1335 assert(machine->ram_size == pcms->below_4g_mem_size + 1336 pcms->above_4g_mem_size); 1337 1338 linux_boot = (machine->kernel_filename != NULL); 1339 1340 /* Allocate RAM. We allocate it as a single memory region and use 1341 * aliases to address portions of it, mostly for backwards compatibility 1342 * with older qemus that used qemu_ram_alloc(). 1343 */ 1344 ram = g_malloc(sizeof(*ram)); 1345 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1346 machine->ram_size); 1347 *ram_memory = ram; 1348 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1349 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1350 0, pcms->below_4g_mem_size); 1351 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1352 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1353 if (pcms->above_4g_mem_size > 0) { 1354 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1355 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1356 pcms->below_4g_mem_size, 1357 pcms->above_4g_mem_size); 1358 memory_region_add_subregion(system_memory, 0x100000000ULL, 1359 ram_above_4g); 1360 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1361 } 1362 1363 if (!pcmc->has_reserved_memory && 1364 (machine->ram_slots || 1365 (machine->maxram_size > machine->ram_size))) { 1366 MachineClass *mc = MACHINE_GET_CLASS(machine); 1367 1368 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1369 mc->name); 1370 exit(EXIT_FAILURE); 1371 } 1372 1373 /* always allocate the device memory information */ 1374 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1375 1376 /* initialize device memory address space */ 1377 if (pcmc->has_reserved_memory && 1378 (machine->ram_size < machine->maxram_size)) { 1379 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1380 1381 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1382 error_report("unsupported amount of memory slots: %"PRIu64, 1383 machine->ram_slots); 1384 exit(EXIT_FAILURE); 1385 } 1386 1387 if (QEMU_ALIGN_UP(machine->maxram_size, 1388 TARGET_PAGE_SIZE) != machine->maxram_size) { 1389 error_report("maximum memory size must by aligned to multiple of " 1390 "%d bytes", TARGET_PAGE_SIZE); 1391 exit(EXIT_FAILURE); 1392 } 1393 1394 machine->device_memory->base = 1395 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1396 1397 if (pcmc->enforce_aligned_dimm) { 1398 /* size device region assuming 1G page max alignment per slot */ 1399 device_mem_size += (1ULL << 30) * machine->ram_slots; 1400 } 1401 1402 if ((machine->device_memory->base + device_mem_size) < 1403 device_mem_size) { 1404 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1405 machine->maxram_size); 1406 exit(EXIT_FAILURE); 1407 } 1408 1409 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1410 "device-memory", device_mem_size); 1411 memory_region_add_subregion(system_memory, machine->device_memory->base, 1412 &machine->device_memory->mr); 1413 } 1414 1415 /* Initialize PC system firmware */ 1416 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1417 1418 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1419 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1420 &error_fatal); 1421 if (pcmc->pci_enabled) { 1422 memory_region_set_readonly(option_rom_mr, true); 1423 } 1424 memory_region_add_subregion_overlap(rom_memory, 1425 PC_ROM_MIN_VGA, 1426 option_rom_mr, 1427 1); 1428 1429 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1430 1431 rom_set_fw(fw_cfg); 1432 1433 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1434 uint64_t *val = g_malloc(sizeof(*val)); 1435 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1436 uint64_t res_mem_end = machine->device_memory->base; 1437 1438 if (!pcmc->broken_reserved_end) { 1439 res_mem_end += memory_region_size(&machine->device_memory->mr); 1440 } 1441 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1442 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1443 } 1444 1445 if (linux_boot) { 1446 load_linux(pcms, fw_cfg); 1447 } 1448 1449 for (i = 0; i < nb_option_roms; i++) { 1450 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1451 } 1452 pcms->fw_cfg = fw_cfg; 1453 1454 /* Init default IOAPIC address space */ 1455 pcms->ioapic_as = &address_space_memory; 1456 } 1457 1458 /* 1459 * The 64bit pci hole starts after "above 4G RAM" and 1460 * potentially the space reserved for memory hotplug. 1461 */ 1462 uint64_t pc_pci_hole64_start(void) 1463 { 1464 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1465 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1466 MachineState *ms = MACHINE(pcms); 1467 uint64_t hole64_start = 0; 1468 1469 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1470 hole64_start = ms->device_memory->base; 1471 if (!pcmc->broken_reserved_end) { 1472 hole64_start += memory_region_size(&ms->device_memory->mr); 1473 } 1474 } else { 1475 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1476 } 1477 1478 return ROUND_UP(hole64_start, 1ULL << 30); 1479 } 1480 1481 qemu_irq pc_allocate_cpu_irq(void) 1482 { 1483 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1484 } 1485 1486 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1487 { 1488 DeviceState *dev = NULL; 1489 1490 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1491 if (pci_bus) { 1492 PCIDevice *pcidev = pci_vga_init(pci_bus); 1493 dev = pcidev ? &pcidev->qdev : NULL; 1494 } else if (isa_bus) { 1495 ISADevice *isadev = isa_vga_init(isa_bus); 1496 dev = isadev ? DEVICE(isadev) : NULL; 1497 } 1498 rom_reset_order_override(); 1499 return dev; 1500 } 1501 1502 static const MemoryRegionOps ioport80_io_ops = { 1503 .write = ioport80_write, 1504 .read = ioport80_read, 1505 .endianness = DEVICE_NATIVE_ENDIAN, 1506 .impl = { 1507 .min_access_size = 1, 1508 .max_access_size = 1, 1509 }, 1510 }; 1511 1512 static const MemoryRegionOps ioportF0_io_ops = { 1513 .write = ioportF0_write, 1514 .read = ioportF0_read, 1515 .endianness = DEVICE_NATIVE_ENDIAN, 1516 .impl = { 1517 .min_access_size = 1, 1518 .max_access_size = 1, 1519 }, 1520 }; 1521 1522 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1523 { 1524 int i; 1525 DriveInfo *fd[MAX_FD]; 1526 qemu_irq *a20_line; 1527 ISADevice *i8042, *port92, *vmmouse; 1528 1529 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1530 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1531 1532 for (i = 0; i < MAX_FD; i++) { 1533 fd[i] = drive_get(IF_FLOPPY, 0, i); 1534 create_fdctrl |= !!fd[i]; 1535 } 1536 if (create_fdctrl) { 1537 fdctrl_init_isa(isa_bus, fd); 1538 } 1539 1540 i8042 = isa_create_simple(isa_bus, "i8042"); 1541 if (!no_vmport) { 1542 vmport_init(isa_bus); 1543 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1544 } else { 1545 vmmouse = NULL; 1546 } 1547 if (vmmouse) { 1548 DeviceState *dev = DEVICE(vmmouse); 1549 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1550 qdev_init_nofail(dev); 1551 } 1552 port92 = isa_create_simple(isa_bus, "port92"); 1553 1554 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1555 i8042_setup_a20_line(i8042, a20_line[0]); 1556 port92_init(port92, a20_line[1]); 1557 g_free(a20_line); 1558 } 1559 1560 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1561 ISADevice **rtc_state, 1562 bool create_fdctrl, 1563 bool no_vmport, 1564 bool has_pit, 1565 uint32_t hpet_irqs) 1566 { 1567 int i; 1568 DeviceState *hpet = NULL; 1569 int pit_isa_irq = 0; 1570 qemu_irq pit_alt_irq = NULL; 1571 qemu_irq rtc_irq = NULL; 1572 ISADevice *pit = NULL; 1573 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1574 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1575 1576 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1577 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1578 1579 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1580 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1581 1582 /* 1583 * Check if an HPET shall be created. 1584 * 1585 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1586 * when the HPET wants to take over. Thus we have to disable the latter. 1587 */ 1588 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1589 /* In order to set property, here not using sysbus_try_create_simple */ 1590 hpet = qdev_try_create(NULL, TYPE_HPET); 1591 if (hpet) { 1592 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1593 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1594 * IRQ8 and IRQ2. 1595 */ 1596 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1597 HPET_INTCAP, NULL); 1598 if (!compat) { 1599 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1600 } 1601 qdev_init_nofail(hpet); 1602 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1603 1604 for (i = 0; i < GSI_NUM_PINS; i++) { 1605 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1606 } 1607 pit_isa_irq = -1; 1608 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1609 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1610 } 1611 } 1612 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1613 1614 qemu_register_boot_set(pc_boot_set, *rtc_state); 1615 1616 if (!xen_enabled() && has_pit) { 1617 if (kvm_pit_in_kernel()) { 1618 pit = kvm_pit_init(isa_bus, 0x40); 1619 } else { 1620 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1621 } 1622 if (hpet) { 1623 /* connect PIT to output control line of the HPET */ 1624 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1625 } 1626 pcspk_init(isa_bus, pit); 1627 } 1628 1629 i8257_dma_init(isa_bus, 0); 1630 1631 /* Super I/O */ 1632 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 1633 } 1634 1635 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1636 { 1637 int i; 1638 1639 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1640 for (i = 0; i < nb_nics; i++) { 1641 NICInfo *nd = &nd_table[i]; 1642 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1643 1644 if (g_str_equal(model, "ne2k_isa")) { 1645 pc_init_ne2k_isa(isa_bus, nd); 1646 } else { 1647 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1648 } 1649 } 1650 rom_reset_order_override(); 1651 } 1652 1653 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1654 { 1655 DeviceState *dev; 1656 SysBusDevice *d; 1657 unsigned int i; 1658 1659 if (kvm_ioapic_in_kernel()) { 1660 dev = qdev_create(NULL, "kvm-ioapic"); 1661 } else { 1662 dev = qdev_create(NULL, "ioapic"); 1663 } 1664 if (parent_name) { 1665 object_property_add_child(object_resolve_path(parent_name, NULL), 1666 "ioapic", OBJECT(dev), NULL); 1667 } 1668 qdev_init_nofail(dev); 1669 d = SYS_BUS_DEVICE(dev); 1670 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1671 1672 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1673 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1674 } 1675 } 1676 1677 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1678 Error **errp) 1679 { 1680 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1681 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1682 1683 /* 1684 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1685 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1686 * addition to cover this case. 1687 */ 1688 if (!pcms->acpi_dev || !acpi_enabled) { 1689 error_setg(errp, 1690 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1691 return; 1692 } 1693 1694 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) { 1695 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1696 return; 1697 } 1698 } 1699 1700 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1701 DeviceState *dev, Error **errp) 1702 { 1703 HotplugHandlerClass *hhc; 1704 Error *local_err = NULL; 1705 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1706 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1707 PCDIMMDevice *dimm = PC_DIMM(dev); 1708 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1709 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 1710 uint64_t align = TARGET_PAGE_SIZE; 1711 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1712 1713 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1714 align = memory_region_get_alignment(mr); 1715 } 1716 1717 pc_dimm_plug(dev, MACHINE(pcms), align, &local_err); 1718 if (local_err) { 1719 goto out; 1720 } 1721 1722 if (is_nvdimm) { 1723 nvdimm_plug(&pcms->acpi_nvdimm_state); 1724 } 1725 1726 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1727 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1728 out: 1729 error_propagate(errp, local_err); 1730 } 1731 1732 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1733 DeviceState *dev, Error **errp) 1734 { 1735 HotplugHandlerClass *hhc; 1736 Error *local_err = NULL; 1737 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1738 1739 /* 1740 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1741 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1742 * addition to cover this case. 1743 */ 1744 if (!pcms->acpi_dev || !acpi_enabled) { 1745 error_setg(&local_err, 1746 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1747 goto out; 1748 } 1749 1750 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1751 error_setg(&local_err, 1752 "nvdimm device hot unplug is not supported yet."); 1753 goto out; 1754 } 1755 1756 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1757 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1758 1759 out: 1760 error_propagate(errp, local_err); 1761 } 1762 1763 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1764 DeviceState *dev, Error **errp) 1765 { 1766 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1767 HotplugHandlerClass *hhc; 1768 Error *local_err = NULL; 1769 1770 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1771 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1772 1773 if (local_err) { 1774 goto out; 1775 } 1776 1777 pc_dimm_unplug(dev, MACHINE(pcms)); 1778 object_unparent(OBJECT(dev)); 1779 1780 out: 1781 error_propagate(errp, local_err); 1782 } 1783 1784 static int pc_apic_cmp(const void *a, const void *b) 1785 { 1786 CPUArchId *apic_a = (CPUArchId *)a; 1787 CPUArchId *apic_b = (CPUArchId *)b; 1788 1789 return apic_a->arch_id - apic_b->arch_id; 1790 } 1791 1792 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 1793 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 1794 * entry corresponding to CPU's apic_id returns NULL. 1795 */ 1796 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1797 { 1798 CPUArchId apic_id, *found_cpu; 1799 1800 apic_id.arch_id = id; 1801 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 1802 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 1803 pc_apic_cmp); 1804 if (found_cpu && idx) { 1805 *idx = found_cpu - ms->possible_cpus->cpus; 1806 } 1807 return found_cpu; 1808 } 1809 1810 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1811 DeviceState *dev, Error **errp) 1812 { 1813 CPUArchId *found_cpu; 1814 HotplugHandlerClass *hhc; 1815 Error *local_err = NULL; 1816 X86CPU *cpu = X86_CPU(dev); 1817 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1818 1819 if (pcms->acpi_dev) { 1820 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1821 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1822 if (local_err) { 1823 goto out; 1824 } 1825 } 1826 1827 /* increment the number of CPUs */ 1828 pcms->boot_cpus++; 1829 if (pcms->rtc) { 1830 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1831 } 1832 if (pcms->fw_cfg) { 1833 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1834 } 1835 1836 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1837 found_cpu->cpu = OBJECT(dev); 1838 out: 1839 error_propagate(errp, local_err); 1840 } 1841 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 1842 DeviceState *dev, Error **errp) 1843 { 1844 int idx = -1; 1845 HotplugHandlerClass *hhc; 1846 Error *local_err = NULL; 1847 X86CPU *cpu = X86_CPU(dev); 1848 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1849 1850 if (!pcms->acpi_dev) { 1851 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 1852 goto out; 1853 } 1854 1855 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1856 assert(idx != -1); 1857 if (idx == 0) { 1858 error_setg(&local_err, "Boot CPU is unpluggable"); 1859 goto out; 1860 } 1861 1862 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1863 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1864 1865 if (local_err) { 1866 goto out; 1867 } 1868 1869 out: 1870 error_propagate(errp, local_err); 1871 1872 } 1873 1874 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 1875 DeviceState *dev, Error **errp) 1876 { 1877 CPUArchId *found_cpu; 1878 HotplugHandlerClass *hhc; 1879 Error *local_err = NULL; 1880 X86CPU *cpu = X86_CPU(dev); 1881 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1882 1883 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1884 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1885 1886 if (local_err) { 1887 goto out; 1888 } 1889 1890 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 1891 found_cpu->cpu = NULL; 1892 object_unparent(OBJECT(dev)); 1893 1894 /* decrement the number of CPUs */ 1895 pcms->boot_cpus--; 1896 /* Update the number of CPUs in CMOS */ 1897 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1898 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1899 out: 1900 error_propagate(errp, local_err); 1901 } 1902 1903 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 1904 DeviceState *dev, Error **errp) 1905 { 1906 int idx; 1907 CPUState *cs; 1908 CPUArchId *cpu_slot; 1909 X86CPUTopoInfo topo; 1910 X86CPU *cpu = X86_CPU(dev); 1911 MachineState *ms = MACHINE(hotplug_dev); 1912 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1913 1914 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 1915 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 1916 ms->cpu_type); 1917 return; 1918 } 1919 1920 /* if APIC ID is not set, set it based on socket/core/thread properties */ 1921 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 1922 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 1923 1924 if (cpu->socket_id < 0) { 1925 error_setg(errp, "CPU socket-id is not set"); 1926 return; 1927 } else if (cpu->socket_id > max_socket) { 1928 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 1929 cpu->socket_id, max_socket); 1930 return; 1931 } 1932 if (cpu->core_id < 0) { 1933 error_setg(errp, "CPU core-id is not set"); 1934 return; 1935 } else if (cpu->core_id > (smp_cores - 1)) { 1936 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 1937 cpu->core_id, smp_cores - 1); 1938 return; 1939 } 1940 if (cpu->thread_id < 0) { 1941 error_setg(errp, "CPU thread-id is not set"); 1942 return; 1943 } else if (cpu->thread_id > (smp_threads - 1)) { 1944 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 1945 cpu->thread_id, smp_threads - 1); 1946 return; 1947 } 1948 1949 topo.pkg_id = cpu->socket_id; 1950 topo.core_id = cpu->core_id; 1951 topo.smt_id = cpu->thread_id; 1952 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 1953 } 1954 1955 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 1956 if (!cpu_slot) { 1957 MachineState *ms = MACHINE(pcms); 1958 1959 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1960 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 1961 " APIC ID %" PRIu32 ", valid index range 0:%d", 1962 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 1963 ms->possible_cpus->len - 1); 1964 return; 1965 } 1966 1967 if (cpu_slot->cpu) { 1968 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 1969 idx, cpu->apic_id); 1970 return; 1971 } 1972 1973 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 1974 * so that machine_query_hotpluggable_cpus would show correct values 1975 */ 1976 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 1977 * once -smp refactoring is complete and there will be CPU private 1978 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 1979 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 1980 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 1981 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 1982 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 1983 return; 1984 } 1985 cpu->socket_id = topo.pkg_id; 1986 1987 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 1988 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 1989 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 1990 return; 1991 } 1992 cpu->core_id = topo.core_id; 1993 1994 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 1995 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 1996 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 1997 return; 1998 } 1999 cpu->thread_id = topo.smt_id; 2000 2001 cs = CPU(cpu); 2002 cs->cpu_index = idx; 2003 2004 numa_cpu_pre_plug(cpu_slot, dev, errp); 2005 } 2006 2007 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2008 DeviceState *dev, Error **errp) 2009 { 2010 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2011 pc_memory_pre_plug(hotplug_dev, dev, errp); 2012 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2013 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2014 } 2015 } 2016 2017 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2018 DeviceState *dev, Error **errp) 2019 { 2020 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2021 pc_memory_plug(hotplug_dev, dev, errp); 2022 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2023 pc_cpu_plug(hotplug_dev, dev, errp); 2024 } 2025 } 2026 2027 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2028 DeviceState *dev, Error **errp) 2029 { 2030 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2031 pc_memory_unplug_request(hotplug_dev, dev, errp); 2032 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2033 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2034 } else { 2035 error_setg(errp, "acpi: device unplug request for not supported device" 2036 " type: %s", object_get_typename(OBJECT(dev))); 2037 } 2038 } 2039 2040 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2041 DeviceState *dev, Error **errp) 2042 { 2043 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2044 pc_memory_unplug(hotplug_dev, dev, errp); 2045 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2046 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2047 } else { 2048 error_setg(errp, "acpi: device unplug for not supported device" 2049 " type: %s", object_get_typename(OBJECT(dev))); 2050 } 2051 } 2052 2053 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 2054 DeviceState *dev) 2055 { 2056 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2057 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2058 return HOTPLUG_HANDLER(machine); 2059 } 2060 2061 return NULL; 2062 } 2063 2064 static void 2065 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2066 const char *name, void *opaque, 2067 Error **errp) 2068 { 2069 MachineState *ms = MACHINE(obj); 2070 int64_t value = memory_region_size(&ms->device_memory->mr); 2071 2072 visit_type_int(v, name, &value, errp); 2073 } 2074 2075 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2076 const char *name, void *opaque, 2077 Error **errp) 2078 { 2079 PCMachineState *pcms = PC_MACHINE(obj); 2080 uint64_t value = pcms->max_ram_below_4g; 2081 2082 visit_type_size(v, name, &value, errp); 2083 } 2084 2085 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2086 const char *name, void *opaque, 2087 Error **errp) 2088 { 2089 PCMachineState *pcms = PC_MACHINE(obj); 2090 Error *error = NULL; 2091 uint64_t value; 2092 2093 visit_type_size(v, name, &value, &error); 2094 if (error) { 2095 error_propagate(errp, error); 2096 return; 2097 } 2098 if (value > (1ULL << 32)) { 2099 error_setg(&error, 2100 "Machine option 'max-ram-below-4g=%"PRIu64 2101 "' expects size less than or equal to 4G", value); 2102 error_propagate(errp, error); 2103 return; 2104 } 2105 2106 if (value < (1ULL << 20)) { 2107 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2108 "BIOS may not work with less than 1MiB", value); 2109 } 2110 2111 pcms->max_ram_below_4g = value; 2112 } 2113 2114 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2115 void *opaque, Error **errp) 2116 { 2117 PCMachineState *pcms = PC_MACHINE(obj); 2118 OnOffAuto vmport = pcms->vmport; 2119 2120 visit_type_OnOffAuto(v, name, &vmport, errp); 2121 } 2122 2123 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2124 void *opaque, Error **errp) 2125 { 2126 PCMachineState *pcms = PC_MACHINE(obj); 2127 2128 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2129 } 2130 2131 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2132 { 2133 bool smm_available = false; 2134 2135 if (pcms->smm == ON_OFF_AUTO_OFF) { 2136 return false; 2137 } 2138 2139 if (tcg_enabled() || qtest_enabled()) { 2140 smm_available = true; 2141 } else if (kvm_enabled()) { 2142 smm_available = kvm_has_smm(); 2143 } 2144 2145 if (smm_available) { 2146 return true; 2147 } 2148 2149 if (pcms->smm == ON_OFF_AUTO_ON) { 2150 error_report("System Management Mode not supported by this hypervisor."); 2151 exit(1); 2152 } 2153 return false; 2154 } 2155 2156 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2157 void *opaque, Error **errp) 2158 { 2159 PCMachineState *pcms = PC_MACHINE(obj); 2160 OnOffAuto smm = pcms->smm; 2161 2162 visit_type_OnOffAuto(v, name, &smm, errp); 2163 } 2164 2165 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2166 void *opaque, Error **errp) 2167 { 2168 PCMachineState *pcms = PC_MACHINE(obj); 2169 2170 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2171 } 2172 2173 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 2174 { 2175 PCMachineState *pcms = PC_MACHINE(obj); 2176 2177 return pcms->acpi_nvdimm_state.is_enabled; 2178 } 2179 2180 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 2181 { 2182 PCMachineState *pcms = PC_MACHINE(obj); 2183 2184 pcms->acpi_nvdimm_state.is_enabled = value; 2185 } 2186 2187 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp) 2188 { 2189 PCMachineState *pcms = PC_MACHINE(obj); 2190 2191 return g_strdup(pcms->acpi_nvdimm_state.persistence_string); 2192 } 2193 2194 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value, 2195 Error **errp) 2196 { 2197 PCMachineState *pcms = PC_MACHINE(obj); 2198 AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state; 2199 2200 if (strcmp(value, "cpu") == 0) 2201 nvdimm_state->persistence = 3; 2202 else if (strcmp(value, "mem-ctrl") == 0) 2203 nvdimm_state->persistence = 2; 2204 else { 2205 error_report("-machine nvdimm-persistence=%s: unsupported option", value); 2206 exit(EXIT_FAILURE); 2207 } 2208 2209 g_free(nvdimm_state->persistence_string); 2210 nvdimm_state->persistence_string = g_strdup(value); 2211 } 2212 2213 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2214 { 2215 PCMachineState *pcms = PC_MACHINE(obj); 2216 2217 return pcms->smbus; 2218 } 2219 2220 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2221 { 2222 PCMachineState *pcms = PC_MACHINE(obj); 2223 2224 pcms->smbus = value; 2225 } 2226 2227 static bool pc_machine_get_sata(Object *obj, Error **errp) 2228 { 2229 PCMachineState *pcms = PC_MACHINE(obj); 2230 2231 return pcms->sata; 2232 } 2233 2234 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2235 { 2236 PCMachineState *pcms = PC_MACHINE(obj); 2237 2238 pcms->sata = value; 2239 } 2240 2241 static bool pc_machine_get_pit(Object *obj, Error **errp) 2242 { 2243 PCMachineState *pcms = PC_MACHINE(obj); 2244 2245 return pcms->pit; 2246 } 2247 2248 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2249 { 2250 PCMachineState *pcms = PC_MACHINE(obj); 2251 2252 pcms->pit = value; 2253 } 2254 2255 static void pc_machine_initfn(Object *obj) 2256 { 2257 PCMachineState *pcms = PC_MACHINE(obj); 2258 2259 pcms->max_ram_below_4g = 0; /* use default */ 2260 pcms->smm = ON_OFF_AUTO_AUTO; 2261 pcms->vmport = ON_OFF_AUTO_AUTO; 2262 /* nvdimm is disabled on default. */ 2263 pcms->acpi_nvdimm_state.is_enabled = false; 2264 /* acpi build is enabled by default if machine supports it */ 2265 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2266 pcms->smbus = true; 2267 pcms->sata = true; 2268 pcms->pit = true; 2269 } 2270 2271 static void pc_machine_reset(void) 2272 { 2273 CPUState *cs; 2274 X86CPU *cpu; 2275 2276 qemu_devices_reset(); 2277 2278 /* Reset APIC after devices have been reset to cancel 2279 * any changes that qemu_devices_reset() might have done. 2280 */ 2281 CPU_FOREACH(cs) { 2282 cpu = X86_CPU(cs); 2283 2284 if (cpu->apic_state) { 2285 device_reset(cpu->apic_state); 2286 } 2287 } 2288 } 2289 2290 static CpuInstanceProperties 2291 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2292 { 2293 MachineClass *mc = MACHINE_GET_CLASS(ms); 2294 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2295 2296 assert(cpu_index < possible_cpus->len); 2297 return possible_cpus->cpus[cpu_index].props; 2298 } 2299 2300 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2301 { 2302 X86CPUTopoInfo topo; 2303 2304 assert(idx < ms->possible_cpus->len); 2305 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2306 smp_cores, smp_threads, &topo); 2307 return topo.pkg_id % nb_numa_nodes; 2308 } 2309 2310 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2311 { 2312 int i; 2313 2314 if (ms->possible_cpus) { 2315 /* 2316 * make sure that max_cpus hasn't changed since the first use, i.e. 2317 * -smp hasn't been parsed after it 2318 */ 2319 assert(ms->possible_cpus->len == max_cpus); 2320 return ms->possible_cpus; 2321 } 2322 2323 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2324 sizeof(CPUArchId) * max_cpus); 2325 ms->possible_cpus->len = max_cpus; 2326 for (i = 0; i < ms->possible_cpus->len; i++) { 2327 X86CPUTopoInfo topo; 2328 2329 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2330 ms->possible_cpus->cpus[i].vcpus_count = 1; 2331 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 2332 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2333 smp_cores, smp_threads, &topo); 2334 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2335 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2336 ms->possible_cpus->cpus[i].props.has_core_id = true; 2337 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2338 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2339 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2340 } 2341 return ms->possible_cpus; 2342 } 2343 2344 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2345 { 2346 /* cpu index isn't used */ 2347 CPUState *cs; 2348 2349 CPU_FOREACH(cs) { 2350 X86CPU *cpu = X86_CPU(cs); 2351 2352 if (!cpu->apic_state) { 2353 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2354 } else { 2355 apic_deliver_nmi(cpu->apic_state); 2356 } 2357 } 2358 } 2359 2360 static void pc_machine_class_init(ObjectClass *oc, void *data) 2361 { 2362 MachineClass *mc = MACHINE_CLASS(oc); 2363 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2364 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2365 NMIClass *nc = NMI_CLASS(oc); 2366 2367 pcmc->pci_enabled = true; 2368 pcmc->has_acpi_build = true; 2369 pcmc->rsdp_in_ram = true; 2370 pcmc->smbios_defaults = true; 2371 pcmc->smbios_uuid_encoded = true; 2372 pcmc->gigabyte_align = true; 2373 pcmc->has_reserved_memory = true; 2374 pcmc->kvmclock_enabled = true; 2375 pcmc->enforce_aligned_dimm = true; 2376 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2377 * to be used at the moment, 32K should be enough for a while. */ 2378 pcmc->acpi_data_size = 0x20000 + 0x8000; 2379 pcmc->save_tsc_khz = true; 2380 pcmc->linuxboot_dma_enabled = true; 2381 assert(!mc->get_hotplug_handler); 2382 mc->get_hotplug_handler = pc_get_hotpug_handler; 2383 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2384 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2385 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2386 mc->auto_enable_numa_with_memhp = true; 2387 mc->has_hotpluggable_cpus = true; 2388 mc->default_boot_order = "cad"; 2389 mc->hot_add_cpu = pc_hot_add_cpu; 2390 mc->block_default_type = IF_IDE; 2391 mc->max_cpus = 255; 2392 mc->reset = pc_machine_reset; 2393 hc->pre_plug = pc_machine_device_pre_plug_cb; 2394 hc->plug = pc_machine_device_plug_cb; 2395 hc->unplug_request = pc_machine_device_unplug_request_cb; 2396 hc->unplug = pc_machine_device_unplug_cb; 2397 nc->nmi_monitor_handler = x86_nmi; 2398 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2399 2400 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2401 pc_machine_get_device_memory_region_size, NULL, 2402 NULL, NULL, &error_abort); 2403 2404 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2405 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2406 NULL, NULL, &error_abort); 2407 2408 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2409 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2410 2411 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2412 pc_machine_get_smm, pc_machine_set_smm, 2413 NULL, NULL, &error_abort); 2414 object_class_property_set_description(oc, PC_MACHINE_SMM, 2415 "Enable SMM (pc & q35)", &error_abort); 2416 2417 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2418 pc_machine_get_vmport, pc_machine_set_vmport, 2419 NULL, NULL, &error_abort); 2420 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2421 "Enable vmport (pc & q35)", &error_abort); 2422 2423 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, 2424 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); 2425 2426 object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST, 2427 pc_machine_get_nvdimm_persistence, 2428 pc_machine_set_nvdimm_persistence, &error_abort); 2429 2430 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2431 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2432 2433 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2434 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2435 2436 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2437 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2438 } 2439 2440 static const TypeInfo pc_machine_info = { 2441 .name = TYPE_PC_MACHINE, 2442 .parent = TYPE_MACHINE, 2443 .abstract = true, 2444 .instance_size = sizeof(PCMachineState), 2445 .instance_init = pc_machine_initfn, 2446 .class_size = sizeof(PCMachineClass), 2447 .class_init = pc_machine_class_init, 2448 .interfaces = (InterfaceInfo[]) { 2449 { TYPE_HOTPLUG_HANDLER }, 2450 { TYPE_NMI }, 2451 { } 2452 }, 2453 }; 2454 2455 static void pc_machine_register_types(void) 2456 { 2457 type_register_static(&pc_machine_info); 2458 } 2459 2460 type_init(pc_machine_register_types) 2461