1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "sysemu/cpus.h" 34 #include "hw/block/fdc.h" 35 #include "hw/ide.h" 36 #include "hw/pci/pci.h" 37 #include "hw/pci/pci_bus.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/timer/hpet.h" 40 #include "hw/firmware/smbios.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "multiboot.h" 44 #include "hw/timer/mc146818rtc.h" 45 #include "hw/dma/i8257.h" 46 #include "hw/timer/i8254.h" 47 #include "hw/input/i8042.h" 48 #include "hw/audio/pcspk.h" 49 #include "hw/pci/msi.h" 50 #include "hw/sysbus.h" 51 #include "sysemu/sysemu.h" 52 #include "sysemu/numa.h" 53 #include "sysemu/kvm.h" 54 #include "sysemu/qtest.h" 55 #include "kvm_i386.h" 56 #include "hw/xen/xen.h" 57 #include "ui/qemu-spice.h" 58 #include "exec/memory.h" 59 #include "exec/address-spaces.h" 60 #include "sysemu/arch_init.h" 61 #include "qemu/bitmap.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "qemu/option.h" 65 #include "hw/acpi/acpi.h" 66 #include "hw/acpi/cpu_hotplug.h" 67 #include "hw/boards.h" 68 #include "acpi-build.h" 69 #include "hw/mem/pc-dimm.h" 70 #include "qapi/error.h" 71 #include "qapi/qapi-visit-common.h" 72 #include "qapi/visitor.h" 73 #include "qom/cpu.h" 74 #include "hw/nmi.h" 75 #include "hw/i386/intel_iommu.h" 76 #include "hw/net/ne2000-isa.h" 77 78 /* debug PC/ISA interrupts */ 79 //#define DEBUG_IRQ 80 81 #ifdef DEBUG_IRQ 82 #define DPRINTF(fmt, ...) \ 83 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 84 #else 85 #define DPRINTF(fmt, ...) 86 #endif 87 88 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 89 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 90 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 91 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 92 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 93 94 #define E820_NR_ENTRIES 16 95 96 struct e820_entry { 97 uint64_t address; 98 uint64_t length; 99 uint32_t type; 100 } QEMU_PACKED __attribute((__aligned__(4))); 101 102 struct e820_table { 103 uint32_t count; 104 struct e820_entry entry[E820_NR_ENTRIES]; 105 } QEMU_PACKED __attribute((__aligned__(4))); 106 107 static struct e820_table e820_reserve; 108 static struct e820_entry *e820_table; 109 static unsigned e820_entries; 110 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 111 112 GlobalProperty pc_compat_3_1[] = { 113 { 114 .driver = "intel-iommu", 115 .property = "dma-drain", 116 .value = "off", 117 }, 118 }; 119 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 120 121 GlobalProperty pc_compat_3_0[] = { 122 { 123 .driver = TYPE_X86_CPU, 124 .property = "x-hv-synic-kvm-only", 125 .value = "on", 126 },{ 127 .driver = "Skylake-Server" "-" TYPE_X86_CPU, 128 .property = "pku", 129 .value = "off", 130 },{ 131 .driver = "Skylake-Server-IBRS" "-" TYPE_X86_CPU, 132 .property = "pku", 133 .value = "off", 134 }, 135 }; 136 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 137 138 GlobalProperty pc_compat_2_12[] = { 139 { 140 .driver = TYPE_X86_CPU, 141 .property = "legacy-cache", 142 .value = "on", 143 },{ 144 .driver = TYPE_X86_CPU, 145 .property = "topoext", 146 .value = "off", 147 },{ 148 .driver = "EPYC-" TYPE_X86_CPU, 149 .property = "xlevel", 150 .value = stringify(0x8000000a), 151 },{ 152 .driver = "EPYC-IBPB-" TYPE_X86_CPU, 153 .property = "xlevel", 154 .value = stringify(0x8000000a), 155 }, 156 }; 157 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 158 159 GlobalProperty pc_compat_2_11[] = { 160 { 161 .driver = TYPE_X86_CPU, 162 .property = "x-migrate-smi-count", 163 .value = "off", 164 },{ 165 .driver = "Skylake-Server" "-" TYPE_X86_CPU, 166 .property = "clflushopt", 167 .value = "off", 168 }, 169 }; 170 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 171 172 GlobalProperty pc_compat_2_10[] = { 173 { 174 .driver = TYPE_X86_CPU, 175 .property = "x-hv-max-vps", 176 .value = "0x40", 177 },{ 178 .driver = "i440FX-pcihost", 179 .property = "x-pci-hole64-fix", 180 .value = "off", 181 },{ 182 .driver = "q35-pcihost", 183 .property = "x-pci-hole64-fix", 184 .value = "off", 185 }, 186 }; 187 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 188 189 GlobalProperty pc_compat_2_9[] = { 190 { 191 .driver = "mch", 192 .property = "extended-tseg-mbytes", 193 .value = stringify(0), 194 }, 195 }; 196 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 197 198 GlobalProperty pc_compat_2_8[] = { 199 { 200 .driver = TYPE_X86_CPU, 201 .property = "tcg-cpuid", 202 .value = "off", 203 }, 204 { 205 .driver = "kvmclock", 206 .property = "x-mach-use-reliable-get-clock", 207 .value = "off", 208 }, 209 { 210 .driver = "ICH9-LPC", 211 .property = "x-smi-broadcast", 212 .value = "off", 213 }, 214 { 215 .driver = TYPE_X86_CPU, 216 .property = "vmware-cpuid-freq", 217 .value = "off", 218 }, 219 { 220 .driver = "Haswell-" TYPE_X86_CPU, 221 .property = "stepping", 222 .value = "1", 223 }, 224 }; 225 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 226 227 GlobalProperty pc_compat_2_7[] = { 228 { 229 .driver = TYPE_X86_CPU, 230 .property = "l3-cache", 231 .value = "off", 232 }, 233 { 234 .driver = TYPE_X86_CPU, 235 .property = "full-cpuid-auto-level", 236 .value = "off", 237 }, 238 { 239 .driver = "Opteron_G3" "-" TYPE_X86_CPU, 240 .property = "family", 241 .value = "15", 242 }, 243 { 244 .driver = "Opteron_G3" "-" TYPE_X86_CPU, 245 .property = "model", 246 .value = "6", 247 }, 248 { 249 .driver = "Opteron_G3" "-" TYPE_X86_CPU, 250 .property = "stepping", 251 .value = "1", 252 }, 253 { 254 .driver = "isa-pcspk", 255 .property = "migrate", 256 .value = "off", 257 }, 258 }; 259 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 260 261 GlobalProperty pc_compat_2_6[] = { 262 { 263 .driver = TYPE_X86_CPU, 264 .property = "cpuid-0xb", 265 .value = "off", 266 },{ 267 .driver = "vmxnet3", 268 .property = "romfile", 269 .value = "", 270 }, 271 { 272 .driver = TYPE_X86_CPU, 273 .property = "fill-mtrr-mask", 274 .value = "off", 275 }, 276 { 277 .driver = "apic-common", 278 .property = "legacy-instance-id", 279 .value = "on", 280 } 281 }; 282 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 283 284 GlobalProperty pc_compat_2_5[] = {}; 285 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 286 287 GlobalProperty pc_compat_2_4[] = { 288 PC_CPU_MODEL_IDS("2.4.0") 289 { 290 .driver = "Haswell-" TYPE_X86_CPU, 291 .property = "abm", 292 .value = "off", 293 }, 294 { 295 .driver = "Haswell-noTSX-" TYPE_X86_CPU, 296 .property = "abm", 297 .value = "off", 298 }, 299 { 300 .driver = "Broadwell-" TYPE_X86_CPU, 301 .property = "abm", 302 .value = "off", 303 }, 304 { 305 .driver = "Broadwell-noTSX-" TYPE_X86_CPU, 306 .property = "abm", 307 .value = "off", 308 }, 309 { 310 .driver = "host" "-" TYPE_X86_CPU, 311 .property = "host-cache-info", 312 .value = "on", 313 }, 314 { 315 .driver = TYPE_X86_CPU, 316 .property = "check", 317 .value = "off", 318 }, 319 { 320 .driver = "qemu64" "-" TYPE_X86_CPU, 321 .property = "sse4a", 322 .value = "on", 323 }, 324 { 325 .driver = "qemu64" "-" TYPE_X86_CPU, 326 .property = "abm", 327 .value = "on", 328 }, 329 { 330 .driver = "qemu64" "-" TYPE_X86_CPU, 331 .property = "popcnt", 332 .value = "on", 333 }, 334 { 335 .driver = "qemu32" "-" TYPE_X86_CPU, 336 .property = "popcnt", 337 .value = "on", 338 },{ 339 .driver = "Opteron_G2" "-" TYPE_X86_CPU, 340 .property = "rdtscp", 341 .value = "on", 342 },{ 343 .driver = "Opteron_G3" "-" TYPE_X86_CPU, 344 .property = "rdtscp", 345 .value = "on", 346 },{ 347 .driver = "Opteron_G4" "-" TYPE_X86_CPU, 348 .property = "rdtscp", 349 .value = "on", 350 },{ 351 .driver = "Opteron_G5" "-" TYPE_X86_CPU, 352 .property = "rdtscp", 353 .value = "on", 354 } 355 }; 356 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 357 358 GlobalProperty pc_compat_2_3[] = { 359 PC_CPU_MODEL_IDS("2.3.0") 360 { 361 .driver = TYPE_X86_CPU, 362 .property = "arat", 363 .value = "off", 364 },{ 365 .driver = "qemu64" "-" TYPE_X86_CPU, 366 .property = "min-level", 367 .value = stringify(4), 368 },{ 369 .driver = "kvm64" "-" TYPE_X86_CPU, 370 .property = "min-level", 371 .value = stringify(5), 372 },{ 373 .driver = "pentium3" "-" TYPE_X86_CPU, 374 .property = "min-level", 375 .value = stringify(2), 376 },{ 377 .driver = "n270" "-" TYPE_X86_CPU, 378 .property = "min-level", 379 .value = stringify(5), 380 },{ 381 .driver = "Conroe" "-" TYPE_X86_CPU, 382 .property = "min-level", 383 .value = stringify(4), 384 },{ 385 .driver = "Penryn" "-" TYPE_X86_CPU, 386 .property = "min-level", 387 .value = stringify(4), 388 },{ 389 .driver = "Nehalem" "-" TYPE_X86_CPU, 390 .property = "min-level", 391 .value = stringify(4), 392 },{ 393 .driver = "n270" "-" TYPE_X86_CPU, 394 .property = "min-xlevel", 395 .value = stringify(0x8000000a), 396 },{ 397 .driver = "Penryn" "-" TYPE_X86_CPU, 398 .property = "min-xlevel", 399 .value = stringify(0x8000000a), 400 },{ 401 .driver = "Conroe" "-" TYPE_X86_CPU, 402 .property = "min-xlevel", 403 .value = stringify(0x8000000a), 404 },{ 405 .driver = "Nehalem" "-" TYPE_X86_CPU, 406 .property = "min-xlevel", 407 .value = stringify(0x8000000a), 408 },{ 409 .driver = "Westmere" "-" TYPE_X86_CPU, 410 .property = "min-xlevel", 411 .value = stringify(0x8000000a), 412 },{ 413 .driver = "SandyBridge" "-" TYPE_X86_CPU, 414 .property = "min-xlevel", 415 .value = stringify(0x8000000a), 416 },{ 417 .driver = "IvyBridge" "-" TYPE_X86_CPU, 418 .property = "min-xlevel", 419 .value = stringify(0x8000000a), 420 },{ 421 .driver = "Haswell" "-" TYPE_X86_CPU, 422 .property = "min-xlevel", 423 .value = stringify(0x8000000a), 424 },{ 425 .driver = "Haswell-noTSX" "-" TYPE_X86_CPU, 426 .property = "min-xlevel", 427 .value = stringify(0x8000000a), 428 },{ 429 .driver = "Broadwell" "-" TYPE_X86_CPU, 430 .property = "min-xlevel", 431 .value = stringify(0x8000000a), 432 },{ 433 .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU, 434 .property = "min-xlevel", 435 .value = stringify(0x8000000a), 436 },{ 437 .driver = TYPE_X86_CPU, 438 .property = "kvm-no-smi-migration", 439 .value = "on", 440 }, 441 }; 442 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 443 444 void gsi_handler(void *opaque, int n, int level) 445 { 446 GSIState *s = opaque; 447 448 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 449 if (n < ISA_NUM_IRQS) { 450 qemu_set_irq(s->i8259_irq[n], level); 451 } 452 qemu_set_irq(s->ioapic_irq[n], level); 453 } 454 455 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 456 unsigned size) 457 { 458 } 459 460 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 461 { 462 return 0xffffffffffffffffULL; 463 } 464 465 /* MSDOS compatibility mode FPU exception support */ 466 static qemu_irq ferr_irq; 467 468 void pc_register_ferr_irq(qemu_irq irq) 469 { 470 ferr_irq = irq; 471 } 472 473 /* XXX: add IGNNE support */ 474 void cpu_set_ferr(CPUX86State *s) 475 { 476 qemu_irq_raise(ferr_irq); 477 } 478 479 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 480 unsigned size) 481 { 482 qemu_irq_lower(ferr_irq); 483 } 484 485 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 486 { 487 return 0xffffffffffffffffULL; 488 } 489 490 /* TSC handling */ 491 uint64_t cpu_get_tsc(CPUX86State *env) 492 { 493 return cpu_get_ticks(); 494 } 495 496 /* IRQ handling */ 497 int cpu_get_pic_interrupt(CPUX86State *env) 498 { 499 X86CPU *cpu = x86_env_get_cpu(env); 500 int intno; 501 502 if (!kvm_irqchip_in_kernel()) { 503 intno = apic_get_interrupt(cpu->apic_state); 504 if (intno >= 0) { 505 return intno; 506 } 507 /* read the irq from the PIC */ 508 if (!apic_accept_pic_intr(cpu->apic_state)) { 509 return -1; 510 } 511 } 512 513 intno = pic_read_irq(isa_pic); 514 return intno; 515 } 516 517 static void pic_irq_request(void *opaque, int irq, int level) 518 { 519 CPUState *cs = first_cpu; 520 X86CPU *cpu = X86_CPU(cs); 521 522 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 523 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 524 CPU_FOREACH(cs) { 525 cpu = X86_CPU(cs); 526 if (apic_accept_pic_intr(cpu->apic_state)) { 527 apic_deliver_pic_intr(cpu->apic_state, level); 528 } 529 } 530 } else { 531 if (level) { 532 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 533 } else { 534 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 535 } 536 } 537 } 538 539 /* PC cmos mappings */ 540 541 #define REG_EQUIPMENT_BYTE 0x14 542 543 int cmos_get_fd_drive_type(FloppyDriveType fd0) 544 { 545 int val; 546 547 switch (fd0) { 548 case FLOPPY_DRIVE_TYPE_144: 549 /* 1.44 Mb 3"5 drive */ 550 val = 4; 551 break; 552 case FLOPPY_DRIVE_TYPE_288: 553 /* 2.88 Mb 3"5 drive */ 554 val = 5; 555 break; 556 case FLOPPY_DRIVE_TYPE_120: 557 /* 1.2 Mb 5"5 drive */ 558 val = 2; 559 break; 560 case FLOPPY_DRIVE_TYPE_NONE: 561 default: 562 val = 0; 563 break; 564 } 565 return val; 566 } 567 568 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 569 int16_t cylinders, int8_t heads, int8_t sectors) 570 { 571 rtc_set_memory(s, type_ofs, 47); 572 rtc_set_memory(s, info_ofs, cylinders); 573 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 574 rtc_set_memory(s, info_ofs + 2, heads); 575 rtc_set_memory(s, info_ofs + 3, 0xff); 576 rtc_set_memory(s, info_ofs + 4, 0xff); 577 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 578 rtc_set_memory(s, info_ofs + 6, cylinders); 579 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 580 rtc_set_memory(s, info_ofs + 8, sectors); 581 } 582 583 /* convert boot_device letter to something recognizable by the bios */ 584 static int boot_device2nibble(char boot_device) 585 { 586 switch(boot_device) { 587 case 'a': 588 case 'b': 589 return 0x01; /* floppy boot */ 590 case 'c': 591 return 0x02; /* hard drive boot */ 592 case 'd': 593 return 0x03; /* CD-ROM boot */ 594 case 'n': 595 return 0x04; /* Network boot */ 596 } 597 return 0; 598 } 599 600 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 601 { 602 #define PC_MAX_BOOT_DEVICES 3 603 int nbds, bds[3] = { 0, }; 604 int i; 605 606 nbds = strlen(boot_device); 607 if (nbds > PC_MAX_BOOT_DEVICES) { 608 error_setg(errp, "Too many boot devices for PC"); 609 return; 610 } 611 for (i = 0; i < nbds; i++) { 612 bds[i] = boot_device2nibble(boot_device[i]); 613 if (bds[i] == 0) { 614 error_setg(errp, "Invalid boot device for PC: '%c'", 615 boot_device[i]); 616 return; 617 } 618 } 619 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 620 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 621 } 622 623 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 624 { 625 set_boot_dev(opaque, boot_device, errp); 626 } 627 628 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 629 { 630 int val, nb, i; 631 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 632 FLOPPY_DRIVE_TYPE_NONE }; 633 634 /* floppy type */ 635 if (floppy) { 636 for (i = 0; i < 2; i++) { 637 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 638 } 639 } 640 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 641 cmos_get_fd_drive_type(fd_type[1]); 642 rtc_set_memory(rtc_state, 0x10, val); 643 644 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 645 nb = 0; 646 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 647 nb++; 648 } 649 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 650 nb++; 651 } 652 switch (nb) { 653 case 0: 654 break; 655 case 1: 656 val |= 0x01; /* 1 drive, ready for boot */ 657 break; 658 case 2: 659 val |= 0x41; /* 2 drives, ready for boot */ 660 break; 661 } 662 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 663 } 664 665 typedef struct pc_cmos_init_late_arg { 666 ISADevice *rtc_state; 667 BusState *idebus[2]; 668 } pc_cmos_init_late_arg; 669 670 typedef struct check_fdc_state { 671 ISADevice *floppy; 672 bool multiple; 673 } CheckFdcState; 674 675 static int check_fdc(Object *obj, void *opaque) 676 { 677 CheckFdcState *state = opaque; 678 Object *fdc; 679 uint32_t iobase; 680 Error *local_err = NULL; 681 682 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 683 if (!fdc) { 684 return 0; 685 } 686 687 iobase = object_property_get_uint(obj, "iobase", &local_err); 688 if (local_err || iobase != 0x3f0) { 689 error_free(local_err); 690 return 0; 691 } 692 693 if (state->floppy) { 694 state->multiple = true; 695 } else { 696 state->floppy = ISA_DEVICE(obj); 697 } 698 return 0; 699 } 700 701 static const char * const fdc_container_path[] = { 702 "/unattached", "/peripheral", "/peripheral-anon" 703 }; 704 705 /* 706 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 707 * and ACPI objects. 708 */ 709 ISADevice *pc_find_fdc0(void) 710 { 711 int i; 712 Object *container; 713 CheckFdcState state = { 0 }; 714 715 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 716 container = container_get(qdev_get_machine(), fdc_container_path[i]); 717 object_child_foreach(container, check_fdc, &state); 718 } 719 720 if (state.multiple) { 721 warn_report("multiple floppy disk controllers with " 722 "iobase=0x3f0 have been found"); 723 error_printf("the one being picked for CMOS setup might not reflect " 724 "your intent"); 725 } 726 727 return state.floppy; 728 } 729 730 static void pc_cmos_init_late(void *opaque) 731 { 732 pc_cmos_init_late_arg *arg = opaque; 733 ISADevice *s = arg->rtc_state; 734 int16_t cylinders; 735 int8_t heads, sectors; 736 int val; 737 int i, trans; 738 739 val = 0; 740 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 741 &cylinders, &heads, §ors) >= 0) { 742 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 743 val |= 0xf0; 744 } 745 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 746 &cylinders, &heads, §ors) >= 0) { 747 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 748 val |= 0x0f; 749 } 750 rtc_set_memory(s, 0x12, val); 751 752 val = 0; 753 for (i = 0; i < 4; i++) { 754 /* NOTE: ide_get_geometry() returns the physical 755 geometry. It is always such that: 1 <= sects <= 63, 1 756 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 757 geometry can be different if a translation is done. */ 758 if (arg->idebus[i / 2] && 759 ide_get_geometry(arg->idebus[i / 2], i % 2, 760 &cylinders, &heads, §ors) >= 0) { 761 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 762 assert((trans & ~3) == 0); 763 val |= trans << (i * 2); 764 } 765 } 766 rtc_set_memory(s, 0x39, val); 767 768 pc_cmos_init_floppy(s, pc_find_fdc0()); 769 770 qemu_unregister_reset(pc_cmos_init_late, opaque); 771 } 772 773 void pc_cmos_init(PCMachineState *pcms, 774 BusState *idebus0, BusState *idebus1, 775 ISADevice *s) 776 { 777 int val; 778 static pc_cmos_init_late_arg arg; 779 780 /* various important CMOS locations needed by PC/Bochs bios */ 781 782 /* memory size */ 783 /* base memory (first MiB) */ 784 val = MIN(pcms->below_4g_mem_size / KiB, 640); 785 rtc_set_memory(s, 0x15, val); 786 rtc_set_memory(s, 0x16, val >> 8); 787 /* extended memory (next 64MiB) */ 788 if (pcms->below_4g_mem_size > 1 * MiB) { 789 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 790 } else { 791 val = 0; 792 } 793 if (val > 65535) 794 val = 65535; 795 rtc_set_memory(s, 0x17, val); 796 rtc_set_memory(s, 0x18, val >> 8); 797 rtc_set_memory(s, 0x30, val); 798 rtc_set_memory(s, 0x31, val >> 8); 799 /* memory between 16MiB and 4GiB */ 800 if (pcms->below_4g_mem_size > 16 * MiB) { 801 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 802 } else { 803 val = 0; 804 } 805 if (val > 65535) 806 val = 65535; 807 rtc_set_memory(s, 0x34, val); 808 rtc_set_memory(s, 0x35, val >> 8); 809 /* memory above 4GiB */ 810 val = pcms->above_4g_mem_size / 65536; 811 rtc_set_memory(s, 0x5b, val); 812 rtc_set_memory(s, 0x5c, val >> 8); 813 rtc_set_memory(s, 0x5d, val >> 16); 814 815 object_property_add_link(OBJECT(pcms), "rtc_state", 816 TYPE_ISA_DEVICE, 817 (Object **)&pcms->rtc, 818 object_property_allow_set_link, 819 OBJ_PROP_LINK_STRONG, &error_abort); 820 object_property_set_link(OBJECT(pcms), OBJECT(s), 821 "rtc_state", &error_abort); 822 823 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 824 825 val = 0; 826 val |= 0x02; /* FPU is there */ 827 val |= 0x04; /* PS/2 mouse installed */ 828 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 829 830 /* hard drives and FDC */ 831 arg.rtc_state = s; 832 arg.idebus[0] = idebus0; 833 arg.idebus[1] = idebus1; 834 qemu_register_reset(pc_cmos_init_late, &arg); 835 } 836 837 #define TYPE_PORT92 "port92" 838 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 839 840 /* port 92 stuff: could be split off */ 841 typedef struct Port92State { 842 ISADevice parent_obj; 843 844 MemoryRegion io; 845 uint8_t outport; 846 qemu_irq a20_out; 847 } Port92State; 848 849 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 850 unsigned size) 851 { 852 Port92State *s = opaque; 853 int oldval = s->outport; 854 855 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 856 s->outport = val; 857 qemu_set_irq(s->a20_out, (val >> 1) & 1); 858 if ((val & 1) && !(oldval & 1)) { 859 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 860 } 861 } 862 863 static uint64_t port92_read(void *opaque, hwaddr addr, 864 unsigned size) 865 { 866 Port92State *s = opaque; 867 uint32_t ret; 868 869 ret = s->outport; 870 DPRINTF("port92: read 0x%02x\n", ret); 871 return ret; 872 } 873 874 static void port92_init(ISADevice *dev, qemu_irq a20_out) 875 { 876 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 877 } 878 879 static const VMStateDescription vmstate_port92_isa = { 880 .name = "port92", 881 .version_id = 1, 882 .minimum_version_id = 1, 883 .fields = (VMStateField[]) { 884 VMSTATE_UINT8(outport, Port92State), 885 VMSTATE_END_OF_LIST() 886 } 887 }; 888 889 static void port92_reset(DeviceState *d) 890 { 891 Port92State *s = PORT92(d); 892 893 s->outport &= ~1; 894 } 895 896 static const MemoryRegionOps port92_ops = { 897 .read = port92_read, 898 .write = port92_write, 899 .impl = { 900 .min_access_size = 1, 901 .max_access_size = 1, 902 }, 903 .endianness = DEVICE_LITTLE_ENDIAN, 904 }; 905 906 static void port92_initfn(Object *obj) 907 { 908 Port92State *s = PORT92(obj); 909 910 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 911 912 s->outport = 0; 913 914 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 915 } 916 917 static void port92_realizefn(DeviceState *dev, Error **errp) 918 { 919 ISADevice *isadev = ISA_DEVICE(dev); 920 Port92State *s = PORT92(dev); 921 922 isa_register_ioport(isadev, &s->io, 0x92); 923 } 924 925 static void port92_class_initfn(ObjectClass *klass, void *data) 926 { 927 DeviceClass *dc = DEVICE_CLASS(klass); 928 929 dc->realize = port92_realizefn; 930 dc->reset = port92_reset; 931 dc->vmsd = &vmstate_port92_isa; 932 /* 933 * Reason: unlike ordinary ISA devices, this one needs additional 934 * wiring: its A20 output line needs to be wired up by 935 * port92_init(). 936 */ 937 dc->user_creatable = false; 938 } 939 940 static const TypeInfo port92_info = { 941 .name = TYPE_PORT92, 942 .parent = TYPE_ISA_DEVICE, 943 .instance_size = sizeof(Port92State), 944 .instance_init = port92_initfn, 945 .class_init = port92_class_initfn, 946 }; 947 948 static void port92_register_types(void) 949 { 950 type_register_static(&port92_info); 951 } 952 953 type_init(port92_register_types) 954 955 static void handle_a20_line_change(void *opaque, int irq, int level) 956 { 957 X86CPU *cpu = opaque; 958 959 /* XXX: send to all CPUs ? */ 960 /* XXX: add logic to handle multiple A20 line sources */ 961 x86_cpu_set_a20(cpu, level); 962 } 963 964 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 965 { 966 int index = le32_to_cpu(e820_reserve.count); 967 struct e820_entry *entry; 968 969 if (type != E820_RAM) { 970 /* old FW_CFG_E820_TABLE entry -- reservations only */ 971 if (index >= E820_NR_ENTRIES) { 972 return -EBUSY; 973 } 974 entry = &e820_reserve.entry[index++]; 975 976 entry->address = cpu_to_le64(address); 977 entry->length = cpu_to_le64(length); 978 entry->type = cpu_to_le32(type); 979 980 e820_reserve.count = cpu_to_le32(index); 981 } 982 983 /* new "etc/e820" file -- include ram too */ 984 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 985 e820_table[e820_entries].address = cpu_to_le64(address); 986 e820_table[e820_entries].length = cpu_to_le64(length); 987 e820_table[e820_entries].type = cpu_to_le32(type); 988 e820_entries++; 989 990 return e820_entries; 991 } 992 993 int e820_get_num_entries(void) 994 { 995 return e820_entries; 996 } 997 998 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 999 { 1000 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 1001 *address = le64_to_cpu(e820_table[idx].address); 1002 *length = le64_to_cpu(e820_table[idx].length); 1003 return true; 1004 } 1005 return false; 1006 } 1007 1008 /* Enables contiguous-apic-ID mode, for compatibility */ 1009 static bool compat_apic_id_mode; 1010 1011 void enable_compat_apic_id_mode(void) 1012 { 1013 compat_apic_id_mode = true; 1014 } 1015 1016 /* Calculates initial APIC ID for a specific CPU index 1017 * 1018 * Currently we need to be able to calculate the APIC ID from the CPU index 1019 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 1020 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 1021 * all CPUs up to max_cpus. 1022 */ 1023 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 1024 { 1025 uint32_t correct_id; 1026 static bool warned; 1027 1028 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 1029 if (compat_apic_id_mode) { 1030 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 1031 error_report("APIC IDs set in compatibility mode, " 1032 "CPU topology won't match the configuration"); 1033 warned = true; 1034 } 1035 return cpu_index; 1036 } else { 1037 return correct_id; 1038 } 1039 } 1040 1041 static void pc_build_smbios(PCMachineState *pcms) 1042 { 1043 uint8_t *smbios_tables, *smbios_anchor; 1044 size_t smbios_tables_len, smbios_anchor_len; 1045 struct smbios_phys_mem_area *mem_array; 1046 unsigned i, array_count; 1047 MachineState *ms = MACHINE(pcms); 1048 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1049 1050 /* tell smbios about cpuid version and features */ 1051 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1052 1053 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 1054 if (smbios_tables) { 1055 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 1056 smbios_tables, smbios_tables_len); 1057 } 1058 1059 /* build the array of physical mem area from e820 table */ 1060 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 1061 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 1062 uint64_t addr, len; 1063 1064 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 1065 mem_array[array_count].address = addr; 1066 mem_array[array_count].length = len; 1067 array_count++; 1068 } 1069 } 1070 smbios_get_tables(mem_array, array_count, 1071 &smbios_tables, &smbios_tables_len, 1072 &smbios_anchor, &smbios_anchor_len); 1073 g_free(mem_array); 1074 1075 if (smbios_anchor) { 1076 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 1077 smbios_tables, smbios_tables_len); 1078 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 1079 smbios_anchor, smbios_anchor_len); 1080 } 1081 } 1082 1083 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 1084 { 1085 FWCfgState *fw_cfg; 1086 uint64_t *numa_fw_cfg; 1087 int i; 1088 const CPUArchIdList *cpus; 1089 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1090 1091 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 1092 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1093 1094 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1095 * 1096 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1097 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1098 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1099 * for CPU hotplug also uses APIC ID and not "CPU index". 1100 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1101 * but the "limit to the APIC ID values SeaBIOS may see". 1102 * 1103 * So for compatibility reasons with old BIOSes we are stuck with 1104 * "etc/max-cpus" actually being apic_id_limit 1105 */ 1106 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1107 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1108 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1109 acpi_tables, acpi_tables_len); 1110 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1111 1112 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1113 &e820_reserve, sizeof(e820_reserve)); 1114 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1115 sizeof(struct e820_entry) * e820_entries); 1116 1117 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1118 /* allocate memory for the NUMA channel: one (64bit) word for the number 1119 * of nodes, one word for each VCPU->node and one word for each node to 1120 * hold the amount of memory. 1121 */ 1122 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1123 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1124 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1125 for (i = 0; i < cpus->len; i++) { 1126 unsigned int apic_id = cpus->cpus[i].arch_id; 1127 assert(apic_id < pcms->apic_id_limit); 1128 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1129 } 1130 for (i = 0; i < nb_numa_nodes; i++) { 1131 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1132 cpu_to_le64(numa_info[i].node_mem); 1133 } 1134 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1135 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1136 sizeof(*numa_fw_cfg)); 1137 1138 return fw_cfg; 1139 } 1140 1141 static long get_file_size(FILE *f) 1142 { 1143 long where, size; 1144 1145 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1146 1147 where = ftell(f); 1148 fseek(f, 0, SEEK_END); 1149 size = ftell(f); 1150 fseek(f, where, SEEK_SET); 1151 1152 return size; 1153 } 1154 1155 /* setup_data types */ 1156 #define SETUP_NONE 0 1157 #define SETUP_E820_EXT 1 1158 #define SETUP_DTB 2 1159 #define SETUP_PCI 3 1160 #define SETUP_EFI 4 1161 1162 struct setup_data { 1163 uint64_t next; 1164 uint32_t type; 1165 uint32_t len; 1166 uint8_t data[0]; 1167 } __attribute__((packed)); 1168 1169 static void load_linux(PCMachineState *pcms, 1170 FWCfgState *fw_cfg) 1171 { 1172 uint16_t protocol; 1173 int setup_size, kernel_size, cmdline_size; 1174 int dtb_size, setup_data_offset; 1175 uint32_t initrd_max; 1176 uint8_t header[8192], *setup, *kernel; 1177 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1178 FILE *f; 1179 char *vmode; 1180 MachineState *machine = MACHINE(pcms); 1181 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1182 struct setup_data *setup_data; 1183 const char *kernel_filename = machine->kernel_filename; 1184 const char *initrd_filename = machine->initrd_filename; 1185 const char *dtb_filename = machine->dtb; 1186 const char *kernel_cmdline = machine->kernel_cmdline; 1187 1188 /* Align to 16 bytes as a paranoia measure */ 1189 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1190 1191 /* load the kernel header */ 1192 f = fopen(kernel_filename, "rb"); 1193 if (!f || !(kernel_size = get_file_size(f)) || 1194 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1195 MIN(ARRAY_SIZE(header), kernel_size)) { 1196 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1197 kernel_filename, strerror(errno)); 1198 exit(1); 1199 } 1200 1201 /* kernel protocol version */ 1202 #if 0 1203 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1204 #endif 1205 if (ldl_p(header+0x202) == 0x53726448) { 1206 protocol = lduw_p(header+0x206); 1207 } else { 1208 /* This looks like a multiboot kernel. If it is, let's stop 1209 treating it like a Linux kernel. */ 1210 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1211 kernel_cmdline, kernel_size, header)) { 1212 return; 1213 } 1214 protocol = 0; 1215 } 1216 1217 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1218 /* Low kernel */ 1219 real_addr = 0x90000; 1220 cmdline_addr = 0x9a000 - cmdline_size; 1221 prot_addr = 0x10000; 1222 } else if (protocol < 0x202) { 1223 /* High but ancient kernel */ 1224 real_addr = 0x90000; 1225 cmdline_addr = 0x9a000 - cmdline_size; 1226 prot_addr = 0x100000; 1227 } else { 1228 /* High and recent kernel */ 1229 real_addr = 0x10000; 1230 cmdline_addr = 0x20000; 1231 prot_addr = 0x100000; 1232 } 1233 1234 #if 0 1235 fprintf(stderr, 1236 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1237 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1238 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1239 real_addr, 1240 cmdline_addr, 1241 prot_addr); 1242 #endif 1243 1244 /* highest address for loading the initrd */ 1245 if (protocol >= 0x203) { 1246 initrd_max = ldl_p(header+0x22c); 1247 } else { 1248 initrd_max = 0x37ffffff; 1249 } 1250 1251 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1252 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1253 } 1254 1255 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1256 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1257 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1258 1259 if (protocol >= 0x202) { 1260 stl_p(header+0x228, cmdline_addr); 1261 } else { 1262 stw_p(header+0x20, 0xA33F); 1263 stw_p(header+0x22, cmdline_addr-real_addr); 1264 } 1265 1266 /* handle vga= parameter */ 1267 vmode = strstr(kernel_cmdline, "vga="); 1268 if (vmode) { 1269 unsigned int video_mode; 1270 /* skip "vga=" */ 1271 vmode += 4; 1272 if (!strncmp(vmode, "normal", 6)) { 1273 video_mode = 0xffff; 1274 } else if (!strncmp(vmode, "ext", 3)) { 1275 video_mode = 0xfffe; 1276 } else if (!strncmp(vmode, "ask", 3)) { 1277 video_mode = 0xfffd; 1278 } else { 1279 video_mode = strtol(vmode, NULL, 0); 1280 } 1281 stw_p(header+0x1fa, video_mode); 1282 } 1283 1284 /* loader type */ 1285 /* High nybble = B reserved for QEMU; low nybble is revision number. 1286 If this code is substantially changed, you may want to consider 1287 incrementing the revision. */ 1288 if (protocol >= 0x200) { 1289 header[0x210] = 0xB0; 1290 } 1291 /* heap */ 1292 if (protocol >= 0x201) { 1293 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1294 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1295 } 1296 1297 /* load initrd */ 1298 if (initrd_filename) { 1299 gsize initrd_size; 1300 gchar *initrd_data; 1301 GError *gerr = NULL; 1302 1303 if (protocol < 0x200) { 1304 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1305 exit(1); 1306 } 1307 1308 if (!g_file_get_contents(initrd_filename, &initrd_data, 1309 &initrd_size, &gerr)) { 1310 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1311 initrd_filename, gerr->message); 1312 exit(1); 1313 } 1314 if (initrd_size >= initrd_max) { 1315 fprintf(stderr, "qemu: initrd is too large, cannot support." 1316 "(max: %"PRIu32", need %"PRId64")\n", 1317 initrd_max, (uint64_t)initrd_size); 1318 exit(1); 1319 } 1320 1321 initrd_addr = (initrd_max-initrd_size) & ~4095; 1322 1323 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1324 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1325 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1326 1327 stl_p(header+0x218, initrd_addr); 1328 stl_p(header+0x21c, initrd_size); 1329 } 1330 1331 /* load kernel and setup */ 1332 setup_size = header[0x1f1]; 1333 if (setup_size == 0) { 1334 setup_size = 4; 1335 } 1336 setup_size = (setup_size+1)*512; 1337 if (setup_size > kernel_size) { 1338 fprintf(stderr, "qemu: invalid kernel header\n"); 1339 exit(1); 1340 } 1341 kernel_size -= setup_size; 1342 1343 setup = g_malloc(setup_size); 1344 kernel = g_malloc(kernel_size); 1345 fseek(f, 0, SEEK_SET); 1346 if (fread(setup, 1, setup_size, f) != setup_size) { 1347 fprintf(stderr, "fread() failed\n"); 1348 exit(1); 1349 } 1350 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1351 fprintf(stderr, "fread() failed\n"); 1352 exit(1); 1353 } 1354 fclose(f); 1355 1356 /* append dtb to kernel */ 1357 if (dtb_filename) { 1358 if (protocol < 0x209) { 1359 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1360 exit(1); 1361 } 1362 1363 dtb_size = get_image_size(dtb_filename); 1364 if (dtb_size <= 0) { 1365 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1366 dtb_filename, strerror(errno)); 1367 exit(1); 1368 } 1369 1370 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1371 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1372 kernel = g_realloc(kernel, kernel_size); 1373 1374 stq_p(header+0x250, prot_addr + setup_data_offset); 1375 1376 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1377 setup_data->next = 0; 1378 setup_data->type = cpu_to_le32(SETUP_DTB); 1379 setup_data->len = cpu_to_le32(dtb_size); 1380 1381 load_image_size(dtb_filename, setup_data->data, dtb_size); 1382 } 1383 1384 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1385 1386 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1387 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1388 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1389 1390 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1391 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1392 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1393 1394 option_rom[nb_option_roms].bootindex = 0; 1395 option_rom[nb_option_roms].name = "linuxboot.bin"; 1396 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1397 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1398 } 1399 nb_option_roms++; 1400 } 1401 1402 #define NE2000_NB_MAX 6 1403 1404 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1405 0x280, 0x380 }; 1406 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1407 1408 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1409 { 1410 static int nb_ne2k = 0; 1411 1412 if (nb_ne2k == NE2000_NB_MAX) 1413 return; 1414 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1415 ne2000_irq[nb_ne2k], nd); 1416 nb_ne2k++; 1417 } 1418 1419 DeviceState *cpu_get_current_apic(void) 1420 { 1421 if (current_cpu) { 1422 X86CPU *cpu = X86_CPU(current_cpu); 1423 return cpu->apic_state; 1424 } else { 1425 return NULL; 1426 } 1427 } 1428 1429 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1430 { 1431 X86CPU *cpu = opaque; 1432 1433 if (level) { 1434 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1435 } 1436 } 1437 1438 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) 1439 { 1440 Object *cpu = NULL; 1441 Error *local_err = NULL; 1442 1443 cpu = object_new(typename); 1444 1445 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1446 object_property_set_bool(cpu, true, "realized", &local_err); 1447 1448 object_unref(cpu); 1449 error_propagate(errp, local_err); 1450 } 1451 1452 void pc_hot_add_cpu(const int64_t id, Error **errp) 1453 { 1454 MachineState *ms = MACHINE(qdev_get_machine()); 1455 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1456 Error *local_err = NULL; 1457 1458 if (id < 0) { 1459 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1460 return; 1461 } 1462 1463 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1464 error_setg(errp, "Unable to add CPU: %" PRIi64 1465 ", resulting APIC ID (%" PRIi64 ") is too large", 1466 id, apic_id); 1467 return; 1468 } 1469 1470 pc_new_cpu(ms->cpu_type, apic_id, &local_err); 1471 if (local_err) { 1472 error_propagate(errp, local_err); 1473 return; 1474 } 1475 } 1476 1477 void pc_cpus_init(PCMachineState *pcms) 1478 { 1479 int i; 1480 const CPUArchIdList *possible_cpus; 1481 MachineState *ms = MACHINE(pcms); 1482 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1483 1484 /* Calculates the limit to CPU APIC ID values 1485 * 1486 * Limit for the APIC ID value, so that all 1487 * CPU APIC IDs are < pcms->apic_id_limit. 1488 * 1489 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1490 */ 1491 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1492 possible_cpus = mc->possible_cpu_arch_ids(ms); 1493 for (i = 0; i < smp_cpus; i++) { 1494 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, 1495 &error_fatal); 1496 } 1497 } 1498 1499 static void pc_build_feature_control_file(PCMachineState *pcms) 1500 { 1501 MachineState *ms = MACHINE(pcms); 1502 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1503 CPUX86State *env = &cpu->env; 1504 uint32_t unused, ecx, edx; 1505 uint64_t feature_control_bits = 0; 1506 uint64_t *val; 1507 1508 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1509 if (ecx & CPUID_EXT_VMX) { 1510 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1511 } 1512 1513 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1514 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1515 (env->mcg_cap & MCG_LMCE_P)) { 1516 feature_control_bits |= FEATURE_CONTROL_LMCE; 1517 } 1518 1519 if (!feature_control_bits) { 1520 return; 1521 } 1522 1523 val = g_malloc(sizeof(*val)); 1524 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1525 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1526 } 1527 1528 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1529 { 1530 if (cpus_count > 0xff) { 1531 /* If the number of CPUs can't be represented in 8 bits, the 1532 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1533 * to make old BIOSes fail more predictably. 1534 */ 1535 rtc_set_memory(rtc, 0x5f, 0); 1536 } else { 1537 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1538 } 1539 } 1540 1541 static 1542 void pc_machine_done(Notifier *notifier, void *data) 1543 { 1544 PCMachineState *pcms = container_of(notifier, 1545 PCMachineState, machine_done); 1546 PCIBus *bus = pcms->bus; 1547 1548 /* set the number of CPUs */ 1549 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1550 1551 if (bus) { 1552 int extra_hosts = 0; 1553 1554 QLIST_FOREACH(bus, &bus->child, sibling) { 1555 /* look for expander root buses */ 1556 if (pci_bus_is_root(bus)) { 1557 extra_hosts++; 1558 } 1559 } 1560 if (extra_hosts && pcms->fw_cfg) { 1561 uint64_t *val = g_malloc(sizeof(*val)); 1562 *val = cpu_to_le64(extra_hosts); 1563 fw_cfg_add_file(pcms->fw_cfg, 1564 "etc/extra-pci-roots", val, sizeof(*val)); 1565 } 1566 } 1567 1568 acpi_setup(); 1569 if (pcms->fw_cfg) { 1570 pc_build_smbios(pcms); 1571 pc_build_feature_control_file(pcms); 1572 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1573 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1574 } 1575 1576 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1577 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1578 1579 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1580 iommu->intr_eim != ON_OFF_AUTO_ON) { 1581 error_report("current -smp configuration requires " 1582 "Extended Interrupt Mode enabled. " 1583 "You can add an IOMMU using: " 1584 "-device intel-iommu,intremap=on,eim=on"); 1585 exit(EXIT_FAILURE); 1586 } 1587 } 1588 } 1589 1590 void pc_guest_info_init(PCMachineState *pcms) 1591 { 1592 int i; 1593 1594 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1595 pcms->numa_nodes = nb_numa_nodes; 1596 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1597 sizeof *pcms->node_mem); 1598 for (i = 0; i < nb_numa_nodes; i++) { 1599 pcms->node_mem[i] = numa_info[i].node_mem; 1600 } 1601 1602 pcms->machine_done.notify = pc_machine_done; 1603 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1604 } 1605 1606 /* setup pci memory address space mapping into system address space */ 1607 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1608 MemoryRegion *pci_address_space) 1609 { 1610 /* Set to lower priority than RAM */ 1611 memory_region_add_subregion_overlap(system_memory, 0x0, 1612 pci_address_space, -1); 1613 } 1614 1615 void pc_acpi_init(const char *default_dsdt) 1616 { 1617 char *filename; 1618 1619 if (acpi_tables != NULL) { 1620 /* manually set via -acpitable, leave it alone */ 1621 return; 1622 } 1623 1624 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1625 if (filename == NULL) { 1626 warn_report("failed to find %s", default_dsdt); 1627 } else { 1628 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1629 &error_abort); 1630 Error *err = NULL; 1631 1632 qemu_opt_set(opts, "file", filename, &error_abort); 1633 1634 acpi_table_add_builtin(opts, &err); 1635 if (err) { 1636 warn_reportf_err(err, "failed to load %s: ", filename); 1637 } 1638 g_free(filename); 1639 } 1640 } 1641 1642 void xen_load_linux(PCMachineState *pcms) 1643 { 1644 int i; 1645 FWCfgState *fw_cfg; 1646 1647 assert(MACHINE(pcms)->kernel_filename != NULL); 1648 1649 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1650 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1651 rom_set_fw(fw_cfg); 1652 1653 load_linux(pcms, fw_cfg); 1654 for (i = 0; i < nb_option_roms; i++) { 1655 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1656 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1657 !strcmp(option_rom[i].name, "multiboot.bin")); 1658 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1659 } 1660 pcms->fw_cfg = fw_cfg; 1661 } 1662 1663 void pc_memory_init(PCMachineState *pcms, 1664 MemoryRegion *system_memory, 1665 MemoryRegion *rom_memory, 1666 MemoryRegion **ram_memory) 1667 { 1668 int linux_boot, i; 1669 MemoryRegion *ram, *option_rom_mr; 1670 MemoryRegion *ram_below_4g, *ram_above_4g; 1671 FWCfgState *fw_cfg; 1672 MachineState *machine = MACHINE(pcms); 1673 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1674 1675 assert(machine->ram_size == pcms->below_4g_mem_size + 1676 pcms->above_4g_mem_size); 1677 1678 linux_boot = (machine->kernel_filename != NULL); 1679 1680 /* Allocate RAM. We allocate it as a single memory region and use 1681 * aliases to address portions of it, mostly for backwards compatibility 1682 * with older qemus that used qemu_ram_alloc(). 1683 */ 1684 ram = g_malloc(sizeof(*ram)); 1685 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1686 machine->ram_size); 1687 *ram_memory = ram; 1688 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1689 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1690 0, pcms->below_4g_mem_size); 1691 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1692 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1693 if (pcms->above_4g_mem_size > 0) { 1694 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1695 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1696 pcms->below_4g_mem_size, 1697 pcms->above_4g_mem_size); 1698 memory_region_add_subregion(system_memory, 0x100000000ULL, 1699 ram_above_4g); 1700 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1701 } 1702 1703 if (!pcmc->has_reserved_memory && 1704 (machine->ram_slots || 1705 (machine->maxram_size > machine->ram_size))) { 1706 MachineClass *mc = MACHINE_GET_CLASS(machine); 1707 1708 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1709 mc->name); 1710 exit(EXIT_FAILURE); 1711 } 1712 1713 /* always allocate the device memory information */ 1714 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1715 1716 /* initialize device memory address space */ 1717 if (pcmc->has_reserved_memory && 1718 (machine->ram_size < machine->maxram_size)) { 1719 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1720 1721 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1722 error_report("unsupported amount of memory slots: %"PRIu64, 1723 machine->ram_slots); 1724 exit(EXIT_FAILURE); 1725 } 1726 1727 if (QEMU_ALIGN_UP(machine->maxram_size, 1728 TARGET_PAGE_SIZE) != machine->maxram_size) { 1729 error_report("maximum memory size must by aligned to multiple of " 1730 "%d bytes", TARGET_PAGE_SIZE); 1731 exit(EXIT_FAILURE); 1732 } 1733 1734 machine->device_memory->base = 1735 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1736 1737 if (pcmc->enforce_aligned_dimm) { 1738 /* size device region assuming 1G page max alignment per slot */ 1739 device_mem_size += (1 * GiB) * machine->ram_slots; 1740 } 1741 1742 if ((machine->device_memory->base + device_mem_size) < 1743 device_mem_size) { 1744 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1745 machine->maxram_size); 1746 exit(EXIT_FAILURE); 1747 } 1748 1749 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1750 "device-memory", device_mem_size); 1751 memory_region_add_subregion(system_memory, machine->device_memory->base, 1752 &machine->device_memory->mr); 1753 } 1754 1755 /* Initialize PC system firmware */ 1756 pc_system_firmware_init(rom_memory, !pcmc->pci_enabled); 1757 1758 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1759 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1760 &error_fatal); 1761 if (pcmc->pci_enabled) { 1762 memory_region_set_readonly(option_rom_mr, true); 1763 } 1764 memory_region_add_subregion_overlap(rom_memory, 1765 PC_ROM_MIN_VGA, 1766 option_rom_mr, 1767 1); 1768 1769 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1770 1771 rom_set_fw(fw_cfg); 1772 1773 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1774 uint64_t *val = g_malloc(sizeof(*val)); 1775 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1776 uint64_t res_mem_end = machine->device_memory->base; 1777 1778 if (!pcmc->broken_reserved_end) { 1779 res_mem_end += memory_region_size(&machine->device_memory->mr); 1780 } 1781 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1782 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1783 } 1784 1785 if (linux_boot) { 1786 load_linux(pcms, fw_cfg); 1787 } 1788 1789 for (i = 0; i < nb_option_roms; i++) { 1790 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1791 } 1792 pcms->fw_cfg = fw_cfg; 1793 1794 /* Init default IOAPIC address space */ 1795 pcms->ioapic_as = &address_space_memory; 1796 } 1797 1798 /* 1799 * The 64bit pci hole starts after "above 4G RAM" and 1800 * potentially the space reserved for memory hotplug. 1801 */ 1802 uint64_t pc_pci_hole64_start(void) 1803 { 1804 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1805 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1806 MachineState *ms = MACHINE(pcms); 1807 uint64_t hole64_start = 0; 1808 1809 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1810 hole64_start = ms->device_memory->base; 1811 if (!pcmc->broken_reserved_end) { 1812 hole64_start += memory_region_size(&ms->device_memory->mr); 1813 } 1814 } else { 1815 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1816 } 1817 1818 return ROUND_UP(hole64_start, 1 * GiB); 1819 } 1820 1821 qemu_irq pc_allocate_cpu_irq(void) 1822 { 1823 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1824 } 1825 1826 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1827 { 1828 DeviceState *dev = NULL; 1829 1830 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1831 if (pci_bus) { 1832 PCIDevice *pcidev = pci_vga_init(pci_bus); 1833 dev = pcidev ? &pcidev->qdev : NULL; 1834 } else if (isa_bus) { 1835 ISADevice *isadev = isa_vga_init(isa_bus); 1836 dev = isadev ? DEVICE(isadev) : NULL; 1837 } 1838 rom_reset_order_override(); 1839 return dev; 1840 } 1841 1842 static const MemoryRegionOps ioport80_io_ops = { 1843 .write = ioport80_write, 1844 .read = ioport80_read, 1845 .endianness = DEVICE_NATIVE_ENDIAN, 1846 .impl = { 1847 .min_access_size = 1, 1848 .max_access_size = 1, 1849 }, 1850 }; 1851 1852 static const MemoryRegionOps ioportF0_io_ops = { 1853 .write = ioportF0_write, 1854 .read = ioportF0_read, 1855 .endianness = DEVICE_NATIVE_ENDIAN, 1856 .impl = { 1857 .min_access_size = 1, 1858 .max_access_size = 1, 1859 }, 1860 }; 1861 1862 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1863 { 1864 int i; 1865 DriveInfo *fd[MAX_FD]; 1866 qemu_irq *a20_line; 1867 ISADevice *i8042, *port92, *vmmouse; 1868 1869 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1870 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1871 1872 for (i = 0; i < MAX_FD; i++) { 1873 fd[i] = drive_get(IF_FLOPPY, 0, i); 1874 create_fdctrl |= !!fd[i]; 1875 } 1876 if (create_fdctrl) { 1877 fdctrl_init_isa(isa_bus, fd); 1878 } 1879 1880 i8042 = isa_create_simple(isa_bus, "i8042"); 1881 if (!no_vmport) { 1882 vmport_init(isa_bus); 1883 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1884 } else { 1885 vmmouse = NULL; 1886 } 1887 if (vmmouse) { 1888 DeviceState *dev = DEVICE(vmmouse); 1889 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1890 qdev_init_nofail(dev); 1891 } 1892 port92 = isa_create_simple(isa_bus, "port92"); 1893 1894 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1895 i8042_setup_a20_line(i8042, a20_line[0]); 1896 port92_init(port92, a20_line[1]); 1897 g_free(a20_line); 1898 } 1899 1900 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1901 ISADevice **rtc_state, 1902 bool create_fdctrl, 1903 bool no_vmport, 1904 bool has_pit, 1905 uint32_t hpet_irqs) 1906 { 1907 int i; 1908 DeviceState *hpet = NULL; 1909 int pit_isa_irq = 0; 1910 qemu_irq pit_alt_irq = NULL; 1911 qemu_irq rtc_irq = NULL; 1912 ISADevice *pit = NULL; 1913 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1914 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1915 1916 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1917 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1918 1919 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1920 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1921 1922 /* 1923 * Check if an HPET shall be created. 1924 * 1925 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1926 * when the HPET wants to take over. Thus we have to disable the latter. 1927 */ 1928 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1929 /* In order to set property, here not using sysbus_try_create_simple */ 1930 hpet = qdev_try_create(NULL, TYPE_HPET); 1931 if (hpet) { 1932 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1933 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1934 * IRQ8 and IRQ2. 1935 */ 1936 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1937 HPET_INTCAP, NULL); 1938 if (!compat) { 1939 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1940 } 1941 qdev_init_nofail(hpet); 1942 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1943 1944 for (i = 0; i < GSI_NUM_PINS; i++) { 1945 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1946 } 1947 pit_isa_irq = -1; 1948 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1949 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1950 } 1951 } 1952 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1953 1954 qemu_register_boot_set(pc_boot_set, *rtc_state); 1955 1956 if (!xen_enabled() && has_pit) { 1957 if (kvm_pit_in_kernel()) { 1958 pit = kvm_pit_init(isa_bus, 0x40); 1959 } else { 1960 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1961 } 1962 if (hpet) { 1963 /* connect PIT to output control line of the HPET */ 1964 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1965 } 1966 pcspk_init(isa_bus, pit); 1967 } 1968 1969 i8257_dma_init(isa_bus, 0); 1970 1971 /* Super I/O */ 1972 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 1973 } 1974 1975 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1976 { 1977 int i; 1978 1979 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1980 for (i = 0; i < nb_nics; i++) { 1981 NICInfo *nd = &nd_table[i]; 1982 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1983 1984 if (g_str_equal(model, "ne2k_isa")) { 1985 pc_init_ne2k_isa(isa_bus, nd); 1986 } else { 1987 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1988 } 1989 } 1990 rom_reset_order_override(); 1991 } 1992 1993 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1994 { 1995 DeviceState *dev; 1996 SysBusDevice *d; 1997 unsigned int i; 1998 1999 if (kvm_ioapic_in_kernel()) { 2000 dev = qdev_create(NULL, "kvm-ioapic"); 2001 } else { 2002 dev = qdev_create(NULL, "ioapic"); 2003 } 2004 if (parent_name) { 2005 object_property_add_child(object_resolve_path(parent_name, NULL), 2006 "ioapic", OBJECT(dev), NULL); 2007 } 2008 qdev_init_nofail(dev); 2009 d = SYS_BUS_DEVICE(dev); 2010 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2011 2012 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2013 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2014 } 2015 } 2016 2017 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2018 Error **errp) 2019 { 2020 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2021 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2022 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2023 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2024 2025 /* 2026 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2027 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2028 * addition to cover this case. 2029 */ 2030 if (!pcms->acpi_dev || !acpi_enabled) { 2031 error_setg(errp, 2032 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2033 return; 2034 } 2035 2036 if (is_nvdimm && !pcms->acpi_nvdimm_state.is_enabled) { 2037 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2038 return; 2039 } 2040 2041 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2042 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2043 } 2044 2045 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2046 DeviceState *dev, Error **errp) 2047 { 2048 HotplugHandlerClass *hhc; 2049 Error *local_err = NULL; 2050 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2051 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2052 2053 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2054 if (local_err) { 2055 goto out; 2056 } 2057 2058 if (is_nvdimm) { 2059 nvdimm_plug(&pcms->acpi_nvdimm_state); 2060 } 2061 2062 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 2063 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2064 out: 2065 error_propagate(errp, local_err); 2066 } 2067 2068 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2069 DeviceState *dev, Error **errp) 2070 { 2071 HotplugHandlerClass *hhc; 2072 Error *local_err = NULL; 2073 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2074 2075 /* 2076 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2077 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2078 * addition to cover this case. 2079 */ 2080 if (!pcms->acpi_dev || !acpi_enabled) { 2081 error_setg(&local_err, 2082 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2083 goto out; 2084 } 2085 2086 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2087 error_setg(&local_err, 2088 "nvdimm device hot unplug is not supported yet."); 2089 goto out; 2090 } 2091 2092 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 2093 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2094 2095 out: 2096 error_propagate(errp, local_err); 2097 } 2098 2099 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2100 DeviceState *dev, Error **errp) 2101 { 2102 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2103 HotplugHandlerClass *hhc; 2104 Error *local_err = NULL; 2105 2106 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 2107 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2108 2109 if (local_err) { 2110 goto out; 2111 } 2112 2113 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2114 object_unparent(OBJECT(dev)); 2115 2116 out: 2117 error_propagate(errp, local_err); 2118 } 2119 2120 static int pc_apic_cmp(const void *a, const void *b) 2121 { 2122 CPUArchId *apic_a = (CPUArchId *)a; 2123 CPUArchId *apic_b = (CPUArchId *)b; 2124 2125 return apic_a->arch_id - apic_b->arch_id; 2126 } 2127 2128 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2129 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2130 * entry corresponding to CPU's apic_id returns NULL. 2131 */ 2132 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2133 { 2134 CPUArchId apic_id, *found_cpu; 2135 2136 apic_id.arch_id = id; 2137 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2138 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2139 pc_apic_cmp); 2140 if (found_cpu && idx) { 2141 *idx = found_cpu - ms->possible_cpus->cpus; 2142 } 2143 return found_cpu; 2144 } 2145 2146 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2147 DeviceState *dev, Error **errp) 2148 { 2149 CPUArchId *found_cpu; 2150 HotplugHandlerClass *hhc; 2151 Error *local_err = NULL; 2152 X86CPU *cpu = X86_CPU(dev); 2153 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2154 2155 if (pcms->acpi_dev) { 2156 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 2157 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2158 if (local_err) { 2159 goto out; 2160 } 2161 } 2162 2163 /* increment the number of CPUs */ 2164 pcms->boot_cpus++; 2165 if (pcms->rtc) { 2166 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2167 } 2168 if (pcms->fw_cfg) { 2169 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2170 } 2171 2172 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2173 found_cpu->cpu = OBJECT(dev); 2174 out: 2175 error_propagate(errp, local_err); 2176 } 2177 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2178 DeviceState *dev, Error **errp) 2179 { 2180 int idx = -1; 2181 HotplugHandlerClass *hhc; 2182 Error *local_err = NULL; 2183 X86CPU *cpu = X86_CPU(dev); 2184 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2185 2186 if (!pcms->acpi_dev) { 2187 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2188 goto out; 2189 } 2190 2191 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2192 assert(idx != -1); 2193 if (idx == 0) { 2194 error_setg(&local_err, "Boot CPU is unpluggable"); 2195 goto out; 2196 } 2197 2198 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 2199 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2200 2201 if (local_err) { 2202 goto out; 2203 } 2204 2205 out: 2206 error_propagate(errp, local_err); 2207 2208 } 2209 2210 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2211 DeviceState *dev, Error **errp) 2212 { 2213 CPUArchId *found_cpu; 2214 HotplugHandlerClass *hhc; 2215 Error *local_err = NULL; 2216 X86CPU *cpu = X86_CPU(dev); 2217 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2218 2219 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 2220 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2221 2222 if (local_err) { 2223 goto out; 2224 } 2225 2226 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2227 found_cpu->cpu = NULL; 2228 object_unparent(OBJECT(dev)); 2229 2230 /* decrement the number of CPUs */ 2231 pcms->boot_cpus--; 2232 /* Update the number of CPUs in CMOS */ 2233 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2234 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2235 out: 2236 error_propagate(errp, local_err); 2237 } 2238 2239 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2240 DeviceState *dev, Error **errp) 2241 { 2242 int idx; 2243 CPUState *cs; 2244 CPUArchId *cpu_slot; 2245 X86CPUTopoInfo topo; 2246 X86CPU *cpu = X86_CPU(dev); 2247 MachineState *ms = MACHINE(hotplug_dev); 2248 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2249 2250 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2251 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2252 ms->cpu_type); 2253 return; 2254 } 2255 2256 /* if APIC ID is not set, set it based on socket/core/thread properties */ 2257 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2258 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 2259 2260 if (cpu->socket_id < 0) { 2261 error_setg(errp, "CPU socket-id is not set"); 2262 return; 2263 } else if (cpu->socket_id > max_socket) { 2264 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2265 cpu->socket_id, max_socket); 2266 return; 2267 } 2268 if (cpu->core_id < 0) { 2269 error_setg(errp, "CPU core-id is not set"); 2270 return; 2271 } else if (cpu->core_id > (smp_cores - 1)) { 2272 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2273 cpu->core_id, smp_cores - 1); 2274 return; 2275 } 2276 if (cpu->thread_id < 0) { 2277 error_setg(errp, "CPU thread-id is not set"); 2278 return; 2279 } else if (cpu->thread_id > (smp_threads - 1)) { 2280 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2281 cpu->thread_id, smp_threads - 1); 2282 return; 2283 } 2284 2285 topo.pkg_id = cpu->socket_id; 2286 topo.core_id = cpu->core_id; 2287 topo.smt_id = cpu->thread_id; 2288 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 2289 } 2290 2291 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2292 if (!cpu_slot) { 2293 MachineState *ms = MACHINE(pcms); 2294 2295 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2296 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 2297 " APIC ID %" PRIu32 ", valid index range 0:%d", 2298 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 2299 ms->possible_cpus->len - 1); 2300 return; 2301 } 2302 2303 if (cpu_slot->cpu) { 2304 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2305 idx, cpu->apic_id); 2306 return; 2307 } 2308 2309 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2310 * so that machine_query_hotpluggable_cpus would show correct values 2311 */ 2312 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2313 * once -smp refactoring is complete and there will be CPU private 2314 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2315 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2316 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2317 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2318 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2319 return; 2320 } 2321 cpu->socket_id = topo.pkg_id; 2322 2323 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2324 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2325 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2326 return; 2327 } 2328 cpu->core_id = topo.core_id; 2329 2330 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2331 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2332 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2333 return; 2334 } 2335 cpu->thread_id = topo.smt_id; 2336 2337 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) { 2338 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2339 return; 2340 } 2341 2342 cs = CPU(cpu); 2343 cs->cpu_index = idx; 2344 2345 numa_cpu_pre_plug(cpu_slot, dev, errp); 2346 } 2347 2348 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2349 DeviceState *dev, Error **errp) 2350 { 2351 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2352 pc_memory_pre_plug(hotplug_dev, dev, errp); 2353 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2354 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2355 } 2356 } 2357 2358 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2359 DeviceState *dev, Error **errp) 2360 { 2361 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2362 pc_memory_plug(hotplug_dev, dev, errp); 2363 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2364 pc_cpu_plug(hotplug_dev, dev, errp); 2365 } 2366 } 2367 2368 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2369 DeviceState *dev, Error **errp) 2370 { 2371 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2372 pc_memory_unplug_request(hotplug_dev, dev, errp); 2373 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2374 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2375 } else { 2376 error_setg(errp, "acpi: device unplug request for not supported device" 2377 " type: %s", object_get_typename(OBJECT(dev))); 2378 } 2379 } 2380 2381 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2382 DeviceState *dev, Error **errp) 2383 { 2384 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2385 pc_memory_unplug(hotplug_dev, dev, errp); 2386 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2387 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2388 } else { 2389 error_setg(errp, "acpi: device unplug for not supported device" 2390 " type: %s", object_get_typename(OBJECT(dev))); 2391 } 2392 } 2393 2394 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 2395 DeviceState *dev) 2396 { 2397 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2398 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2399 return HOTPLUG_HANDLER(machine); 2400 } 2401 2402 return NULL; 2403 } 2404 2405 static void 2406 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2407 const char *name, void *opaque, 2408 Error **errp) 2409 { 2410 MachineState *ms = MACHINE(obj); 2411 int64_t value = memory_region_size(&ms->device_memory->mr); 2412 2413 visit_type_int(v, name, &value, errp); 2414 } 2415 2416 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2417 const char *name, void *opaque, 2418 Error **errp) 2419 { 2420 PCMachineState *pcms = PC_MACHINE(obj); 2421 uint64_t value = pcms->max_ram_below_4g; 2422 2423 visit_type_size(v, name, &value, errp); 2424 } 2425 2426 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2427 const char *name, void *opaque, 2428 Error **errp) 2429 { 2430 PCMachineState *pcms = PC_MACHINE(obj); 2431 Error *error = NULL; 2432 uint64_t value; 2433 2434 visit_type_size(v, name, &value, &error); 2435 if (error) { 2436 error_propagate(errp, error); 2437 return; 2438 } 2439 if (value > 4 * GiB) { 2440 error_setg(&error, 2441 "Machine option 'max-ram-below-4g=%"PRIu64 2442 "' expects size less than or equal to 4G", value); 2443 error_propagate(errp, error); 2444 return; 2445 } 2446 2447 if (value < 1 * MiB) { 2448 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2449 "BIOS may not work with less than 1MiB", value); 2450 } 2451 2452 pcms->max_ram_below_4g = value; 2453 } 2454 2455 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2456 void *opaque, Error **errp) 2457 { 2458 PCMachineState *pcms = PC_MACHINE(obj); 2459 OnOffAuto vmport = pcms->vmport; 2460 2461 visit_type_OnOffAuto(v, name, &vmport, errp); 2462 } 2463 2464 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2465 void *opaque, Error **errp) 2466 { 2467 PCMachineState *pcms = PC_MACHINE(obj); 2468 2469 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2470 } 2471 2472 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2473 { 2474 bool smm_available = false; 2475 2476 if (pcms->smm == ON_OFF_AUTO_OFF) { 2477 return false; 2478 } 2479 2480 if (tcg_enabled() || qtest_enabled()) { 2481 smm_available = true; 2482 } else if (kvm_enabled()) { 2483 smm_available = kvm_has_smm(); 2484 } 2485 2486 if (smm_available) { 2487 return true; 2488 } 2489 2490 if (pcms->smm == ON_OFF_AUTO_ON) { 2491 error_report("System Management Mode not supported by this hypervisor."); 2492 exit(1); 2493 } 2494 return false; 2495 } 2496 2497 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2498 void *opaque, Error **errp) 2499 { 2500 PCMachineState *pcms = PC_MACHINE(obj); 2501 OnOffAuto smm = pcms->smm; 2502 2503 visit_type_OnOffAuto(v, name, &smm, errp); 2504 } 2505 2506 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2507 void *opaque, Error **errp) 2508 { 2509 PCMachineState *pcms = PC_MACHINE(obj); 2510 2511 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2512 } 2513 2514 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 2515 { 2516 PCMachineState *pcms = PC_MACHINE(obj); 2517 2518 return pcms->acpi_nvdimm_state.is_enabled; 2519 } 2520 2521 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 2522 { 2523 PCMachineState *pcms = PC_MACHINE(obj); 2524 2525 pcms->acpi_nvdimm_state.is_enabled = value; 2526 } 2527 2528 static char *pc_machine_get_nvdimm_persistence(Object *obj, Error **errp) 2529 { 2530 PCMachineState *pcms = PC_MACHINE(obj); 2531 2532 return g_strdup(pcms->acpi_nvdimm_state.persistence_string); 2533 } 2534 2535 static void pc_machine_set_nvdimm_persistence(Object *obj, const char *value, 2536 Error **errp) 2537 { 2538 PCMachineState *pcms = PC_MACHINE(obj); 2539 AcpiNVDIMMState *nvdimm_state = &pcms->acpi_nvdimm_state; 2540 2541 if (strcmp(value, "cpu") == 0) 2542 nvdimm_state->persistence = 3; 2543 else if (strcmp(value, "mem-ctrl") == 0) 2544 nvdimm_state->persistence = 2; 2545 else { 2546 error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", 2547 value); 2548 return; 2549 } 2550 2551 g_free(nvdimm_state->persistence_string); 2552 nvdimm_state->persistence_string = g_strdup(value); 2553 } 2554 2555 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2556 { 2557 PCMachineState *pcms = PC_MACHINE(obj); 2558 2559 return pcms->smbus_enabled; 2560 } 2561 2562 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2563 { 2564 PCMachineState *pcms = PC_MACHINE(obj); 2565 2566 pcms->smbus_enabled = value; 2567 } 2568 2569 static bool pc_machine_get_sata(Object *obj, Error **errp) 2570 { 2571 PCMachineState *pcms = PC_MACHINE(obj); 2572 2573 return pcms->sata_enabled; 2574 } 2575 2576 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2577 { 2578 PCMachineState *pcms = PC_MACHINE(obj); 2579 2580 pcms->sata_enabled = value; 2581 } 2582 2583 static bool pc_machine_get_pit(Object *obj, Error **errp) 2584 { 2585 PCMachineState *pcms = PC_MACHINE(obj); 2586 2587 return pcms->pit_enabled; 2588 } 2589 2590 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2591 { 2592 PCMachineState *pcms = PC_MACHINE(obj); 2593 2594 pcms->pit_enabled = value; 2595 } 2596 2597 static void pc_machine_initfn(Object *obj) 2598 { 2599 PCMachineState *pcms = PC_MACHINE(obj); 2600 2601 pcms->max_ram_below_4g = 0; /* use default */ 2602 pcms->smm = ON_OFF_AUTO_AUTO; 2603 pcms->vmport = ON_OFF_AUTO_AUTO; 2604 /* nvdimm is disabled on default. */ 2605 pcms->acpi_nvdimm_state.is_enabled = false; 2606 /* acpi build is enabled by default if machine supports it */ 2607 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2608 pcms->smbus_enabled = true; 2609 pcms->sata_enabled = true; 2610 pcms->pit_enabled = true; 2611 } 2612 2613 static void pc_machine_reset(void) 2614 { 2615 CPUState *cs; 2616 X86CPU *cpu; 2617 2618 qemu_devices_reset(); 2619 2620 /* Reset APIC after devices have been reset to cancel 2621 * any changes that qemu_devices_reset() might have done. 2622 */ 2623 CPU_FOREACH(cs) { 2624 cpu = X86_CPU(cs); 2625 2626 if (cpu->apic_state) { 2627 device_reset(cpu->apic_state); 2628 } 2629 } 2630 } 2631 2632 static CpuInstanceProperties 2633 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2634 { 2635 MachineClass *mc = MACHINE_GET_CLASS(ms); 2636 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2637 2638 assert(cpu_index < possible_cpus->len); 2639 return possible_cpus->cpus[cpu_index].props; 2640 } 2641 2642 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2643 { 2644 X86CPUTopoInfo topo; 2645 2646 assert(idx < ms->possible_cpus->len); 2647 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2648 smp_cores, smp_threads, &topo); 2649 return topo.pkg_id % nb_numa_nodes; 2650 } 2651 2652 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2653 { 2654 int i; 2655 2656 if (ms->possible_cpus) { 2657 /* 2658 * make sure that max_cpus hasn't changed since the first use, i.e. 2659 * -smp hasn't been parsed after it 2660 */ 2661 assert(ms->possible_cpus->len == max_cpus); 2662 return ms->possible_cpus; 2663 } 2664 2665 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2666 sizeof(CPUArchId) * max_cpus); 2667 ms->possible_cpus->len = max_cpus; 2668 for (i = 0; i < ms->possible_cpus->len; i++) { 2669 X86CPUTopoInfo topo; 2670 2671 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2672 ms->possible_cpus->cpus[i].vcpus_count = 1; 2673 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 2674 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2675 smp_cores, smp_threads, &topo); 2676 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2677 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2678 ms->possible_cpus->cpus[i].props.has_core_id = true; 2679 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2680 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2681 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2682 } 2683 return ms->possible_cpus; 2684 } 2685 2686 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2687 { 2688 /* cpu index isn't used */ 2689 CPUState *cs; 2690 2691 CPU_FOREACH(cs) { 2692 X86CPU *cpu = X86_CPU(cs); 2693 2694 if (!cpu->apic_state) { 2695 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2696 } else { 2697 apic_deliver_nmi(cpu->apic_state); 2698 } 2699 } 2700 } 2701 2702 static void pc_machine_class_init(ObjectClass *oc, void *data) 2703 { 2704 MachineClass *mc = MACHINE_CLASS(oc); 2705 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2706 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2707 NMIClass *nc = NMI_CLASS(oc); 2708 2709 pcmc->pci_enabled = true; 2710 pcmc->has_acpi_build = true; 2711 pcmc->rsdp_in_ram = true; 2712 pcmc->smbios_defaults = true; 2713 pcmc->smbios_uuid_encoded = true; 2714 pcmc->gigabyte_align = true; 2715 pcmc->has_reserved_memory = true; 2716 pcmc->kvmclock_enabled = true; 2717 pcmc->enforce_aligned_dimm = true; 2718 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2719 * to be used at the moment, 32K should be enough for a while. */ 2720 pcmc->acpi_data_size = 0x20000 + 0x8000; 2721 pcmc->save_tsc_khz = true; 2722 pcmc->linuxboot_dma_enabled = true; 2723 assert(!mc->get_hotplug_handler); 2724 mc->get_hotplug_handler = pc_get_hotpug_handler; 2725 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2726 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2727 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2728 mc->auto_enable_numa_with_memhp = true; 2729 mc->has_hotpluggable_cpus = true; 2730 mc->default_boot_order = "cad"; 2731 mc->hot_add_cpu = pc_hot_add_cpu; 2732 mc->block_default_type = IF_IDE; 2733 mc->max_cpus = 255; 2734 mc->reset = pc_machine_reset; 2735 hc->pre_plug = pc_machine_device_pre_plug_cb; 2736 hc->plug = pc_machine_device_plug_cb; 2737 hc->unplug_request = pc_machine_device_unplug_request_cb; 2738 hc->unplug = pc_machine_device_unplug_cb; 2739 nc->nmi_monitor_handler = x86_nmi; 2740 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2741 2742 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2743 pc_machine_get_device_memory_region_size, NULL, 2744 NULL, NULL, &error_abort); 2745 2746 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2747 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2748 NULL, NULL, &error_abort); 2749 2750 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2751 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2752 2753 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2754 pc_machine_get_smm, pc_machine_set_smm, 2755 NULL, NULL, &error_abort); 2756 object_class_property_set_description(oc, PC_MACHINE_SMM, 2757 "Enable SMM (pc & q35)", &error_abort); 2758 2759 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2760 pc_machine_get_vmport, pc_machine_set_vmport, 2761 NULL, NULL, &error_abort); 2762 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2763 "Enable vmport (pc & q35)", &error_abort); 2764 2765 object_class_property_add_bool(oc, PC_MACHINE_NVDIMM, 2766 pc_machine_get_nvdimm, pc_machine_set_nvdimm, &error_abort); 2767 2768 object_class_property_add_str(oc, PC_MACHINE_NVDIMM_PERSIST, 2769 pc_machine_get_nvdimm_persistence, 2770 pc_machine_set_nvdimm_persistence, &error_abort); 2771 2772 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2773 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2774 2775 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2776 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2777 2778 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2779 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2780 } 2781 2782 static const TypeInfo pc_machine_info = { 2783 .name = TYPE_PC_MACHINE, 2784 .parent = TYPE_MACHINE, 2785 .abstract = true, 2786 .instance_size = sizeof(PCMachineState), 2787 .instance_init = pc_machine_initfn, 2788 .class_size = sizeof(PCMachineClass), 2789 .class_init = pc_machine_class_init, 2790 .interfaces = (InterfaceInfo[]) { 2791 { TYPE_HOTPLUG_HANDLER }, 2792 { TYPE_NMI }, 2793 { } 2794 }, 2795 }; 2796 2797 static void pc_machine_register_types(void) 2798 { 2799 type_register_static(&pc_machine_info); 2800 } 2801 2802 type_init(pc_machine_register_types) 2803