1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/nvram/fw_cfg.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/smbios/smbios.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "multiboot.h" 40 #include "hw/timer/mc146818rtc.h" 41 #include "hw/timer/i8254.h" 42 #include "hw/audio/pcspk.h" 43 #include "hw/pci/msi.h" 44 #include "hw/sysbus.h" 45 #include "sysemu/sysemu.h" 46 #include "sysemu/numa.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/qtest.h" 49 #include "kvm_i386.h" 50 #include "hw/xen/xen.h" 51 #include "sysemu/block-backend.h" 52 #include "hw/block/block.h" 53 #include "ui/qemu-spice.h" 54 #include "exec/memory.h" 55 #include "exec/address-spaces.h" 56 #include "sysemu/arch_init.h" 57 #include "qemu/bitmap.h" 58 #include "qemu/config-file.h" 59 #include "qemu/error-report.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/boards.h" 63 #include "hw/pci/pci_host.h" 64 #include "acpi-build.h" 65 #include "hw/mem/pc-dimm.h" 66 #include "qapi/visitor.h" 67 #include "qapi-visit.h" 68 #include "qom/cpu.h" 69 70 /* debug PC/ISA interrupts */ 71 //#define DEBUG_IRQ 72 73 #ifdef DEBUG_IRQ 74 #define DPRINTF(fmt, ...) \ 75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 76 #else 77 #define DPRINTF(fmt, ...) 78 #endif 79 80 #define BIOS_CFG_IOPORT 0x510 81 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 82 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 83 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 84 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 85 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 86 87 #define E820_NR_ENTRIES 16 88 89 struct e820_entry { 90 uint64_t address; 91 uint64_t length; 92 uint32_t type; 93 } QEMU_PACKED __attribute((__aligned__(4))); 94 95 struct e820_table { 96 uint32_t count; 97 struct e820_entry entry[E820_NR_ENTRIES]; 98 } QEMU_PACKED __attribute((__aligned__(4))); 99 100 static struct e820_table e820_reserve; 101 static struct e820_entry *e820_table; 102 static unsigned e820_entries; 103 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 104 105 void gsi_handler(void *opaque, int n, int level) 106 { 107 GSIState *s = opaque; 108 109 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 110 if (n < ISA_NUM_IRQS) { 111 qemu_set_irq(s->i8259_irq[n], level); 112 } 113 qemu_set_irq(s->ioapic_irq[n], level); 114 } 115 116 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 117 unsigned size) 118 { 119 } 120 121 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 122 { 123 return 0xffffffffffffffffULL; 124 } 125 126 /* MSDOS compatibility mode FPU exception support */ 127 static qemu_irq ferr_irq; 128 129 void pc_register_ferr_irq(qemu_irq irq) 130 { 131 ferr_irq = irq; 132 } 133 134 /* XXX: add IGNNE support */ 135 void cpu_set_ferr(CPUX86State *s) 136 { 137 qemu_irq_raise(ferr_irq); 138 } 139 140 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 141 unsigned size) 142 { 143 qemu_irq_lower(ferr_irq); 144 } 145 146 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 147 { 148 return 0xffffffffffffffffULL; 149 } 150 151 /* TSC handling */ 152 uint64_t cpu_get_tsc(CPUX86State *env) 153 { 154 return cpu_get_ticks(); 155 } 156 157 /* IRQ handling */ 158 int cpu_get_pic_interrupt(CPUX86State *env) 159 { 160 X86CPU *cpu = x86_env_get_cpu(env); 161 int intno; 162 163 intno = apic_get_interrupt(cpu->apic_state); 164 if (intno >= 0) { 165 return intno; 166 } 167 /* read the irq from the PIC */ 168 if (!apic_accept_pic_intr(cpu->apic_state)) { 169 return -1; 170 } 171 172 intno = pic_read_irq(isa_pic); 173 return intno; 174 } 175 176 static void pic_irq_request(void *opaque, int irq, int level) 177 { 178 CPUState *cs = first_cpu; 179 X86CPU *cpu = X86_CPU(cs); 180 181 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 182 if (cpu->apic_state) { 183 CPU_FOREACH(cs) { 184 cpu = X86_CPU(cs); 185 if (apic_accept_pic_intr(cpu->apic_state)) { 186 apic_deliver_pic_intr(cpu->apic_state, level); 187 } 188 } 189 } else { 190 if (level) { 191 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 192 } else { 193 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 194 } 195 } 196 } 197 198 /* PC cmos mappings */ 199 200 #define REG_EQUIPMENT_BYTE 0x14 201 202 static int cmos_get_fd_drive_type(FDriveType fd0) 203 { 204 int val; 205 206 switch (fd0) { 207 case FDRIVE_DRV_144: 208 /* 1.44 Mb 3"5 drive */ 209 val = 4; 210 break; 211 case FDRIVE_DRV_288: 212 /* 2.88 Mb 3"5 drive */ 213 val = 5; 214 break; 215 case FDRIVE_DRV_120: 216 /* 1.2 Mb 5"5 drive */ 217 val = 2; 218 break; 219 case FDRIVE_DRV_NONE: 220 default: 221 val = 0; 222 break; 223 } 224 return val; 225 } 226 227 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 228 int16_t cylinders, int8_t heads, int8_t sectors) 229 { 230 rtc_set_memory(s, type_ofs, 47); 231 rtc_set_memory(s, info_ofs, cylinders); 232 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 233 rtc_set_memory(s, info_ofs + 2, heads); 234 rtc_set_memory(s, info_ofs + 3, 0xff); 235 rtc_set_memory(s, info_ofs + 4, 0xff); 236 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 237 rtc_set_memory(s, info_ofs + 6, cylinders); 238 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 239 rtc_set_memory(s, info_ofs + 8, sectors); 240 } 241 242 /* convert boot_device letter to something recognizable by the bios */ 243 static int boot_device2nibble(char boot_device) 244 { 245 switch(boot_device) { 246 case 'a': 247 case 'b': 248 return 0x01; /* floppy boot */ 249 case 'c': 250 return 0x02; /* hard drive boot */ 251 case 'd': 252 return 0x03; /* CD-ROM boot */ 253 case 'n': 254 return 0x04; /* Network boot */ 255 } 256 return 0; 257 } 258 259 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 260 { 261 #define PC_MAX_BOOT_DEVICES 3 262 int nbds, bds[3] = { 0, }; 263 int i; 264 265 nbds = strlen(boot_device); 266 if (nbds > PC_MAX_BOOT_DEVICES) { 267 error_setg(errp, "Too many boot devices for PC"); 268 return; 269 } 270 for (i = 0; i < nbds; i++) { 271 bds[i] = boot_device2nibble(boot_device[i]); 272 if (bds[i] == 0) { 273 error_setg(errp, "Invalid boot device for PC: '%c'", 274 boot_device[i]); 275 return; 276 } 277 } 278 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 279 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 280 } 281 282 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 283 { 284 set_boot_dev(opaque, boot_device, errp); 285 } 286 287 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 288 { 289 int val, nb, i; 290 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 291 292 /* floppy type */ 293 if (floppy) { 294 for (i = 0; i < 2; i++) { 295 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 296 } 297 } 298 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 299 cmos_get_fd_drive_type(fd_type[1]); 300 rtc_set_memory(rtc_state, 0x10, val); 301 302 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 303 nb = 0; 304 if (fd_type[0] < FDRIVE_DRV_NONE) { 305 nb++; 306 } 307 if (fd_type[1] < FDRIVE_DRV_NONE) { 308 nb++; 309 } 310 switch (nb) { 311 case 0: 312 break; 313 case 1: 314 val |= 0x01; /* 1 drive, ready for boot */ 315 break; 316 case 2: 317 val |= 0x41; /* 2 drives, ready for boot */ 318 break; 319 } 320 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 321 } 322 323 typedef struct pc_cmos_init_late_arg { 324 ISADevice *rtc_state; 325 BusState *idebus[2]; 326 } pc_cmos_init_late_arg; 327 328 typedef struct check_fdc_state { 329 ISADevice *floppy; 330 bool multiple; 331 } CheckFdcState; 332 333 static int check_fdc(Object *obj, void *opaque) 334 { 335 CheckFdcState *state = opaque; 336 Object *fdc; 337 uint32_t iobase; 338 Error *local_err = NULL; 339 340 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 341 if (!fdc) { 342 return 0; 343 } 344 345 iobase = object_property_get_int(obj, "iobase", &local_err); 346 if (local_err || iobase != 0x3f0) { 347 error_free(local_err); 348 return 0; 349 } 350 351 if (state->floppy) { 352 state->multiple = true; 353 } else { 354 state->floppy = ISA_DEVICE(obj); 355 } 356 return 0; 357 } 358 359 static const char * const fdc_container_path[] = { 360 "/unattached", "/peripheral", "/peripheral-anon" 361 }; 362 363 /* 364 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 365 * and ACPI objects. 366 */ 367 ISADevice *pc_find_fdc0(void) 368 { 369 int i; 370 Object *container; 371 CheckFdcState state = { 0 }; 372 373 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 374 container = container_get(qdev_get_machine(), fdc_container_path[i]); 375 object_child_foreach(container, check_fdc, &state); 376 } 377 378 if (state.multiple) { 379 error_report("warning: multiple floppy disk controllers with " 380 "iobase=0x3f0 have been found;\n" 381 "the one being picked for CMOS setup might not reflect " 382 "your intent"); 383 } 384 385 return state.floppy; 386 } 387 388 static void pc_cmos_init_late(void *opaque) 389 { 390 pc_cmos_init_late_arg *arg = opaque; 391 ISADevice *s = arg->rtc_state; 392 int16_t cylinders; 393 int8_t heads, sectors; 394 int val; 395 int i, trans; 396 397 val = 0; 398 if (ide_get_geometry(arg->idebus[0], 0, 399 &cylinders, &heads, §ors) >= 0) { 400 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 401 val |= 0xf0; 402 } 403 if (ide_get_geometry(arg->idebus[0], 1, 404 &cylinders, &heads, §ors) >= 0) { 405 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 406 val |= 0x0f; 407 } 408 rtc_set_memory(s, 0x12, val); 409 410 val = 0; 411 for (i = 0; i < 4; i++) { 412 /* NOTE: ide_get_geometry() returns the physical 413 geometry. It is always such that: 1 <= sects <= 63, 1 414 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 415 geometry can be different if a translation is done. */ 416 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 417 &cylinders, &heads, §ors) >= 0) { 418 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 419 assert((trans & ~3) == 0); 420 val |= trans << (i * 2); 421 } 422 } 423 rtc_set_memory(s, 0x39, val); 424 425 pc_cmos_init_floppy(s, pc_find_fdc0()); 426 427 qemu_unregister_reset(pc_cmos_init_late, opaque); 428 } 429 430 void pc_cmos_init(PCMachineState *pcms, 431 BusState *idebus0, BusState *idebus1, 432 ISADevice *s) 433 { 434 int val; 435 static pc_cmos_init_late_arg arg; 436 437 /* various important CMOS locations needed by PC/Bochs bios */ 438 439 /* memory size */ 440 /* base memory (first MiB) */ 441 val = MIN(pcms->below_4g_mem_size / 1024, 640); 442 rtc_set_memory(s, 0x15, val); 443 rtc_set_memory(s, 0x16, val >> 8); 444 /* extended memory (next 64MiB) */ 445 if (pcms->below_4g_mem_size > 1024 * 1024) { 446 val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024; 447 } else { 448 val = 0; 449 } 450 if (val > 65535) 451 val = 65535; 452 rtc_set_memory(s, 0x17, val); 453 rtc_set_memory(s, 0x18, val >> 8); 454 rtc_set_memory(s, 0x30, val); 455 rtc_set_memory(s, 0x31, val >> 8); 456 /* memory between 16MiB and 4GiB */ 457 if (pcms->below_4g_mem_size > 16 * 1024 * 1024) { 458 val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536; 459 } else { 460 val = 0; 461 } 462 if (val > 65535) 463 val = 65535; 464 rtc_set_memory(s, 0x34, val); 465 rtc_set_memory(s, 0x35, val >> 8); 466 /* memory above 4GiB */ 467 val = pcms->above_4g_mem_size / 65536; 468 rtc_set_memory(s, 0x5b, val); 469 rtc_set_memory(s, 0x5c, val >> 8); 470 rtc_set_memory(s, 0x5d, val >> 16); 471 472 /* set the number of CPU */ 473 rtc_set_memory(s, 0x5f, smp_cpus - 1); 474 475 object_property_add_link(OBJECT(pcms), "rtc_state", 476 TYPE_ISA_DEVICE, 477 (Object **)&pcms->rtc, 478 object_property_allow_set_link, 479 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 480 object_property_set_link(OBJECT(pcms), OBJECT(s), 481 "rtc_state", &error_abort); 482 483 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 484 485 val = 0; 486 val |= 0x02; /* FPU is there */ 487 val |= 0x04; /* PS/2 mouse installed */ 488 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 489 490 /* hard drives and FDC */ 491 arg.rtc_state = s; 492 arg.idebus[0] = idebus0; 493 arg.idebus[1] = idebus1; 494 qemu_register_reset(pc_cmos_init_late, &arg); 495 } 496 497 #define TYPE_PORT92 "port92" 498 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 499 500 /* port 92 stuff: could be split off */ 501 typedef struct Port92State { 502 ISADevice parent_obj; 503 504 MemoryRegion io; 505 uint8_t outport; 506 qemu_irq *a20_out; 507 } Port92State; 508 509 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 510 unsigned size) 511 { 512 Port92State *s = opaque; 513 int oldval = s->outport; 514 515 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 516 s->outport = val; 517 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 518 if ((val & 1) && !(oldval & 1)) { 519 qemu_system_reset_request(); 520 } 521 } 522 523 static uint64_t port92_read(void *opaque, hwaddr addr, 524 unsigned size) 525 { 526 Port92State *s = opaque; 527 uint32_t ret; 528 529 ret = s->outport; 530 DPRINTF("port92: read 0x%02x\n", ret); 531 return ret; 532 } 533 534 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 535 { 536 Port92State *s = PORT92(dev); 537 538 s->a20_out = a20_out; 539 } 540 541 static const VMStateDescription vmstate_port92_isa = { 542 .name = "port92", 543 .version_id = 1, 544 .minimum_version_id = 1, 545 .fields = (VMStateField[]) { 546 VMSTATE_UINT8(outport, Port92State), 547 VMSTATE_END_OF_LIST() 548 } 549 }; 550 551 static void port92_reset(DeviceState *d) 552 { 553 Port92State *s = PORT92(d); 554 555 s->outport &= ~1; 556 } 557 558 static const MemoryRegionOps port92_ops = { 559 .read = port92_read, 560 .write = port92_write, 561 .impl = { 562 .min_access_size = 1, 563 .max_access_size = 1, 564 }, 565 .endianness = DEVICE_LITTLE_ENDIAN, 566 }; 567 568 static void port92_initfn(Object *obj) 569 { 570 Port92State *s = PORT92(obj); 571 572 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 573 574 s->outport = 0; 575 } 576 577 static void port92_realizefn(DeviceState *dev, Error **errp) 578 { 579 ISADevice *isadev = ISA_DEVICE(dev); 580 Port92State *s = PORT92(dev); 581 582 isa_register_ioport(isadev, &s->io, 0x92); 583 } 584 585 static void port92_class_initfn(ObjectClass *klass, void *data) 586 { 587 DeviceClass *dc = DEVICE_CLASS(klass); 588 589 dc->realize = port92_realizefn; 590 dc->reset = port92_reset; 591 dc->vmsd = &vmstate_port92_isa; 592 /* 593 * Reason: unlike ordinary ISA devices, this one needs additional 594 * wiring: its A20 output line needs to be wired up by 595 * port92_init(). 596 */ 597 dc->cannot_instantiate_with_device_add_yet = true; 598 } 599 600 static const TypeInfo port92_info = { 601 .name = TYPE_PORT92, 602 .parent = TYPE_ISA_DEVICE, 603 .instance_size = sizeof(Port92State), 604 .instance_init = port92_initfn, 605 .class_init = port92_class_initfn, 606 }; 607 608 static void port92_register_types(void) 609 { 610 type_register_static(&port92_info); 611 } 612 613 type_init(port92_register_types) 614 615 static void handle_a20_line_change(void *opaque, int irq, int level) 616 { 617 X86CPU *cpu = opaque; 618 619 /* XXX: send to all CPUs ? */ 620 /* XXX: add logic to handle multiple A20 line sources */ 621 x86_cpu_set_a20(cpu, level); 622 } 623 624 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 625 { 626 int index = le32_to_cpu(e820_reserve.count); 627 struct e820_entry *entry; 628 629 if (type != E820_RAM) { 630 /* old FW_CFG_E820_TABLE entry -- reservations only */ 631 if (index >= E820_NR_ENTRIES) { 632 return -EBUSY; 633 } 634 entry = &e820_reserve.entry[index++]; 635 636 entry->address = cpu_to_le64(address); 637 entry->length = cpu_to_le64(length); 638 entry->type = cpu_to_le32(type); 639 640 e820_reserve.count = cpu_to_le32(index); 641 } 642 643 /* new "etc/e820" file -- include ram too */ 644 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 645 e820_table[e820_entries].address = cpu_to_le64(address); 646 e820_table[e820_entries].length = cpu_to_le64(length); 647 e820_table[e820_entries].type = cpu_to_le32(type); 648 e820_entries++; 649 650 return e820_entries; 651 } 652 653 int e820_get_num_entries(void) 654 { 655 return e820_entries; 656 } 657 658 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 659 { 660 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 661 *address = le64_to_cpu(e820_table[idx].address); 662 *length = le64_to_cpu(e820_table[idx].length); 663 return true; 664 } 665 return false; 666 } 667 668 /* Enables contiguous-apic-ID mode, for compatibility */ 669 static bool compat_apic_id_mode; 670 671 void enable_compat_apic_id_mode(void) 672 { 673 compat_apic_id_mode = true; 674 } 675 676 /* Calculates initial APIC ID for a specific CPU index 677 * 678 * Currently we need to be able to calculate the APIC ID from the CPU index 679 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 680 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 681 * all CPUs up to max_cpus. 682 */ 683 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 684 { 685 uint32_t correct_id; 686 static bool warned; 687 688 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 689 if (compat_apic_id_mode) { 690 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 691 error_report("APIC IDs set in compatibility mode, " 692 "CPU topology won't match the configuration"); 693 warned = true; 694 } 695 return cpu_index; 696 } else { 697 return correct_id; 698 } 699 } 700 701 /* Calculates the limit to CPU APIC ID values 702 * 703 * This function returns the limit for the APIC ID value, so that all 704 * CPU APIC IDs are < pc_apic_id_limit(). 705 * 706 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 707 */ 708 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 709 { 710 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 711 } 712 713 static void pc_build_smbios(FWCfgState *fw_cfg) 714 { 715 uint8_t *smbios_tables, *smbios_anchor; 716 size_t smbios_tables_len, smbios_anchor_len; 717 struct smbios_phys_mem_area *mem_array; 718 unsigned i, array_count; 719 720 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 721 if (smbios_tables) { 722 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 723 smbios_tables, smbios_tables_len); 724 } 725 726 /* build the array of physical mem area from e820 table */ 727 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 728 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 729 uint64_t addr, len; 730 731 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 732 mem_array[array_count].address = addr; 733 mem_array[array_count].length = len; 734 array_count++; 735 } 736 } 737 smbios_get_tables(mem_array, array_count, 738 &smbios_tables, &smbios_tables_len, 739 &smbios_anchor, &smbios_anchor_len); 740 g_free(mem_array); 741 742 if (smbios_anchor) { 743 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 744 smbios_tables, smbios_tables_len); 745 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 746 smbios_anchor, smbios_anchor_len); 747 } 748 } 749 750 static FWCfgState *bochs_bios_init(AddressSpace *as) 751 { 752 FWCfgState *fw_cfg; 753 uint64_t *numa_fw_cfg; 754 int i, j; 755 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 756 757 fw_cfg = fw_cfg_init_io_dma(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 4, as); 758 759 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 760 * 761 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 762 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 763 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 764 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 765 * may see". 766 * 767 * So, this means we must not use max_cpus, here, but the maximum possible 768 * APIC ID value, plus one. 769 * 770 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 771 * the APIC ID, not the "CPU index" 772 */ 773 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 774 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 775 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 776 acpi_tables, acpi_tables_len); 777 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 778 779 pc_build_smbios(fw_cfg); 780 781 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 782 &e820_reserve, sizeof(e820_reserve)); 783 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 784 sizeof(struct e820_entry) * e820_entries); 785 786 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 787 /* allocate memory for the NUMA channel: one (64bit) word for the number 788 * of nodes, one word for each VCPU->node and one word for each node to 789 * hold the amount of memory. 790 */ 791 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 792 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 793 for (i = 0; i < max_cpus; i++) { 794 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 795 assert(apic_id < apic_id_limit); 796 for (j = 0; j < nb_numa_nodes; j++) { 797 if (test_bit(i, numa_info[j].node_cpu)) { 798 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 799 break; 800 } 801 } 802 } 803 for (i = 0; i < nb_numa_nodes; i++) { 804 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 805 } 806 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 807 (1 + apic_id_limit + nb_numa_nodes) * 808 sizeof(*numa_fw_cfg)); 809 810 return fw_cfg; 811 } 812 813 static long get_file_size(FILE *f) 814 { 815 long where, size; 816 817 /* XXX: on Unix systems, using fstat() probably makes more sense */ 818 819 where = ftell(f); 820 fseek(f, 0, SEEK_END); 821 size = ftell(f); 822 fseek(f, where, SEEK_SET); 823 824 return size; 825 } 826 827 static void load_linux(PCMachineState *pcms, 828 FWCfgState *fw_cfg) 829 { 830 uint16_t protocol; 831 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 832 uint32_t initrd_max; 833 uint8_t header[8192], *setup, *kernel, *initrd_data; 834 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 835 FILE *f; 836 char *vmode; 837 MachineState *machine = MACHINE(pcms); 838 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 839 const char *kernel_filename = machine->kernel_filename; 840 const char *initrd_filename = machine->initrd_filename; 841 const char *kernel_cmdline = machine->kernel_cmdline; 842 843 /* Align to 16 bytes as a paranoia measure */ 844 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 845 846 /* load the kernel header */ 847 f = fopen(kernel_filename, "rb"); 848 if (!f || !(kernel_size = get_file_size(f)) || 849 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 850 MIN(ARRAY_SIZE(header), kernel_size)) { 851 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 852 kernel_filename, strerror(errno)); 853 exit(1); 854 } 855 856 /* kernel protocol version */ 857 #if 0 858 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 859 #endif 860 if (ldl_p(header+0x202) == 0x53726448) { 861 protocol = lduw_p(header+0x206); 862 } else { 863 /* This looks like a multiboot kernel. If it is, let's stop 864 treating it like a Linux kernel. */ 865 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 866 kernel_cmdline, kernel_size, header)) { 867 return; 868 } 869 protocol = 0; 870 } 871 872 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 873 /* Low kernel */ 874 real_addr = 0x90000; 875 cmdline_addr = 0x9a000 - cmdline_size; 876 prot_addr = 0x10000; 877 } else if (protocol < 0x202) { 878 /* High but ancient kernel */ 879 real_addr = 0x90000; 880 cmdline_addr = 0x9a000 - cmdline_size; 881 prot_addr = 0x100000; 882 } else { 883 /* High and recent kernel */ 884 real_addr = 0x10000; 885 cmdline_addr = 0x20000; 886 prot_addr = 0x100000; 887 } 888 889 #if 0 890 fprintf(stderr, 891 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 892 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 893 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 894 real_addr, 895 cmdline_addr, 896 prot_addr); 897 #endif 898 899 /* highest address for loading the initrd */ 900 if (protocol >= 0x203) { 901 initrd_max = ldl_p(header+0x22c); 902 } else { 903 initrd_max = 0x37ffffff; 904 } 905 906 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 907 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 908 } 909 910 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 911 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 912 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 913 914 if (protocol >= 0x202) { 915 stl_p(header+0x228, cmdline_addr); 916 } else { 917 stw_p(header+0x20, 0xA33F); 918 stw_p(header+0x22, cmdline_addr-real_addr); 919 } 920 921 /* handle vga= parameter */ 922 vmode = strstr(kernel_cmdline, "vga="); 923 if (vmode) { 924 unsigned int video_mode; 925 /* skip "vga=" */ 926 vmode += 4; 927 if (!strncmp(vmode, "normal", 6)) { 928 video_mode = 0xffff; 929 } else if (!strncmp(vmode, "ext", 3)) { 930 video_mode = 0xfffe; 931 } else if (!strncmp(vmode, "ask", 3)) { 932 video_mode = 0xfffd; 933 } else { 934 video_mode = strtol(vmode, NULL, 0); 935 } 936 stw_p(header+0x1fa, video_mode); 937 } 938 939 /* loader type */ 940 /* High nybble = B reserved for QEMU; low nybble is revision number. 941 If this code is substantially changed, you may want to consider 942 incrementing the revision. */ 943 if (protocol >= 0x200) { 944 header[0x210] = 0xB0; 945 } 946 /* heap */ 947 if (protocol >= 0x201) { 948 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 949 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 950 } 951 952 /* load initrd */ 953 if (initrd_filename) { 954 if (protocol < 0x200) { 955 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 956 exit(1); 957 } 958 959 initrd_size = get_image_size(initrd_filename); 960 if (initrd_size < 0) { 961 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 962 initrd_filename, strerror(errno)); 963 exit(1); 964 } 965 966 initrd_addr = (initrd_max-initrd_size) & ~4095; 967 968 initrd_data = g_malloc(initrd_size); 969 load_image(initrd_filename, initrd_data); 970 971 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 972 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 973 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 974 975 stl_p(header+0x218, initrd_addr); 976 stl_p(header+0x21c, initrd_size); 977 } 978 979 /* load kernel and setup */ 980 setup_size = header[0x1f1]; 981 if (setup_size == 0) { 982 setup_size = 4; 983 } 984 setup_size = (setup_size+1)*512; 985 if (setup_size > kernel_size) { 986 fprintf(stderr, "qemu: invalid kernel header\n"); 987 exit(1); 988 } 989 kernel_size -= setup_size; 990 991 setup = g_malloc(setup_size); 992 kernel = g_malloc(kernel_size); 993 fseek(f, 0, SEEK_SET); 994 if (fread(setup, 1, setup_size, f) != setup_size) { 995 fprintf(stderr, "fread() failed\n"); 996 exit(1); 997 } 998 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 999 fprintf(stderr, "fread() failed\n"); 1000 exit(1); 1001 } 1002 fclose(f); 1003 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1004 1005 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1006 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1007 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1008 1009 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1010 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1011 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1012 1013 option_rom[nb_option_roms].name = "linuxboot.bin"; 1014 option_rom[nb_option_roms].bootindex = 0; 1015 nb_option_roms++; 1016 } 1017 1018 #define NE2000_NB_MAX 6 1019 1020 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1021 0x280, 0x380 }; 1022 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1023 1024 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1025 { 1026 static int nb_ne2k = 0; 1027 1028 if (nb_ne2k == NE2000_NB_MAX) 1029 return; 1030 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1031 ne2000_irq[nb_ne2k], nd); 1032 nb_ne2k++; 1033 } 1034 1035 DeviceState *cpu_get_current_apic(void) 1036 { 1037 if (current_cpu) { 1038 X86CPU *cpu = X86_CPU(current_cpu); 1039 return cpu->apic_state; 1040 } else { 1041 return NULL; 1042 } 1043 } 1044 1045 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1046 { 1047 X86CPU *cpu = opaque; 1048 1049 if (level) { 1050 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1051 } 1052 } 1053 1054 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 1055 Error **errp) 1056 { 1057 X86CPU *cpu = NULL; 1058 Error *local_err = NULL; 1059 1060 cpu = cpu_x86_create(cpu_model, &local_err); 1061 if (local_err != NULL) { 1062 goto out; 1063 } 1064 1065 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1066 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1067 1068 out: 1069 if (local_err) { 1070 error_propagate(errp, local_err); 1071 object_unref(OBJECT(cpu)); 1072 cpu = NULL; 1073 } 1074 return cpu; 1075 } 1076 1077 void pc_hot_add_cpu(const int64_t id, Error **errp) 1078 { 1079 X86CPU *cpu; 1080 MachineState *machine = MACHINE(qdev_get_machine()); 1081 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1082 Error *local_err = NULL; 1083 1084 if (id < 0) { 1085 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1086 return; 1087 } 1088 1089 if (cpu_exists(apic_id)) { 1090 error_setg(errp, "Unable to add CPU: %" PRIi64 1091 ", it already exists", id); 1092 return; 1093 } 1094 1095 if (id >= max_cpus) { 1096 error_setg(errp, "Unable to add CPU: %" PRIi64 1097 ", max allowed: %d", id, max_cpus - 1); 1098 return; 1099 } 1100 1101 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1102 error_setg(errp, "Unable to add CPU: %" PRIi64 1103 ", resulting APIC ID (%" PRIi64 ") is too large", 1104 id, apic_id); 1105 return; 1106 } 1107 1108 cpu = pc_new_cpu(machine->cpu_model, apic_id, &local_err); 1109 if (local_err) { 1110 error_propagate(errp, local_err); 1111 return; 1112 } 1113 object_unref(OBJECT(cpu)); 1114 } 1115 1116 void pc_cpus_init(PCMachineState *pcms) 1117 { 1118 int i; 1119 X86CPU *cpu = NULL; 1120 MachineState *machine = MACHINE(pcms); 1121 unsigned long apic_id_limit; 1122 1123 /* init CPUs */ 1124 if (machine->cpu_model == NULL) { 1125 #ifdef TARGET_X86_64 1126 machine->cpu_model = "qemu64"; 1127 #else 1128 machine->cpu_model = "qemu32"; 1129 #endif 1130 } 1131 1132 apic_id_limit = pc_apic_id_limit(max_cpus); 1133 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1134 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1135 apic_id_limit - 1); 1136 exit(1); 1137 } 1138 1139 for (i = 0; i < smp_cpus; i++) { 1140 cpu = pc_new_cpu(machine->cpu_model, x86_cpu_apic_id_from_index(i), 1141 &error_fatal); 1142 object_unref(OBJECT(cpu)); 1143 } 1144 1145 /* tell smbios about cpuid version and features */ 1146 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1147 } 1148 1149 /* pci-info ROM file. Little endian format */ 1150 typedef struct PcRomPciInfo { 1151 uint64_t w32_min; 1152 uint64_t w32_max; 1153 uint64_t w64_min; 1154 uint64_t w64_max; 1155 } PcRomPciInfo; 1156 1157 typedef struct PcGuestInfoState { 1158 PcGuestInfo info; 1159 Notifier machine_done; 1160 } PcGuestInfoState; 1161 1162 static 1163 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1164 { 1165 PcGuestInfoState *guest_info_state = container_of(notifier, 1166 PcGuestInfoState, 1167 machine_done); 1168 PCIBus *bus = PC_MACHINE(qdev_get_machine())->bus; 1169 1170 if (bus) { 1171 int extra_hosts = 0; 1172 1173 QLIST_FOREACH(bus, &bus->child, sibling) { 1174 /* look for expander root buses */ 1175 if (pci_bus_is_root(bus)) { 1176 extra_hosts++; 1177 } 1178 } 1179 if (extra_hosts && guest_info_state->info.fw_cfg) { 1180 uint64_t *val = g_malloc(sizeof(*val)); 1181 *val = cpu_to_le64(extra_hosts); 1182 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1183 "etc/extra-pci-roots", val, sizeof(*val)); 1184 } 1185 } 1186 1187 acpi_setup(&guest_info_state->info); 1188 } 1189 1190 PcGuestInfo *pc_guest_info_init(PCMachineState *pcms) 1191 { 1192 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1193 PcGuestInfo *guest_info = &guest_info_state->info; 1194 int i, j; 1195 1196 guest_info->ram_size_below_4g = pcms->below_4g_mem_size; 1197 guest_info->ram_size = pcms->below_4g_mem_size + pcms->above_4g_mem_size; 1198 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1199 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1200 guest_info->numa_nodes = nb_numa_nodes; 1201 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1202 sizeof *guest_info->node_mem); 1203 for (i = 0; i < nb_numa_nodes; i++) { 1204 guest_info->node_mem[i] = numa_info[i].node_mem; 1205 } 1206 1207 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1208 sizeof *guest_info->node_cpu); 1209 1210 for (i = 0; i < max_cpus; i++) { 1211 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1212 assert(apic_id < guest_info->apic_id_limit); 1213 for (j = 0; j < nb_numa_nodes; j++) { 1214 if (test_bit(i, numa_info[j].node_cpu)) { 1215 guest_info->node_cpu[apic_id] = j; 1216 break; 1217 } 1218 } 1219 } 1220 1221 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1222 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1223 return guest_info; 1224 } 1225 1226 /* setup pci memory address space mapping into system address space */ 1227 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1228 MemoryRegion *pci_address_space) 1229 { 1230 /* Set to lower priority than RAM */ 1231 memory_region_add_subregion_overlap(system_memory, 0x0, 1232 pci_address_space, -1); 1233 } 1234 1235 void pc_acpi_init(const char *default_dsdt) 1236 { 1237 char *filename; 1238 1239 if (acpi_tables != NULL) { 1240 /* manually set via -acpitable, leave it alone */ 1241 return; 1242 } 1243 1244 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1245 if (filename == NULL) { 1246 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1247 } else { 1248 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1249 &error_abort); 1250 Error *err = NULL; 1251 1252 qemu_opt_set(opts, "file", filename, &error_abort); 1253 1254 acpi_table_add_builtin(opts, &err); 1255 if (err) { 1256 error_report("WARNING: failed to load %s: %s", filename, 1257 error_get_pretty(err)); 1258 error_free(err); 1259 } 1260 g_free(filename); 1261 } 1262 } 1263 1264 FWCfgState *xen_load_linux(PCMachineState *pcms, 1265 PcGuestInfo *guest_info) 1266 { 1267 int i; 1268 FWCfgState *fw_cfg; 1269 1270 assert(MACHINE(pcms)->kernel_filename != NULL); 1271 1272 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1273 rom_set_fw(fw_cfg); 1274 1275 load_linux(pcms, fw_cfg); 1276 for (i = 0; i < nb_option_roms; i++) { 1277 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1278 !strcmp(option_rom[i].name, "multiboot.bin")); 1279 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1280 } 1281 guest_info->fw_cfg = fw_cfg; 1282 return fw_cfg; 1283 } 1284 1285 FWCfgState *pc_memory_init(PCMachineState *pcms, 1286 MemoryRegion *system_memory, 1287 MemoryRegion *rom_memory, 1288 MemoryRegion **ram_memory, 1289 PcGuestInfo *guest_info) 1290 { 1291 int linux_boot, i; 1292 MemoryRegion *ram, *option_rom_mr; 1293 MemoryRegion *ram_below_4g, *ram_above_4g; 1294 FWCfgState *fw_cfg; 1295 MachineState *machine = MACHINE(pcms); 1296 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1297 1298 assert(machine->ram_size == pcms->below_4g_mem_size + 1299 pcms->above_4g_mem_size); 1300 1301 linux_boot = (machine->kernel_filename != NULL); 1302 1303 /* Allocate RAM. We allocate it as a single memory region and use 1304 * aliases to address portions of it, mostly for backwards compatibility 1305 * with older qemus that used qemu_ram_alloc(). 1306 */ 1307 ram = g_malloc(sizeof(*ram)); 1308 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1309 machine->ram_size); 1310 *ram_memory = ram; 1311 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1312 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1313 0, pcms->below_4g_mem_size); 1314 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1315 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1316 if (pcms->above_4g_mem_size > 0) { 1317 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1318 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1319 pcms->below_4g_mem_size, 1320 pcms->above_4g_mem_size); 1321 memory_region_add_subregion(system_memory, 0x100000000ULL, 1322 ram_above_4g); 1323 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1324 } 1325 1326 if (!guest_info->has_reserved_memory && 1327 (machine->ram_slots || 1328 (machine->maxram_size > machine->ram_size))) { 1329 MachineClass *mc = MACHINE_GET_CLASS(machine); 1330 1331 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1332 mc->name); 1333 exit(EXIT_FAILURE); 1334 } 1335 1336 /* initialize hotplug memory address space */ 1337 if (guest_info->has_reserved_memory && 1338 (machine->ram_size < machine->maxram_size)) { 1339 ram_addr_t hotplug_mem_size = 1340 machine->maxram_size - machine->ram_size; 1341 1342 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1343 error_report("unsupported amount of memory slots: %"PRIu64, 1344 machine->ram_slots); 1345 exit(EXIT_FAILURE); 1346 } 1347 1348 if (QEMU_ALIGN_UP(machine->maxram_size, 1349 TARGET_PAGE_SIZE) != machine->maxram_size) { 1350 error_report("maximum memory size must by aligned to multiple of " 1351 "%d bytes", TARGET_PAGE_SIZE); 1352 exit(EXIT_FAILURE); 1353 } 1354 1355 pcms->hotplug_memory.base = 1356 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30); 1357 1358 if (pcmc->enforce_aligned_dimm) { 1359 /* size hotplug region assuming 1G page max alignment per slot */ 1360 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1361 } 1362 1363 if ((pcms->hotplug_memory.base + hotplug_mem_size) < 1364 hotplug_mem_size) { 1365 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1366 machine->maxram_size); 1367 exit(EXIT_FAILURE); 1368 } 1369 1370 memory_region_init(&pcms->hotplug_memory.mr, OBJECT(pcms), 1371 "hotplug-memory", hotplug_mem_size); 1372 memory_region_add_subregion(system_memory, pcms->hotplug_memory.base, 1373 &pcms->hotplug_memory.mr); 1374 } 1375 1376 /* Initialize PC system firmware */ 1377 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1378 1379 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1380 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1381 &error_fatal); 1382 vmstate_register_ram_global(option_rom_mr); 1383 memory_region_add_subregion_overlap(rom_memory, 1384 PC_ROM_MIN_VGA, 1385 option_rom_mr, 1386 1); 1387 1388 fw_cfg = bochs_bios_init(&address_space_memory); 1389 1390 rom_set_fw(fw_cfg); 1391 1392 if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) { 1393 uint64_t *val = g_malloc(sizeof(*val)); 1394 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1395 uint64_t res_mem_end = pcms->hotplug_memory.base; 1396 1397 if (!pcmc->broken_reserved_end) { 1398 res_mem_end += memory_region_size(&pcms->hotplug_memory.mr); 1399 } 1400 *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30)); 1401 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1402 } 1403 1404 if (linux_boot) { 1405 load_linux(pcms, fw_cfg); 1406 } 1407 1408 for (i = 0; i < nb_option_roms; i++) { 1409 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1410 } 1411 guest_info->fw_cfg = fw_cfg; 1412 return fw_cfg; 1413 } 1414 1415 qemu_irq pc_allocate_cpu_irq(void) 1416 { 1417 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1418 } 1419 1420 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1421 { 1422 DeviceState *dev = NULL; 1423 1424 if (pci_bus) { 1425 PCIDevice *pcidev = pci_vga_init(pci_bus); 1426 dev = pcidev ? &pcidev->qdev : NULL; 1427 } else if (isa_bus) { 1428 ISADevice *isadev = isa_vga_init(isa_bus); 1429 dev = isadev ? DEVICE(isadev) : NULL; 1430 } 1431 return dev; 1432 } 1433 1434 static const MemoryRegionOps ioport80_io_ops = { 1435 .write = ioport80_write, 1436 .read = ioport80_read, 1437 .endianness = DEVICE_NATIVE_ENDIAN, 1438 .impl = { 1439 .min_access_size = 1, 1440 .max_access_size = 1, 1441 }, 1442 }; 1443 1444 static const MemoryRegionOps ioportF0_io_ops = { 1445 .write = ioportF0_write, 1446 .read = ioportF0_read, 1447 .endianness = DEVICE_NATIVE_ENDIAN, 1448 .impl = { 1449 .min_access_size = 1, 1450 .max_access_size = 1, 1451 }, 1452 }; 1453 1454 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1455 ISADevice **rtc_state, 1456 bool create_fdctrl, 1457 bool no_vmport, 1458 uint32 hpet_irqs) 1459 { 1460 int i; 1461 DriveInfo *fd[MAX_FD]; 1462 DeviceState *hpet = NULL; 1463 int pit_isa_irq = 0; 1464 qemu_irq pit_alt_irq = NULL; 1465 qemu_irq rtc_irq = NULL; 1466 qemu_irq *a20_line; 1467 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1468 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1469 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1470 1471 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1472 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1473 1474 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1475 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1476 1477 /* 1478 * Check if an HPET shall be created. 1479 * 1480 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1481 * when the HPET wants to take over. Thus we have to disable the latter. 1482 */ 1483 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1484 /* In order to set property, here not using sysbus_try_create_simple */ 1485 hpet = qdev_try_create(NULL, TYPE_HPET); 1486 if (hpet) { 1487 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1488 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1489 * IRQ8 and IRQ2. 1490 */ 1491 uint8_t compat = object_property_get_int(OBJECT(hpet), 1492 HPET_INTCAP, NULL); 1493 if (!compat) { 1494 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1495 } 1496 qdev_init_nofail(hpet); 1497 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1498 1499 for (i = 0; i < GSI_NUM_PINS; i++) { 1500 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1501 } 1502 pit_isa_irq = -1; 1503 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1504 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1505 } 1506 } 1507 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1508 1509 qemu_register_boot_set(pc_boot_set, *rtc_state); 1510 1511 if (!xen_enabled()) { 1512 if (kvm_pit_in_kernel()) { 1513 pit = kvm_pit_init(isa_bus, 0x40); 1514 } else { 1515 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1516 } 1517 if (hpet) { 1518 /* connect PIT to output control line of the HPET */ 1519 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1520 } 1521 pcspk_init(isa_bus, pit); 1522 } 1523 1524 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1525 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1526 1527 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1528 i8042 = isa_create_simple(isa_bus, "i8042"); 1529 i8042_setup_a20_line(i8042, &a20_line[0]); 1530 if (!no_vmport) { 1531 vmport_init(isa_bus); 1532 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1533 } else { 1534 vmmouse = NULL; 1535 } 1536 if (vmmouse) { 1537 DeviceState *dev = DEVICE(vmmouse); 1538 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1539 qdev_init_nofail(dev); 1540 } 1541 port92 = isa_create_simple(isa_bus, "port92"); 1542 port92_init(port92, &a20_line[1]); 1543 1544 DMA_init(0); 1545 1546 for(i = 0; i < MAX_FD; i++) { 1547 fd[i] = drive_get(IF_FLOPPY, 0, i); 1548 create_fdctrl |= !!fd[i]; 1549 } 1550 if (create_fdctrl) { 1551 fdctrl_init_isa(isa_bus, fd); 1552 } 1553 } 1554 1555 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1556 { 1557 int i; 1558 1559 for (i = 0; i < nb_nics; i++) { 1560 NICInfo *nd = &nd_table[i]; 1561 1562 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1563 pc_init_ne2k_isa(isa_bus, nd); 1564 } else { 1565 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1566 } 1567 } 1568 } 1569 1570 void pc_pci_device_init(PCIBus *pci_bus) 1571 { 1572 int max_bus; 1573 int bus; 1574 1575 max_bus = drive_get_max_bus(IF_SCSI); 1576 for (bus = 0; bus <= max_bus; bus++) { 1577 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1578 } 1579 } 1580 1581 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1582 { 1583 DeviceState *dev; 1584 SysBusDevice *d; 1585 unsigned int i; 1586 1587 if (kvm_ioapic_in_kernel()) { 1588 dev = qdev_create(NULL, "kvm-ioapic"); 1589 } else { 1590 dev = qdev_create(NULL, "ioapic"); 1591 } 1592 if (parent_name) { 1593 object_property_add_child(object_resolve_path(parent_name, NULL), 1594 "ioapic", OBJECT(dev), NULL); 1595 } 1596 qdev_init_nofail(dev); 1597 d = SYS_BUS_DEVICE(dev); 1598 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1599 1600 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1601 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1602 } 1603 } 1604 1605 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1606 DeviceState *dev, Error **errp) 1607 { 1608 HotplugHandlerClass *hhc; 1609 Error *local_err = NULL; 1610 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1611 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1612 PCDIMMDevice *dimm = PC_DIMM(dev); 1613 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1614 MemoryRegion *mr = ddc->get_memory_region(dimm); 1615 uint64_t align = TARGET_PAGE_SIZE; 1616 1617 if (memory_region_get_alignment(mr) && pcmc->enforce_aligned_dimm) { 1618 align = memory_region_get_alignment(mr); 1619 } 1620 1621 if (!pcms->acpi_dev) { 1622 error_setg(&local_err, 1623 "memory hotplug is not enabled: missing acpi device"); 1624 goto out; 1625 } 1626 1627 pc_dimm_memory_plug(dev, &pcms->hotplug_memory, mr, align, &local_err); 1628 if (local_err) { 1629 goto out; 1630 } 1631 1632 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1633 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 1634 out: 1635 error_propagate(errp, local_err); 1636 } 1637 1638 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1639 DeviceState *dev, Error **errp) 1640 { 1641 HotplugHandlerClass *hhc; 1642 Error *local_err = NULL; 1643 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1644 1645 if (!pcms->acpi_dev) { 1646 error_setg(&local_err, 1647 "memory hotplug is not enabled: missing acpi device"); 1648 goto out; 1649 } 1650 1651 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1652 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1653 1654 out: 1655 error_propagate(errp, local_err); 1656 } 1657 1658 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1659 DeviceState *dev, Error **errp) 1660 { 1661 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1662 PCDIMMDevice *dimm = PC_DIMM(dev); 1663 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1664 MemoryRegion *mr = ddc->get_memory_region(dimm); 1665 HotplugHandlerClass *hhc; 1666 Error *local_err = NULL; 1667 1668 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1669 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1670 1671 if (local_err) { 1672 goto out; 1673 } 1674 1675 pc_dimm_memory_unplug(dev, &pcms->hotplug_memory, mr); 1676 object_unparent(OBJECT(dev)); 1677 1678 out: 1679 error_propagate(errp, local_err); 1680 } 1681 1682 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1683 DeviceState *dev, Error **errp) 1684 { 1685 HotplugHandlerClass *hhc; 1686 Error *local_err = NULL; 1687 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1688 1689 if (!dev->hotplugged) { 1690 goto out; 1691 } 1692 1693 if (!pcms->acpi_dev) { 1694 error_setg(&local_err, 1695 "cpu hotplug is not enabled: missing acpi device"); 1696 goto out; 1697 } 1698 1699 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1700 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1701 if (local_err) { 1702 goto out; 1703 } 1704 1705 /* increment the number of CPUs */ 1706 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1707 out: 1708 error_propagate(errp, local_err); 1709 } 1710 1711 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1712 DeviceState *dev, Error **errp) 1713 { 1714 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1715 pc_dimm_plug(hotplug_dev, dev, errp); 1716 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1717 pc_cpu_plug(hotplug_dev, dev, errp); 1718 } 1719 } 1720 1721 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1722 DeviceState *dev, Error **errp) 1723 { 1724 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1725 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1726 } else { 1727 error_setg(errp, "acpi: device unplug request for not supported device" 1728 " type: %s", object_get_typename(OBJECT(dev))); 1729 } 1730 } 1731 1732 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1733 DeviceState *dev, Error **errp) 1734 { 1735 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1736 pc_dimm_unplug(hotplug_dev, dev, errp); 1737 } else { 1738 error_setg(errp, "acpi: device unplug for not supported device" 1739 " type: %s", object_get_typename(OBJECT(dev))); 1740 } 1741 } 1742 1743 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1744 DeviceState *dev) 1745 { 1746 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1747 1748 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1749 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1750 return HOTPLUG_HANDLER(machine); 1751 } 1752 1753 return pcmc->get_hotplug_handler ? 1754 pcmc->get_hotplug_handler(machine, dev) : NULL; 1755 } 1756 1757 static void 1758 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1759 const char *name, Error **errp) 1760 { 1761 PCMachineState *pcms = PC_MACHINE(obj); 1762 int64_t value = memory_region_size(&pcms->hotplug_memory.mr); 1763 1764 visit_type_int(v, &value, name, errp); 1765 } 1766 1767 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1768 void *opaque, const char *name, 1769 Error **errp) 1770 { 1771 PCMachineState *pcms = PC_MACHINE(obj); 1772 uint64_t value = pcms->max_ram_below_4g; 1773 1774 visit_type_size(v, &value, name, errp); 1775 } 1776 1777 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1778 void *opaque, const char *name, 1779 Error **errp) 1780 { 1781 PCMachineState *pcms = PC_MACHINE(obj); 1782 Error *error = NULL; 1783 uint64_t value; 1784 1785 visit_type_size(v, &value, name, &error); 1786 if (error) { 1787 error_propagate(errp, error); 1788 return; 1789 } 1790 if (value > (1ULL << 32)) { 1791 error_setg(&error, 1792 "Machine option 'max-ram-below-4g=%"PRIu64 1793 "' expects size less than or equal to 4G", value); 1794 error_propagate(errp, error); 1795 return; 1796 } 1797 1798 if (value < (1ULL << 20)) { 1799 error_report("Warning: small max_ram_below_4g(%"PRIu64 1800 ") less than 1M. BIOS may not work..", 1801 value); 1802 } 1803 1804 pcms->max_ram_below_4g = value; 1805 } 1806 1807 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1808 const char *name, Error **errp) 1809 { 1810 PCMachineState *pcms = PC_MACHINE(obj); 1811 OnOffAuto vmport = pcms->vmport; 1812 1813 visit_type_OnOffAuto(v, &vmport, name, errp); 1814 } 1815 1816 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1817 const char *name, Error **errp) 1818 { 1819 PCMachineState *pcms = PC_MACHINE(obj); 1820 1821 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1822 } 1823 1824 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 1825 { 1826 bool smm_available = false; 1827 1828 if (pcms->smm == ON_OFF_AUTO_OFF) { 1829 return false; 1830 } 1831 1832 if (tcg_enabled() || qtest_enabled()) { 1833 smm_available = true; 1834 } else if (kvm_enabled()) { 1835 smm_available = kvm_has_smm(); 1836 } 1837 1838 if (smm_available) { 1839 return true; 1840 } 1841 1842 if (pcms->smm == ON_OFF_AUTO_ON) { 1843 error_report("System Management Mode not supported by this hypervisor."); 1844 exit(1); 1845 } 1846 return false; 1847 } 1848 1849 static void pc_machine_get_smm(Object *obj, Visitor *v, void *opaque, 1850 const char *name, Error **errp) 1851 { 1852 PCMachineState *pcms = PC_MACHINE(obj); 1853 OnOffAuto smm = pcms->smm; 1854 1855 visit_type_OnOffAuto(v, &smm, name, errp); 1856 } 1857 1858 static void pc_machine_set_smm(Object *obj, Visitor *v, void *opaque, 1859 const char *name, Error **errp) 1860 { 1861 PCMachineState *pcms = PC_MACHINE(obj); 1862 1863 visit_type_OnOffAuto(v, &pcms->smm, name, errp); 1864 } 1865 1866 static bool pc_machine_get_nvdimm(Object *obj, Error **errp) 1867 { 1868 PCMachineState *pcms = PC_MACHINE(obj); 1869 1870 return pcms->nvdimm; 1871 } 1872 1873 static void pc_machine_set_nvdimm(Object *obj, bool value, Error **errp) 1874 { 1875 PCMachineState *pcms = PC_MACHINE(obj); 1876 1877 pcms->nvdimm = value; 1878 } 1879 1880 static void pc_machine_initfn(Object *obj) 1881 { 1882 PCMachineState *pcms = PC_MACHINE(obj); 1883 1884 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1885 pc_machine_get_hotplug_memory_region_size, 1886 NULL, NULL, NULL, &error_abort); 1887 1888 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1889 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1890 pc_machine_get_max_ram_below_4g, 1891 pc_machine_set_max_ram_below_4g, 1892 NULL, NULL, &error_abort); 1893 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1894 "Maximum ram below the 4G boundary (32bit boundary)", 1895 &error_abort); 1896 1897 pcms->smm = ON_OFF_AUTO_AUTO; 1898 object_property_add(obj, PC_MACHINE_SMM, "OnOffAuto", 1899 pc_machine_get_smm, 1900 pc_machine_set_smm, 1901 NULL, NULL, &error_abort); 1902 object_property_set_description(obj, PC_MACHINE_SMM, 1903 "Enable SMM (pc & q35)", 1904 &error_abort); 1905 1906 pcms->vmport = ON_OFF_AUTO_AUTO; 1907 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1908 pc_machine_get_vmport, 1909 pc_machine_set_vmport, 1910 NULL, NULL, &error_abort); 1911 object_property_set_description(obj, PC_MACHINE_VMPORT, 1912 "Enable vmport (pc & q35)", 1913 &error_abort); 1914 1915 /* nvdimm is disabled on default. */ 1916 pcms->nvdimm = false; 1917 object_property_add_bool(obj, PC_MACHINE_NVDIMM, pc_machine_get_nvdimm, 1918 pc_machine_set_nvdimm, &error_abort); 1919 } 1920 1921 static void pc_machine_reset(void) 1922 { 1923 CPUState *cs; 1924 X86CPU *cpu; 1925 1926 qemu_devices_reset(); 1927 1928 /* Reset APIC after devices have been reset to cancel 1929 * any changes that qemu_devices_reset() might have done. 1930 */ 1931 CPU_FOREACH(cs) { 1932 cpu = X86_CPU(cs); 1933 1934 if (cpu->apic_state) { 1935 device_reset(cpu->apic_state); 1936 } 1937 } 1938 } 1939 1940 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1941 { 1942 X86CPUTopoInfo topo; 1943 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1944 &topo); 1945 return topo.pkg_id; 1946 } 1947 1948 static void pc_machine_class_init(ObjectClass *oc, void *data) 1949 { 1950 MachineClass *mc = MACHINE_CLASS(oc); 1951 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1952 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1953 1954 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1955 pcmc->pci_enabled = true; 1956 pcmc->has_acpi_build = true; 1957 pcmc->rsdp_in_ram = true; 1958 pcmc->smbios_defaults = true; 1959 pcmc->smbios_uuid_encoded = true; 1960 pcmc->gigabyte_align = true; 1961 pcmc->has_reserved_memory = true; 1962 pcmc->kvmclock_enabled = true; 1963 pcmc->enforce_aligned_dimm = true; 1964 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1965 * to be used at the moment, 32K should be enough for a while. */ 1966 pcmc->acpi_data_size = 0x20000 + 0x8000; 1967 mc->get_hotplug_handler = pc_get_hotpug_handler; 1968 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1969 mc->default_boot_order = "cad"; 1970 mc->hot_add_cpu = pc_hot_add_cpu; 1971 mc->max_cpus = 255; 1972 mc->reset = pc_machine_reset; 1973 hc->plug = pc_machine_device_plug_cb; 1974 hc->unplug_request = pc_machine_device_unplug_request_cb; 1975 hc->unplug = pc_machine_device_unplug_cb; 1976 } 1977 1978 static const TypeInfo pc_machine_info = { 1979 .name = TYPE_PC_MACHINE, 1980 .parent = TYPE_MACHINE, 1981 .abstract = true, 1982 .instance_size = sizeof(PCMachineState), 1983 .instance_init = pc_machine_initfn, 1984 .class_size = sizeof(PCMachineClass), 1985 .class_init = pc_machine_class_init, 1986 .interfaces = (InterfaceInfo[]) { 1987 { TYPE_HOTPLUG_HANDLER }, 1988 { } 1989 }, 1990 }; 1991 1992 static void pc_machine_register_types(void) 1993 { 1994 type_register_static(&pc_machine_info); 1995 } 1996 1997 type_init(pc_machine_register_types) 1998