1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide/internal.h" 37 #include "hw/ide/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/pci-bridge/pci_expander_bridge.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/timer/hpet.h" 43 #include "hw/firmware/smbios.h" 44 #include "hw/loader.h" 45 #include "elf.h" 46 #include "migration/vmstate.h" 47 #include "multiboot.h" 48 #include "hw/rtc/mc146818rtc.h" 49 #include "hw/intc/i8259.h" 50 #include "hw/intc/ioapic.h" 51 #include "hw/timer/i8254.h" 52 #include "hw/input/i8042.h" 53 #include "hw/irq.h" 54 #include "hw/audio/pcspk.h" 55 #include "hw/pci/msi.h" 56 #include "hw/sysbus.h" 57 #include "sysemu/sysemu.h" 58 #include "sysemu/tcg.h" 59 #include "sysemu/numa.h" 60 #include "sysemu/kvm.h" 61 #include "sysemu/xen.h" 62 #include "sysemu/reset.h" 63 #include "sysemu/runstate.h" 64 #include "kvm/kvm_i386.h" 65 #include "hw/xen/xen.h" 66 #include "hw/xen/start_info.h" 67 #include "ui/qemu-spice.h" 68 #include "exec/memory.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "hw/cxl/cxl.h" 80 #include "hw/cxl/cxl_host.h" 81 #include "qapi/error.h" 82 #include "qapi/qapi-visit-common.h" 83 #include "qapi/qapi-visit-machine.h" 84 #include "qapi/visitor.h" 85 #include "hw/core/cpu.h" 86 #include "hw/usb.h" 87 #include "hw/i386/intel_iommu.h" 88 #include "hw/net/ne2000-isa.h" 89 #include "standard-headers/asm-x86/bootparam.h" 90 #include "hw/virtio/virtio-iommu.h" 91 #include "hw/virtio/virtio-pmem-pci.h" 92 #include "hw/virtio/virtio-mem-pci.h" 93 #include "hw/i386/kvm/xen_overlay.h" 94 #include "hw/i386/kvm/xen_evtchn.h" 95 #include "hw/i386/kvm/xen_gnttab.h" 96 #include "hw/i386/kvm/xen_xenstore.h" 97 #include "hw/mem/memory-device.h" 98 #include "sysemu/replay.h" 99 #include "target/i386/cpu.h" 100 #include "e820_memory_layout.h" 101 #include "fw_cfg.h" 102 #include "trace.h" 103 #include CONFIG_DEVICES 104 105 #ifdef CONFIG_XEN_EMU 106 #include "hw/xen/xen-legacy-backend.h" 107 #include "hw/xen/xen-bus.h" 108 #endif 109 110 /* 111 * Helper for setting model-id for CPU models that changed model-id 112 * depending on QEMU versions up to QEMU 2.4. 113 */ 114 #define PC_CPU_MODEL_IDS(v) \ 115 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 116 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 117 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 118 119 GlobalProperty pc_compat_8_0[] = {}; 120 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 121 122 GlobalProperty pc_compat_7_2[] = { 123 { "ICH9-LPC", "noreboot", "true" }, 124 }; 125 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 126 127 GlobalProperty pc_compat_7_1[] = {}; 128 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 129 130 GlobalProperty pc_compat_7_0[] = {}; 131 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 132 133 GlobalProperty pc_compat_6_2[] = { 134 { "virtio-mem", "unplugged-inaccessible", "off" }, 135 }; 136 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 137 138 GlobalProperty pc_compat_6_1[] = { 139 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 140 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 141 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 142 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 143 }; 144 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 145 146 GlobalProperty pc_compat_6_0[] = { 147 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 148 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 149 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 150 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 151 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 152 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 153 }; 154 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 155 156 GlobalProperty pc_compat_5_2[] = { 157 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 158 }; 159 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 160 161 GlobalProperty pc_compat_5_1[] = { 162 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 163 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 164 }; 165 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 166 167 GlobalProperty pc_compat_5_0[] = { 168 }; 169 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 170 171 GlobalProperty pc_compat_4_2[] = { 172 { "mch", "smbase-smram", "off" }, 173 }; 174 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 175 176 GlobalProperty pc_compat_4_1[] = {}; 177 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 178 179 GlobalProperty pc_compat_4_0[] = {}; 180 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 181 182 GlobalProperty pc_compat_3_1[] = { 183 { "intel-iommu", "dma-drain", "off" }, 184 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 185 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 186 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 187 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 188 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 189 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 190 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 191 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 192 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 193 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 194 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 195 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 196 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 197 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 198 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 199 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 200 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 201 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 202 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 203 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 204 }; 205 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 206 207 GlobalProperty pc_compat_3_0[] = { 208 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 209 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 210 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 211 }; 212 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 213 214 GlobalProperty pc_compat_2_12[] = { 215 { TYPE_X86_CPU, "legacy-cache", "on" }, 216 { TYPE_X86_CPU, "topoext", "off" }, 217 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 218 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 219 }; 220 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 221 222 GlobalProperty pc_compat_2_11[] = { 223 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 224 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 225 }; 226 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 227 228 GlobalProperty pc_compat_2_10[] = { 229 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 230 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 231 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 232 }; 233 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 234 235 GlobalProperty pc_compat_2_9[] = { 236 { "mch", "extended-tseg-mbytes", "0" }, 237 }; 238 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 239 240 GlobalProperty pc_compat_2_8[] = { 241 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 242 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 243 { "ICH9-LPC", "x-smi-broadcast", "off" }, 244 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 245 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 246 }; 247 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 248 249 GlobalProperty pc_compat_2_7[] = { 250 { TYPE_X86_CPU, "l3-cache", "off" }, 251 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 252 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 253 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 254 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 255 { "isa-pcspk", "migrate", "off" }, 256 }; 257 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 258 259 GlobalProperty pc_compat_2_6[] = { 260 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 261 { "vmxnet3", "romfile", "" }, 262 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 263 { "apic-common", "legacy-instance-id", "on", } 264 }; 265 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 266 267 GlobalProperty pc_compat_2_5[] = {}; 268 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 269 270 GlobalProperty pc_compat_2_4[] = { 271 PC_CPU_MODEL_IDS("2.4.0") 272 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 273 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 274 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 275 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 276 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 277 { TYPE_X86_CPU, "check", "off" }, 278 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 279 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 280 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 281 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 282 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 283 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 284 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 285 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 286 }; 287 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 288 289 GlobalProperty pc_compat_2_3[] = { 290 PC_CPU_MODEL_IDS("2.3.0") 291 { TYPE_X86_CPU, "arat", "off" }, 292 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 293 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 294 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 295 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 296 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 297 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 298 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 299 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 300 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 301 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 302 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 303 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 304 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 305 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 306 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 307 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 308 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 309 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 310 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 311 }; 312 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 313 314 GlobalProperty pc_compat_2_2[] = { 315 PC_CPU_MODEL_IDS("2.2.0") 316 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 317 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 318 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 319 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 320 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 321 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 322 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 323 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 324 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 325 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 326 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 327 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 328 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 329 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 330 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 331 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 332 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 333 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 334 }; 335 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 336 337 GlobalProperty pc_compat_2_1[] = { 338 PC_CPU_MODEL_IDS("2.1.0") 339 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 340 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 341 }; 342 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 343 344 GlobalProperty pc_compat_2_0[] = { 345 PC_CPU_MODEL_IDS("2.0.0") 346 { "virtio-scsi-pci", "any_layout", "off" }, 347 { "PIIX4_PM", "memory-hotplug-support", "off" }, 348 { "apic", "version", "0x11" }, 349 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 350 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 351 { "pci-serial", "prog_if", "0" }, 352 { "pci-serial-2x", "prog_if", "0" }, 353 { "pci-serial-4x", "prog_if", "0" }, 354 { "virtio-net-pci", "guest_announce", "off" }, 355 { "ICH9-LPC", "memory-hotplug-support", "off" }, 356 }; 357 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 358 359 GlobalProperty pc_compat_1_7[] = { 360 PC_CPU_MODEL_IDS("1.7.0") 361 { TYPE_USB_DEVICE, "msos-desc", "no" }, 362 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 363 { "hpet", HPET_INTCAP, "4" }, 364 }; 365 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 366 367 GlobalProperty pc_compat_1_6[] = { 368 PC_CPU_MODEL_IDS("1.6.0") 369 { "e1000", "mitigation", "off" }, 370 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 371 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 372 { "i440FX-pcihost", "short_root_bus", "1" }, 373 { "q35-pcihost", "short_root_bus", "1" }, 374 }; 375 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 376 377 GlobalProperty pc_compat_1_5[] = { 378 PC_CPU_MODEL_IDS("1.5.0") 379 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 380 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 381 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 382 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 383 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 384 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 385 { "virtio-net-pci", "any_layout", "off" }, 386 { TYPE_X86_CPU, "pmu", "on" }, 387 { "i440FX-pcihost", "short_root_bus", "0" }, 388 { "q35-pcihost", "short_root_bus", "0" }, 389 }; 390 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 391 392 GlobalProperty pc_compat_1_4[] = { 393 PC_CPU_MODEL_IDS("1.4.0") 394 { "scsi-hd", "discard_granularity", "0" }, 395 { "scsi-cd", "discard_granularity", "0" }, 396 { "ide-hd", "discard_granularity", "0" }, 397 { "ide-cd", "discard_granularity", "0" }, 398 { "virtio-blk-pci", "discard_granularity", "0" }, 399 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 400 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 401 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 402 { "e1000", "romfile", "pxe-e1000.rom" }, 403 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 404 { "pcnet", "romfile", "pxe-pcnet.rom" }, 405 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 406 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 407 { "486-" TYPE_X86_CPU, "model", "0" }, 408 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 409 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 410 }; 411 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 412 413 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 414 { 415 GSIState *s; 416 417 s = g_new0(GSIState, 1); 418 if (kvm_ioapic_in_kernel()) { 419 kvm_pc_setup_irq_routing(pci_enabled); 420 } 421 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 422 423 return s; 424 } 425 426 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 427 unsigned size) 428 { 429 } 430 431 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 432 { 433 return 0xffffffffffffffffULL; 434 } 435 436 /* MSDOS compatibility mode FPU exception support */ 437 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 438 unsigned size) 439 { 440 if (tcg_enabled()) { 441 cpu_set_ignne(); 442 } 443 } 444 445 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 446 { 447 return 0xffffffffffffffffULL; 448 } 449 450 /* PC cmos mappings */ 451 452 #define REG_EQUIPMENT_BYTE 0x14 453 454 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 455 int16_t cylinders, int8_t heads, int8_t sectors) 456 { 457 mc146818rtc_set_cmos_data(s, type_ofs, 47); 458 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 459 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 460 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 461 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 462 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 463 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 464 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 465 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 466 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 467 } 468 469 /* convert boot_device letter to something recognizable by the bios */ 470 static int boot_device2nibble(char boot_device) 471 { 472 switch(boot_device) { 473 case 'a': 474 case 'b': 475 return 0x01; /* floppy boot */ 476 case 'c': 477 return 0x02; /* hard drive boot */ 478 case 'd': 479 return 0x03; /* CD-ROM boot */ 480 case 'n': 481 return 0x04; /* Network boot */ 482 } 483 return 0; 484 } 485 486 static void set_boot_dev(MC146818RtcState *s, const char *boot_device, 487 Error **errp) 488 { 489 #define PC_MAX_BOOT_DEVICES 3 490 int nbds, bds[3] = { 0, }; 491 int i; 492 493 nbds = strlen(boot_device); 494 if (nbds > PC_MAX_BOOT_DEVICES) { 495 error_setg(errp, "Too many boot devices for PC"); 496 return; 497 } 498 for (i = 0; i < nbds; i++) { 499 bds[i] = boot_device2nibble(boot_device[i]); 500 if (bds[i] == 0) { 501 error_setg(errp, "Invalid boot device for PC: '%c'", 502 boot_device[i]); 503 return; 504 } 505 } 506 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 507 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 508 } 509 510 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 511 { 512 set_boot_dev(opaque, boot_device, errp); 513 } 514 515 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 516 { 517 int val, nb, i; 518 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 519 FLOPPY_DRIVE_TYPE_NONE }; 520 521 /* floppy type */ 522 if (floppy) { 523 for (i = 0; i < 2; i++) { 524 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 525 } 526 } 527 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 528 cmos_get_fd_drive_type(fd_type[1]); 529 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 530 531 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 532 nb = 0; 533 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 534 nb++; 535 } 536 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 537 nb++; 538 } 539 switch (nb) { 540 case 0: 541 break; 542 case 1: 543 val |= 0x01; /* 1 drive, ready for boot */ 544 break; 545 case 2: 546 val |= 0x41; /* 2 drives, ready for boot */ 547 break; 548 } 549 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 550 } 551 552 typedef struct pc_cmos_init_late_arg { 553 MC146818RtcState *rtc_state; 554 BusState *idebus[2]; 555 } pc_cmos_init_late_arg; 556 557 typedef struct check_fdc_state { 558 ISADevice *floppy; 559 bool multiple; 560 } CheckFdcState; 561 562 static int check_fdc(Object *obj, void *opaque) 563 { 564 CheckFdcState *state = opaque; 565 Object *fdc; 566 uint32_t iobase; 567 Error *local_err = NULL; 568 569 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 570 if (!fdc) { 571 return 0; 572 } 573 574 iobase = object_property_get_uint(obj, "iobase", &local_err); 575 if (local_err || iobase != 0x3f0) { 576 error_free(local_err); 577 return 0; 578 } 579 580 if (state->floppy) { 581 state->multiple = true; 582 } else { 583 state->floppy = ISA_DEVICE(obj); 584 } 585 return 0; 586 } 587 588 static const char * const fdc_container_path[] = { 589 "/unattached", "/peripheral", "/peripheral-anon" 590 }; 591 592 /* 593 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 594 * and ACPI objects. 595 */ 596 static ISADevice *pc_find_fdc0(void) 597 { 598 int i; 599 Object *container; 600 CheckFdcState state = { 0 }; 601 602 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 603 container = container_get(qdev_get_machine(), fdc_container_path[i]); 604 object_child_foreach(container, check_fdc, &state); 605 } 606 607 if (state.multiple) { 608 warn_report("multiple floppy disk controllers with " 609 "iobase=0x3f0 have been found"); 610 error_printf("the one being picked for CMOS setup might not reflect " 611 "your intent"); 612 } 613 614 return state.floppy; 615 } 616 617 static void pc_cmos_init_late(void *opaque) 618 { 619 pc_cmos_init_late_arg *arg = opaque; 620 MC146818RtcState *s = arg->rtc_state; 621 int16_t cylinders; 622 int8_t heads, sectors; 623 int val; 624 int i, trans; 625 626 val = 0; 627 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 628 &cylinders, &heads, §ors) >= 0) { 629 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 630 val |= 0xf0; 631 } 632 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 633 &cylinders, &heads, §ors) >= 0) { 634 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 635 val |= 0x0f; 636 } 637 mc146818rtc_set_cmos_data(s, 0x12, val); 638 639 val = 0; 640 for (i = 0; i < 4; i++) { 641 /* NOTE: ide_get_geometry() returns the physical 642 geometry. It is always such that: 1 <= sects <= 63, 1 643 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 644 geometry can be different if a translation is done. */ 645 if (arg->idebus[i / 2] && 646 ide_get_geometry(arg->idebus[i / 2], i % 2, 647 &cylinders, &heads, §ors) >= 0) { 648 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 649 assert((trans & ~3) == 0); 650 val |= trans << (i * 2); 651 } 652 } 653 mc146818rtc_set_cmos_data(s, 0x39, val); 654 655 pc_cmos_init_floppy(s, pc_find_fdc0()); 656 657 qemu_unregister_reset(pc_cmos_init_late, opaque); 658 } 659 660 void pc_cmos_init(PCMachineState *pcms, 661 BusState *idebus0, BusState *idebus1, 662 ISADevice *rtc) 663 { 664 int val; 665 static pc_cmos_init_late_arg arg; 666 X86MachineState *x86ms = X86_MACHINE(pcms); 667 MC146818RtcState *s = MC146818_RTC(rtc); 668 669 /* various important CMOS locations needed by PC/Bochs bios */ 670 671 /* memory size */ 672 /* base memory (first MiB) */ 673 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 674 mc146818rtc_set_cmos_data(s, 0x15, val); 675 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 676 /* extended memory (next 64MiB) */ 677 if (x86ms->below_4g_mem_size > 1 * MiB) { 678 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 679 } else { 680 val = 0; 681 } 682 if (val > 65535) 683 val = 65535; 684 mc146818rtc_set_cmos_data(s, 0x17, val); 685 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 686 mc146818rtc_set_cmos_data(s, 0x30, val); 687 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 688 /* memory between 16MiB and 4GiB */ 689 if (x86ms->below_4g_mem_size > 16 * MiB) { 690 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 691 } else { 692 val = 0; 693 } 694 if (val > 65535) 695 val = 65535; 696 mc146818rtc_set_cmos_data(s, 0x34, val); 697 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 698 /* memory above 4GiB */ 699 val = x86ms->above_4g_mem_size / 65536; 700 mc146818rtc_set_cmos_data(s, 0x5b, val); 701 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 702 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 703 704 object_property_add_link(OBJECT(pcms), "rtc_state", 705 TYPE_ISA_DEVICE, 706 (Object **)&x86ms->rtc, 707 object_property_allow_set_link, 708 OBJ_PROP_LINK_STRONG); 709 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 710 &error_abort); 711 712 set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal); 713 714 val = 0; 715 val |= 0x02; /* FPU is there */ 716 val |= 0x04; /* PS/2 mouse installed */ 717 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 718 719 /* hard drives and FDC */ 720 arg.rtc_state = s; 721 arg.idebus[0] = idebus0; 722 arg.idebus[1] = idebus1; 723 qemu_register_reset(pc_cmos_init_late, &arg); 724 } 725 726 static void handle_a20_line_change(void *opaque, int irq, int level) 727 { 728 X86CPU *cpu = opaque; 729 730 /* XXX: send to all CPUs ? */ 731 /* XXX: add logic to handle multiple A20 line sources */ 732 x86_cpu_set_a20(cpu, level); 733 } 734 735 #define NE2000_NB_MAX 6 736 737 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 738 0x280, 0x380 }; 739 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 740 741 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 742 { 743 static int nb_ne2k = 0; 744 745 if (nb_ne2k == NE2000_NB_MAX) 746 return; 747 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 748 ne2000_irq[nb_ne2k], nd); 749 nb_ne2k++; 750 } 751 752 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 753 { 754 X86CPU *cpu = opaque; 755 756 if (level) { 757 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 758 } 759 } 760 761 static 762 void pc_machine_done(Notifier *notifier, void *data) 763 { 764 PCMachineState *pcms = container_of(notifier, 765 PCMachineState, machine_done); 766 X86MachineState *x86ms = X86_MACHINE(pcms); 767 768 cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state, 769 &error_fatal); 770 771 if (pcms->cxl_devices_state.is_enabled) { 772 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 773 } 774 775 /* set the number of CPUs */ 776 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 777 778 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 779 780 acpi_setup(); 781 if (x86ms->fw_cfg) { 782 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 783 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 784 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 785 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 786 } 787 } 788 789 void pc_guest_info_init(PCMachineState *pcms) 790 { 791 X86MachineState *x86ms = X86_MACHINE(pcms); 792 793 x86ms->apic_xrupt_override = true; 794 pcms->machine_done.notify = pc_machine_done; 795 qemu_add_machine_init_done_notifier(&pcms->machine_done); 796 } 797 798 /* setup pci memory address space mapping into system address space */ 799 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 800 MemoryRegion *pci_address_space) 801 { 802 /* Set to lower priority than RAM */ 803 memory_region_add_subregion_overlap(system_memory, 0x0, 804 pci_address_space, -1); 805 } 806 807 void xen_load_linux(PCMachineState *pcms) 808 { 809 int i; 810 FWCfgState *fw_cfg; 811 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 812 X86MachineState *x86ms = X86_MACHINE(pcms); 813 814 assert(MACHINE(pcms)->kernel_filename != NULL); 815 816 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 817 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 818 rom_set_fw(fw_cfg); 819 820 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 821 pcmc->pvh_enabled); 822 for (i = 0; i < nb_option_roms; i++) { 823 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 824 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 825 !strcmp(option_rom[i].name, "pvh.bin") || 826 !strcmp(option_rom[i].name, "multiboot.bin") || 827 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 828 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 829 } 830 x86ms->fw_cfg = fw_cfg; 831 } 832 833 #define PC_ROM_MIN_VGA 0xc0000 834 #define PC_ROM_MIN_OPTION 0xc8000 835 #define PC_ROM_MAX 0xe0000 836 #define PC_ROM_ALIGN 0x800 837 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 838 839 static hwaddr pc_above_4g_end(PCMachineState *pcms) 840 { 841 X86MachineState *x86ms = X86_MACHINE(pcms); 842 843 if (pcms->sgx_epc.size != 0) { 844 return sgx_epc_above_4g_end(&pcms->sgx_epc); 845 } 846 847 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 848 } 849 850 static void pc_get_device_memory_range(PCMachineState *pcms, 851 hwaddr *base, 852 ram_addr_t *device_mem_size) 853 { 854 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 855 MachineState *machine = MACHINE(pcms); 856 ram_addr_t size; 857 hwaddr addr; 858 859 size = machine->maxram_size - machine->ram_size; 860 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 861 862 if (pcmc->enforce_aligned_dimm) { 863 /* size device region assuming 1G page max alignment per slot */ 864 size += (1 * GiB) * machine->ram_slots; 865 } 866 867 *base = addr; 868 *device_mem_size = size; 869 } 870 871 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 872 { 873 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 874 hwaddr cxl_base; 875 ram_addr_t size; 876 877 if (pcmc->has_reserved_memory) { 878 pc_get_device_memory_range(pcms, &cxl_base, &size); 879 cxl_base += size; 880 } else { 881 cxl_base = pc_above_4g_end(pcms); 882 } 883 884 return cxl_base; 885 } 886 887 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 888 { 889 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 890 891 if (pcms->cxl_devices_state.fixed_windows) { 892 GList *it; 893 894 start = ROUND_UP(start, 256 * MiB); 895 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 896 CXLFixedWindow *fw = it->data; 897 start += fw->size; 898 } 899 } 900 901 return start; 902 } 903 904 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 905 { 906 X86CPU *cpu = X86_CPU(first_cpu); 907 908 /* 32-bit systems don't have hole64 thus return max CPU address */ 909 if (cpu->phys_bits <= 32) { 910 return ((hwaddr)1 << cpu->phys_bits) - 1; 911 } 912 913 return pc_pci_hole64_start() + pci_hole64_size - 1; 914 } 915 916 /* 917 * AMD systems with an IOMMU have an additional hole close to the 918 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 919 * on kernel version, VFIO may or may not let you DMA map those ranges. 920 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 921 * with certain memory sizes. It's also wrong to use those IOVA ranges 922 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 923 * The ranges reserved for Hyper-Transport are: 924 * 925 * FD_0000_0000h - FF_FFFF_FFFFh 926 * 927 * The ranges represent the following: 928 * 929 * Base Address Top Address Use 930 * 931 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 932 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 933 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 934 * FD_F910_0000h FD_F91F_FFFFh System Management 935 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 936 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 937 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 938 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 939 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 940 * FE_2000_0000h FF_FFFF_FFFFh Reserved 941 * 942 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 943 * Table 3: Special Address Controls (GPA) for more information. 944 */ 945 #define AMD_HT_START 0xfd00000000UL 946 #define AMD_HT_END 0xffffffffffUL 947 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 948 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 949 950 void pc_memory_init(PCMachineState *pcms, 951 MemoryRegion *system_memory, 952 MemoryRegion *rom_memory, 953 MemoryRegion **ram_memory, 954 uint64_t pci_hole64_size) 955 { 956 int linux_boot, i; 957 MemoryRegion *option_rom_mr; 958 MemoryRegion *ram_below_4g, *ram_above_4g; 959 FWCfgState *fw_cfg; 960 MachineState *machine = MACHINE(pcms); 961 MachineClass *mc = MACHINE_GET_CLASS(machine); 962 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 963 X86MachineState *x86ms = X86_MACHINE(pcms); 964 hwaddr maxphysaddr, maxusedaddr; 965 hwaddr cxl_base, cxl_resv_end = 0; 966 X86CPU *cpu = X86_CPU(first_cpu); 967 968 assert(machine->ram_size == x86ms->below_4g_mem_size + 969 x86ms->above_4g_mem_size); 970 971 linux_boot = (machine->kernel_filename != NULL); 972 973 /* 974 * The HyperTransport range close to the 1T boundary is unique to AMD 975 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 976 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 977 * older machine types (<= 7.0) for compatibility purposes. 978 */ 979 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 980 /* Bail out if max possible address does not cross HT range */ 981 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 982 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 983 } 984 985 /* 986 * Advertise the HT region if address space covers the reserved 987 * region or if we relocate. 988 */ 989 if (cpu->phys_bits >= 40) { 990 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 991 } 992 } 993 994 /* 995 * phys-bits is required to be appropriately configured 996 * to make sure max used GPA is reachable. 997 */ 998 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 999 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 1000 if (maxphysaddr < maxusedaddr) { 1001 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 1002 " phys-bits too low (%u)", 1003 maxphysaddr, maxusedaddr, cpu->phys_bits); 1004 exit(EXIT_FAILURE); 1005 } 1006 1007 /* 1008 * Split single memory region and use aliases to address portions of it, 1009 * done for backwards compatibility with older qemus. 1010 */ 1011 *ram_memory = machine->ram; 1012 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1013 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 1014 0, x86ms->below_4g_mem_size); 1015 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1016 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 1017 if (x86ms->above_4g_mem_size > 0) { 1018 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1019 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 1020 machine->ram, 1021 x86ms->below_4g_mem_size, 1022 x86ms->above_4g_mem_size); 1023 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 1024 ram_above_4g); 1025 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 1026 E820_RAM); 1027 } 1028 1029 if (pcms->sgx_epc.size != 0) { 1030 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 1031 } 1032 1033 if (!pcmc->has_reserved_memory && 1034 (machine->ram_slots || 1035 (machine->maxram_size > machine->ram_size))) { 1036 1037 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1038 mc->name); 1039 exit(EXIT_FAILURE); 1040 } 1041 1042 /* always allocate the device memory information */ 1043 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1044 1045 /* initialize device memory address space */ 1046 if (pcmc->has_reserved_memory && 1047 (machine->ram_size < machine->maxram_size)) { 1048 ram_addr_t device_mem_size; 1049 1050 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1051 error_report("unsupported amount of memory slots: %"PRIu64, 1052 machine->ram_slots); 1053 exit(EXIT_FAILURE); 1054 } 1055 1056 if (QEMU_ALIGN_UP(machine->maxram_size, 1057 TARGET_PAGE_SIZE) != machine->maxram_size) { 1058 error_report("maximum memory size must by aligned to multiple of " 1059 "%d bytes", TARGET_PAGE_SIZE); 1060 exit(EXIT_FAILURE); 1061 } 1062 1063 pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size); 1064 1065 if ((machine->device_memory->base + device_mem_size) < 1066 device_mem_size) { 1067 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1068 machine->maxram_size); 1069 exit(EXIT_FAILURE); 1070 } 1071 1072 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1073 "device-memory", device_mem_size); 1074 memory_region_add_subregion(system_memory, machine->device_memory->base, 1075 &machine->device_memory->mr); 1076 } 1077 1078 if (pcms->cxl_devices_state.is_enabled) { 1079 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 1080 hwaddr cxl_size = MiB; 1081 1082 cxl_base = pc_get_cxl_range_start(pcms); 1083 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 1084 memory_region_add_subregion(system_memory, cxl_base, mr); 1085 cxl_resv_end = cxl_base + cxl_size; 1086 if (pcms->cxl_devices_state.fixed_windows) { 1087 hwaddr cxl_fmw_base; 1088 GList *it; 1089 1090 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 1091 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 1092 CXLFixedWindow *fw = it->data; 1093 1094 fw->base = cxl_fmw_base; 1095 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 1096 "cxl-fixed-memory-region", fw->size); 1097 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 1098 cxl_fmw_base += fw->size; 1099 cxl_resv_end = cxl_fmw_base; 1100 } 1101 } 1102 } 1103 1104 /* Initialize PC system firmware */ 1105 pc_system_firmware_init(pcms, rom_memory); 1106 1107 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1108 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1109 &error_fatal); 1110 if (pcmc->pci_enabled) { 1111 memory_region_set_readonly(option_rom_mr, true); 1112 } 1113 memory_region_add_subregion_overlap(rom_memory, 1114 PC_ROM_MIN_VGA, 1115 option_rom_mr, 1116 1); 1117 1118 fw_cfg = fw_cfg_arch_create(machine, 1119 x86ms->boot_cpus, x86ms->apic_id_limit); 1120 1121 rom_set_fw(fw_cfg); 1122 1123 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1124 uint64_t *val = g_malloc(sizeof(*val)); 1125 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1126 uint64_t res_mem_end = machine->device_memory->base; 1127 1128 if (!pcmc->broken_reserved_end) { 1129 res_mem_end += memory_region_size(&machine->device_memory->mr); 1130 } 1131 1132 if (pcms->cxl_devices_state.is_enabled) { 1133 res_mem_end = cxl_resv_end; 1134 } 1135 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1136 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1137 } 1138 1139 if (linux_boot) { 1140 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 1141 pcmc->pvh_enabled); 1142 } 1143 1144 for (i = 0; i < nb_option_roms; i++) { 1145 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1146 } 1147 x86ms->fw_cfg = fw_cfg; 1148 1149 /* Init default IOAPIC address space */ 1150 x86ms->ioapic_as = &address_space_memory; 1151 1152 /* Init ACPI memory hotplug IO base address */ 1153 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1154 } 1155 1156 /* 1157 * The 64bit pci hole starts after "above 4G RAM" and 1158 * potentially the space reserved for memory hotplug. 1159 */ 1160 uint64_t pc_pci_hole64_start(void) 1161 { 1162 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1163 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1164 MachineState *ms = MACHINE(pcms); 1165 uint64_t hole64_start = 0; 1166 ram_addr_t size = 0; 1167 1168 if (pcms->cxl_devices_state.is_enabled) { 1169 hole64_start = pc_get_cxl_range_end(pcms); 1170 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1171 pc_get_device_memory_range(pcms, &hole64_start, &size); 1172 if (!pcmc->broken_reserved_end) { 1173 hole64_start += size; 1174 } 1175 } else { 1176 hole64_start = pc_above_4g_end(pcms); 1177 } 1178 1179 return ROUND_UP(hole64_start, 1 * GiB); 1180 } 1181 1182 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1183 { 1184 DeviceState *dev = NULL; 1185 1186 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1187 if (pci_bus) { 1188 PCIDevice *pcidev = pci_vga_init(pci_bus); 1189 dev = pcidev ? &pcidev->qdev : NULL; 1190 } else if (isa_bus) { 1191 ISADevice *isadev = isa_vga_init(isa_bus); 1192 dev = isadev ? DEVICE(isadev) : NULL; 1193 } 1194 rom_reset_order_override(); 1195 return dev; 1196 } 1197 1198 static const MemoryRegionOps ioport80_io_ops = { 1199 .write = ioport80_write, 1200 .read = ioport80_read, 1201 .endianness = DEVICE_NATIVE_ENDIAN, 1202 .impl = { 1203 .min_access_size = 1, 1204 .max_access_size = 1, 1205 }, 1206 }; 1207 1208 static const MemoryRegionOps ioportF0_io_ops = { 1209 .write = ioportF0_write, 1210 .read = ioportF0_read, 1211 .endianness = DEVICE_NATIVE_ENDIAN, 1212 .impl = { 1213 .min_access_size = 1, 1214 .max_access_size = 1, 1215 }, 1216 }; 1217 1218 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1219 bool create_i8042, bool no_vmport) 1220 { 1221 int i; 1222 DriveInfo *fd[MAX_FD]; 1223 qemu_irq *a20_line; 1224 ISADevice *fdc, *i8042, *port92, *vmmouse; 1225 1226 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1227 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1228 1229 for (i = 0; i < MAX_FD; i++) { 1230 fd[i] = drive_get(IF_FLOPPY, 0, i); 1231 create_fdctrl |= !!fd[i]; 1232 } 1233 if (create_fdctrl) { 1234 fdc = isa_new(TYPE_ISA_FDC); 1235 if (fdc) { 1236 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1237 isa_fdc_init_drives(fdc, fd); 1238 } 1239 } 1240 1241 if (!create_i8042) { 1242 return; 1243 } 1244 1245 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1246 if (!no_vmport) { 1247 isa_create_simple(isa_bus, TYPE_VMPORT); 1248 vmmouse = isa_try_new("vmmouse"); 1249 } else { 1250 vmmouse = NULL; 1251 } 1252 if (vmmouse) { 1253 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1254 &error_abort); 1255 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1256 } 1257 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1258 1259 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1260 i8042_setup_a20_line(i8042, a20_line[0]); 1261 qdev_connect_gpio_out_named(DEVICE(port92), 1262 PORT92_A20_LINE, 0, a20_line[1]); 1263 g_free(a20_line); 1264 } 1265 1266 void pc_basic_device_init(struct PCMachineState *pcms, 1267 ISABus *isa_bus, qemu_irq *gsi, 1268 ISADevice **rtc_state, 1269 bool create_fdctrl, 1270 uint32_t hpet_irqs) 1271 { 1272 int i; 1273 DeviceState *hpet = NULL; 1274 int pit_isa_irq = 0; 1275 qemu_irq pit_alt_irq = NULL; 1276 qemu_irq rtc_irq = NULL; 1277 ISADevice *pit = NULL; 1278 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1279 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1280 X86MachineState *x86ms = X86_MACHINE(pcms); 1281 1282 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1283 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1284 1285 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1286 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1287 1288 /* 1289 * Check if an HPET shall be created. 1290 * 1291 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1292 * when the HPET wants to take over. Thus we have to disable the latter. 1293 */ 1294 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1295 kvm_has_pit_state2())) { 1296 hpet = qdev_try_new(TYPE_HPET); 1297 if (!hpet) { 1298 error_report("couldn't create HPET device"); 1299 exit(1); 1300 } 1301 /* 1302 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1303 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1304 * IRQ2. 1305 */ 1306 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1307 HPET_INTCAP, NULL); 1308 if (!compat) { 1309 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1310 } 1311 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1312 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1313 1314 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1315 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1316 } 1317 pit_isa_irq = -1; 1318 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1319 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1320 } 1321 *rtc_state = ISA_DEVICE(mc146818_rtc_init(isa_bus, 2000, rtc_irq)); 1322 1323 #ifdef CONFIG_XEN_EMU 1324 if (xen_mode == XEN_EMULATE) { 1325 xen_evtchn_connect_gsis(gsi); 1326 if (pcms->bus) { 1327 pci_create_simple(pcms->bus, -1, "xen-platform"); 1328 } 1329 xen_bus_init(); 1330 xen_be_init(); 1331 } 1332 #endif 1333 1334 qemu_register_boot_set(pc_boot_set, *rtc_state); 1335 1336 if (!xen_enabled() && 1337 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1338 if (kvm_pit_in_kernel()) { 1339 pit = kvm_pit_init(isa_bus, 0x40); 1340 } else { 1341 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1342 } 1343 if (hpet) { 1344 /* connect PIT to output control line of the HPET */ 1345 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1346 } 1347 pcspk_init(pcms->pcspk, isa_bus, pit); 1348 } 1349 1350 /* Super I/O */ 1351 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1352 pcms->vmport != ON_OFF_AUTO_ON); 1353 } 1354 1355 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1356 { 1357 int i; 1358 1359 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1360 for (i = 0; i < nb_nics; i++) { 1361 NICInfo *nd = &nd_table[i]; 1362 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1363 1364 if (g_str_equal(model, "ne2k_isa")) { 1365 pc_init_ne2k_isa(isa_bus, nd); 1366 } else { 1367 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1368 } 1369 } 1370 rom_reset_order_override(); 1371 } 1372 1373 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1374 { 1375 qemu_irq *i8259; 1376 1377 if (kvm_pic_in_kernel()) { 1378 i8259 = kvm_i8259_init(isa_bus); 1379 } else if (xen_enabled()) { 1380 i8259 = xen_interrupt_controller_init(); 1381 } else { 1382 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1383 } 1384 1385 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1386 i8259_irqs[i] = i8259[i]; 1387 } 1388 1389 g_free(i8259); 1390 } 1391 1392 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1393 Error **errp) 1394 { 1395 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1396 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1397 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1398 const MachineState *ms = MACHINE(hotplug_dev); 1399 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1400 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1401 Error *local_err = NULL; 1402 1403 /* 1404 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1405 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1406 * addition to cover this case. 1407 */ 1408 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1409 error_setg(errp, 1410 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1411 return; 1412 } 1413 1414 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1415 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1416 return; 1417 } 1418 1419 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1420 if (local_err) { 1421 error_propagate(errp, local_err); 1422 return; 1423 } 1424 1425 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1426 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1427 } 1428 1429 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1430 DeviceState *dev, Error **errp) 1431 { 1432 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1433 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1434 MachineState *ms = MACHINE(hotplug_dev); 1435 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1436 1437 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1438 1439 if (is_nvdimm) { 1440 nvdimm_plug(ms->nvdimms_state); 1441 } 1442 1443 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1444 } 1445 1446 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1447 DeviceState *dev, Error **errp) 1448 { 1449 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1450 1451 /* 1452 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1453 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1454 * addition to cover this case. 1455 */ 1456 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1457 error_setg(errp, 1458 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1459 return; 1460 } 1461 1462 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1463 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1464 return; 1465 } 1466 1467 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1468 errp); 1469 } 1470 1471 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1472 DeviceState *dev, Error **errp) 1473 { 1474 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1475 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1476 Error *local_err = NULL; 1477 1478 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1479 if (local_err) { 1480 goto out; 1481 } 1482 1483 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1484 qdev_unrealize(dev); 1485 out: 1486 error_propagate(errp, local_err); 1487 } 1488 1489 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1490 DeviceState *dev, Error **errp) 1491 { 1492 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1493 Error *local_err = NULL; 1494 1495 if (!hotplug_dev2 && dev->hotplugged) { 1496 /* 1497 * Without a bus hotplug handler, we cannot control the plug/unplug 1498 * order. We should never reach this point when hotplugging on x86, 1499 * however, better add a safety net. 1500 */ 1501 error_setg(errp, "hotplug of virtio based memory devices not supported" 1502 " on this bus."); 1503 return; 1504 } 1505 /* 1506 * First, see if we can plug this memory device at all. If that 1507 * succeeds, branch of to the actual hotplug handler. 1508 */ 1509 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1510 &local_err); 1511 if (!local_err && hotplug_dev2) { 1512 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1513 } 1514 error_propagate(errp, local_err); 1515 } 1516 1517 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1518 DeviceState *dev, Error **errp) 1519 { 1520 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1521 Error *local_err = NULL; 1522 1523 /* 1524 * Plug the memory device first and then branch off to the actual 1525 * hotplug handler. If that one fails, we can easily undo the memory 1526 * device bits. 1527 */ 1528 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1529 if (hotplug_dev2) { 1530 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1531 if (local_err) { 1532 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1533 } 1534 } 1535 error_propagate(errp, local_err); 1536 } 1537 1538 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1539 DeviceState *dev, Error **errp) 1540 { 1541 /* We don't support hot unplug of virtio based memory devices */ 1542 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1543 } 1544 1545 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1546 DeviceState *dev, Error **errp) 1547 { 1548 /* We don't support hot unplug of virtio based memory devices */ 1549 } 1550 1551 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1552 DeviceState *dev, Error **errp) 1553 { 1554 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1555 pc_memory_pre_plug(hotplug_dev, dev, errp); 1556 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1557 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1558 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1559 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1560 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1561 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1562 /* Declare the APIC range as the reserved MSI region */ 1563 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1564 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1565 1566 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1567 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1568 resv_prop_str, errp); 1569 g_free(resv_prop_str); 1570 } 1571 1572 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1573 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1574 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1575 1576 if (pcms->iommu) { 1577 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1578 "for x86 yet."); 1579 return; 1580 } 1581 pcms->iommu = dev; 1582 } 1583 } 1584 1585 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1586 DeviceState *dev, Error **errp) 1587 { 1588 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1589 pc_memory_plug(hotplug_dev, dev, errp); 1590 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1591 x86_cpu_plug(hotplug_dev, dev, errp); 1592 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1593 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1594 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1595 } 1596 } 1597 1598 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1599 DeviceState *dev, Error **errp) 1600 { 1601 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1602 pc_memory_unplug_request(hotplug_dev, dev, errp); 1603 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1604 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1605 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1606 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1607 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1608 } else { 1609 error_setg(errp, "acpi: device unplug request for not supported device" 1610 " type: %s", object_get_typename(OBJECT(dev))); 1611 } 1612 } 1613 1614 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1615 DeviceState *dev, Error **errp) 1616 { 1617 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1618 pc_memory_unplug(hotplug_dev, dev, errp); 1619 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1620 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1621 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1622 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1623 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1624 } else { 1625 error_setg(errp, "acpi: device unplug for not supported device" 1626 " type: %s", object_get_typename(OBJECT(dev))); 1627 } 1628 } 1629 1630 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1631 DeviceState *dev) 1632 { 1633 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1634 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1635 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1636 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1637 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1638 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1639 return HOTPLUG_HANDLER(machine); 1640 } 1641 1642 return NULL; 1643 } 1644 1645 static void 1646 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1647 const char *name, void *opaque, 1648 Error **errp) 1649 { 1650 MachineState *ms = MACHINE(obj); 1651 int64_t value = 0; 1652 1653 if (ms->device_memory) { 1654 value = memory_region_size(&ms->device_memory->mr); 1655 } 1656 1657 visit_type_int(v, name, &value, errp); 1658 } 1659 1660 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1661 void *opaque, Error **errp) 1662 { 1663 PCMachineState *pcms = PC_MACHINE(obj); 1664 OnOffAuto vmport = pcms->vmport; 1665 1666 visit_type_OnOffAuto(v, name, &vmport, errp); 1667 } 1668 1669 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1670 void *opaque, Error **errp) 1671 { 1672 PCMachineState *pcms = PC_MACHINE(obj); 1673 1674 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1675 } 1676 1677 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1678 { 1679 PCMachineState *pcms = PC_MACHINE(obj); 1680 1681 return pcms->smbus_enabled; 1682 } 1683 1684 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1685 { 1686 PCMachineState *pcms = PC_MACHINE(obj); 1687 1688 pcms->smbus_enabled = value; 1689 } 1690 1691 static bool pc_machine_get_sata(Object *obj, Error **errp) 1692 { 1693 PCMachineState *pcms = PC_MACHINE(obj); 1694 1695 return pcms->sata_enabled; 1696 } 1697 1698 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1699 { 1700 PCMachineState *pcms = PC_MACHINE(obj); 1701 1702 pcms->sata_enabled = value; 1703 } 1704 1705 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1706 { 1707 PCMachineState *pcms = PC_MACHINE(obj); 1708 1709 return pcms->hpet_enabled; 1710 } 1711 1712 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1713 { 1714 PCMachineState *pcms = PC_MACHINE(obj); 1715 1716 pcms->hpet_enabled = value; 1717 } 1718 1719 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1720 { 1721 PCMachineState *pcms = PC_MACHINE(obj); 1722 1723 return pcms->i8042_enabled; 1724 } 1725 1726 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1727 { 1728 PCMachineState *pcms = PC_MACHINE(obj); 1729 1730 pcms->i8042_enabled = value; 1731 } 1732 1733 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1734 { 1735 PCMachineState *pcms = PC_MACHINE(obj); 1736 1737 return pcms->default_bus_bypass_iommu; 1738 } 1739 1740 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1741 Error **errp) 1742 { 1743 PCMachineState *pcms = PC_MACHINE(obj); 1744 1745 pcms->default_bus_bypass_iommu = value; 1746 } 1747 1748 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1749 void *opaque, Error **errp) 1750 { 1751 PCMachineState *pcms = PC_MACHINE(obj); 1752 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1753 1754 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1755 } 1756 1757 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1758 void *opaque, Error **errp) 1759 { 1760 PCMachineState *pcms = PC_MACHINE(obj); 1761 1762 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1763 } 1764 1765 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1766 const char *name, void *opaque, 1767 Error **errp) 1768 { 1769 PCMachineState *pcms = PC_MACHINE(obj); 1770 uint64_t value = pcms->max_ram_below_4g; 1771 1772 visit_type_size(v, name, &value, errp); 1773 } 1774 1775 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1776 const char *name, void *opaque, 1777 Error **errp) 1778 { 1779 PCMachineState *pcms = PC_MACHINE(obj); 1780 uint64_t value; 1781 1782 if (!visit_type_size(v, name, &value, errp)) { 1783 return; 1784 } 1785 if (value > 4 * GiB) { 1786 error_setg(errp, 1787 "Machine option 'max-ram-below-4g=%"PRIu64 1788 "' expects size less than or equal to 4G", value); 1789 return; 1790 } 1791 1792 if (value < 1 * MiB) { 1793 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1794 "BIOS may not work with less than 1MiB", value); 1795 } 1796 1797 pcms->max_ram_below_4g = value; 1798 } 1799 1800 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1801 const char *name, void *opaque, 1802 Error **errp) 1803 { 1804 PCMachineState *pcms = PC_MACHINE(obj); 1805 uint64_t value = pcms->max_fw_size; 1806 1807 visit_type_size(v, name, &value, errp); 1808 } 1809 1810 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1811 const char *name, void *opaque, 1812 Error **errp) 1813 { 1814 PCMachineState *pcms = PC_MACHINE(obj); 1815 uint64_t value; 1816 1817 if (!visit_type_size(v, name, &value, errp)) { 1818 return; 1819 } 1820 1821 /* 1822 * We don't have a theoretically justifiable exact lower bound on the base 1823 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1824 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1825 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1826 * size. 1827 */ 1828 if (value > 16 * MiB) { 1829 error_setg(errp, 1830 "User specified max allowed firmware size %" PRIu64 " is " 1831 "greater than 16MiB. If combined firwmare size exceeds " 1832 "16MiB the system may not boot, or experience intermittent" 1833 "stability issues.", 1834 value); 1835 return; 1836 } 1837 1838 pcms->max_fw_size = value; 1839 } 1840 1841 1842 static void pc_machine_initfn(Object *obj) 1843 { 1844 PCMachineState *pcms = PC_MACHINE(obj); 1845 1846 #ifdef CONFIG_VMPORT 1847 pcms->vmport = ON_OFF_AUTO_AUTO; 1848 #else 1849 pcms->vmport = ON_OFF_AUTO_OFF; 1850 #endif /* CONFIG_VMPORT */ 1851 pcms->max_ram_below_4g = 0; /* use default */ 1852 pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32; 1853 1854 /* acpi build is enabled by default if machine supports it */ 1855 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1856 pcms->smbus_enabled = true; 1857 pcms->sata_enabled = true; 1858 pcms->i8042_enabled = true; 1859 pcms->max_fw_size = 8 * MiB; 1860 #ifdef CONFIG_HPET 1861 pcms->hpet_enabled = true; 1862 #endif 1863 pcms->default_bus_bypass_iommu = false; 1864 1865 pc_system_flash_create(pcms); 1866 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1867 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1868 OBJECT(pcms->pcspk), "audiodev"); 1869 cxl_machine_init(obj, &pcms->cxl_devices_state); 1870 } 1871 1872 int pc_machine_kvm_type(MachineState *machine, const char *kvm_type) 1873 { 1874 #ifdef CONFIG_XEN_EMU 1875 if (xen_mode == XEN_EMULATE) { 1876 xen_overlay_create(); 1877 xen_evtchn_create(); 1878 xen_gnttab_create(); 1879 xen_xenstore_create(); 1880 } 1881 #endif 1882 return 0; 1883 } 1884 1885 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1886 { 1887 CPUState *cs; 1888 X86CPU *cpu; 1889 1890 qemu_devices_reset(reason); 1891 1892 /* Reset APIC after devices have been reset to cancel 1893 * any changes that qemu_devices_reset() might have done. 1894 */ 1895 CPU_FOREACH(cs) { 1896 cpu = X86_CPU(cs); 1897 1898 x86_cpu_after_reset(cpu); 1899 } 1900 } 1901 1902 static void pc_machine_wakeup(MachineState *machine) 1903 { 1904 cpu_synchronize_all_states(); 1905 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1906 cpu_synchronize_all_post_reset(); 1907 } 1908 1909 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1910 { 1911 X86IOMMUState *iommu = x86_iommu_get_default(); 1912 IntelIOMMUState *intel_iommu; 1913 1914 if (iommu && 1915 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1916 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1917 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1918 if (!intel_iommu->caching_mode) { 1919 error_setg(errp, "Device assignment is not allowed without " 1920 "enabling caching-mode=on for Intel IOMMU."); 1921 return false; 1922 } 1923 } 1924 1925 return true; 1926 } 1927 1928 static void pc_machine_class_init(ObjectClass *oc, void *data) 1929 { 1930 MachineClass *mc = MACHINE_CLASS(oc); 1931 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1932 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1933 1934 pcmc->pci_enabled = true; 1935 pcmc->has_acpi_build = true; 1936 pcmc->rsdp_in_ram = true; 1937 pcmc->smbios_defaults = true; 1938 pcmc->smbios_uuid_encoded = true; 1939 pcmc->gigabyte_align = true; 1940 pcmc->has_reserved_memory = true; 1941 pcmc->kvmclock_enabled = true; 1942 pcmc->enforce_aligned_dimm = true; 1943 pcmc->enforce_amd_1tb_hole = true; 1944 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1945 * to be used at the moment, 32K should be enough for a while. */ 1946 pcmc->acpi_data_size = 0x20000 + 0x8000; 1947 pcmc->pvh_enabled = true; 1948 pcmc->kvmclock_create_always = true; 1949 pcmc->resizable_acpi_blob = true; 1950 assert(!mc->get_hotplug_handler); 1951 mc->get_hotplug_handler = pc_get_hotplug_handler; 1952 mc->hotplug_allowed = pc_hotplug_allowed; 1953 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1954 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1955 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1956 mc->auto_enable_numa_with_memhp = true; 1957 mc->auto_enable_numa_with_memdev = true; 1958 mc->has_hotpluggable_cpus = true; 1959 mc->default_boot_order = "cad"; 1960 mc->block_default_type = IF_IDE; 1961 mc->max_cpus = 255; 1962 mc->reset = pc_machine_reset; 1963 mc->wakeup = pc_machine_wakeup; 1964 hc->pre_plug = pc_machine_device_pre_plug_cb; 1965 hc->plug = pc_machine_device_plug_cb; 1966 hc->unplug_request = pc_machine_device_unplug_request_cb; 1967 hc->unplug = pc_machine_device_unplug_cb; 1968 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1969 mc->nvdimm_supported = true; 1970 mc->smp_props.dies_supported = true; 1971 mc->default_ram_id = "pc.ram"; 1972 1973 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1974 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1975 NULL, NULL); 1976 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1977 "Maximum ram below the 4G boundary (32bit boundary)"); 1978 1979 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1980 pc_machine_get_device_memory_region_size, NULL, 1981 NULL, NULL); 1982 1983 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1984 pc_machine_get_vmport, pc_machine_set_vmport, 1985 NULL, NULL); 1986 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1987 "Enable vmport (pc & q35)"); 1988 1989 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1990 pc_machine_get_smbus, pc_machine_set_smbus); 1991 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1992 "Enable/disable system management bus"); 1993 1994 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1995 pc_machine_get_sata, pc_machine_set_sata); 1996 object_class_property_set_description(oc, PC_MACHINE_SATA, 1997 "Enable/disable Serial ATA bus"); 1998 1999 object_class_property_add_bool(oc, "hpet", 2000 pc_machine_get_hpet, pc_machine_set_hpet); 2001 object_class_property_set_description(oc, "hpet", 2002 "Enable/disable high precision event timer emulation"); 2003 2004 object_class_property_add_bool(oc, PC_MACHINE_I8042, 2005 pc_machine_get_i8042, pc_machine_set_i8042); 2006 2007 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 2008 pc_machine_get_default_bus_bypass_iommu, 2009 pc_machine_set_default_bus_bypass_iommu); 2010 2011 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 2012 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 2013 NULL, NULL); 2014 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 2015 "Maximum combined firmware size"); 2016 2017 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 2018 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 2019 NULL, NULL); 2020 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 2021 "SMBIOS Entry Point type [32, 64]"); 2022 } 2023 2024 static const TypeInfo pc_machine_info = { 2025 .name = TYPE_PC_MACHINE, 2026 .parent = TYPE_X86_MACHINE, 2027 .abstract = true, 2028 .instance_size = sizeof(PCMachineState), 2029 .instance_init = pc_machine_initfn, 2030 .class_size = sizeof(PCMachineClass), 2031 .class_init = pc_machine_class_init, 2032 .interfaces = (InterfaceInfo[]) { 2033 { TYPE_HOTPLUG_HANDLER }, 2034 { } 2035 }, 2036 }; 2037 2038 static void pc_machine_register_types(void) 2039 { 2040 type_register_static(&pc_machine_info); 2041 } 2042 2043 type_init(pc_machine_register_types) 2044