1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/numa.h" 45 #include "sysemu/kvm.h" 46 #include "kvm_i386.h" 47 #include "hw/xen/xen.h" 48 #include "sysemu/block-backend.h" 49 #include "hw/block/block.h" 50 #include "ui/qemu-spice.h" 51 #include "exec/memory.h" 52 #include "exec/address-spaces.h" 53 #include "sysemu/arch_init.h" 54 #include "qemu/bitmap.h" 55 #include "qemu/config-file.h" 56 #include "hw/acpi/acpi.h" 57 #include "hw/acpi/cpu_hotplug.h" 58 #include "hw/cpu/icc_bus.h" 59 #include "hw/boards.h" 60 #include "hw/pci/pci_host.h" 61 #include "acpi-build.h" 62 #include "hw/mem/pc-dimm.h" 63 #include "trace.h" 64 #include "qapi/visitor.h" 65 #include "qapi-visit.h" 66 67 /* debug PC/ISA interrupts */ 68 //#define DEBUG_IRQ 69 70 #ifdef DEBUG_IRQ 71 #define DPRINTF(fmt, ...) \ 72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 73 #else 74 #define DPRINTF(fmt, ...) 75 #endif 76 77 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 78 * (128K) and other BIOS datastructures (less than 4K reported to be used at 79 * the moment, 32K should be enough for a while). */ 80 static unsigned acpi_data_size = 0x20000 + 0x8000; 81 void pc_set_legacy_acpi_data_size(void) 82 { 83 acpi_data_size = 0x10000; 84 } 85 86 #define BIOS_CFG_IOPORT 0x510 87 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 88 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 89 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 90 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 91 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 92 93 #define E820_NR_ENTRIES 16 94 95 struct e820_entry { 96 uint64_t address; 97 uint64_t length; 98 uint32_t type; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 struct e820_table { 102 uint32_t count; 103 struct e820_entry entry[E820_NR_ENTRIES]; 104 } QEMU_PACKED __attribute((__aligned__(4))); 105 106 static struct e820_table e820_reserve; 107 static struct e820_entry *e820_table; 108 static unsigned e820_entries; 109 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 110 111 void gsi_handler(void *opaque, int n, int level) 112 { 113 GSIState *s = opaque; 114 115 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 116 if (n < ISA_NUM_IRQS) { 117 qemu_set_irq(s->i8259_irq[n], level); 118 } 119 qemu_set_irq(s->ioapic_irq[n], level); 120 } 121 122 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 123 unsigned size) 124 { 125 } 126 127 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 128 { 129 return 0xffffffffffffffffULL; 130 } 131 132 /* MSDOS compatibility mode FPU exception support */ 133 static qemu_irq ferr_irq; 134 135 void pc_register_ferr_irq(qemu_irq irq) 136 { 137 ferr_irq = irq; 138 } 139 140 /* XXX: add IGNNE support */ 141 void cpu_set_ferr(CPUX86State *s) 142 { 143 qemu_irq_raise(ferr_irq); 144 } 145 146 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 147 unsigned size) 148 { 149 qemu_irq_lower(ferr_irq); 150 } 151 152 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 153 { 154 return 0xffffffffffffffffULL; 155 } 156 157 /* TSC handling */ 158 uint64_t cpu_get_tsc(CPUX86State *env) 159 { 160 return cpu_get_ticks(); 161 } 162 163 /* SMM support */ 164 165 static cpu_set_smm_t smm_set; 166 static void *smm_arg; 167 168 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 169 { 170 assert(smm_set == NULL); 171 assert(smm_arg == NULL); 172 smm_set = callback; 173 smm_arg = arg; 174 } 175 176 void cpu_smm_update(CPUX86State *env) 177 { 178 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 179 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 180 } 181 } 182 183 184 /* IRQ handling */ 185 int cpu_get_pic_interrupt(CPUX86State *env) 186 { 187 X86CPU *cpu = x86_env_get_cpu(env); 188 int intno; 189 190 intno = apic_get_interrupt(cpu->apic_state); 191 if (intno >= 0) { 192 return intno; 193 } 194 /* read the irq from the PIC */ 195 if (!apic_accept_pic_intr(cpu->apic_state)) { 196 return -1; 197 } 198 199 intno = pic_read_irq(isa_pic); 200 return intno; 201 } 202 203 static void pic_irq_request(void *opaque, int irq, int level) 204 { 205 CPUState *cs = first_cpu; 206 X86CPU *cpu = X86_CPU(cs); 207 208 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 209 if (cpu->apic_state) { 210 CPU_FOREACH(cs) { 211 cpu = X86_CPU(cs); 212 if (apic_accept_pic_intr(cpu->apic_state)) { 213 apic_deliver_pic_intr(cpu->apic_state, level); 214 } 215 } 216 } else { 217 if (level) { 218 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 219 } else { 220 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 221 } 222 } 223 } 224 225 /* PC cmos mappings */ 226 227 #define REG_EQUIPMENT_BYTE 0x14 228 229 static int cmos_get_fd_drive_type(FDriveType fd0) 230 { 231 int val; 232 233 switch (fd0) { 234 case FDRIVE_DRV_144: 235 /* 1.44 Mb 3"5 drive */ 236 val = 4; 237 break; 238 case FDRIVE_DRV_288: 239 /* 2.88 Mb 3"5 drive */ 240 val = 5; 241 break; 242 case FDRIVE_DRV_120: 243 /* 1.2 Mb 5"5 drive */ 244 val = 2; 245 break; 246 case FDRIVE_DRV_NONE: 247 default: 248 val = 0; 249 break; 250 } 251 return val; 252 } 253 254 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 255 int16_t cylinders, int8_t heads, int8_t sectors) 256 { 257 rtc_set_memory(s, type_ofs, 47); 258 rtc_set_memory(s, info_ofs, cylinders); 259 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 260 rtc_set_memory(s, info_ofs + 2, heads); 261 rtc_set_memory(s, info_ofs + 3, 0xff); 262 rtc_set_memory(s, info_ofs + 4, 0xff); 263 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 264 rtc_set_memory(s, info_ofs + 6, cylinders); 265 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 266 rtc_set_memory(s, info_ofs + 8, sectors); 267 } 268 269 /* convert boot_device letter to something recognizable by the bios */ 270 static int boot_device2nibble(char boot_device) 271 { 272 switch(boot_device) { 273 case 'a': 274 case 'b': 275 return 0x01; /* floppy boot */ 276 case 'c': 277 return 0x02; /* hard drive boot */ 278 case 'd': 279 return 0x03; /* CD-ROM boot */ 280 case 'n': 281 return 0x04; /* Network boot */ 282 } 283 return 0; 284 } 285 286 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 287 { 288 #define PC_MAX_BOOT_DEVICES 3 289 int nbds, bds[3] = { 0, }; 290 int i; 291 292 nbds = strlen(boot_device); 293 if (nbds > PC_MAX_BOOT_DEVICES) { 294 error_setg(errp, "Too many boot devices for PC"); 295 return; 296 } 297 for (i = 0; i < nbds; i++) { 298 bds[i] = boot_device2nibble(boot_device[i]); 299 if (bds[i] == 0) { 300 error_setg(errp, "Invalid boot device for PC: '%c'", 301 boot_device[i]); 302 return; 303 } 304 } 305 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 306 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 307 } 308 309 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 310 { 311 set_boot_dev(opaque, boot_device, errp); 312 } 313 314 typedef struct pc_cmos_init_late_arg { 315 ISADevice *rtc_state; 316 BusState *idebus[2]; 317 } pc_cmos_init_late_arg; 318 319 static void pc_cmos_init_late(void *opaque) 320 { 321 pc_cmos_init_late_arg *arg = opaque; 322 ISADevice *s = arg->rtc_state; 323 int16_t cylinders; 324 int8_t heads, sectors; 325 int val; 326 int i, trans; 327 328 val = 0; 329 if (ide_get_geometry(arg->idebus[0], 0, 330 &cylinders, &heads, §ors) >= 0) { 331 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 332 val |= 0xf0; 333 } 334 if (ide_get_geometry(arg->idebus[0], 1, 335 &cylinders, &heads, §ors) >= 0) { 336 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 337 val |= 0x0f; 338 } 339 rtc_set_memory(s, 0x12, val); 340 341 val = 0; 342 for (i = 0; i < 4; i++) { 343 /* NOTE: ide_get_geometry() returns the physical 344 geometry. It is always such that: 1 <= sects <= 63, 1 345 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 346 geometry can be different if a translation is done. */ 347 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 348 &cylinders, &heads, §ors) >= 0) { 349 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 350 assert((trans & ~3) == 0); 351 val |= trans << (i * 2); 352 } 353 } 354 rtc_set_memory(s, 0x39, val); 355 356 qemu_unregister_reset(pc_cmos_init_late, opaque); 357 } 358 359 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 360 const char *boot_device, MachineState *machine, 361 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 362 ISADevice *s) 363 { 364 int val, nb, i; 365 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 366 static pc_cmos_init_late_arg arg; 367 PCMachineState *pc_machine = PC_MACHINE(machine); 368 Error *local_err = NULL; 369 370 /* various important CMOS locations needed by PC/Bochs bios */ 371 372 /* memory size */ 373 /* base memory (first MiB) */ 374 val = MIN(ram_size / 1024, 640); 375 rtc_set_memory(s, 0x15, val); 376 rtc_set_memory(s, 0x16, val >> 8); 377 /* extended memory (next 64MiB) */ 378 if (ram_size > 1024 * 1024) { 379 val = (ram_size - 1024 * 1024) / 1024; 380 } else { 381 val = 0; 382 } 383 if (val > 65535) 384 val = 65535; 385 rtc_set_memory(s, 0x17, val); 386 rtc_set_memory(s, 0x18, val >> 8); 387 rtc_set_memory(s, 0x30, val); 388 rtc_set_memory(s, 0x31, val >> 8); 389 /* memory between 16MiB and 4GiB */ 390 if (ram_size > 16 * 1024 * 1024) { 391 val = (ram_size - 16 * 1024 * 1024) / 65536; 392 } else { 393 val = 0; 394 } 395 if (val > 65535) 396 val = 65535; 397 rtc_set_memory(s, 0x34, val); 398 rtc_set_memory(s, 0x35, val >> 8); 399 /* memory above 4GiB */ 400 val = above_4g_mem_size / 65536; 401 rtc_set_memory(s, 0x5b, val); 402 rtc_set_memory(s, 0x5c, val >> 8); 403 rtc_set_memory(s, 0x5d, val >> 16); 404 405 /* set the number of CPU */ 406 rtc_set_memory(s, 0x5f, smp_cpus - 1); 407 408 object_property_add_link(OBJECT(machine), "rtc_state", 409 TYPE_ISA_DEVICE, 410 (Object **)&pc_machine->rtc, 411 object_property_allow_set_link, 412 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 413 object_property_set_link(OBJECT(machine), OBJECT(s), 414 "rtc_state", &error_abort); 415 416 set_boot_dev(s, boot_device, &local_err); 417 if (local_err) { 418 error_report_err(local_err); 419 exit(1); 420 } 421 422 /* floppy type */ 423 if (floppy) { 424 for (i = 0; i < 2; i++) { 425 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 426 } 427 } 428 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 429 cmos_get_fd_drive_type(fd_type[1]); 430 rtc_set_memory(s, 0x10, val); 431 432 val = 0; 433 nb = 0; 434 if (fd_type[0] < FDRIVE_DRV_NONE) { 435 nb++; 436 } 437 if (fd_type[1] < FDRIVE_DRV_NONE) { 438 nb++; 439 } 440 switch (nb) { 441 case 0: 442 break; 443 case 1: 444 val |= 0x01; /* 1 drive, ready for boot */ 445 break; 446 case 2: 447 val |= 0x41; /* 2 drives, ready for boot */ 448 break; 449 } 450 val |= 0x02; /* FPU is there */ 451 val |= 0x04; /* PS/2 mouse installed */ 452 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 453 454 /* hard drives */ 455 arg.rtc_state = s; 456 arg.idebus[0] = idebus0; 457 arg.idebus[1] = idebus1; 458 qemu_register_reset(pc_cmos_init_late, &arg); 459 } 460 461 #define TYPE_PORT92 "port92" 462 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 463 464 /* port 92 stuff: could be split off */ 465 typedef struct Port92State { 466 ISADevice parent_obj; 467 468 MemoryRegion io; 469 uint8_t outport; 470 qemu_irq *a20_out; 471 } Port92State; 472 473 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 474 unsigned size) 475 { 476 Port92State *s = opaque; 477 int oldval = s->outport; 478 479 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 480 s->outport = val; 481 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 482 if ((val & 1) && !(oldval & 1)) { 483 qemu_system_reset_request(); 484 } 485 } 486 487 static uint64_t port92_read(void *opaque, hwaddr addr, 488 unsigned size) 489 { 490 Port92State *s = opaque; 491 uint32_t ret; 492 493 ret = s->outport; 494 DPRINTF("port92: read 0x%02x\n", ret); 495 return ret; 496 } 497 498 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 499 { 500 Port92State *s = PORT92(dev); 501 502 s->a20_out = a20_out; 503 } 504 505 static const VMStateDescription vmstate_port92_isa = { 506 .name = "port92", 507 .version_id = 1, 508 .minimum_version_id = 1, 509 .fields = (VMStateField[]) { 510 VMSTATE_UINT8(outport, Port92State), 511 VMSTATE_END_OF_LIST() 512 } 513 }; 514 515 static void port92_reset(DeviceState *d) 516 { 517 Port92State *s = PORT92(d); 518 519 s->outport &= ~1; 520 } 521 522 static const MemoryRegionOps port92_ops = { 523 .read = port92_read, 524 .write = port92_write, 525 .impl = { 526 .min_access_size = 1, 527 .max_access_size = 1, 528 }, 529 .endianness = DEVICE_LITTLE_ENDIAN, 530 }; 531 532 static void port92_initfn(Object *obj) 533 { 534 Port92State *s = PORT92(obj); 535 536 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 537 538 s->outport = 0; 539 } 540 541 static void port92_realizefn(DeviceState *dev, Error **errp) 542 { 543 ISADevice *isadev = ISA_DEVICE(dev); 544 Port92State *s = PORT92(dev); 545 546 isa_register_ioport(isadev, &s->io, 0x92); 547 } 548 549 static void port92_class_initfn(ObjectClass *klass, void *data) 550 { 551 DeviceClass *dc = DEVICE_CLASS(klass); 552 553 dc->realize = port92_realizefn; 554 dc->reset = port92_reset; 555 dc->vmsd = &vmstate_port92_isa; 556 /* 557 * Reason: unlike ordinary ISA devices, this one needs additional 558 * wiring: its A20 output line needs to be wired up by 559 * port92_init(). 560 */ 561 dc->cannot_instantiate_with_device_add_yet = true; 562 } 563 564 static const TypeInfo port92_info = { 565 .name = TYPE_PORT92, 566 .parent = TYPE_ISA_DEVICE, 567 .instance_size = sizeof(Port92State), 568 .instance_init = port92_initfn, 569 .class_init = port92_class_initfn, 570 }; 571 572 static void port92_register_types(void) 573 { 574 type_register_static(&port92_info); 575 } 576 577 type_init(port92_register_types) 578 579 static void handle_a20_line_change(void *opaque, int irq, int level) 580 { 581 X86CPU *cpu = opaque; 582 583 /* XXX: send to all CPUs ? */ 584 /* XXX: add logic to handle multiple A20 line sources */ 585 x86_cpu_set_a20(cpu, level); 586 } 587 588 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 589 { 590 int index = le32_to_cpu(e820_reserve.count); 591 struct e820_entry *entry; 592 593 if (type != E820_RAM) { 594 /* old FW_CFG_E820_TABLE entry -- reservations only */ 595 if (index >= E820_NR_ENTRIES) { 596 return -EBUSY; 597 } 598 entry = &e820_reserve.entry[index++]; 599 600 entry->address = cpu_to_le64(address); 601 entry->length = cpu_to_le64(length); 602 entry->type = cpu_to_le32(type); 603 604 e820_reserve.count = cpu_to_le32(index); 605 } 606 607 /* new "etc/e820" file -- include ram too */ 608 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 609 e820_table[e820_entries].address = cpu_to_le64(address); 610 e820_table[e820_entries].length = cpu_to_le64(length); 611 e820_table[e820_entries].type = cpu_to_le32(type); 612 e820_entries++; 613 614 return e820_entries; 615 } 616 617 int e820_get_num_entries(void) 618 { 619 return e820_entries; 620 } 621 622 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 623 { 624 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 625 *address = le64_to_cpu(e820_table[idx].address); 626 *length = le64_to_cpu(e820_table[idx].length); 627 return true; 628 } 629 return false; 630 } 631 632 /* Calculates the limit to CPU APIC ID values 633 * 634 * This function returns the limit for the APIC ID value, so that all 635 * CPU APIC IDs are < pc_apic_id_limit(). 636 * 637 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 638 */ 639 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 640 { 641 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 642 } 643 644 static FWCfgState *bochs_bios_init(void) 645 { 646 FWCfgState *fw_cfg; 647 uint8_t *smbios_tables, *smbios_anchor; 648 size_t smbios_tables_len, smbios_anchor_len; 649 uint64_t *numa_fw_cfg; 650 int i, j; 651 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 652 653 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 654 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 655 * 656 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 657 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 658 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 659 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 660 * may see". 661 * 662 * So, this means we must not use max_cpus, here, but the maximum possible 663 * APIC ID value, plus one. 664 * 665 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 666 * the APIC ID, not the "CPU index" 667 */ 668 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 669 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 670 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 671 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 672 acpi_tables, acpi_tables_len); 673 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 674 675 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 676 if (smbios_tables) { 677 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 678 smbios_tables, smbios_tables_len); 679 } 680 681 smbios_get_tables(&smbios_tables, &smbios_tables_len, 682 &smbios_anchor, &smbios_anchor_len); 683 if (smbios_anchor) { 684 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 685 smbios_tables, smbios_tables_len); 686 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 687 smbios_anchor, smbios_anchor_len); 688 } 689 690 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 691 &e820_reserve, sizeof(e820_reserve)); 692 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 693 sizeof(struct e820_entry) * e820_entries); 694 695 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 696 /* allocate memory for the NUMA channel: one (64bit) word for the number 697 * of nodes, one word for each VCPU->node and one word for each node to 698 * hold the amount of memory. 699 */ 700 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 701 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 702 for (i = 0; i < max_cpus; i++) { 703 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 704 assert(apic_id < apic_id_limit); 705 for (j = 0; j < nb_numa_nodes; j++) { 706 if (test_bit(i, numa_info[j].node_cpu)) { 707 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 708 break; 709 } 710 } 711 } 712 for (i = 0; i < nb_numa_nodes; i++) { 713 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 714 } 715 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 716 (1 + apic_id_limit + nb_numa_nodes) * 717 sizeof(*numa_fw_cfg)); 718 719 return fw_cfg; 720 } 721 722 static long get_file_size(FILE *f) 723 { 724 long where, size; 725 726 /* XXX: on Unix systems, using fstat() probably makes more sense */ 727 728 where = ftell(f); 729 fseek(f, 0, SEEK_END); 730 size = ftell(f); 731 fseek(f, where, SEEK_SET); 732 733 return size; 734 } 735 736 static void load_linux(FWCfgState *fw_cfg, 737 const char *kernel_filename, 738 const char *initrd_filename, 739 const char *kernel_cmdline, 740 hwaddr max_ram_size) 741 { 742 uint16_t protocol; 743 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 744 uint32_t initrd_max; 745 uint8_t header[8192], *setup, *kernel, *initrd_data; 746 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 747 FILE *f; 748 char *vmode; 749 750 /* Align to 16 bytes as a paranoia measure */ 751 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 752 753 /* load the kernel header */ 754 f = fopen(kernel_filename, "rb"); 755 if (!f || !(kernel_size = get_file_size(f)) || 756 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 757 MIN(ARRAY_SIZE(header), kernel_size)) { 758 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 759 kernel_filename, strerror(errno)); 760 exit(1); 761 } 762 763 /* kernel protocol version */ 764 #if 0 765 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 766 #endif 767 if (ldl_p(header+0x202) == 0x53726448) { 768 protocol = lduw_p(header+0x206); 769 } else { 770 /* This looks like a multiboot kernel. If it is, let's stop 771 treating it like a Linux kernel. */ 772 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 773 kernel_cmdline, kernel_size, header)) { 774 return; 775 } 776 protocol = 0; 777 } 778 779 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 780 /* Low kernel */ 781 real_addr = 0x90000; 782 cmdline_addr = 0x9a000 - cmdline_size; 783 prot_addr = 0x10000; 784 } else if (protocol < 0x202) { 785 /* High but ancient kernel */ 786 real_addr = 0x90000; 787 cmdline_addr = 0x9a000 - cmdline_size; 788 prot_addr = 0x100000; 789 } else { 790 /* High and recent kernel */ 791 real_addr = 0x10000; 792 cmdline_addr = 0x20000; 793 prot_addr = 0x100000; 794 } 795 796 #if 0 797 fprintf(stderr, 798 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 799 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 800 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 801 real_addr, 802 cmdline_addr, 803 prot_addr); 804 #endif 805 806 /* highest address for loading the initrd */ 807 if (protocol >= 0x203) { 808 initrd_max = ldl_p(header+0x22c); 809 } else { 810 initrd_max = 0x37ffffff; 811 } 812 813 if (initrd_max >= max_ram_size - acpi_data_size) { 814 initrd_max = max_ram_size - acpi_data_size - 1; 815 } 816 817 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 818 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 819 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 820 821 if (protocol >= 0x202) { 822 stl_p(header+0x228, cmdline_addr); 823 } else { 824 stw_p(header+0x20, 0xA33F); 825 stw_p(header+0x22, cmdline_addr-real_addr); 826 } 827 828 /* handle vga= parameter */ 829 vmode = strstr(kernel_cmdline, "vga="); 830 if (vmode) { 831 unsigned int video_mode; 832 /* skip "vga=" */ 833 vmode += 4; 834 if (!strncmp(vmode, "normal", 6)) { 835 video_mode = 0xffff; 836 } else if (!strncmp(vmode, "ext", 3)) { 837 video_mode = 0xfffe; 838 } else if (!strncmp(vmode, "ask", 3)) { 839 video_mode = 0xfffd; 840 } else { 841 video_mode = strtol(vmode, NULL, 0); 842 } 843 stw_p(header+0x1fa, video_mode); 844 } 845 846 /* loader type */ 847 /* High nybble = B reserved for QEMU; low nybble is revision number. 848 If this code is substantially changed, you may want to consider 849 incrementing the revision. */ 850 if (protocol >= 0x200) { 851 header[0x210] = 0xB0; 852 } 853 /* heap */ 854 if (protocol >= 0x201) { 855 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 856 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 857 } 858 859 /* load initrd */ 860 if (initrd_filename) { 861 if (protocol < 0x200) { 862 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 863 exit(1); 864 } 865 866 initrd_size = get_image_size(initrd_filename); 867 if (initrd_size < 0) { 868 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 869 initrd_filename, strerror(errno)); 870 exit(1); 871 } 872 873 initrd_addr = (initrd_max-initrd_size) & ~4095; 874 875 initrd_data = g_malloc(initrd_size); 876 load_image(initrd_filename, initrd_data); 877 878 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 879 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 880 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 881 882 stl_p(header+0x218, initrd_addr); 883 stl_p(header+0x21c, initrd_size); 884 } 885 886 /* load kernel and setup */ 887 setup_size = header[0x1f1]; 888 if (setup_size == 0) { 889 setup_size = 4; 890 } 891 setup_size = (setup_size+1)*512; 892 kernel_size -= setup_size; 893 894 setup = g_malloc(setup_size); 895 kernel = g_malloc(kernel_size); 896 fseek(f, 0, SEEK_SET); 897 if (fread(setup, 1, setup_size, f) != setup_size) { 898 fprintf(stderr, "fread() failed\n"); 899 exit(1); 900 } 901 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 902 fprintf(stderr, "fread() failed\n"); 903 exit(1); 904 } 905 fclose(f); 906 memcpy(setup, header, MIN(sizeof(header), setup_size)); 907 908 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 909 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 910 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 911 912 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 913 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 914 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 915 916 option_rom[nb_option_roms].name = "linuxboot.bin"; 917 option_rom[nb_option_roms].bootindex = 0; 918 nb_option_roms++; 919 } 920 921 #define NE2000_NB_MAX 6 922 923 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 924 0x280, 0x380 }; 925 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 926 927 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 928 { 929 static int nb_ne2k = 0; 930 931 if (nb_ne2k == NE2000_NB_MAX) 932 return; 933 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 934 ne2000_irq[nb_ne2k], nd); 935 nb_ne2k++; 936 } 937 938 DeviceState *cpu_get_current_apic(void) 939 { 940 if (current_cpu) { 941 X86CPU *cpu = X86_CPU(current_cpu); 942 return cpu->apic_state; 943 } else { 944 return NULL; 945 } 946 } 947 948 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 949 { 950 X86CPU *cpu = opaque; 951 952 if (level) { 953 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 954 } 955 } 956 957 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 958 DeviceState *icc_bridge, Error **errp) 959 { 960 X86CPU *cpu; 961 Error *local_err = NULL; 962 963 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 964 if (local_err != NULL) { 965 error_propagate(errp, local_err); 966 return NULL; 967 } 968 969 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 970 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 971 972 if (local_err) { 973 error_propagate(errp, local_err); 974 object_unref(OBJECT(cpu)); 975 cpu = NULL; 976 } 977 return cpu; 978 } 979 980 static const char *current_cpu_model; 981 982 void pc_hot_add_cpu(const int64_t id, Error **errp) 983 { 984 DeviceState *icc_bridge; 985 int64_t apic_id = x86_cpu_apic_id_from_index(id); 986 987 if (id < 0) { 988 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 989 return; 990 } 991 992 if (cpu_exists(apic_id)) { 993 error_setg(errp, "Unable to add CPU: %" PRIi64 994 ", it already exists", id); 995 return; 996 } 997 998 if (id >= max_cpus) { 999 error_setg(errp, "Unable to add CPU: %" PRIi64 1000 ", max allowed: %d", id, max_cpus - 1); 1001 return; 1002 } 1003 1004 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1005 error_setg(errp, "Unable to add CPU: %" PRIi64 1006 ", resulting APIC ID (%" PRIi64 ") is too large", 1007 id, apic_id); 1008 return; 1009 } 1010 1011 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1012 TYPE_ICC_BRIDGE, NULL)); 1013 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1014 } 1015 1016 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1017 { 1018 int i; 1019 X86CPU *cpu = NULL; 1020 Error *error = NULL; 1021 unsigned long apic_id_limit; 1022 1023 /* init CPUs */ 1024 if (cpu_model == NULL) { 1025 #ifdef TARGET_X86_64 1026 cpu_model = "qemu64"; 1027 #else 1028 cpu_model = "qemu32"; 1029 #endif 1030 } 1031 current_cpu_model = cpu_model; 1032 1033 apic_id_limit = pc_apic_id_limit(max_cpus); 1034 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1035 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1036 apic_id_limit - 1); 1037 exit(1); 1038 } 1039 1040 for (i = 0; i < smp_cpus; i++) { 1041 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1042 icc_bridge, &error); 1043 if (error) { 1044 error_report_err(error); 1045 exit(1); 1046 } 1047 } 1048 1049 /* map APIC MMIO area if CPU has APIC */ 1050 if (cpu && cpu->apic_state) { 1051 /* XXX: what if the base changes? */ 1052 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1053 APIC_DEFAULT_ADDRESS, 0x1000); 1054 } 1055 1056 /* tell smbios about cpuid version and features */ 1057 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1058 } 1059 1060 /* pci-info ROM file. Little endian format */ 1061 typedef struct PcRomPciInfo { 1062 uint64_t w32_min; 1063 uint64_t w32_max; 1064 uint64_t w64_min; 1065 uint64_t w64_max; 1066 } PcRomPciInfo; 1067 1068 typedef struct PcGuestInfoState { 1069 PcGuestInfo info; 1070 Notifier machine_done; 1071 } PcGuestInfoState; 1072 1073 static 1074 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1075 { 1076 PcGuestInfoState *guest_info_state = container_of(notifier, 1077 PcGuestInfoState, 1078 machine_done); 1079 acpi_setup(&guest_info_state->info); 1080 } 1081 1082 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1083 ram_addr_t above_4g_mem_size) 1084 { 1085 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1086 PcGuestInfo *guest_info = &guest_info_state->info; 1087 int i, j; 1088 1089 guest_info->ram_size_below_4g = below_4g_mem_size; 1090 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1091 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1092 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1093 guest_info->numa_nodes = nb_numa_nodes; 1094 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1095 sizeof *guest_info->node_mem); 1096 for (i = 0; i < nb_numa_nodes; i++) { 1097 guest_info->node_mem[i] = numa_info[i].node_mem; 1098 } 1099 1100 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1101 sizeof *guest_info->node_cpu); 1102 1103 for (i = 0; i < max_cpus; i++) { 1104 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1105 assert(apic_id < guest_info->apic_id_limit); 1106 for (j = 0; j < nb_numa_nodes; j++) { 1107 if (test_bit(i, numa_info[j].node_cpu)) { 1108 guest_info->node_cpu[apic_id] = j; 1109 break; 1110 } 1111 } 1112 } 1113 1114 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1115 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1116 return guest_info; 1117 } 1118 1119 /* setup pci memory address space mapping into system address space */ 1120 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1121 MemoryRegion *pci_address_space) 1122 { 1123 /* Set to lower priority than RAM */ 1124 memory_region_add_subregion_overlap(system_memory, 0x0, 1125 pci_address_space, -1); 1126 } 1127 1128 void pc_acpi_init(const char *default_dsdt) 1129 { 1130 char *filename; 1131 1132 if (acpi_tables != NULL) { 1133 /* manually set via -acpitable, leave it alone */ 1134 return; 1135 } 1136 1137 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1138 if (filename == NULL) { 1139 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1140 } else { 1141 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1142 &error_abort); 1143 Error *err = NULL; 1144 1145 qemu_opt_set(opts, "file", filename, &error_abort); 1146 1147 acpi_table_add_builtin(opts, &err); 1148 if (err) { 1149 error_report("WARNING: failed to load %s: %s", filename, 1150 error_get_pretty(err)); 1151 error_free(err); 1152 } 1153 g_free(filename); 1154 } 1155 } 1156 1157 FWCfgState *xen_load_linux(const char *kernel_filename, 1158 const char *kernel_cmdline, 1159 const char *initrd_filename, 1160 ram_addr_t below_4g_mem_size, 1161 PcGuestInfo *guest_info) 1162 { 1163 int i; 1164 FWCfgState *fw_cfg; 1165 1166 assert(kernel_filename != NULL); 1167 1168 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1169 rom_set_fw(fw_cfg); 1170 1171 load_linux(fw_cfg, kernel_filename, initrd_filename, 1172 kernel_cmdline, below_4g_mem_size); 1173 for (i = 0; i < nb_option_roms; i++) { 1174 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1175 !strcmp(option_rom[i].name, "multiboot.bin")); 1176 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1177 } 1178 guest_info->fw_cfg = fw_cfg; 1179 return fw_cfg; 1180 } 1181 1182 FWCfgState *pc_memory_init(MachineState *machine, 1183 MemoryRegion *system_memory, 1184 ram_addr_t below_4g_mem_size, 1185 ram_addr_t above_4g_mem_size, 1186 MemoryRegion *rom_memory, 1187 MemoryRegion **ram_memory, 1188 PcGuestInfo *guest_info) 1189 { 1190 int linux_boot, i; 1191 MemoryRegion *ram, *option_rom_mr; 1192 MemoryRegion *ram_below_4g, *ram_above_4g; 1193 FWCfgState *fw_cfg; 1194 PCMachineState *pcms = PC_MACHINE(machine); 1195 1196 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1197 1198 linux_boot = (machine->kernel_filename != NULL); 1199 1200 /* Allocate RAM. We allocate it as a single memory region and use 1201 * aliases to address portions of it, mostly for backwards compatibility 1202 * with older qemus that used qemu_ram_alloc(). 1203 */ 1204 ram = g_malloc(sizeof(*ram)); 1205 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1206 machine->ram_size); 1207 *ram_memory = ram; 1208 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1209 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1210 0, below_4g_mem_size); 1211 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1212 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1213 if (above_4g_mem_size > 0) { 1214 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1215 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1216 below_4g_mem_size, above_4g_mem_size); 1217 memory_region_add_subregion(system_memory, 0x100000000ULL, 1218 ram_above_4g); 1219 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1220 } 1221 1222 if (!guest_info->has_reserved_memory && 1223 (machine->ram_slots || 1224 (machine->maxram_size > machine->ram_size))) { 1225 MachineClass *mc = MACHINE_GET_CLASS(machine); 1226 1227 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1228 mc->name); 1229 exit(EXIT_FAILURE); 1230 } 1231 1232 /* initialize hotplug memory address space */ 1233 if (guest_info->has_reserved_memory && 1234 (machine->ram_size < machine->maxram_size)) { 1235 ram_addr_t hotplug_mem_size = 1236 machine->maxram_size - machine->ram_size; 1237 1238 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1239 error_report("unsupported amount of memory slots: %"PRIu64, 1240 machine->ram_slots); 1241 exit(EXIT_FAILURE); 1242 } 1243 1244 if (QEMU_ALIGN_UP(machine->maxram_size, 1245 TARGET_PAGE_SIZE) != machine->maxram_size) { 1246 error_report("maximum memory size must by aligned to multiple of " 1247 "%d bytes", TARGET_PAGE_SIZE); 1248 exit(EXIT_FAILURE); 1249 } 1250 1251 pcms->hotplug_memory_base = 1252 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1253 1254 if (pcms->enforce_aligned_dimm) { 1255 /* size hotplug region assuming 1G page max alignment per slot */ 1256 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1257 } 1258 1259 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1260 hotplug_mem_size) { 1261 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1262 machine->maxram_size); 1263 exit(EXIT_FAILURE); 1264 } 1265 1266 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1267 "hotplug-memory", hotplug_mem_size); 1268 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1269 &pcms->hotplug_memory); 1270 } 1271 1272 /* Initialize PC system firmware */ 1273 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1274 1275 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1276 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1277 &error_abort); 1278 vmstate_register_ram_global(option_rom_mr); 1279 memory_region_add_subregion_overlap(rom_memory, 1280 PC_ROM_MIN_VGA, 1281 option_rom_mr, 1282 1); 1283 1284 fw_cfg = bochs_bios_init(); 1285 rom_set_fw(fw_cfg); 1286 1287 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1288 uint64_t *val = g_malloc(sizeof(*val)); 1289 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1290 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1291 } 1292 1293 if (linux_boot) { 1294 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1295 machine->kernel_cmdline, below_4g_mem_size); 1296 } 1297 1298 for (i = 0; i < nb_option_roms; i++) { 1299 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1300 } 1301 guest_info->fw_cfg = fw_cfg; 1302 return fw_cfg; 1303 } 1304 1305 qemu_irq *pc_allocate_cpu_irq(void) 1306 { 1307 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1308 } 1309 1310 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1311 { 1312 DeviceState *dev = NULL; 1313 1314 if (pci_bus) { 1315 PCIDevice *pcidev = pci_vga_init(pci_bus); 1316 dev = pcidev ? &pcidev->qdev : NULL; 1317 } else if (isa_bus) { 1318 ISADevice *isadev = isa_vga_init(isa_bus); 1319 dev = isadev ? DEVICE(isadev) : NULL; 1320 } 1321 return dev; 1322 } 1323 1324 static void cpu_request_exit(void *opaque, int irq, int level) 1325 { 1326 CPUState *cpu = current_cpu; 1327 1328 if (cpu && level) { 1329 cpu_exit(cpu); 1330 } 1331 } 1332 1333 static const MemoryRegionOps ioport80_io_ops = { 1334 .write = ioport80_write, 1335 .read = ioport80_read, 1336 .endianness = DEVICE_NATIVE_ENDIAN, 1337 .impl = { 1338 .min_access_size = 1, 1339 .max_access_size = 1, 1340 }, 1341 }; 1342 1343 static const MemoryRegionOps ioportF0_io_ops = { 1344 .write = ioportF0_write, 1345 .read = ioportF0_read, 1346 .endianness = DEVICE_NATIVE_ENDIAN, 1347 .impl = { 1348 .min_access_size = 1, 1349 .max_access_size = 1, 1350 }, 1351 }; 1352 1353 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1354 ISADevice **rtc_state, 1355 ISADevice **floppy, 1356 bool no_vmport, 1357 uint32 hpet_irqs) 1358 { 1359 int i; 1360 DriveInfo *fd[MAX_FD]; 1361 DeviceState *hpet = NULL; 1362 int pit_isa_irq = 0; 1363 qemu_irq pit_alt_irq = NULL; 1364 qemu_irq rtc_irq = NULL; 1365 qemu_irq *a20_line; 1366 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1367 qemu_irq *cpu_exit_irq; 1368 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1369 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1370 1371 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1372 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1373 1374 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1375 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1376 1377 /* 1378 * Check if an HPET shall be created. 1379 * 1380 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1381 * when the HPET wants to take over. Thus we have to disable the latter. 1382 */ 1383 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1384 /* In order to set property, here not using sysbus_try_create_simple */ 1385 hpet = qdev_try_create(NULL, TYPE_HPET); 1386 if (hpet) { 1387 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1388 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1389 * IRQ8 and IRQ2. 1390 */ 1391 uint8_t compat = object_property_get_int(OBJECT(hpet), 1392 HPET_INTCAP, NULL); 1393 if (!compat) { 1394 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1395 } 1396 qdev_init_nofail(hpet); 1397 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1398 1399 for (i = 0; i < GSI_NUM_PINS; i++) { 1400 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1401 } 1402 pit_isa_irq = -1; 1403 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1404 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1405 } 1406 } 1407 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1408 1409 qemu_register_boot_set(pc_boot_set, *rtc_state); 1410 1411 if (!xen_enabled()) { 1412 if (kvm_irqchip_in_kernel()) { 1413 pit = kvm_pit_init(isa_bus, 0x40); 1414 } else { 1415 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1416 } 1417 if (hpet) { 1418 /* connect PIT to output control line of the HPET */ 1419 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1420 } 1421 pcspk_init(isa_bus, pit); 1422 } 1423 1424 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1425 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1426 1427 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1428 i8042 = isa_create_simple(isa_bus, "i8042"); 1429 i8042_setup_a20_line(i8042, &a20_line[0]); 1430 if (!no_vmport) { 1431 vmport_init(isa_bus); 1432 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1433 } else { 1434 vmmouse = NULL; 1435 } 1436 if (vmmouse) { 1437 DeviceState *dev = DEVICE(vmmouse); 1438 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1439 qdev_init_nofail(dev); 1440 } 1441 port92 = isa_create_simple(isa_bus, "port92"); 1442 port92_init(port92, &a20_line[1]); 1443 1444 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1445 DMA_init(0, cpu_exit_irq); 1446 1447 for(i = 0; i < MAX_FD; i++) { 1448 fd[i] = drive_get(IF_FLOPPY, 0, i); 1449 } 1450 *floppy = fdctrl_init_isa(isa_bus, fd); 1451 } 1452 1453 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1454 { 1455 int i; 1456 1457 for (i = 0; i < nb_nics; i++) { 1458 NICInfo *nd = &nd_table[i]; 1459 1460 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1461 pc_init_ne2k_isa(isa_bus, nd); 1462 } else { 1463 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1464 } 1465 } 1466 } 1467 1468 void pc_pci_device_init(PCIBus *pci_bus) 1469 { 1470 int max_bus; 1471 int bus; 1472 1473 max_bus = drive_get_max_bus(IF_SCSI); 1474 for (bus = 0; bus <= max_bus; bus++) { 1475 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1476 } 1477 } 1478 1479 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1480 { 1481 DeviceState *dev; 1482 SysBusDevice *d; 1483 unsigned int i; 1484 1485 if (kvm_irqchip_in_kernel()) { 1486 dev = qdev_create(NULL, "kvm-ioapic"); 1487 } else { 1488 dev = qdev_create(NULL, "ioapic"); 1489 } 1490 if (parent_name) { 1491 object_property_add_child(object_resolve_path(parent_name, NULL), 1492 "ioapic", OBJECT(dev), NULL); 1493 } 1494 qdev_init_nofail(dev); 1495 d = SYS_BUS_DEVICE(dev); 1496 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1497 1498 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1499 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1500 } 1501 } 1502 1503 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1504 { 1505 MachineClass *mc = MACHINE_CLASS(oc); 1506 QEMUMachine *qm = data; 1507 1508 mc->family = qm->family; 1509 mc->name = qm->name; 1510 mc->alias = qm->alias; 1511 mc->desc = qm->desc; 1512 mc->init = qm->init; 1513 mc->reset = qm->reset; 1514 mc->hot_add_cpu = qm->hot_add_cpu; 1515 mc->kvm_type = qm->kvm_type; 1516 mc->block_default_type = qm->block_default_type; 1517 mc->units_per_default_bus = qm->units_per_default_bus; 1518 mc->max_cpus = qm->max_cpus; 1519 mc->no_serial = qm->no_serial; 1520 mc->no_parallel = qm->no_parallel; 1521 mc->use_virtcon = qm->use_virtcon; 1522 mc->use_sclp = qm->use_sclp; 1523 mc->no_floppy = qm->no_floppy; 1524 mc->no_cdrom = qm->no_cdrom; 1525 mc->no_sdcard = qm->no_sdcard; 1526 mc->is_default = qm->is_default; 1527 mc->default_machine_opts = qm->default_machine_opts; 1528 mc->default_boot_order = qm->default_boot_order; 1529 mc->default_display = qm->default_display; 1530 mc->compat_props = qm->compat_props; 1531 mc->hw_version = qm->hw_version; 1532 } 1533 1534 void qemu_register_pc_machine(QEMUMachine *m) 1535 { 1536 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1537 TypeInfo ti = { 1538 .name = name, 1539 .parent = TYPE_PC_MACHINE, 1540 .class_init = pc_generic_machine_class_init, 1541 .class_data = (void *)m, 1542 }; 1543 1544 type_register(&ti); 1545 g_free(name); 1546 } 1547 1548 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1549 DeviceState *dev, Error **errp) 1550 { 1551 int slot; 1552 HotplugHandlerClass *hhc; 1553 Error *local_err = NULL; 1554 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1555 MachineState *machine = MACHINE(hotplug_dev); 1556 PCDIMMDevice *dimm = PC_DIMM(dev); 1557 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1558 MemoryRegion *mr = ddc->get_memory_region(dimm); 1559 uint64_t existing_dimms_capacity = 0; 1560 uint64_t align = TARGET_PAGE_SIZE; 1561 uint64_t addr; 1562 1563 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 1564 if (local_err) { 1565 goto out; 1566 } 1567 1568 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1569 align = memory_region_get_alignment(mr); 1570 } 1571 1572 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1573 memory_region_size(&pcms->hotplug_memory), 1574 !addr ? NULL : &addr, align, 1575 memory_region_size(mr), &local_err); 1576 if (local_err) { 1577 goto out; 1578 } 1579 1580 existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); 1581 if (local_err) { 1582 goto out; 1583 } 1584 1585 if (existing_dimms_capacity + memory_region_size(mr) > 1586 machine->maxram_size - machine->ram_size) { 1587 error_setg(&local_err, "not enough space, currently 0x%" PRIx64 1588 " in use of total hot pluggable 0x" RAM_ADDR_FMT, 1589 existing_dimms_capacity, 1590 machine->maxram_size - machine->ram_size); 1591 goto out; 1592 } 1593 1594 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1595 if (local_err) { 1596 goto out; 1597 } 1598 trace_mhp_pc_dimm_assigned_address(addr); 1599 1600 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1601 if (local_err) { 1602 goto out; 1603 } 1604 1605 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1606 machine->ram_slots, &local_err); 1607 if (local_err) { 1608 goto out; 1609 } 1610 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1611 if (local_err) { 1612 goto out; 1613 } 1614 trace_mhp_pc_dimm_assigned_slot(slot); 1615 1616 if (!pcms->acpi_dev) { 1617 error_setg(&local_err, 1618 "memory hotplug is not enabled: missing acpi device"); 1619 goto out; 1620 } 1621 1622 if (kvm_enabled() && !kvm_has_free_slot(machine)) { 1623 error_setg(&local_err, "hypervisor has no free memory slots left"); 1624 goto out; 1625 } 1626 1627 memory_region_add_subregion(&pcms->hotplug_memory, 1628 addr - pcms->hotplug_memory_base, mr); 1629 vmstate_register_ram(mr, dev); 1630 1631 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1632 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1633 out: 1634 error_propagate(errp, local_err); 1635 } 1636 1637 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1638 DeviceState *dev, Error **errp) 1639 { 1640 HotplugHandlerClass *hhc; 1641 Error *local_err = NULL; 1642 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1643 1644 if (!dev->hotplugged) { 1645 goto out; 1646 } 1647 1648 if (!pcms->acpi_dev) { 1649 error_setg(&local_err, 1650 "cpu hotplug is not enabled: missing acpi device"); 1651 goto out; 1652 } 1653 1654 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1655 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1656 if (local_err) { 1657 goto out; 1658 } 1659 1660 /* increment the number of CPUs */ 1661 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1662 out: 1663 error_propagate(errp, local_err); 1664 } 1665 1666 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1667 DeviceState *dev, Error **errp) 1668 { 1669 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1670 pc_dimm_plug(hotplug_dev, dev, errp); 1671 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1672 pc_cpu_plug(hotplug_dev, dev, errp); 1673 } 1674 } 1675 1676 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1677 DeviceState *dev, Error **errp) 1678 { 1679 error_setg(errp, "acpi: device unplug request for not supported device" 1680 " type: %s", object_get_typename(OBJECT(dev))); 1681 } 1682 1683 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1684 DeviceState *dev, Error **errp) 1685 { 1686 error_setg(errp, "acpi: device unplug for not supported device" 1687 " type: %s", object_get_typename(OBJECT(dev))); 1688 } 1689 1690 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1691 DeviceState *dev) 1692 { 1693 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1694 1695 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1696 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1697 return HOTPLUG_HANDLER(machine); 1698 } 1699 1700 return pcmc->get_hotplug_handler ? 1701 pcmc->get_hotplug_handler(machine, dev) : NULL; 1702 } 1703 1704 static void 1705 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1706 const char *name, Error **errp) 1707 { 1708 PCMachineState *pcms = PC_MACHINE(obj); 1709 int64_t value = memory_region_size(&pcms->hotplug_memory); 1710 1711 visit_type_int(v, &value, name, errp); 1712 } 1713 1714 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1715 void *opaque, const char *name, 1716 Error **errp) 1717 { 1718 PCMachineState *pcms = PC_MACHINE(obj); 1719 uint64_t value = pcms->max_ram_below_4g; 1720 1721 visit_type_size(v, &value, name, errp); 1722 } 1723 1724 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1725 void *opaque, const char *name, 1726 Error **errp) 1727 { 1728 PCMachineState *pcms = PC_MACHINE(obj); 1729 Error *error = NULL; 1730 uint64_t value; 1731 1732 visit_type_size(v, &value, name, &error); 1733 if (error) { 1734 error_propagate(errp, error); 1735 return; 1736 } 1737 if (value > (1ULL << 32)) { 1738 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1739 "Machine option 'max-ram-below-4g=%"PRIu64 1740 "' expects size less than or equal to 4G", value); 1741 error_propagate(errp, error); 1742 return; 1743 } 1744 1745 if (value < (1ULL << 20)) { 1746 error_report("Warning: small max_ram_below_4g(%"PRIu64 1747 ") less than 1M. BIOS may not work..", 1748 value); 1749 } 1750 1751 pcms->max_ram_below_4g = value; 1752 } 1753 1754 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1755 const char *name, Error **errp) 1756 { 1757 PCMachineState *pcms = PC_MACHINE(obj); 1758 OnOffAuto vmport = pcms->vmport; 1759 1760 visit_type_OnOffAuto(v, &vmport, name, errp); 1761 } 1762 1763 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1764 const char *name, Error **errp) 1765 { 1766 PCMachineState *pcms = PC_MACHINE(obj); 1767 1768 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1769 } 1770 1771 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1772 { 1773 PCMachineState *pcms = PC_MACHINE(obj); 1774 1775 return pcms->enforce_aligned_dimm; 1776 } 1777 1778 static void pc_machine_initfn(Object *obj) 1779 { 1780 PCMachineState *pcms = PC_MACHINE(obj); 1781 1782 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1783 pc_machine_get_hotplug_memory_region_size, 1784 NULL, NULL, NULL, NULL); 1785 1786 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1787 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1788 pc_machine_get_max_ram_below_4g, 1789 pc_machine_set_max_ram_below_4g, 1790 NULL, NULL, NULL); 1791 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1792 "Maximum ram below the 4G boundary (32bit boundary)", 1793 NULL); 1794 1795 pcms->vmport = ON_OFF_AUTO_AUTO; 1796 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1797 pc_machine_get_vmport, 1798 pc_machine_set_vmport, 1799 NULL, NULL, NULL); 1800 object_property_set_description(obj, PC_MACHINE_VMPORT, 1801 "Enable vmport (pc & q35)", 1802 NULL); 1803 1804 pcms->enforce_aligned_dimm = true; 1805 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1806 pc_machine_get_aligned_dimm, 1807 NULL, NULL); 1808 } 1809 1810 static void pc_machine_class_init(ObjectClass *oc, void *data) 1811 { 1812 MachineClass *mc = MACHINE_CLASS(oc); 1813 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1814 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1815 1816 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1817 mc->get_hotplug_handler = pc_get_hotpug_handler; 1818 hc->plug = pc_machine_device_plug_cb; 1819 hc->unplug_request = pc_machine_device_unplug_request_cb; 1820 hc->unplug = pc_machine_device_unplug_cb; 1821 } 1822 1823 static const TypeInfo pc_machine_info = { 1824 .name = TYPE_PC_MACHINE, 1825 .parent = TYPE_MACHINE, 1826 .abstract = true, 1827 .instance_size = sizeof(PCMachineState), 1828 .instance_init = pc_machine_initfn, 1829 .class_size = sizeof(PCMachineClass), 1830 .class_init = pc_machine_class_init, 1831 .interfaces = (InterfaceInfo[]) { 1832 { TYPE_HOTPLUG_HANDLER }, 1833 { } 1834 }, 1835 }; 1836 1837 static void pc_machine_register_types(void) 1838 { 1839 type_register_static(&pc_machine_info); 1840 } 1841 1842 type_init(pc_machine_register_types) 1843