1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "multiboot.h" 45 #include "hw/timer/mc146818rtc.h" 46 #include "hw/dma/i8257.h" 47 #include "hw/timer/i8254.h" 48 #include "hw/input/i8042.h" 49 #include "hw/audio/pcspk.h" 50 #include "hw/pci/msi.h" 51 #include "hw/sysbus.h" 52 #include "sysemu/sysemu.h" 53 #include "sysemu/tcg.h" 54 #include "sysemu/numa.h" 55 #include "sysemu/kvm.h" 56 #include "sysemu/qtest.h" 57 #include "kvm_i386.h" 58 #include "hw/xen/xen.h" 59 #include "hw/xen/start_info.h" 60 #include "ui/qemu-spice.h" 61 #include "exec/memory.h" 62 #include "exec/address-spaces.h" 63 #include "sysemu/arch_init.h" 64 #include "qemu/bitmap.h" 65 #include "qemu/config-file.h" 66 #include "qemu/error-report.h" 67 #include "qemu/option.h" 68 #include "hw/acpi/acpi.h" 69 #include "hw/acpi/cpu_hotplug.h" 70 #include "hw/boards.h" 71 #include "acpi-build.h" 72 #include "hw/mem/pc-dimm.h" 73 #include "qapi/error.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qapi/visitor.h" 76 #include "qom/cpu.h" 77 #include "hw/nmi.h" 78 #include "hw/usb.h" 79 #include "hw/i386/intel_iommu.h" 80 #include "hw/net/ne2000-isa.h" 81 #include "standard-headers/asm-x86/bootparam.h" 82 #include "hw/virtio/virtio-pmem-pci.h" 83 #include "hw/mem/memory-device.h" 84 #include "sysemu/replay.h" 85 #include "qapi/qmp/qerror.h" 86 87 /* debug PC/ISA interrupts */ 88 //#define DEBUG_IRQ 89 90 #ifdef DEBUG_IRQ 91 #define DPRINTF(fmt, ...) \ 92 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 93 #else 94 #define DPRINTF(fmt, ...) 95 #endif 96 97 #define E820_NR_ENTRIES 16 98 99 struct e820_entry { 100 uint64_t address; 101 uint64_t length; 102 uint32_t type; 103 } QEMU_PACKED __attribute((__aligned__(4))); 104 105 struct e820_table { 106 uint32_t count; 107 struct e820_entry entry[E820_NR_ENTRIES]; 108 } QEMU_PACKED __attribute((__aligned__(4))); 109 110 static struct e820_table e820_reserve; 111 static struct e820_entry *e820_table; 112 static unsigned e820_entries; 113 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 114 115 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 116 static size_t pvh_start_addr; 117 118 GlobalProperty pc_compat_4_0[] = {}; 119 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 120 121 GlobalProperty pc_compat_3_1[] = { 122 { "intel-iommu", "dma-drain", "off" }, 123 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 124 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 125 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 126 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 127 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 128 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 129 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 130 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 131 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 132 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 133 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 134 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 136 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 137 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 138 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 139 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 140 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 141 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 142 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 143 }; 144 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 145 146 GlobalProperty pc_compat_3_0[] = { 147 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 148 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 149 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 150 }; 151 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 152 153 GlobalProperty pc_compat_2_12[] = { 154 { TYPE_X86_CPU, "legacy-cache", "on" }, 155 { TYPE_X86_CPU, "topoext", "off" }, 156 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 157 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 158 }; 159 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 160 161 GlobalProperty pc_compat_2_11[] = { 162 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 163 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 164 }; 165 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 166 167 GlobalProperty pc_compat_2_10[] = { 168 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 169 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 170 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 171 }; 172 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 173 174 GlobalProperty pc_compat_2_9[] = { 175 { "mch", "extended-tseg-mbytes", "0" }, 176 }; 177 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 178 179 GlobalProperty pc_compat_2_8[] = { 180 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 181 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 182 { "ICH9-LPC", "x-smi-broadcast", "off" }, 183 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 184 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 185 }; 186 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 187 188 GlobalProperty pc_compat_2_7[] = { 189 { TYPE_X86_CPU, "l3-cache", "off" }, 190 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 191 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 192 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 193 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 194 { "isa-pcspk", "migrate", "off" }, 195 }; 196 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 197 198 GlobalProperty pc_compat_2_6[] = { 199 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 200 { "vmxnet3", "romfile", "" }, 201 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 202 { "apic-common", "legacy-instance-id", "on", } 203 }; 204 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 205 206 GlobalProperty pc_compat_2_5[] = {}; 207 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 208 209 GlobalProperty pc_compat_2_4[] = { 210 PC_CPU_MODEL_IDS("2.4.0") 211 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 212 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 213 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 214 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 215 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 216 { TYPE_X86_CPU, "check", "off" }, 217 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 218 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 219 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 220 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 221 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 222 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 223 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 224 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 225 }; 226 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 227 228 GlobalProperty pc_compat_2_3[] = { 229 PC_CPU_MODEL_IDS("2.3.0") 230 { TYPE_X86_CPU, "arat", "off" }, 231 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 232 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 233 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 234 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 235 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 236 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 237 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 238 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 250 }; 251 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 252 253 GlobalProperty pc_compat_2_2[] = { 254 PC_CPU_MODEL_IDS("2.2.0") 255 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 270 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 271 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 272 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 273 }; 274 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 275 276 GlobalProperty pc_compat_2_1[] = { 277 PC_CPU_MODEL_IDS("2.1.0") 278 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 279 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 280 }; 281 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 282 283 GlobalProperty pc_compat_2_0[] = { 284 PC_CPU_MODEL_IDS("2.0.0") 285 { "virtio-scsi-pci", "any_layout", "off" }, 286 { "PIIX4_PM", "memory-hotplug-support", "off" }, 287 { "apic", "version", "0x11" }, 288 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 289 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 290 { "pci-serial", "prog_if", "0" }, 291 { "pci-serial-2x", "prog_if", "0" }, 292 { "pci-serial-4x", "prog_if", "0" }, 293 { "virtio-net-pci", "guest_announce", "off" }, 294 { "ICH9-LPC", "memory-hotplug-support", "off" }, 295 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 296 { "ioh3420", COMPAT_PROP_PCP, "off" }, 297 }; 298 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 299 300 GlobalProperty pc_compat_1_7[] = { 301 PC_CPU_MODEL_IDS("1.7.0") 302 { TYPE_USB_DEVICE, "msos-desc", "no" }, 303 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 304 { "hpet", HPET_INTCAP, "4" }, 305 }; 306 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 307 308 GlobalProperty pc_compat_1_6[] = { 309 PC_CPU_MODEL_IDS("1.6.0") 310 { "e1000", "mitigation", "off" }, 311 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 312 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 313 { "i440FX-pcihost", "short_root_bus", "1" }, 314 { "q35-pcihost", "short_root_bus", "1" }, 315 }; 316 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 317 318 GlobalProperty pc_compat_1_5[] = { 319 PC_CPU_MODEL_IDS("1.5.0") 320 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 321 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 322 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 323 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 324 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 325 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 326 { "virtio-net-pci", "any_layout", "off" }, 327 { TYPE_X86_CPU, "pmu", "on" }, 328 { "i440FX-pcihost", "short_root_bus", "0" }, 329 { "q35-pcihost", "short_root_bus", "0" }, 330 }; 331 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 332 333 GlobalProperty pc_compat_1_4[] = { 334 PC_CPU_MODEL_IDS("1.4.0") 335 { "scsi-hd", "discard_granularity", "0" }, 336 { "scsi-cd", "discard_granularity", "0" }, 337 { "scsi-disk", "discard_granularity", "0" }, 338 { "ide-hd", "discard_granularity", "0" }, 339 { "ide-cd", "discard_granularity", "0" }, 340 { "ide-drive", "discard_granularity", "0" }, 341 { "virtio-blk-pci", "discard_granularity", "0" }, 342 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 343 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 344 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 345 { "e1000", "romfile", "pxe-e1000.rom" }, 346 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 347 { "pcnet", "romfile", "pxe-pcnet.rom" }, 348 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 349 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 350 { "486-" TYPE_X86_CPU, "model", "0" }, 351 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 352 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 353 }; 354 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 355 356 void gsi_handler(void *opaque, int n, int level) 357 { 358 GSIState *s = opaque; 359 360 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 361 if (n < ISA_NUM_IRQS) { 362 qemu_set_irq(s->i8259_irq[n], level); 363 } 364 qemu_set_irq(s->ioapic_irq[n], level); 365 } 366 367 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 368 unsigned size) 369 { 370 } 371 372 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 373 { 374 return 0xffffffffffffffffULL; 375 } 376 377 /* MSDOS compatibility mode FPU exception support */ 378 static qemu_irq ferr_irq; 379 380 void pc_register_ferr_irq(qemu_irq irq) 381 { 382 ferr_irq = irq; 383 } 384 385 /* XXX: add IGNNE support */ 386 void cpu_set_ferr(CPUX86State *s) 387 { 388 qemu_irq_raise(ferr_irq); 389 } 390 391 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 392 unsigned size) 393 { 394 qemu_irq_lower(ferr_irq); 395 } 396 397 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 398 { 399 return 0xffffffffffffffffULL; 400 } 401 402 /* TSC handling */ 403 uint64_t cpu_get_tsc(CPUX86State *env) 404 { 405 return cpu_get_ticks(); 406 } 407 408 /* IRQ handling */ 409 int cpu_get_pic_interrupt(CPUX86State *env) 410 { 411 X86CPU *cpu = env_archcpu(env); 412 int intno; 413 414 if (!kvm_irqchip_in_kernel()) { 415 intno = apic_get_interrupt(cpu->apic_state); 416 if (intno >= 0) { 417 return intno; 418 } 419 /* read the irq from the PIC */ 420 if (!apic_accept_pic_intr(cpu->apic_state)) { 421 return -1; 422 } 423 } 424 425 intno = pic_read_irq(isa_pic); 426 return intno; 427 } 428 429 static void pic_irq_request(void *opaque, int irq, int level) 430 { 431 CPUState *cs = first_cpu; 432 X86CPU *cpu = X86_CPU(cs); 433 434 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 435 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 436 CPU_FOREACH(cs) { 437 cpu = X86_CPU(cs); 438 if (apic_accept_pic_intr(cpu->apic_state)) { 439 apic_deliver_pic_intr(cpu->apic_state, level); 440 } 441 } 442 } else { 443 if (level) { 444 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 445 } else { 446 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 447 } 448 } 449 } 450 451 /* PC cmos mappings */ 452 453 #define REG_EQUIPMENT_BYTE 0x14 454 455 int cmos_get_fd_drive_type(FloppyDriveType fd0) 456 { 457 int val; 458 459 switch (fd0) { 460 case FLOPPY_DRIVE_TYPE_144: 461 /* 1.44 Mb 3"5 drive */ 462 val = 4; 463 break; 464 case FLOPPY_DRIVE_TYPE_288: 465 /* 2.88 Mb 3"5 drive */ 466 val = 5; 467 break; 468 case FLOPPY_DRIVE_TYPE_120: 469 /* 1.2 Mb 5"5 drive */ 470 val = 2; 471 break; 472 case FLOPPY_DRIVE_TYPE_NONE: 473 default: 474 val = 0; 475 break; 476 } 477 return val; 478 } 479 480 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 481 int16_t cylinders, int8_t heads, int8_t sectors) 482 { 483 rtc_set_memory(s, type_ofs, 47); 484 rtc_set_memory(s, info_ofs, cylinders); 485 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 486 rtc_set_memory(s, info_ofs + 2, heads); 487 rtc_set_memory(s, info_ofs + 3, 0xff); 488 rtc_set_memory(s, info_ofs + 4, 0xff); 489 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 490 rtc_set_memory(s, info_ofs + 6, cylinders); 491 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 492 rtc_set_memory(s, info_ofs + 8, sectors); 493 } 494 495 /* convert boot_device letter to something recognizable by the bios */ 496 static int boot_device2nibble(char boot_device) 497 { 498 switch(boot_device) { 499 case 'a': 500 case 'b': 501 return 0x01; /* floppy boot */ 502 case 'c': 503 return 0x02; /* hard drive boot */ 504 case 'd': 505 return 0x03; /* CD-ROM boot */ 506 case 'n': 507 return 0x04; /* Network boot */ 508 } 509 return 0; 510 } 511 512 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 513 { 514 #define PC_MAX_BOOT_DEVICES 3 515 int nbds, bds[3] = { 0, }; 516 int i; 517 518 nbds = strlen(boot_device); 519 if (nbds > PC_MAX_BOOT_DEVICES) { 520 error_setg(errp, "Too many boot devices for PC"); 521 return; 522 } 523 for (i = 0; i < nbds; i++) { 524 bds[i] = boot_device2nibble(boot_device[i]); 525 if (bds[i] == 0) { 526 error_setg(errp, "Invalid boot device for PC: '%c'", 527 boot_device[i]); 528 return; 529 } 530 } 531 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 532 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 533 } 534 535 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 536 { 537 set_boot_dev(opaque, boot_device, errp); 538 } 539 540 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 541 { 542 int val, nb, i; 543 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 544 FLOPPY_DRIVE_TYPE_NONE }; 545 546 /* floppy type */ 547 if (floppy) { 548 for (i = 0; i < 2; i++) { 549 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 550 } 551 } 552 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 553 cmos_get_fd_drive_type(fd_type[1]); 554 rtc_set_memory(rtc_state, 0x10, val); 555 556 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 557 nb = 0; 558 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 559 nb++; 560 } 561 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 562 nb++; 563 } 564 switch (nb) { 565 case 0: 566 break; 567 case 1: 568 val |= 0x01; /* 1 drive, ready for boot */ 569 break; 570 case 2: 571 val |= 0x41; /* 2 drives, ready for boot */ 572 break; 573 } 574 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 575 } 576 577 typedef struct pc_cmos_init_late_arg { 578 ISADevice *rtc_state; 579 BusState *idebus[2]; 580 } pc_cmos_init_late_arg; 581 582 typedef struct check_fdc_state { 583 ISADevice *floppy; 584 bool multiple; 585 } CheckFdcState; 586 587 static int check_fdc(Object *obj, void *opaque) 588 { 589 CheckFdcState *state = opaque; 590 Object *fdc; 591 uint32_t iobase; 592 Error *local_err = NULL; 593 594 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 595 if (!fdc) { 596 return 0; 597 } 598 599 iobase = object_property_get_uint(obj, "iobase", &local_err); 600 if (local_err || iobase != 0x3f0) { 601 error_free(local_err); 602 return 0; 603 } 604 605 if (state->floppy) { 606 state->multiple = true; 607 } else { 608 state->floppy = ISA_DEVICE(obj); 609 } 610 return 0; 611 } 612 613 static const char * const fdc_container_path[] = { 614 "/unattached", "/peripheral", "/peripheral-anon" 615 }; 616 617 /* 618 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 619 * and ACPI objects. 620 */ 621 ISADevice *pc_find_fdc0(void) 622 { 623 int i; 624 Object *container; 625 CheckFdcState state = { 0 }; 626 627 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 628 container = container_get(qdev_get_machine(), fdc_container_path[i]); 629 object_child_foreach(container, check_fdc, &state); 630 } 631 632 if (state.multiple) { 633 warn_report("multiple floppy disk controllers with " 634 "iobase=0x3f0 have been found"); 635 error_printf("the one being picked for CMOS setup might not reflect " 636 "your intent"); 637 } 638 639 return state.floppy; 640 } 641 642 static void pc_cmos_init_late(void *opaque) 643 { 644 pc_cmos_init_late_arg *arg = opaque; 645 ISADevice *s = arg->rtc_state; 646 int16_t cylinders; 647 int8_t heads, sectors; 648 int val; 649 int i, trans; 650 651 val = 0; 652 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 653 &cylinders, &heads, §ors) >= 0) { 654 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 655 val |= 0xf0; 656 } 657 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 658 &cylinders, &heads, §ors) >= 0) { 659 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 660 val |= 0x0f; 661 } 662 rtc_set_memory(s, 0x12, val); 663 664 val = 0; 665 for (i = 0; i < 4; i++) { 666 /* NOTE: ide_get_geometry() returns the physical 667 geometry. It is always such that: 1 <= sects <= 63, 1 668 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 669 geometry can be different if a translation is done. */ 670 if (arg->idebus[i / 2] && 671 ide_get_geometry(arg->idebus[i / 2], i % 2, 672 &cylinders, &heads, §ors) >= 0) { 673 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 674 assert((trans & ~3) == 0); 675 val |= trans << (i * 2); 676 } 677 } 678 rtc_set_memory(s, 0x39, val); 679 680 pc_cmos_init_floppy(s, pc_find_fdc0()); 681 682 qemu_unregister_reset(pc_cmos_init_late, opaque); 683 } 684 685 void pc_cmos_init(PCMachineState *pcms, 686 BusState *idebus0, BusState *idebus1, 687 ISADevice *s) 688 { 689 int val; 690 static pc_cmos_init_late_arg arg; 691 692 /* various important CMOS locations needed by PC/Bochs bios */ 693 694 /* memory size */ 695 /* base memory (first MiB) */ 696 val = MIN(pcms->below_4g_mem_size / KiB, 640); 697 rtc_set_memory(s, 0x15, val); 698 rtc_set_memory(s, 0x16, val >> 8); 699 /* extended memory (next 64MiB) */ 700 if (pcms->below_4g_mem_size > 1 * MiB) { 701 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 702 } else { 703 val = 0; 704 } 705 if (val > 65535) 706 val = 65535; 707 rtc_set_memory(s, 0x17, val); 708 rtc_set_memory(s, 0x18, val >> 8); 709 rtc_set_memory(s, 0x30, val); 710 rtc_set_memory(s, 0x31, val >> 8); 711 /* memory between 16MiB and 4GiB */ 712 if (pcms->below_4g_mem_size > 16 * MiB) { 713 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 714 } else { 715 val = 0; 716 } 717 if (val > 65535) 718 val = 65535; 719 rtc_set_memory(s, 0x34, val); 720 rtc_set_memory(s, 0x35, val >> 8); 721 /* memory above 4GiB */ 722 val = pcms->above_4g_mem_size / 65536; 723 rtc_set_memory(s, 0x5b, val); 724 rtc_set_memory(s, 0x5c, val >> 8); 725 rtc_set_memory(s, 0x5d, val >> 16); 726 727 object_property_add_link(OBJECT(pcms), "rtc_state", 728 TYPE_ISA_DEVICE, 729 (Object **)&pcms->rtc, 730 object_property_allow_set_link, 731 OBJ_PROP_LINK_STRONG, &error_abort); 732 object_property_set_link(OBJECT(pcms), OBJECT(s), 733 "rtc_state", &error_abort); 734 735 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 736 737 val = 0; 738 val |= 0x02; /* FPU is there */ 739 val |= 0x04; /* PS/2 mouse installed */ 740 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 741 742 /* hard drives and FDC */ 743 arg.rtc_state = s; 744 arg.idebus[0] = idebus0; 745 arg.idebus[1] = idebus1; 746 qemu_register_reset(pc_cmos_init_late, &arg); 747 } 748 749 #define TYPE_PORT92 "port92" 750 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 751 752 /* port 92 stuff: could be split off */ 753 typedef struct Port92State { 754 ISADevice parent_obj; 755 756 MemoryRegion io; 757 uint8_t outport; 758 qemu_irq a20_out; 759 } Port92State; 760 761 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 762 unsigned size) 763 { 764 Port92State *s = opaque; 765 int oldval = s->outport; 766 767 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 768 s->outport = val; 769 qemu_set_irq(s->a20_out, (val >> 1) & 1); 770 if ((val & 1) && !(oldval & 1)) { 771 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 772 } 773 } 774 775 static uint64_t port92_read(void *opaque, hwaddr addr, 776 unsigned size) 777 { 778 Port92State *s = opaque; 779 uint32_t ret; 780 781 ret = s->outport; 782 DPRINTF("port92: read 0x%02x\n", ret); 783 return ret; 784 } 785 786 static void port92_init(ISADevice *dev, qemu_irq a20_out) 787 { 788 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 789 } 790 791 static const VMStateDescription vmstate_port92_isa = { 792 .name = "port92", 793 .version_id = 1, 794 .minimum_version_id = 1, 795 .fields = (VMStateField[]) { 796 VMSTATE_UINT8(outport, Port92State), 797 VMSTATE_END_OF_LIST() 798 } 799 }; 800 801 static void port92_reset(DeviceState *d) 802 { 803 Port92State *s = PORT92(d); 804 805 s->outport &= ~1; 806 } 807 808 static const MemoryRegionOps port92_ops = { 809 .read = port92_read, 810 .write = port92_write, 811 .impl = { 812 .min_access_size = 1, 813 .max_access_size = 1, 814 }, 815 .endianness = DEVICE_LITTLE_ENDIAN, 816 }; 817 818 static void port92_initfn(Object *obj) 819 { 820 Port92State *s = PORT92(obj); 821 822 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 823 824 s->outport = 0; 825 826 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 827 } 828 829 static void port92_realizefn(DeviceState *dev, Error **errp) 830 { 831 ISADevice *isadev = ISA_DEVICE(dev); 832 Port92State *s = PORT92(dev); 833 834 isa_register_ioport(isadev, &s->io, 0x92); 835 } 836 837 static void port92_class_initfn(ObjectClass *klass, void *data) 838 { 839 DeviceClass *dc = DEVICE_CLASS(klass); 840 841 dc->realize = port92_realizefn; 842 dc->reset = port92_reset; 843 dc->vmsd = &vmstate_port92_isa; 844 /* 845 * Reason: unlike ordinary ISA devices, this one needs additional 846 * wiring: its A20 output line needs to be wired up by 847 * port92_init(). 848 */ 849 dc->user_creatable = false; 850 } 851 852 static const TypeInfo port92_info = { 853 .name = TYPE_PORT92, 854 .parent = TYPE_ISA_DEVICE, 855 .instance_size = sizeof(Port92State), 856 .instance_init = port92_initfn, 857 .class_init = port92_class_initfn, 858 }; 859 860 static void port92_register_types(void) 861 { 862 type_register_static(&port92_info); 863 } 864 865 type_init(port92_register_types) 866 867 static void handle_a20_line_change(void *opaque, int irq, int level) 868 { 869 X86CPU *cpu = opaque; 870 871 /* XXX: send to all CPUs ? */ 872 /* XXX: add logic to handle multiple A20 line sources */ 873 x86_cpu_set_a20(cpu, level); 874 } 875 876 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 877 { 878 int index = le32_to_cpu(e820_reserve.count); 879 struct e820_entry *entry; 880 881 if (type != E820_RAM) { 882 /* old FW_CFG_E820_TABLE entry -- reservations only */ 883 if (index >= E820_NR_ENTRIES) { 884 return -EBUSY; 885 } 886 entry = &e820_reserve.entry[index++]; 887 888 entry->address = cpu_to_le64(address); 889 entry->length = cpu_to_le64(length); 890 entry->type = cpu_to_le32(type); 891 892 e820_reserve.count = cpu_to_le32(index); 893 } 894 895 /* new "etc/e820" file -- include ram too */ 896 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 897 e820_table[e820_entries].address = cpu_to_le64(address); 898 e820_table[e820_entries].length = cpu_to_le64(length); 899 e820_table[e820_entries].type = cpu_to_le32(type); 900 e820_entries++; 901 902 return e820_entries; 903 } 904 905 int e820_get_num_entries(void) 906 { 907 return e820_entries; 908 } 909 910 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 911 { 912 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 913 *address = le64_to_cpu(e820_table[idx].address); 914 *length = le64_to_cpu(e820_table[idx].length); 915 return true; 916 } 917 return false; 918 } 919 920 /* Calculates initial APIC ID for a specific CPU index 921 * 922 * Currently we need to be able to calculate the APIC ID from the CPU index 923 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 924 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 925 * all CPUs up to max_cpus. 926 */ 927 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, 928 unsigned int cpu_index) 929 { 930 MachineState *ms = MACHINE(pcms); 931 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 932 uint32_t correct_id; 933 static bool warned; 934 935 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, 936 ms->smp.threads, cpu_index); 937 if (pcmc->compat_apic_id_mode) { 938 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 939 error_report("APIC IDs set in compatibility mode, " 940 "CPU topology won't match the configuration"); 941 warned = true; 942 } 943 return cpu_index; 944 } else { 945 return correct_id; 946 } 947 } 948 949 static void pc_build_smbios(PCMachineState *pcms) 950 { 951 uint8_t *smbios_tables, *smbios_anchor; 952 size_t smbios_tables_len, smbios_anchor_len; 953 struct smbios_phys_mem_area *mem_array; 954 unsigned i, array_count; 955 MachineState *ms = MACHINE(pcms); 956 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 957 958 /* tell smbios about cpuid version and features */ 959 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 960 961 smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); 962 if (smbios_tables) { 963 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 964 smbios_tables, smbios_tables_len); 965 } 966 967 /* build the array of physical mem area from e820 table */ 968 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 969 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 970 uint64_t addr, len; 971 972 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 973 mem_array[array_count].address = addr; 974 mem_array[array_count].length = len; 975 array_count++; 976 } 977 } 978 smbios_get_tables(ms, mem_array, array_count, 979 &smbios_tables, &smbios_tables_len, 980 &smbios_anchor, &smbios_anchor_len); 981 g_free(mem_array); 982 983 if (smbios_anchor) { 984 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 985 smbios_tables, smbios_tables_len); 986 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 987 smbios_anchor, smbios_anchor_len); 988 } 989 } 990 991 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 992 { 993 FWCfgState *fw_cfg; 994 uint64_t *numa_fw_cfg; 995 int i; 996 const CPUArchIdList *cpus; 997 MachineClass *mc = MACHINE_GET_CLASS(pcms); 998 999 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 1000 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1001 1002 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1003 * 1004 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1005 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1006 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1007 * for CPU hotplug also uses APIC ID and not "CPU index". 1008 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1009 * but the "limit to the APIC ID values SeaBIOS may see". 1010 * 1011 * So for compatibility reasons with old BIOSes we are stuck with 1012 * "etc/max-cpus" actually being apic_id_limit 1013 */ 1014 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1015 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1016 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1017 acpi_tables, acpi_tables_len); 1018 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1019 1020 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1021 &e820_reserve, sizeof(e820_reserve)); 1022 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1023 sizeof(struct e820_entry) * e820_entries); 1024 1025 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1026 /* allocate memory for the NUMA channel: one (64bit) word for the number 1027 * of nodes, one word for each VCPU->node and one word for each node to 1028 * hold the amount of memory. 1029 */ 1030 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1031 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1032 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1033 for (i = 0; i < cpus->len; i++) { 1034 unsigned int apic_id = cpus->cpus[i].arch_id; 1035 assert(apic_id < pcms->apic_id_limit); 1036 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1037 } 1038 for (i = 0; i < nb_numa_nodes; i++) { 1039 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1040 cpu_to_le64(numa_info[i].node_mem); 1041 } 1042 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1043 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1044 sizeof(*numa_fw_cfg)); 1045 1046 return fw_cfg; 1047 } 1048 1049 static long get_file_size(FILE *f) 1050 { 1051 long where, size; 1052 1053 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1054 1055 where = ftell(f); 1056 fseek(f, 0, SEEK_END); 1057 size = ftell(f); 1058 fseek(f, where, SEEK_SET); 1059 1060 return size; 1061 } 1062 1063 struct setup_data { 1064 uint64_t next; 1065 uint32_t type; 1066 uint32_t len; 1067 uint8_t data[0]; 1068 } __attribute__((packed)); 1069 1070 1071 /* 1072 * The entry point into the kernel for PVH boot is different from 1073 * the native entry point. The PVH entry is defined by the x86/HVM 1074 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 1075 * 1076 * This function is passed to load_elf() when it is called from 1077 * load_elfboot() which then additionally checks for an ELF Note of 1078 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 1079 * parse the PVH entry address from the ELF Note. 1080 * 1081 * Due to trickery in elf_opts.h, load_elf() is actually available as 1082 * load_elf32() or load_elf64() and this routine needs to be able 1083 * to deal with being called as 32 or 64 bit. 1084 * 1085 * The address of the PVH entry point is saved to the 'pvh_start_addr' 1086 * global variable. (although the entry point is 32-bit, the kernel 1087 * binary can be either 32-bit or 64-bit). 1088 */ 1089 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 1090 { 1091 size_t *elf_note_data_addr; 1092 1093 /* Check if ELF Note header passed in is valid */ 1094 if (arg1 == NULL) { 1095 return 0; 1096 } 1097 1098 if (is64) { 1099 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 1100 uint64_t nhdr_size64 = sizeof(struct elf64_note); 1101 uint64_t phdr_align = *(uint64_t *)arg2; 1102 uint64_t nhdr_namesz = nhdr64->n_namesz; 1103 1104 elf_note_data_addr = 1105 ((void *)nhdr64) + nhdr_size64 + 1106 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1107 } else { 1108 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 1109 uint32_t nhdr_size32 = sizeof(struct elf32_note); 1110 uint32_t phdr_align = *(uint32_t *)arg2; 1111 uint32_t nhdr_namesz = nhdr32->n_namesz; 1112 1113 elf_note_data_addr = 1114 ((void *)nhdr32) + nhdr_size32 + 1115 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1116 } 1117 1118 pvh_start_addr = *elf_note_data_addr; 1119 1120 return pvh_start_addr; 1121 } 1122 1123 static bool load_elfboot(const char *kernel_filename, 1124 int kernel_file_size, 1125 uint8_t *header, 1126 size_t pvh_xen_start_addr, 1127 FWCfgState *fw_cfg) 1128 { 1129 uint32_t flags = 0; 1130 uint32_t mh_load_addr = 0; 1131 uint32_t elf_kernel_size = 0; 1132 uint64_t elf_entry; 1133 uint64_t elf_low, elf_high; 1134 int kernel_size; 1135 1136 if (ldl_p(header) != 0x464c457f) { 1137 return false; /* no elfboot */ 1138 } 1139 1140 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 1141 flags = elf_is64 ? 1142 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 1143 1144 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 1145 error_report("elfboot unsupported flags = %x", flags); 1146 exit(1); 1147 } 1148 1149 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 1150 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1151 NULL, &elf_note_type, &elf_entry, 1152 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1153 0, 0); 1154 1155 if (kernel_size < 0) { 1156 error_report("Error while loading elf kernel"); 1157 exit(1); 1158 } 1159 mh_load_addr = elf_low; 1160 elf_kernel_size = elf_high - elf_low; 1161 1162 if (pvh_start_addr == 0) { 1163 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1164 exit(1); 1165 } 1166 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1167 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1168 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1169 1170 return true; 1171 } 1172 1173 static void load_linux(PCMachineState *pcms, 1174 FWCfgState *fw_cfg) 1175 { 1176 uint16_t protocol; 1177 int setup_size, kernel_size, cmdline_size; 1178 int dtb_size, setup_data_offset; 1179 uint32_t initrd_max; 1180 uint8_t header[8192], *setup, *kernel; 1181 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1182 FILE *f; 1183 char *vmode; 1184 MachineState *machine = MACHINE(pcms); 1185 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1186 struct setup_data *setup_data; 1187 const char *kernel_filename = machine->kernel_filename; 1188 const char *initrd_filename = machine->initrd_filename; 1189 const char *dtb_filename = machine->dtb; 1190 const char *kernel_cmdline = machine->kernel_cmdline; 1191 1192 /* Align to 16 bytes as a paranoia measure */ 1193 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1194 1195 /* load the kernel header */ 1196 f = fopen(kernel_filename, "rb"); 1197 if (!f || !(kernel_size = get_file_size(f)) || 1198 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1199 MIN(ARRAY_SIZE(header), kernel_size)) { 1200 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1201 kernel_filename, strerror(errno)); 1202 exit(1); 1203 } 1204 1205 /* kernel protocol version */ 1206 #if 0 1207 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1208 #endif 1209 if (ldl_p(header+0x202) == 0x53726448) { 1210 protocol = lduw_p(header+0x206); 1211 } else { 1212 /* 1213 * This could be a multiboot kernel. If it is, let's stop treating it 1214 * like a Linux kernel. 1215 * Note: some multiboot images could be in the ELF format (the same of 1216 * PVH), so we try multiboot first since we check the multiboot magic 1217 * header before to load it. 1218 */ 1219 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1220 kernel_cmdline, kernel_size, header)) { 1221 return; 1222 } 1223 /* 1224 * Check if the file is an uncompressed kernel file (ELF) and load it, 1225 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1226 * If load_elfboot() is successful, populate the fw_cfg info. 1227 */ 1228 if (pcmc->pvh_enabled && 1229 load_elfboot(kernel_filename, kernel_size, 1230 header, pvh_start_addr, fw_cfg)) { 1231 fclose(f); 1232 1233 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1234 strlen(kernel_cmdline) + 1); 1235 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1236 1237 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1238 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1239 header, sizeof(header)); 1240 1241 /* load initrd */ 1242 if (initrd_filename) { 1243 gsize initrd_size; 1244 gchar *initrd_data; 1245 GError *gerr = NULL; 1246 1247 if (!g_file_get_contents(initrd_filename, &initrd_data, 1248 &initrd_size, &gerr)) { 1249 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1250 initrd_filename, gerr->message); 1251 exit(1); 1252 } 1253 1254 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1255 if (initrd_size >= initrd_max) { 1256 fprintf(stderr, "qemu: initrd is too large, cannot support." 1257 "(max: %"PRIu32", need %"PRId64")\n", 1258 initrd_max, (uint64_t)initrd_size); 1259 exit(1); 1260 } 1261 1262 initrd_addr = (initrd_max - initrd_size) & ~4095; 1263 1264 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1265 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1266 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1267 initrd_size); 1268 } 1269 1270 option_rom[nb_option_roms].bootindex = 0; 1271 option_rom[nb_option_roms].name = "pvh.bin"; 1272 nb_option_roms++; 1273 1274 return; 1275 } 1276 protocol = 0; 1277 } 1278 1279 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1280 /* Low kernel */ 1281 real_addr = 0x90000; 1282 cmdline_addr = 0x9a000 - cmdline_size; 1283 prot_addr = 0x10000; 1284 } else if (protocol < 0x202) { 1285 /* High but ancient kernel */ 1286 real_addr = 0x90000; 1287 cmdline_addr = 0x9a000 - cmdline_size; 1288 prot_addr = 0x100000; 1289 } else { 1290 /* High and recent kernel */ 1291 real_addr = 0x10000; 1292 cmdline_addr = 0x20000; 1293 prot_addr = 0x100000; 1294 } 1295 1296 #if 0 1297 fprintf(stderr, 1298 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1299 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1300 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1301 real_addr, 1302 cmdline_addr, 1303 prot_addr); 1304 #endif 1305 1306 /* highest address for loading the initrd */ 1307 if (protocol >= 0x20c && 1308 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1309 /* 1310 * Linux has supported initrd up to 4 GB for a very long time (2007, 1311 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1312 * though it only sets initrd_max to 2 GB to "work around bootloader 1313 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1314 * has supported this. 1315 * 1316 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1317 * be loaded into any address. 1318 * 1319 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1320 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1321 * field). 1322 * 1323 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1324 */ 1325 initrd_max = UINT32_MAX; 1326 } else if (protocol >= 0x203) { 1327 initrd_max = ldl_p(header+0x22c); 1328 } else { 1329 initrd_max = 0x37ffffff; 1330 } 1331 1332 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1333 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1334 } 1335 1336 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1337 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1338 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1339 1340 if (protocol >= 0x202) { 1341 stl_p(header+0x228, cmdline_addr); 1342 } else { 1343 stw_p(header+0x20, 0xA33F); 1344 stw_p(header+0x22, cmdline_addr-real_addr); 1345 } 1346 1347 /* handle vga= parameter */ 1348 vmode = strstr(kernel_cmdline, "vga="); 1349 if (vmode) { 1350 unsigned int video_mode; 1351 /* skip "vga=" */ 1352 vmode += 4; 1353 if (!strncmp(vmode, "normal", 6)) { 1354 video_mode = 0xffff; 1355 } else if (!strncmp(vmode, "ext", 3)) { 1356 video_mode = 0xfffe; 1357 } else if (!strncmp(vmode, "ask", 3)) { 1358 video_mode = 0xfffd; 1359 } else { 1360 video_mode = strtol(vmode, NULL, 0); 1361 } 1362 stw_p(header+0x1fa, video_mode); 1363 } 1364 1365 /* loader type */ 1366 /* High nybble = B reserved for QEMU; low nybble is revision number. 1367 If this code is substantially changed, you may want to consider 1368 incrementing the revision. */ 1369 if (protocol >= 0x200) { 1370 header[0x210] = 0xB0; 1371 } 1372 /* heap */ 1373 if (protocol >= 0x201) { 1374 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1375 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1376 } 1377 1378 /* load initrd */ 1379 if (initrd_filename) { 1380 gsize initrd_size; 1381 gchar *initrd_data; 1382 GError *gerr = NULL; 1383 1384 if (protocol < 0x200) { 1385 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1386 exit(1); 1387 } 1388 1389 if (!g_file_get_contents(initrd_filename, &initrd_data, 1390 &initrd_size, &gerr)) { 1391 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1392 initrd_filename, gerr->message); 1393 exit(1); 1394 } 1395 if (initrd_size >= initrd_max) { 1396 fprintf(stderr, "qemu: initrd is too large, cannot support." 1397 "(max: %"PRIu32", need %"PRId64")\n", 1398 initrd_max, (uint64_t)initrd_size); 1399 exit(1); 1400 } 1401 1402 initrd_addr = (initrd_max-initrd_size) & ~4095; 1403 1404 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1405 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1406 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1407 1408 stl_p(header+0x218, initrd_addr); 1409 stl_p(header+0x21c, initrd_size); 1410 } 1411 1412 /* load kernel and setup */ 1413 setup_size = header[0x1f1]; 1414 if (setup_size == 0) { 1415 setup_size = 4; 1416 } 1417 setup_size = (setup_size+1)*512; 1418 if (setup_size > kernel_size) { 1419 fprintf(stderr, "qemu: invalid kernel header\n"); 1420 exit(1); 1421 } 1422 kernel_size -= setup_size; 1423 1424 setup = g_malloc(setup_size); 1425 kernel = g_malloc(kernel_size); 1426 fseek(f, 0, SEEK_SET); 1427 if (fread(setup, 1, setup_size, f) != setup_size) { 1428 fprintf(stderr, "fread() failed\n"); 1429 exit(1); 1430 } 1431 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1432 fprintf(stderr, "fread() failed\n"); 1433 exit(1); 1434 } 1435 fclose(f); 1436 1437 /* append dtb to kernel */ 1438 if (dtb_filename) { 1439 if (protocol < 0x209) { 1440 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1441 exit(1); 1442 } 1443 1444 dtb_size = get_image_size(dtb_filename); 1445 if (dtb_size <= 0) { 1446 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1447 dtb_filename, strerror(errno)); 1448 exit(1); 1449 } 1450 1451 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1452 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1453 kernel = g_realloc(kernel, kernel_size); 1454 1455 stq_p(header+0x250, prot_addr + setup_data_offset); 1456 1457 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1458 setup_data->next = 0; 1459 setup_data->type = cpu_to_le32(SETUP_DTB); 1460 setup_data->len = cpu_to_le32(dtb_size); 1461 1462 load_image_size(dtb_filename, setup_data->data, dtb_size); 1463 } 1464 1465 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1466 1467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1468 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1469 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1470 1471 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1472 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1473 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1474 1475 option_rom[nb_option_roms].bootindex = 0; 1476 option_rom[nb_option_roms].name = "linuxboot.bin"; 1477 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1478 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1479 } 1480 nb_option_roms++; 1481 } 1482 1483 #define NE2000_NB_MAX 6 1484 1485 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1486 0x280, 0x380 }; 1487 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1488 1489 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1490 { 1491 static int nb_ne2k = 0; 1492 1493 if (nb_ne2k == NE2000_NB_MAX) 1494 return; 1495 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1496 ne2000_irq[nb_ne2k], nd); 1497 nb_ne2k++; 1498 } 1499 1500 DeviceState *cpu_get_current_apic(void) 1501 { 1502 if (current_cpu) { 1503 X86CPU *cpu = X86_CPU(current_cpu); 1504 return cpu->apic_state; 1505 } else { 1506 return NULL; 1507 } 1508 } 1509 1510 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1511 { 1512 X86CPU *cpu = opaque; 1513 1514 if (level) { 1515 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1516 } 1517 } 1518 1519 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) 1520 { 1521 Object *cpu = NULL; 1522 Error *local_err = NULL; 1523 CPUX86State *env = NULL; 1524 1525 cpu = object_new(MACHINE(pcms)->cpu_type); 1526 1527 env = &X86_CPU(cpu)->env; 1528 env->nr_dies = pcms->smp_dies; 1529 1530 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1531 object_property_set_bool(cpu, true, "realized", &local_err); 1532 1533 object_unref(cpu); 1534 error_propagate(errp, local_err); 1535 } 1536 1537 /* 1538 * This function is very similar to smp_parse() 1539 * in hw/core/machine.c but includes CPU die support. 1540 */ 1541 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 1542 { 1543 PCMachineState *pcms = PC_MACHINE(ms); 1544 1545 if (opts) { 1546 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 1547 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 1548 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 1549 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 1550 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 1551 1552 /* compute missing values, prefer sockets over cores over threads */ 1553 if (cpus == 0 || sockets == 0) { 1554 cores = cores > 0 ? cores : 1; 1555 threads = threads > 0 ? threads : 1; 1556 if (cpus == 0) { 1557 sockets = sockets > 0 ? sockets : 1; 1558 cpus = cores * threads * dies * sockets; 1559 } else { 1560 ms->smp.max_cpus = 1561 qemu_opt_get_number(opts, "maxcpus", cpus); 1562 sockets = ms->smp.max_cpus / (cores * threads * dies); 1563 } 1564 } else if (cores == 0) { 1565 threads = threads > 0 ? threads : 1; 1566 cores = cpus / (sockets * dies * threads); 1567 cores = cores > 0 ? cores : 1; 1568 } else if (threads == 0) { 1569 threads = cpus / (cores * dies * sockets); 1570 threads = threads > 0 ? threads : 1; 1571 } else if (sockets * dies * cores * threads < cpus) { 1572 error_report("cpu topology: " 1573 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 1574 "smp_cpus (%u)", 1575 sockets, dies, cores, threads, cpus); 1576 exit(1); 1577 } 1578 1579 ms->smp.max_cpus = 1580 qemu_opt_get_number(opts, "maxcpus", cpus); 1581 1582 if (ms->smp.max_cpus < cpus) { 1583 error_report("maxcpus must be equal to or greater than smp"); 1584 exit(1); 1585 } 1586 1587 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 1588 error_report("cpu topology: " 1589 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 1590 "maxcpus (%u)", 1591 sockets, dies, cores, threads, 1592 ms->smp.max_cpus); 1593 exit(1); 1594 } 1595 1596 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 1597 warn_report("Invalid CPU topology deprecated: " 1598 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 1599 "!= maxcpus (%u)", 1600 sockets, dies, cores, threads, 1601 ms->smp.max_cpus); 1602 } 1603 1604 ms->smp.cpus = cpus; 1605 ms->smp.cores = cores; 1606 ms->smp.threads = threads; 1607 pcms->smp_dies = dies; 1608 } 1609 1610 if (ms->smp.cpus > 1) { 1611 Error *blocker = NULL; 1612 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 1613 replay_add_blocker(blocker); 1614 } 1615 } 1616 1617 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 1618 { 1619 PCMachineState *pcms = PC_MACHINE(ms); 1620 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); 1621 Error *local_err = NULL; 1622 1623 if (id < 0) { 1624 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1625 return; 1626 } 1627 1628 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1629 error_setg(errp, "Unable to add CPU: %" PRIi64 1630 ", resulting APIC ID (%" PRIi64 ") is too large", 1631 id, apic_id); 1632 return; 1633 } 1634 1635 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err); 1636 if (local_err) { 1637 error_propagate(errp, local_err); 1638 return; 1639 } 1640 } 1641 1642 void pc_cpus_init(PCMachineState *pcms) 1643 { 1644 int i; 1645 const CPUArchIdList *possible_cpus; 1646 MachineState *ms = MACHINE(pcms); 1647 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1648 1649 /* Calculates the limit to CPU APIC ID values 1650 * 1651 * Limit for the APIC ID value, so that all 1652 * CPU APIC IDs are < pcms->apic_id_limit. 1653 * 1654 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1655 */ 1656 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, 1657 ms->smp.max_cpus - 1) + 1; 1658 possible_cpus = mc->possible_cpu_arch_ids(ms); 1659 for (i = 0; i < ms->smp.cpus; i++) { 1660 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal); 1661 } 1662 } 1663 1664 static void pc_build_feature_control_file(PCMachineState *pcms) 1665 { 1666 MachineState *ms = MACHINE(pcms); 1667 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1668 CPUX86State *env = &cpu->env; 1669 uint32_t unused, ecx, edx; 1670 uint64_t feature_control_bits = 0; 1671 uint64_t *val; 1672 1673 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1674 if (ecx & CPUID_EXT_VMX) { 1675 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1676 } 1677 1678 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1679 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1680 (env->mcg_cap & MCG_LMCE_P)) { 1681 feature_control_bits |= FEATURE_CONTROL_LMCE; 1682 } 1683 1684 if (!feature_control_bits) { 1685 return; 1686 } 1687 1688 val = g_malloc(sizeof(*val)); 1689 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1690 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1691 } 1692 1693 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1694 { 1695 if (cpus_count > 0xff) { 1696 /* If the number of CPUs can't be represented in 8 bits, the 1697 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1698 * to make old BIOSes fail more predictably. 1699 */ 1700 rtc_set_memory(rtc, 0x5f, 0); 1701 } else { 1702 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1703 } 1704 } 1705 1706 static 1707 void pc_machine_done(Notifier *notifier, void *data) 1708 { 1709 PCMachineState *pcms = container_of(notifier, 1710 PCMachineState, machine_done); 1711 PCIBus *bus = pcms->bus; 1712 1713 /* set the number of CPUs */ 1714 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1715 1716 if (bus) { 1717 int extra_hosts = 0; 1718 1719 QLIST_FOREACH(bus, &bus->child, sibling) { 1720 /* look for expander root buses */ 1721 if (pci_bus_is_root(bus)) { 1722 extra_hosts++; 1723 } 1724 } 1725 if (extra_hosts && pcms->fw_cfg) { 1726 uint64_t *val = g_malloc(sizeof(*val)); 1727 *val = cpu_to_le64(extra_hosts); 1728 fw_cfg_add_file(pcms->fw_cfg, 1729 "etc/extra-pci-roots", val, sizeof(*val)); 1730 } 1731 } 1732 1733 acpi_setup(); 1734 if (pcms->fw_cfg) { 1735 pc_build_smbios(pcms); 1736 pc_build_feature_control_file(pcms); 1737 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1738 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1739 } 1740 1741 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1742 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1743 1744 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1745 iommu->intr_eim != ON_OFF_AUTO_ON) { 1746 error_report("current -smp configuration requires " 1747 "Extended Interrupt Mode enabled. " 1748 "You can add an IOMMU using: " 1749 "-device intel-iommu,intremap=on,eim=on"); 1750 exit(EXIT_FAILURE); 1751 } 1752 } 1753 } 1754 1755 void pc_guest_info_init(PCMachineState *pcms) 1756 { 1757 int i; 1758 1759 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1760 pcms->numa_nodes = nb_numa_nodes; 1761 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1762 sizeof *pcms->node_mem); 1763 for (i = 0; i < nb_numa_nodes; i++) { 1764 pcms->node_mem[i] = numa_info[i].node_mem; 1765 } 1766 1767 pcms->machine_done.notify = pc_machine_done; 1768 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1769 } 1770 1771 /* setup pci memory address space mapping into system address space */ 1772 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1773 MemoryRegion *pci_address_space) 1774 { 1775 /* Set to lower priority than RAM */ 1776 memory_region_add_subregion_overlap(system_memory, 0x0, 1777 pci_address_space, -1); 1778 } 1779 1780 void xen_load_linux(PCMachineState *pcms) 1781 { 1782 int i; 1783 FWCfgState *fw_cfg; 1784 1785 assert(MACHINE(pcms)->kernel_filename != NULL); 1786 1787 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1788 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1789 rom_set_fw(fw_cfg); 1790 1791 load_linux(pcms, fw_cfg); 1792 for (i = 0; i < nb_option_roms; i++) { 1793 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1794 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1795 !strcmp(option_rom[i].name, "pvh.bin") || 1796 !strcmp(option_rom[i].name, "multiboot.bin")); 1797 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1798 } 1799 pcms->fw_cfg = fw_cfg; 1800 } 1801 1802 void pc_memory_init(PCMachineState *pcms, 1803 MemoryRegion *system_memory, 1804 MemoryRegion *rom_memory, 1805 MemoryRegion **ram_memory) 1806 { 1807 int linux_boot, i; 1808 MemoryRegion *ram, *option_rom_mr; 1809 MemoryRegion *ram_below_4g, *ram_above_4g; 1810 FWCfgState *fw_cfg; 1811 MachineState *machine = MACHINE(pcms); 1812 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1813 1814 assert(machine->ram_size == pcms->below_4g_mem_size + 1815 pcms->above_4g_mem_size); 1816 1817 linux_boot = (machine->kernel_filename != NULL); 1818 1819 /* Allocate RAM. We allocate it as a single memory region and use 1820 * aliases to address portions of it, mostly for backwards compatibility 1821 * with older qemus that used qemu_ram_alloc(). 1822 */ 1823 ram = g_malloc(sizeof(*ram)); 1824 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1825 machine->ram_size); 1826 *ram_memory = ram; 1827 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1828 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1829 0, pcms->below_4g_mem_size); 1830 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1831 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1832 if (pcms->above_4g_mem_size > 0) { 1833 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1834 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1835 pcms->below_4g_mem_size, 1836 pcms->above_4g_mem_size); 1837 memory_region_add_subregion(system_memory, 0x100000000ULL, 1838 ram_above_4g); 1839 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1840 } 1841 1842 if (!pcmc->has_reserved_memory && 1843 (machine->ram_slots || 1844 (machine->maxram_size > machine->ram_size))) { 1845 MachineClass *mc = MACHINE_GET_CLASS(machine); 1846 1847 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1848 mc->name); 1849 exit(EXIT_FAILURE); 1850 } 1851 1852 /* always allocate the device memory information */ 1853 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1854 1855 /* initialize device memory address space */ 1856 if (pcmc->has_reserved_memory && 1857 (machine->ram_size < machine->maxram_size)) { 1858 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1859 1860 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1861 error_report("unsupported amount of memory slots: %"PRIu64, 1862 machine->ram_slots); 1863 exit(EXIT_FAILURE); 1864 } 1865 1866 if (QEMU_ALIGN_UP(machine->maxram_size, 1867 TARGET_PAGE_SIZE) != machine->maxram_size) { 1868 error_report("maximum memory size must by aligned to multiple of " 1869 "%d bytes", TARGET_PAGE_SIZE); 1870 exit(EXIT_FAILURE); 1871 } 1872 1873 machine->device_memory->base = 1874 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1875 1876 if (pcmc->enforce_aligned_dimm) { 1877 /* size device region assuming 1G page max alignment per slot */ 1878 device_mem_size += (1 * GiB) * machine->ram_slots; 1879 } 1880 1881 if ((machine->device_memory->base + device_mem_size) < 1882 device_mem_size) { 1883 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1884 machine->maxram_size); 1885 exit(EXIT_FAILURE); 1886 } 1887 1888 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1889 "device-memory", device_mem_size); 1890 memory_region_add_subregion(system_memory, machine->device_memory->base, 1891 &machine->device_memory->mr); 1892 } 1893 1894 /* Initialize PC system firmware */ 1895 pc_system_firmware_init(pcms, rom_memory); 1896 1897 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1898 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1899 &error_fatal); 1900 if (pcmc->pci_enabled) { 1901 memory_region_set_readonly(option_rom_mr, true); 1902 } 1903 memory_region_add_subregion_overlap(rom_memory, 1904 PC_ROM_MIN_VGA, 1905 option_rom_mr, 1906 1); 1907 1908 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1909 1910 rom_set_fw(fw_cfg); 1911 1912 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1913 uint64_t *val = g_malloc(sizeof(*val)); 1914 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1915 uint64_t res_mem_end = machine->device_memory->base; 1916 1917 if (!pcmc->broken_reserved_end) { 1918 res_mem_end += memory_region_size(&machine->device_memory->mr); 1919 } 1920 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1921 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1922 } 1923 1924 if (linux_boot) { 1925 load_linux(pcms, fw_cfg); 1926 } 1927 1928 for (i = 0; i < nb_option_roms; i++) { 1929 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1930 } 1931 pcms->fw_cfg = fw_cfg; 1932 1933 /* Init default IOAPIC address space */ 1934 pcms->ioapic_as = &address_space_memory; 1935 } 1936 1937 /* 1938 * The 64bit pci hole starts after "above 4G RAM" and 1939 * potentially the space reserved for memory hotplug. 1940 */ 1941 uint64_t pc_pci_hole64_start(void) 1942 { 1943 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1944 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1945 MachineState *ms = MACHINE(pcms); 1946 uint64_t hole64_start = 0; 1947 1948 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1949 hole64_start = ms->device_memory->base; 1950 if (!pcmc->broken_reserved_end) { 1951 hole64_start += memory_region_size(&ms->device_memory->mr); 1952 } 1953 } else { 1954 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1955 } 1956 1957 return ROUND_UP(hole64_start, 1 * GiB); 1958 } 1959 1960 qemu_irq pc_allocate_cpu_irq(void) 1961 { 1962 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1963 } 1964 1965 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1966 { 1967 DeviceState *dev = NULL; 1968 1969 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1970 if (pci_bus) { 1971 PCIDevice *pcidev = pci_vga_init(pci_bus); 1972 dev = pcidev ? &pcidev->qdev : NULL; 1973 } else if (isa_bus) { 1974 ISADevice *isadev = isa_vga_init(isa_bus); 1975 dev = isadev ? DEVICE(isadev) : NULL; 1976 } 1977 rom_reset_order_override(); 1978 return dev; 1979 } 1980 1981 static const MemoryRegionOps ioport80_io_ops = { 1982 .write = ioport80_write, 1983 .read = ioport80_read, 1984 .endianness = DEVICE_NATIVE_ENDIAN, 1985 .impl = { 1986 .min_access_size = 1, 1987 .max_access_size = 1, 1988 }, 1989 }; 1990 1991 static const MemoryRegionOps ioportF0_io_ops = { 1992 .write = ioportF0_write, 1993 .read = ioportF0_read, 1994 .endianness = DEVICE_NATIVE_ENDIAN, 1995 .impl = { 1996 .min_access_size = 1, 1997 .max_access_size = 1, 1998 }, 1999 }; 2000 2001 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 2002 { 2003 int i; 2004 DriveInfo *fd[MAX_FD]; 2005 qemu_irq *a20_line; 2006 ISADevice *i8042, *port92, *vmmouse; 2007 2008 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 2009 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 2010 2011 for (i = 0; i < MAX_FD; i++) { 2012 fd[i] = drive_get(IF_FLOPPY, 0, i); 2013 create_fdctrl |= !!fd[i]; 2014 } 2015 if (create_fdctrl) { 2016 fdctrl_init_isa(isa_bus, fd); 2017 } 2018 2019 i8042 = isa_create_simple(isa_bus, "i8042"); 2020 if (!no_vmport) { 2021 vmport_init(isa_bus); 2022 vmmouse = isa_try_create(isa_bus, "vmmouse"); 2023 } else { 2024 vmmouse = NULL; 2025 } 2026 if (vmmouse) { 2027 DeviceState *dev = DEVICE(vmmouse); 2028 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 2029 qdev_init_nofail(dev); 2030 } 2031 port92 = isa_create_simple(isa_bus, "port92"); 2032 2033 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 2034 i8042_setup_a20_line(i8042, a20_line[0]); 2035 port92_init(port92, a20_line[1]); 2036 g_free(a20_line); 2037 } 2038 2039 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 2040 ISADevice **rtc_state, 2041 bool create_fdctrl, 2042 bool no_vmport, 2043 bool has_pit, 2044 uint32_t hpet_irqs) 2045 { 2046 int i; 2047 DeviceState *hpet = NULL; 2048 int pit_isa_irq = 0; 2049 qemu_irq pit_alt_irq = NULL; 2050 qemu_irq rtc_irq = NULL; 2051 ISADevice *pit = NULL; 2052 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 2053 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 2054 2055 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 2056 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 2057 2058 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 2059 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 2060 2061 /* 2062 * Check if an HPET shall be created. 2063 * 2064 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 2065 * when the HPET wants to take over. Thus we have to disable the latter. 2066 */ 2067 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 2068 /* In order to set property, here not using sysbus_try_create_simple */ 2069 hpet = qdev_try_create(NULL, TYPE_HPET); 2070 if (hpet) { 2071 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 2072 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 2073 * IRQ8 and IRQ2. 2074 */ 2075 uint8_t compat = object_property_get_uint(OBJECT(hpet), 2076 HPET_INTCAP, NULL); 2077 if (!compat) { 2078 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 2079 } 2080 qdev_init_nofail(hpet); 2081 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 2082 2083 for (i = 0; i < GSI_NUM_PINS; i++) { 2084 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 2085 } 2086 pit_isa_irq = -1; 2087 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 2088 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 2089 } 2090 } 2091 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 2092 2093 qemu_register_boot_set(pc_boot_set, *rtc_state); 2094 2095 if (!xen_enabled() && has_pit) { 2096 if (kvm_pit_in_kernel()) { 2097 pit = kvm_pit_init(isa_bus, 0x40); 2098 } else { 2099 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 2100 } 2101 if (hpet) { 2102 /* connect PIT to output control line of the HPET */ 2103 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 2104 } 2105 pcspk_init(isa_bus, pit); 2106 } 2107 2108 i8257_dma_init(isa_bus, 0); 2109 2110 /* Super I/O */ 2111 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 2112 } 2113 2114 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 2115 { 2116 int i; 2117 2118 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 2119 for (i = 0; i < nb_nics; i++) { 2120 NICInfo *nd = &nd_table[i]; 2121 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 2122 2123 if (g_str_equal(model, "ne2k_isa")) { 2124 pc_init_ne2k_isa(isa_bus, nd); 2125 } else { 2126 pci_nic_init_nofail(nd, pci_bus, model, NULL); 2127 } 2128 } 2129 rom_reset_order_override(); 2130 } 2131 2132 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 2133 { 2134 DeviceState *dev; 2135 SysBusDevice *d; 2136 unsigned int i; 2137 2138 if (kvm_ioapic_in_kernel()) { 2139 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 2140 } else { 2141 dev = qdev_create(NULL, TYPE_IOAPIC); 2142 } 2143 if (parent_name) { 2144 object_property_add_child(object_resolve_path(parent_name, NULL), 2145 "ioapic", OBJECT(dev), NULL); 2146 } 2147 qdev_init_nofail(dev); 2148 d = SYS_BUS_DEVICE(dev); 2149 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2150 2151 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2152 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2153 } 2154 } 2155 2156 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2157 Error **errp) 2158 { 2159 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2160 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2161 const MachineState *ms = MACHINE(hotplug_dev); 2162 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2163 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2164 Error *local_err = NULL; 2165 2166 /* 2167 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2168 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2169 * addition to cover this case. 2170 */ 2171 if (!pcms->acpi_dev || !acpi_enabled) { 2172 error_setg(errp, 2173 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2174 return; 2175 } 2176 2177 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2178 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2179 return; 2180 } 2181 2182 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 2183 if (local_err) { 2184 error_propagate(errp, local_err); 2185 return; 2186 } 2187 2188 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2189 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2190 } 2191 2192 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2193 DeviceState *dev, Error **errp) 2194 { 2195 Error *local_err = NULL; 2196 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2197 MachineState *ms = MACHINE(hotplug_dev); 2198 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2199 2200 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2201 if (local_err) { 2202 goto out; 2203 } 2204 2205 if (is_nvdimm) { 2206 nvdimm_plug(ms->nvdimms_state); 2207 } 2208 2209 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2210 out: 2211 error_propagate(errp, local_err); 2212 } 2213 2214 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2215 DeviceState *dev, Error **errp) 2216 { 2217 Error *local_err = NULL; 2218 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2219 2220 /* 2221 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2222 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2223 * addition to cover this case. 2224 */ 2225 if (!pcms->acpi_dev || !acpi_enabled) { 2226 error_setg(&local_err, 2227 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2228 goto out; 2229 } 2230 2231 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2232 error_setg(&local_err, 2233 "nvdimm device hot unplug is not supported yet."); 2234 goto out; 2235 } 2236 2237 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2238 &local_err); 2239 out: 2240 error_propagate(errp, local_err); 2241 } 2242 2243 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2244 DeviceState *dev, Error **errp) 2245 { 2246 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2247 Error *local_err = NULL; 2248 2249 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2250 if (local_err) { 2251 goto out; 2252 } 2253 2254 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2255 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2256 out: 2257 error_propagate(errp, local_err); 2258 } 2259 2260 static int pc_apic_cmp(const void *a, const void *b) 2261 { 2262 CPUArchId *apic_a = (CPUArchId *)a; 2263 CPUArchId *apic_b = (CPUArchId *)b; 2264 2265 return apic_a->arch_id - apic_b->arch_id; 2266 } 2267 2268 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2269 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2270 * entry corresponding to CPU's apic_id returns NULL. 2271 */ 2272 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2273 { 2274 CPUArchId apic_id, *found_cpu; 2275 2276 apic_id.arch_id = id; 2277 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2278 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2279 pc_apic_cmp); 2280 if (found_cpu && idx) { 2281 *idx = found_cpu - ms->possible_cpus->cpus; 2282 } 2283 return found_cpu; 2284 } 2285 2286 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2287 DeviceState *dev, Error **errp) 2288 { 2289 CPUArchId *found_cpu; 2290 Error *local_err = NULL; 2291 X86CPU *cpu = X86_CPU(dev); 2292 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2293 2294 if (pcms->acpi_dev) { 2295 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2296 if (local_err) { 2297 goto out; 2298 } 2299 } 2300 2301 /* increment the number of CPUs */ 2302 pcms->boot_cpus++; 2303 if (pcms->rtc) { 2304 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2305 } 2306 if (pcms->fw_cfg) { 2307 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2308 } 2309 2310 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2311 found_cpu->cpu = OBJECT(dev); 2312 out: 2313 error_propagate(errp, local_err); 2314 } 2315 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2316 DeviceState *dev, Error **errp) 2317 { 2318 int idx = -1; 2319 Error *local_err = NULL; 2320 X86CPU *cpu = X86_CPU(dev); 2321 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2322 2323 if (!pcms->acpi_dev) { 2324 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2325 goto out; 2326 } 2327 2328 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2329 assert(idx != -1); 2330 if (idx == 0) { 2331 error_setg(&local_err, "Boot CPU is unpluggable"); 2332 goto out; 2333 } 2334 2335 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2336 &local_err); 2337 if (local_err) { 2338 goto out; 2339 } 2340 2341 out: 2342 error_propagate(errp, local_err); 2343 2344 } 2345 2346 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2347 DeviceState *dev, Error **errp) 2348 { 2349 CPUArchId *found_cpu; 2350 Error *local_err = NULL; 2351 X86CPU *cpu = X86_CPU(dev); 2352 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2353 2354 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2355 if (local_err) { 2356 goto out; 2357 } 2358 2359 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2360 found_cpu->cpu = NULL; 2361 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2362 2363 /* decrement the number of CPUs */ 2364 pcms->boot_cpus--; 2365 /* Update the number of CPUs in CMOS */ 2366 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2367 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2368 out: 2369 error_propagate(errp, local_err); 2370 } 2371 2372 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2373 DeviceState *dev, Error **errp) 2374 { 2375 int idx; 2376 CPUState *cs; 2377 CPUArchId *cpu_slot; 2378 X86CPUTopoInfo topo; 2379 X86CPU *cpu = X86_CPU(dev); 2380 CPUX86State *env = &cpu->env; 2381 MachineState *ms = MACHINE(hotplug_dev); 2382 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2383 unsigned int smp_cores = ms->smp.cores; 2384 unsigned int smp_threads = ms->smp.threads; 2385 2386 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2387 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2388 ms->cpu_type); 2389 return; 2390 } 2391 2392 env->nr_dies = pcms->smp_dies; 2393 2394 /* 2395 * If APIC ID is not set, 2396 * set it based on socket/die/core/thread properties. 2397 */ 2398 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2399 int max_socket = (ms->smp.max_cpus - 1) / 2400 smp_threads / smp_cores / pcms->smp_dies; 2401 2402 if (cpu->socket_id < 0) { 2403 error_setg(errp, "CPU socket-id is not set"); 2404 return; 2405 } else if (cpu->socket_id > max_socket) { 2406 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2407 cpu->socket_id, max_socket); 2408 return; 2409 } else if (cpu->die_id > pcms->smp_dies - 1) { 2410 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 2411 cpu->die_id, max_socket); 2412 return; 2413 } 2414 if (cpu->core_id < 0) { 2415 error_setg(errp, "CPU core-id is not set"); 2416 return; 2417 } else if (cpu->core_id > (smp_cores - 1)) { 2418 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2419 cpu->core_id, smp_cores - 1); 2420 return; 2421 } 2422 if (cpu->thread_id < 0) { 2423 error_setg(errp, "CPU thread-id is not set"); 2424 return; 2425 } else if (cpu->thread_id > (smp_threads - 1)) { 2426 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2427 cpu->thread_id, smp_threads - 1); 2428 return; 2429 } 2430 2431 topo.pkg_id = cpu->socket_id; 2432 topo.die_id = cpu->die_id; 2433 topo.core_id = cpu->core_id; 2434 topo.smt_id = cpu->thread_id; 2435 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, 2436 smp_threads, &topo); 2437 } 2438 2439 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2440 if (!cpu_slot) { 2441 MachineState *ms = MACHINE(pcms); 2442 2443 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2444 smp_cores, smp_threads, &topo); 2445 error_setg(errp, 2446 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 2447 " APIC ID %" PRIu32 ", valid index range 0:%d", 2448 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 2449 cpu->apic_id, ms->possible_cpus->len - 1); 2450 return; 2451 } 2452 2453 if (cpu_slot->cpu) { 2454 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2455 idx, cpu->apic_id); 2456 return; 2457 } 2458 2459 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2460 * so that machine_query_hotpluggable_cpus would show correct values 2461 */ 2462 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2463 * once -smp refactoring is complete and there will be CPU private 2464 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2465 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2466 smp_cores, smp_threads, &topo); 2467 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2468 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2469 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2470 return; 2471 } 2472 cpu->socket_id = topo.pkg_id; 2473 2474 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 2475 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 2476 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 2477 return; 2478 } 2479 cpu->die_id = topo.die_id; 2480 2481 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2482 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2483 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2484 return; 2485 } 2486 cpu->core_id = topo.core_id; 2487 2488 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2489 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2490 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2491 return; 2492 } 2493 cpu->thread_id = topo.smt_id; 2494 2495 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 2496 !kvm_hv_vpindex_settable()) { 2497 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2498 return; 2499 } 2500 2501 cs = CPU(cpu); 2502 cs->cpu_index = idx; 2503 2504 numa_cpu_pre_plug(cpu_slot, dev, errp); 2505 } 2506 2507 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 2508 DeviceState *dev, Error **errp) 2509 { 2510 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2511 Error *local_err = NULL; 2512 2513 if (!hotplug_dev2) { 2514 /* 2515 * Without a bus hotplug handler, we cannot control the plug/unplug 2516 * order. This should never be the case on x86, however better add 2517 * a safety net. 2518 */ 2519 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 2520 return; 2521 } 2522 /* 2523 * First, see if we can plug this memory device at all. If that 2524 * succeeds, branch of to the actual hotplug handler. 2525 */ 2526 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2527 &local_err); 2528 if (!local_err) { 2529 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2530 } 2531 error_propagate(errp, local_err); 2532 } 2533 2534 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 2535 DeviceState *dev, Error **errp) 2536 { 2537 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2538 Error *local_err = NULL; 2539 2540 /* 2541 * Plug the memory device first and then branch off to the actual 2542 * hotplug handler. If that one fails, we can easily undo the memory 2543 * device bits. 2544 */ 2545 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2546 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2547 if (local_err) { 2548 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2549 } 2550 error_propagate(errp, local_err); 2551 } 2552 2553 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 2554 DeviceState *dev, Error **errp) 2555 { 2556 /* We don't support virtio pmem hot unplug */ 2557 error_setg(errp, "virtio pmem device unplug not supported."); 2558 } 2559 2560 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 2561 DeviceState *dev, Error **errp) 2562 { 2563 /* We don't support virtio pmem hot unplug */ 2564 } 2565 2566 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2567 DeviceState *dev, Error **errp) 2568 { 2569 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2570 pc_memory_pre_plug(hotplug_dev, dev, errp); 2571 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2572 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2573 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2574 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 2575 } 2576 } 2577 2578 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2579 DeviceState *dev, Error **errp) 2580 { 2581 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2582 pc_memory_plug(hotplug_dev, dev, errp); 2583 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2584 pc_cpu_plug(hotplug_dev, dev, errp); 2585 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2586 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 2587 } 2588 } 2589 2590 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2591 DeviceState *dev, Error **errp) 2592 { 2593 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2594 pc_memory_unplug_request(hotplug_dev, dev, errp); 2595 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2596 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2597 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2598 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 2599 } else { 2600 error_setg(errp, "acpi: device unplug request for not supported device" 2601 " type: %s", object_get_typename(OBJECT(dev))); 2602 } 2603 } 2604 2605 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2606 DeviceState *dev, Error **errp) 2607 { 2608 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2609 pc_memory_unplug(hotplug_dev, dev, errp); 2610 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2611 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2612 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2613 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 2614 } else { 2615 error_setg(errp, "acpi: device unplug for not supported device" 2616 " type: %s", object_get_typename(OBJECT(dev))); 2617 } 2618 } 2619 2620 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2621 DeviceState *dev) 2622 { 2623 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2624 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 2625 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2626 return HOTPLUG_HANDLER(machine); 2627 } 2628 2629 return NULL; 2630 } 2631 2632 static void 2633 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2634 const char *name, void *opaque, 2635 Error **errp) 2636 { 2637 MachineState *ms = MACHINE(obj); 2638 int64_t value = 0; 2639 2640 if (ms->device_memory) { 2641 value = memory_region_size(&ms->device_memory->mr); 2642 } 2643 2644 visit_type_int(v, name, &value, errp); 2645 } 2646 2647 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2648 const char *name, void *opaque, 2649 Error **errp) 2650 { 2651 PCMachineState *pcms = PC_MACHINE(obj); 2652 uint64_t value = pcms->max_ram_below_4g; 2653 2654 visit_type_size(v, name, &value, errp); 2655 } 2656 2657 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2658 const char *name, void *opaque, 2659 Error **errp) 2660 { 2661 PCMachineState *pcms = PC_MACHINE(obj); 2662 Error *error = NULL; 2663 uint64_t value; 2664 2665 visit_type_size(v, name, &value, &error); 2666 if (error) { 2667 error_propagate(errp, error); 2668 return; 2669 } 2670 if (value > 4 * GiB) { 2671 error_setg(&error, 2672 "Machine option 'max-ram-below-4g=%"PRIu64 2673 "' expects size less than or equal to 4G", value); 2674 error_propagate(errp, error); 2675 return; 2676 } 2677 2678 if (value < 1 * MiB) { 2679 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2680 "BIOS may not work with less than 1MiB", value); 2681 } 2682 2683 pcms->max_ram_below_4g = value; 2684 } 2685 2686 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2687 void *opaque, Error **errp) 2688 { 2689 PCMachineState *pcms = PC_MACHINE(obj); 2690 OnOffAuto vmport = pcms->vmport; 2691 2692 visit_type_OnOffAuto(v, name, &vmport, errp); 2693 } 2694 2695 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2696 void *opaque, Error **errp) 2697 { 2698 PCMachineState *pcms = PC_MACHINE(obj); 2699 2700 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2701 } 2702 2703 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2704 { 2705 bool smm_available = false; 2706 2707 if (pcms->smm == ON_OFF_AUTO_OFF) { 2708 return false; 2709 } 2710 2711 if (tcg_enabled() || qtest_enabled()) { 2712 smm_available = true; 2713 } else if (kvm_enabled()) { 2714 smm_available = kvm_has_smm(); 2715 } 2716 2717 if (smm_available) { 2718 return true; 2719 } 2720 2721 if (pcms->smm == ON_OFF_AUTO_ON) { 2722 error_report("System Management Mode not supported by this hypervisor."); 2723 exit(1); 2724 } 2725 return false; 2726 } 2727 2728 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2729 void *opaque, Error **errp) 2730 { 2731 PCMachineState *pcms = PC_MACHINE(obj); 2732 OnOffAuto smm = pcms->smm; 2733 2734 visit_type_OnOffAuto(v, name, &smm, errp); 2735 } 2736 2737 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2738 void *opaque, Error **errp) 2739 { 2740 PCMachineState *pcms = PC_MACHINE(obj); 2741 2742 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2743 } 2744 2745 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2746 { 2747 PCMachineState *pcms = PC_MACHINE(obj); 2748 2749 return pcms->smbus_enabled; 2750 } 2751 2752 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2753 { 2754 PCMachineState *pcms = PC_MACHINE(obj); 2755 2756 pcms->smbus_enabled = value; 2757 } 2758 2759 static bool pc_machine_get_sata(Object *obj, Error **errp) 2760 { 2761 PCMachineState *pcms = PC_MACHINE(obj); 2762 2763 return pcms->sata_enabled; 2764 } 2765 2766 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2767 { 2768 PCMachineState *pcms = PC_MACHINE(obj); 2769 2770 pcms->sata_enabled = value; 2771 } 2772 2773 static bool pc_machine_get_pit(Object *obj, Error **errp) 2774 { 2775 PCMachineState *pcms = PC_MACHINE(obj); 2776 2777 return pcms->pit_enabled; 2778 } 2779 2780 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2781 { 2782 PCMachineState *pcms = PC_MACHINE(obj); 2783 2784 pcms->pit_enabled = value; 2785 } 2786 2787 static void pc_machine_initfn(Object *obj) 2788 { 2789 PCMachineState *pcms = PC_MACHINE(obj); 2790 2791 pcms->max_ram_below_4g = 0; /* use default */ 2792 pcms->smm = ON_OFF_AUTO_AUTO; 2793 pcms->vmport = ON_OFF_AUTO_AUTO; 2794 /* acpi build is enabled by default if machine supports it */ 2795 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2796 pcms->smbus_enabled = true; 2797 pcms->sata_enabled = true; 2798 pcms->pit_enabled = true; 2799 pcms->smp_dies = 1; 2800 2801 pc_system_flash_create(pcms); 2802 } 2803 2804 static void pc_machine_reset(MachineState *machine) 2805 { 2806 CPUState *cs; 2807 X86CPU *cpu; 2808 2809 qemu_devices_reset(); 2810 2811 /* Reset APIC after devices have been reset to cancel 2812 * any changes that qemu_devices_reset() might have done. 2813 */ 2814 CPU_FOREACH(cs) { 2815 cpu = X86_CPU(cs); 2816 2817 if (cpu->apic_state) { 2818 device_reset(cpu->apic_state); 2819 } 2820 } 2821 } 2822 2823 static CpuInstanceProperties 2824 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2825 { 2826 MachineClass *mc = MACHINE_GET_CLASS(ms); 2827 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2828 2829 assert(cpu_index < possible_cpus->len); 2830 return possible_cpus->cpus[cpu_index].props; 2831 } 2832 2833 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2834 { 2835 X86CPUTopoInfo topo; 2836 PCMachineState *pcms = PC_MACHINE(ms); 2837 2838 assert(idx < ms->possible_cpus->len); 2839 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2840 pcms->smp_dies, ms->smp.cores, 2841 ms->smp.threads, &topo); 2842 return topo.pkg_id % nb_numa_nodes; 2843 } 2844 2845 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2846 { 2847 PCMachineState *pcms = PC_MACHINE(ms); 2848 int i; 2849 unsigned int max_cpus = ms->smp.max_cpus; 2850 2851 if (ms->possible_cpus) { 2852 /* 2853 * make sure that max_cpus hasn't changed since the first use, i.e. 2854 * -smp hasn't been parsed after it 2855 */ 2856 assert(ms->possible_cpus->len == max_cpus); 2857 return ms->possible_cpus; 2858 } 2859 2860 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2861 sizeof(CPUArchId) * max_cpus); 2862 ms->possible_cpus->len = max_cpus; 2863 for (i = 0; i < ms->possible_cpus->len; i++) { 2864 X86CPUTopoInfo topo; 2865 2866 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2867 ms->possible_cpus->cpus[i].vcpus_count = 1; 2868 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); 2869 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2870 pcms->smp_dies, ms->smp.cores, 2871 ms->smp.threads, &topo); 2872 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2873 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2874 ms->possible_cpus->cpus[i].props.has_die_id = true; 2875 ms->possible_cpus->cpus[i].props.die_id = topo.die_id; 2876 ms->possible_cpus->cpus[i].props.has_core_id = true; 2877 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2878 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2879 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2880 } 2881 return ms->possible_cpus; 2882 } 2883 2884 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2885 { 2886 /* cpu index isn't used */ 2887 CPUState *cs; 2888 2889 CPU_FOREACH(cs) { 2890 X86CPU *cpu = X86_CPU(cs); 2891 2892 if (!cpu->apic_state) { 2893 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2894 } else { 2895 apic_deliver_nmi(cpu->apic_state); 2896 } 2897 } 2898 } 2899 2900 static void pc_machine_class_init(ObjectClass *oc, void *data) 2901 { 2902 MachineClass *mc = MACHINE_CLASS(oc); 2903 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2904 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2905 NMIClass *nc = NMI_CLASS(oc); 2906 2907 pcmc->pci_enabled = true; 2908 pcmc->has_acpi_build = true; 2909 pcmc->rsdp_in_ram = true; 2910 pcmc->smbios_defaults = true; 2911 pcmc->smbios_uuid_encoded = true; 2912 pcmc->gigabyte_align = true; 2913 pcmc->has_reserved_memory = true; 2914 pcmc->kvmclock_enabled = true; 2915 pcmc->enforce_aligned_dimm = true; 2916 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2917 * to be used at the moment, 32K should be enough for a while. */ 2918 pcmc->acpi_data_size = 0x20000 + 0x8000; 2919 pcmc->save_tsc_khz = true; 2920 pcmc->linuxboot_dma_enabled = true; 2921 pcmc->pvh_enabled = true; 2922 assert(!mc->get_hotplug_handler); 2923 mc->get_hotplug_handler = pc_get_hotplug_handler; 2924 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2925 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2926 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2927 mc->auto_enable_numa_with_memhp = true; 2928 mc->has_hotpluggable_cpus = true; 2929 mc->default_boot_order = "cad"; 2930 mc->hot_add_cpu = pc_hot_add_cpu; 2931 mc->smp_parse = pc_smp_parse; 2932 mc->block_default_type = IF_IDE; 2933 mc->max_cpus = 255; 2934 mc->reset = pc_machine_reset; 2935 hc->pre_plug = pc_machine_device_pre_plug_cb; 2936 hc->plug = pc_machine_device_plug_cb; 2937 hc->unplug_request = pc_machine_device_unplug_request_cb; 2938 hc->unplug = pc_machine_device_unplug_cb; 2939 nc->nmi_monitor_handler = x86_nmi; 2940 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2941 mc->nvdimm_supported = true; 2942 mc->numa_mem_supported = true; 2943 2944 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2945 pc_machine_get_device_memory_region_size, NULL, 2946 NULL, NULL, &error_abort); 2947 2948 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2949 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2950 NULL, NULL, &error_abort); 2951 2952 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2953 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2954 2955 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2956 pc_machine_get_smm, pc_machine_set_smm, 2957 NULL, NULL, &error_abort); 2958 object_class_property_set_description(oc, PC_MACHINE_SMM, 2959 "Enable SMM (pc & q35)", &error_abort); 2960 2961 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2962 pc_machine_get_vmport, pc_machine_set_vmport, 2963 NULL, NULL, &error_abort); 2964 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2965 "Enable vmport (pc & q35)", &error_abort); 2966 2967 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2968 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2969 2970 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2971 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2972 2973 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2974 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2975 } 2976 2977 static const TypeInfo pc_machine_info = { 2978 .name = TYPE_PC_MACHINE, 2979 .parent = TYPE_MACHINE, 2980 .abstract = true, 2981 .instance_size = sizeof(PCMachineState), 2982 .instance_init = pc_machine_initfn, 2983 .class_size = sizeof(PCMachineClass), 2984 .class_init = pc_machine_class_init, 2985 .interfaces = (InterfaceInfo[]) { 2986 { TYPE_HOTPLUG_HANDLER }, 2987 { TYPE_NMI }, 2988 { } 2989 }, 2990 }; 2991 2992 static void pc_machine_register_types(void) 2993 { 2994 type_register_static(&pc_machine_info); 2995 } 2996 2997 type_init(pc_machine_register_types) 2998