xref: /openbmc/qemu/hw/i386/pc.c (revision 764a6ee9)
1 /*
2  * QEMU PC System Emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial-isa.h"
29 #include "hw/char/parallel.h"
30 #include "hw/hyperv/hv-balloon.h"
31 #include "hw/i386/fw_cfg.h"
32 #include "hw/i386/vmport.h"
33 #include "sysemu/cpus.h"
34 #include "hw/ide/ide-bus.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/loader.h"
37 #include "hw/rtc/mc146818rtc.h"
38 #include "hw/intc/i8259.h"
39 #include "hw/timer/i8254.h"
40 #include "hw/input/i8042.h"
41 #include "hw/audio/pcspk.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/xen.h"
44 #include "sysemu/reset.h"
45 #include "kvm/kvm_i386.h"
46 #include "hw/xen/xen.h"
47 #include "qapi/qmp/qlist.h"
48 #include "qemu/error-report.h"
49 #include "hw/acpi/cpu_hotplug.h"
50 #include "acpi-build.h"
51 #include "hw/mem/nvdimm.h"
52 #include "hw/cxl/cxl_host.h"
53 #include "hw/usb.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/net/ne2000-isa.h"
56 #include "hw/virtio/virtio-iommu.h"
57 #include "hw/virtio/virtio-md-pci.h"
58 #include "hw/i386/kvm/xen_overlay.h"
59 #include "hw/i386/kvm/xen_evtchn.h"
60 #include "hw/i386/kvm/xen_gnttab.h"
61 #include "hw/i386/kvm/xen_xenstore.h"
62 #include "hw/mem/memory-device.h"
63 #include "e820_memory_layout.h"
64 #include "trace.h"
65 #include "sev.h"
66 #include CONFIG_DEVICES
67 
68 #ifdef CONFIG_XEN_EMU
69 #include "hw/xen/xen-legacy-backend.h"
70 #include "hw/xen/xen-bus.h"
71 #endif
72 
73 /*
74  * Helper for setting model-id for CPU models that changed model-id
75  * depending on QEMU versions up to QEMU 2.4.
76  */
77 #define PC_CPU_MODEL_IDS(v) \
78     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
79     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
80     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
81 
82 GlobalProperty pc_compat_9_1[] = {
83     { "ICH9-LPC", "x-smi-swsmi-timer", "off" },
84     { "ICH9-LPC", "x-smi-periodic-timer", "off" },
85 };
86 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1);
87 
88 GlobalProperty pc_compat_9_0[] = {
89     { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" },
90     { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" },
91     { TYPE_X86_CPU, "guest-phys-bits", "0" },
92     { "sev-guest", "legacy-vm-type", "on" },
93     { TYPE_X86_CPU, "legacy-multi-node", "on" },
94 };
95 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0);
96 
97 GlobalProperty pc_compat_8_2[] = {};
98 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2);
99 
100 GlobalProperty pc_compat_8_1[] = {};
101 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1);
102 
103 GlobalProperty pc_compat_8_0[] = {
104     { "virtio-mem", "unplugged-inaccessible", "auto" },
105 };
106 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0);
107 
108 GlobalProperty pc_compat_7_2[] = {
109     { "ICH9-LPC", "noreboot", "true" },
110 };
111 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2);
112 
113 GlobalProperty pc_compat_7_1[] = {};
114 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
115 
116 GlobalProperty pc_compat_7_0[] = {};
117 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
118 
119 GlobalProperty pc_compat_6_2[] = {
120     { "virtio-mem", "unplugged-inaccessible", "off" },
121 };
122 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
123 
124 GlobalProperty pc_compat_6_1[] = {
125     { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
126     { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
127     { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
128     { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
129 };
130 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
131 
132 GlobalProperty pc_compat_6_0[] = {
133     { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
134     { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
135     { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
136     { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
137     { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
138     { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
139 };
140 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
141 
142 GlobalProperty pc_compat_5_2[] = {
143     { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
144 };
145 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
146 
147 GlobalProperty pc_compat_5_1[] = {
148     { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
149     { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
150 };
151 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
152 
153 GlobalProperty pc_compat_5_0[] = {
154 };
155 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
156 
157 GlobalProperty pc_compat_4_2[] = {
158     { "mch", "smbase-smram", "off" },
159 };
160 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
161 
162 GlobalProperty pc_compat_4_1[] = {};
163 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
164 
165 GlobalProperty pc_compat_4_0[] = {};
166 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
167 
168 GlobalProperty pc_compat_3_1[] = {
169     { "intel-iommu", "dma-drain", "off" },
170     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
171     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
172     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
173     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
174     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
175     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
176     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
177     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
178     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
179     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
180     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
181     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
182     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
183     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
184     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
185     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
186     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
187     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
188     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
189     { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
190 };
191 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
192 
193 GlobalProperty pc_compat_3_0[] = {
194     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
195     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
196     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
197 };
198 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
199 
200 GlobalProperty pc_compat_2_12[] = {
201     { TYPE_X86_CPU, "legacy-cache", "on" },
202     { TYPE_X86_CPU, "topoext", "off" },
203     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
204     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
205 };
206 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
207 
208 GlobalProperty pc_compat_2_11[] = {
209     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
210     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
211 };
212 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
213 
214 GlobalProperty pc_compat_2_10[] = {
215     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
216     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
217     { "q35-pcihost", "x-pci-hole64-fix", "off" },
218 };
219 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
220 
221 GlobalProperty pc_compat_2_9[] = {
222     { "mch", "extended-tseg-mbytes", "0" },
223 };
224 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
225 
226 GlobalProperty pc_compat_2_8[] = {
227     { TYPE_X86_CPU, "tcg-cpuid", "off" },
228     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
229     { "ICH9-LPC", "x-smi-broadcast", "off" },
230     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
231     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
232 };
233 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
234 
235 GlobalProperty pc_compat_2_7[] = {
236     { TYPE_X86_CPU, "l3-cache", "off" },
237     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
238     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
239     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
240     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
241     { "isa-pcspk", "migrate", "off" },
242 };
243 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
244 
245 GlobalProperty pc_compat_2_6[] = {
246     { TYPE_X86_CPU, "cpuid-0xb", "off" },
247     { "vmxnet3", "romfile", "" },
248     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
249     { "apic-common", "legacy-instance-id", "on", }
250 };
251 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
252 
253 GlobalProperty pc_compat_2_5[] = {};
254 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
255 
256 GlobalProperty pc_compat_2_4[] = {
257     PC_CPU_MODEL_IDS("2.4.0")
258     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
259     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
260     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
261     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
262     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
263     { TYPE_X86_CPU, "check", "off" },
264     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
265     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
266     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
267     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
268     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
269     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
270     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
271     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
272 };
273 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
274 
275 /*
276  * @PC_FW_DATA:
277  * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables
278  * and other BIOS datastructures.
279  *
280  * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K
281  * reported to be used at the moment, 32K should be enough for a while.
282  */
283 #define PC_FW_DATA (0x20000 + 0x8000)
284 
285 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
286 {
287     GSIState *s;
288 
289     s = g_new0(GSIState, 1);
290     if (kvm_ioapic_in_kernel()) {
291         kvm_pc_setup_irq_routing(pci_enabled);
292     }
293     *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS);
294 
295     return s;
296 }
297 
298 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
299                            unsigned size)
300 {
301 }
302 
303 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
304 {
305     return 0xffffffffffffffffULL;
306 }
307 
308 /* MS-DOS compatibility mode FPU exception support */
309 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
310                            unsigned size)
311 {
312     if (tcg_enabled()) {
313         cpu_set_ignne();
314     }
315 }
316 
317 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
318 {
319     return 0xffffffffffffffffULL;
320 }
321 
322 /* PC cmos mappings */
323 
324 #define REG_EQUIPMENT_BYTE          0x14
325 
326 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs,
327                          int16_t cylinders, int8_t heads, int8_t sectors)
328 {
329     mc146818rtc_set_cmos_data(s, type_ofs, 47);
330     mc146818rtc_set_cmos_data(s, info_ofs, cylinders);
331     mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8);
332     mc146818rtc_set_cmos_data(s, info_ofs + 2, heads);
333     mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff);
334     mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff);
335     mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
336     mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders);
337     mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8);
338     mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors);
339 }
340 
341 /* convert boot_device letter to something recognizable by the bios */
342 static int boot_device2nibble(char boot_device)
343 {
344     switch(boot_device) {
345     case 'a':
346     case 'b':
347         return 0x01; /* floppy boot */
348     case 'c':
349         return 0x02; /* hard drive boot */
350     case 'd':
351         return 0x03; /* CD-ROM boot */
352     case 'n':
353         return 0x04; /* Network boot */
354     }
355     return 0;
356 }
357 
358 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s,
359                          const char *boot_device, Error **errp)
360 {
361 #define PC_MAX_BOOT_DEVICES 3
362     int nbds, bds[3] = { 0, };
363     int i;
364 
365     nbds = strlen(boot_device);
366     if (nbds > PC_MAX_BOOT_DEVICES) {
367         error_setg(errp, "Too many boot devices for PC");
368         return;
369     }
370     for (i = 0; i < nbds; i++) {
371         bds[i] = boot_device2nibble(boot_device[i]);
372         if (bds[i] == 0) {
373             error_setg(errp, "Invalid boot device for PC: '%c'",
374                        boot_device[i]);
375             return;
376         }
377     }
378     mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]);
379     mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk);
380 }
381 
382 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
383 {
384     PCMachineState *pcms = opaque;
385     X86MachineState *x86ms = X86_MACHINE(pcms);
386 
387     set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp);
388 }
389 
390 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy)
391 {
392     int val, nb;
393     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
394                                    FLOPPY_DRIVE_TYPE_NONE };
395 
396 #ifdef CONFIG_FDC_ISA
397     /* floppy type */
398     if (floppy) {
399         for (int i = 0; i < 2; i++) {
400             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
401         }
402     }
403 #endif
404 
405     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
406         cmos_get_fd_drive_type(fd_type[1]);
407     mc146818rtc_set_cmos_data(rtc_state, 0x10, val);
408 
409     val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE);
410     nb = 0;
411     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
412         nb++;
413     }
414     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
415         nb++;
416     }
417     switch (nb) {
418     case 0:
419         break;
420     case 1:
421         val |= 0x01; /* 1 drive, ready for boot */
422         break;
423     case 2:
424         val |= 0x41; /* 2 drives, ready for boot */
425         break;
426     }
427     mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val);
428 }
429 
430 typedef struct check_fdc_state {
431     ISADevice *floppy;
432     bool multiple;
433 } CheckFdcState;
434 
435 static int check_fdc(Object *obj, void *opaque)
436 {
437     CheckFdcState *state = opaque;
438     Object *fdc;
439     uint32_t iobase;
440     Error *local_err = NULL;
441 
442     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
443     if (!fdc) {
444         return 0;
445     }
446 
447     iobase = object_property_get_uint(obj, "iobase", &local_err);
448     if (local_err || iobase != 0x3f0) {
449         error_free(local_err);
450         return 0;
451     }
452 
453     if (state->floppy) {
454         state->multiple = true;
455     } else {
456         state->floppy = ISA_DEVICE(obj);
457     }
458     return 0;
459 }
460 
461 static const char * const fdc_container_path[] = {
462     "/unattached", "/peripheral", "/peripheral-anon"
463 };
464 
465 /*
466  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
467  * and ACPI objects.
468  */
469 static ISADevice *pc_find_fdc0(void)
470 {
471     int i;
472     Object *container;
473     CheckFdcState state = { 0 };
474 
475     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
476         container = container_get(qdev_get_machine(), fdc_container_path[i]);
477         object_child_foreach(container, check_fdc, &state);
478     }
479 
480     if (state.multiple) {
481         warn_report("multiple floppy disk controllers with "
482                     "iobase=0x3f0 have been found");
483         error_printf("the one being picked for CMOS setup might not reflect "
484                      "your intent");
485     }
486 
487     return state.floppy;
488 }
489 
490 static void pc_cmos_init_late(PCMachineState *pcms)
491 {
492     X86MachineState *x86ms = X86_MACHINE(pcms);
493     MC146818RtcState *s = MC146818_RTC(x86ms->rtc);
494     int16_t cylinders;
495     int8_t heads, sectors;
496     int val;
497     int i, trans;
498 
499     val = 0;
500     if (pcms->idebus[0] &&
501         ide_get_geometry(pcms->idebus[0], 0,
502                          &cylinders, &heads, &sectors) >= 0) {
503         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
504         val |= 0xf0;
505     }
506     if (pcms->idebus[0] &&
507         ide_get_geometry(pcms->idebus[0], 1,
508                          &cylinders, &heads, &sectors) >= 0) {
509         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
510         val |= 0x0f;
511     }
512     mc146818rtc_set_cmos_data(s, 0x12, val);
513 
514     val = 0;
515     for (i = 0; i < 4; i++) {
516         /* NOTE: ide_get_geometry() returns the physical
517            geometry.  It is always such that: 1 <= sects <= 63, 1
518            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
519            geometry can be different if a translation is done. */
520         BusState *idebus = pcms->idebus[i / 2];
521         if (idebus &&
522             ide_get_geometry(idebus, i % 2,
523                              &cylinders, &heads, &sectors) >= 0) {
524             trans = ide_get_bios_chs_trans(idebus, i % 2) - 1;
525             assert((trans & ~3) == 0);
526             val |= trans << (i * 2);
527         }
528     }
529     mc146818rtc_set_cmos_data(s, 0x39, val);
530 
531     pc_cmos_init_floppy(s, pc_find_fdc0());
532 
533     /* various important CMOS locations needed by PC/Bochs bios */
534 
535     /* memory size */
536     /* base memory (first MiB) */
537     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
538     mc146818rtc_set_cmos_data(s, 0x15, val);
539     mc146818rtc_set_cmos_data(s, 0x16, val >> 8);
540     /* extended memory (next 64MiB) */
541     if (x86ms->below_4g_mem_size > 1 * MiB) {
542         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
543     } else {
544         val = 0;
545     }
546     if (val > 65535)
547         val = 65535;
548     mc146818rtc_set_cmos_data(s, 0x17, val);
549     mc146818rtc_set_cmos_data(s, 0x18, val >> 8);
550     mc146818rtc_set_cmos_data(s, 0x30, val);
551     mc146818rtc_set_cmos_data(s, 0x31, val >> 8);
552     /* memory between 16MiB and 4GiB */
553     if (x86ms->below_4g_mem_size > 16 * MiB) {
554         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
555     } else {
556         val = 0;
557     }
558     if (val > 65535)
559         val = 65535;
560     mc146818rtc_set_cmos_data(s, 0x34, val);
561     mc146818rtc_set_cmos_data(s, 0x35, val >> 8);
562     /* memory above 4GiB */
563     val = x86ms->above_4g_mem_size / 65536;
564     mc146818rtc_set_cmos_data(s, 0x5b, val);
565     mc146818rtc_set_cmos_data(s, 0x5c, val >> 8);
566     mc146818rtc_set_cmos_data(s, 0x5d, val >> 16);
567 
568     val = 0;
569     val |= 0x02; /* FPU is there */
570     val |= 0x04; /* PS/2 mouse installed */
571     mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val);
572 }
573 
574 static void handle_a20_line_change(void *opaque, int irq, int level)
575 {
576     X86CPU *cpu = opaque;
577 
578     /* XXX: send to all CPUs ? */
579     /* XXX: add logic to handle multiple A20 line sources */
580     x86_cpu_set_a20(cpu, level);
581 }
582 
583 #define NE2000_NB_MAX 6
584 
585 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
586                                               0x280, 0x380 };
587 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
588 
589 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp)
590 {
591     static int nb_ne2k = 0;
592 
593     if (nb_ne2k == NE2000_NB_MAX) {
594         error_setg(errp,
595                    "maximum number of ISA NE2000 devices exceeded");
596         return false;
597     }
598     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
599                     ne2000_irq[nb_ne2k], nd);
600     nb_ne2k++;
601     return true;
602 }
603 
604 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
605 {
606     X86CPU *cpu = opaque;
607 
608     if (level) {
609         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
610     }
611 }
612 
613 static
614 void pc_machine_done(Notifier *notifier, void *data)
615 {
616     PCMachineState *pcms = container_of(notifier,
617                                         PCMachineState, machine_done);
618     X86MachineState *x86ms = X86_MACHINE(pcms);
619 
620     cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state,
621                               &error_fatal);
622 
623     if (pcms->cxl_devices_state.is_enabled) {
624         cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
625     }
626 
627     /* set the number of CPUs */
628     x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
629 
630     fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg);
631 
632     acpi_setup();
633     if (x86ms->fw_cfg) {
634         fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type);
635         fw_cfg_add_e820(x86ms->fw_cfg);
636         fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
637         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
638         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
639     }
640 
641     pc_cmos_init_late(pcms);
642 }
643 
644 /* setup pci memory address space mapping into system address space */
645 void pc_pci_as_mapping_init(MemoryRegion *system_memory,
646                             MemoryRegion *pci_address_space)
647 {
648     /* Set to lower priority than RAM */
649     memory_region_add_subregion_overlap(system_memory, 0x0,
650                                         pci_address_space, -1);
651 }
652 
653 void xen_load_linux(PCMachineState *pcms)
654 {
655     int i;
656     FWCfgState *fw_cfg;
657     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
658     X86MachineState *x86ms = X86_MACHINE(pcms);
659 
660     assert(MACHINE(pcms)->kernel_filename != NULL);
661 
662     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
663                                 &address_space_memory);
664     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
665     rom_set_fw(fw_cfg);
666 
667     x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled);
668     for (i = 0; i < nb_option_roms; i++) {
669         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
670                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
671                !strcmp(option_rom[i].name, "pvh.bin") ||
672                !strcmp(option_rom[i].name, "multiboot.bin") ||
673                !strcmp(option_rom[i].name, "multiboot_dma.bin"));
674         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
675     }
676     x86ms->fw_cfg = fw_cfg;
677 }
678 
679 #define PC_ROM_MIN_VGA     0xc0000
680 #define PC_ROM_MIN_OPTION  0xc8000
681 #define PC_ROM_MAX         0xe0000
682 #define PC_ROM_ALIGN       0x800
683 #define PC_ROM_SIZE        (PC_ROM_MAX - PC_ROM_MIN_VGA)
684 
685 static hwaddr pc_above_4g_end(PCMachineState *pcms)
686 {
687     X86MachineState *x86ms = X86_MACHINE(pcms);
688 
689     if (pcms->sgx_epc.size != 0) {
690         return sgx_epc_above_4g_end(&pcms->sgx_epc);
691     }
692 
693     return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
694 }
695 
696 static void pc_get_device_memory_range(PCMachineState *pcms,
697                                        hwaddr *base,
698                                        ram_addr_t *device_mem_size)
699 {
700     MachineState *machine = MACHINE(pcms);
701     ram_addr_t size;
702     hwaddr addr;
703 
704     size = machine->maxram_size - machine->ram_size;
705     addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
706 
707     /* size device region assuming 1G page max alignment per slot */
708     size += (1 * GiB) * machine->ram_slots;
709 
710     *base = addr;
711     *device_mem_size = size;
712 }
713 
714 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
715 {
716     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
717     MachineState *ms = MACHINE(pcms);
718     hwaddr cxl_base;
719     ram_addr_t size;
720 
721     if (pcmc->has_reserved_memory &&
722         (ms->ram_size < ms->maxram_size)) {
723         pc_get_device_memory_range(pcms, &cxl_base, &size);
724         cxl_base += size;
725     } else {
726         cxl_base = pc_above_4g_end(pcms);
727     }
728 
729     return cxl_base;
730 }
731 
732 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
733 {
734     uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
735 
736     if (pcms->cxl_devices_state.fixed_windows) {
737         GList *it;
738 
739         start = ROUND_UP(start, 256 * MiB);
740         for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
741             CXLFixedWindow *fw = it->data;
742             start += fw->size;
743         }
744     }
745 
746     return start;
747 }
748 
749 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
750 {
751     X86CPU *cpu = X86_CPU(first_cpu);
752     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
753     MachineState *ms = MACHINE(pcms);
754 
755     if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
756         /* 64-bit systems */
757         return pc_pci_hole64_start() + pci_hole64_size - 1;
758     }
759 
760     /* 32-bit systems */
761     if (pcmc->broken_32bit_mem_addr_check) {
762         /* old value for compatibility reasons */
763         return ((hwaddr)1 << cpu->phys_bits) - 1;
764     }
765 
766     /*
767      * 32-bit systems don't have hole64 but they might have a region for
768      * memory devices. Even if additional hotplugged memory devices might
769      * not be usable by most guest OSes, we need to still consider them for
770      * calculating the highest possible GPA so that we can properly report
771      * if someone configures them on a CPU that cannot possibly address them.
772      */
773     if (pcmc->has_reserved_memory &&
774         (ms->ram_size < ms->maxram_size)) {
775         hwaddr devmem_start;
776         ram_addr_t devmem_size;
777 
778         pc_get_device_memory_range(pcms, &devmem_start, &devmem_size);
779         devmem_start += devmem_size;
780         return devmem_start - 1;
781     }
782 
783     /* configuration without any memory hotplug */
784     return pc_above_4g_end(pcms) - 1;
785 }
786 
787 /*
788  * AMD systems with an IOMMU have an additional hole close to the
789  * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
790  * on kernel version, VFIO may or may not let you DMA map those ranges.
791  * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
792  * with certain memory sizes. It's also wrong to use those IOVA ranges
793  * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
794  * The ranges reserved for Hyper-Transport are:
795  *
796  * FD_0000_0000h - FF_FFFF_FFFFh
797  *
798  * The ranges represent the following:
799  *
800  * Base Address   Top Address  Use
801  *
802  * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
803  * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
804  * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
805  * FD_F910_0000h FD_F91F_FFFFh System Management
806  * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
807  * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
808  * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
809  * FD_FE00_0000h FD_FFFF_FFFFh Configuration
810  * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
811  * FE_2000_0000h FF_FFFF_FFFFh Reserved
812  *
813  * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
814  * Table 3: Special Address Controls (GPA) for more information.
815  */
816 #define AMD_HT_START         0xfd00000000UL
817 #define AMD_HT_END           0xffffffffffUL
818 #define AMD_ABOVE_1TB_START  (AMD_HT_END + 1)
819 #define AMD_HT_SIZE          (AMD_ABOVE_1TB_START - AMD_HT_START)
820 
821 void pc_memory_init(PCMachineState *pcms,
822                     MemoryRegion *system_memory,
823                     MemoryRegion *rom_memory,
824                     uint64_t pci_hole64_size)
825 {
826     int linux_boot, i;
827     MemoryRegion *option_rom_mr;
828     MemoryRegion *ram_below_4g, *ram_above_4g;
829     FWCfgState *fw_cfg;
830     MachineState *machine = MACHINE(pcms);
831     MachineClass *mc = MACHINE_GET_CLASS(machine);
832     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
833     X86MachineState *x86ms = X86_MACHINE(pcms);
834     hwaddr maxphysaddr, maxusedaddr;
835     hwaddr cxl_base, cxl_resv_end = 0;
836     X86CPU *cpu = X86_CPU(first_cpu);
837 
838     assert(machine->ram_size == x86ms->below_4g_mem_size +
839                                 x86ms->above_4g_mem_size);
840 
841     linux_boot = (machine->kernel_filename != NULL);
842 
843     /*
844      * The HyperTransport range close to the 1T boundary is unique to AMD
845      * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
846      * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
847      * older machine types (<= 7.0) for compatibility purposes.
848      */
849     if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
850         /* Bail out if max possible address does not cross HT range */
851         if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
852             x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
853         }
854 
855         /*
856          * Advertise the HT region if address space covers the reserved
857          * region or if we relocate.
858          */
859         if (cpu->phys_bits >= 40) {
860             e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
861         }
862     }
863 
864     /*
865      * phys-bits is required to be appropriately configured
866      * to make sure max used GPA is reachable.
867      */
868     maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
869     maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
870     if (maxphysaddr < maxusedaddr) {
871         error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
872                      " phys-bits too low (%u)",
873                      maxphysaddr, maxusedaddr, cpu->phys_bits);
874         exit(EXIT_FAILURE);
875     }
876 
877     /*
878      * Split single memory region and use aliases to address portions of it,
879      * done for backwards compatibility with older qemus.
880      */
881     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
882     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
883                              0, x86ms->below_4g_mem_size);
884     memory_region_add_subregion(system_memory, 0, ram_below_4g);
885     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
886     if (x86ms->above_4g_mem_size > 0) {
887         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
888         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
889                                  machine->ram,
890                                  x86ms->below_4g_mem_size,
891                                  x86ms->above_4g_mem_size);
892         memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
893                                     ram_above_4g);
894         e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
895                        E820_RAM);
896     }
897 
898     if (pcms->sgx_epc.size != 0) {
899         e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
900     }
901 
902     if (!pcmc->has_reserved_memory &&
903         (machine->ram_slots ||
904          (machine->maxram_size > machine->ram_size))) {
905 
906         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
907                      mc->name);
908         exit(EXIT_FAILURE);
909     }
910 
911     /* initialize device memory address space */
912     if (pcmc->has_reserved_memory &&
913         (machine->ram_size < machine->maxram_size)) {
914         ram_addr_t device_mem_size;
915         hwaddr device_mem_base;
916 
917         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
918             error_report("unsupported amount of memory slots: %"PRIu64,
919                          machine->ram_slots);
920             exit(EXIT_FAILURE);
921         }
922 
923         if (QEMU_ALIGN_UP(machine->maxram_size,
924                           TARGET_PAGE_SIZE) != machine->maxram_size) {
925             error_report("maximum memory size must by aligned to multiple of "
926                          "%d bytes", TARGET_PAGE_SIZE);
927             exit(EXIT_FAILURE);
928         }
929 
930         pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size);
931 
932         if (device_mem_base + device_mem_size < device_mem_size) {
933             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
934                          machine->maxram_size);
935             exit(EXIT_FAILURE);
936         }
937         machine_memory_devices_init(machine, device_mem_base, device_mem_size);
938     }
939 
940     if (pcms->cxl_devices_state.is_enabled) {
941         MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
942         hwaddr cxl_size = MiB;
943 
944         cxl_base = pc_get_cxl_range_start(pcms);
945         memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
946         memory_region_add_subregion(system_memory, cxl_base, mr);
947         cxl_resv_end = cxl_base + cxl_size;
948         if (pcms->cxl_devices_state.fixed_windows) {
949             hwaddr cxl_fmw_base;
950             GList *it;
951 
952             cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
953             for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
954                 CXLFixedWindow *fw = it->data;
955 
956                 fw->base = cxl_fmw_base;
957                 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
958                                       "cxl-fixed-memory-region", fw->size);
959                 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
960                 cxl_fmw_base += fw->size;
961                 cxl_resv_end = cxl_fmw_base;
962             }
963         }
964     }
965 
966     /* Initialize PC system firmware */
967     pc_system_firmware_init(pcms, rom_memory);
968 
969     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
970     if (machine_require_guest_memfd(machine)) {
971         memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom",
972                                            PC_ROM_SIZE, &error_fatal);
973     } else {
974         memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
975                                &error_fatal);
976         if (pcmc->pci_enabled) {
977             memory_region_set_readonly(option_rom_mr, true);
978         }
979     }
980     memory_region_add_subregion_overlap(rom_memory,
981                                         PC_ROM_MIN_VGA,
982                                         option_rom_mr,
983                                         1);
984 
985     fw_cfg = fw_cfg_arch_create(machine,
986                                 x86ms->boot_cpus, x86ms->apic_id_limit);
987 
988     rom_set_fw(fw_cfg);
989 
990     if (machine->device_memory) {
991         uint64_t *val = g_malloc(sizeof(*val));
992         uint64_t res_mem_end = machine->device_memory->base;
993 
994         if (!pcmc->broken_reserved_end) {
995             res_mem_end += memory_region_size(&machine->device_memory->mr);
996         }
997 
998         if (pcms->cxl_devices_state.is_enabled) {
999             res_mem_end = cxl_resv_end;
1000         }
1001         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1002         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1003     }
1004 
1005     if (linux_boot) {
1006         x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled);
1007     }
1008 
1009     for (i = 0; i < nb_option_roms; i++) {
1010         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1011     }
1012     x86ms->fw_cfg = fw_cfg;
1013 
1014     /* Init default IOAPIC address space */
1015     x86ms->ioapic_as = &address_space_memory;
1016 
1017     /* Init ACPI memory hotplug IO base address */
1018     pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1019 }
1020 
1021 /*
1022  * The 64bit pci hole starts after "above 4G RAM" and
1023  * potentially the space reserved for memory hotplug.
1024  */
1025 uint64_t pc_pci_hole64_start(void)
1026 {
1027     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1028     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1029     MachineState *ms = MACHINE(pcms);
1030     uint64_t hole64_start = 0;
1031     ram_addr_t size = 0;
1032 
1033     if (pcms->cxl_devices_state.is_enabled) {
1034         hole64_start = pc_get_cxl_range_end(pcms);
1035     } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1036         pc_get_device_memory_range(pcms, &hole64_start, &size);
1037         if (!pcmc->broken_reserved_end) {
1038             hole64_start += size;
1039         }
1040     } else {
1041         hole64_start = pc_above_4g_end(pcms);
1042     }
1043 
1044     return ROUND_UP(hole64_start, 1 * GiB);
1045 }
1046 
1047 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1048 {
1049     DeviceState *dev = NULL;
1050 
1051     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1052     if (pci_bus) {
1053         PCIDevice *pcidev = pci_vga_init(pci_bus);
1054         dev = pcidev ? &pcidev->qdev : NULL;
1055     } else if (isa_bus) {
1056         ISADevice *isadev = isa_vga_init(isa_bus);
1057         dev = isadev ? DEVICE(isadev) : NULL;
1058     }
1059     rom_reset_order_override();
1060     return dev;
1061 }
1062 
1063 static const MemoryRegionOps ioport80_io_ops = {
1064     .write = ioport80_write,
1065     .read = ioport80_read,
1066     .endianness = DEVICE_NATIVE_ENDIAN,
1067     .impl = {
1068         .min_access_size = 1,
1069         .max_access_size = 1,
1070     },
1071 };
1072 
1073 static const MemoryRegionOps ioportF0_io_ops = {
1074     .write = ioportF0_write,
1075     .read = ioportF0_read,
1076     .endianness = DEVICE_NATIVE_ENDIAN,
1077     .impl = {
1078         .min_access_size = 1,
1079         .max_access_size = 1,
1080     },
1081 };
1082 
1083 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1084                             bool create_i8042, bool no_vmport, Error **errp)
1085 {
1086     int i;
1087     DriveInfo *fd[MAX_FD];
1088     qemu_irq *a20_line;
1089     ISADevice *i8042, *port92, *vmmouse;
1090 
1091     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1092     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1093 
1094     for (i = 0; i < MAX_FD; i++) {
1095         fd[i] = drive_get(IF_FLOPPY, 0, i);
1096         create_fdctrl |= !!fd[i];
1097     }
1098     if (create_fdctrl) {
1099 #ifdef CONFIG_FDC_ISA
1100         ISADevice *fdc = isa_new(TYPE_ISA_FDC);
1101         if (fdc) {
1102             isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1103             isa_fdc_init_drives(fdc, fd);
1104         }
1105 #endif
1106     }
1107 
1108     if (!create_i8042) {
1109         if (!no_vmport) {
1110             error_setg(errp,
1111                        "vmport requires the i8042 controller to be enabled");
1112         }
1113         return;
1114     }
1115 
1116     i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1117     if (!no_vmport) {
1118         isa_create_simple(isa_bus, TYPE_VMPORT);
1119         vmmouse = isa_try_new("vmmouse");
1120     } else {
1121         vmmouse = NULL;
1122     }
1123     if (vmmouse) {
1124         object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1125                                  &error_abort);
1126         isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1127     }
1128     port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1129 
1130     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1131     qdev_connect_gpio_out_named(DEVICE(i8042),
1132                                 I8042_A20_LINE, 0, a20_line[0]);
1133     qdev_connect_gpio_out_named(DEVICE(port92),
1134                                 PORT92_A20_LINE, 0, a20_line[1]);
1135     g_free(a20_line);
1136 }
1137 
1138 void pc_basic_device_init(struct PCMachineState *pcms,
1139                           ISABus *isa_bus, qemu_irq *gsi,
1140                           ISADevice *rtc_state,
1141                           bool create_fdctrl,
1142                           uint32_t hpet_irqs)
1143 {
1144     int i;
1145     DeviceState *hpet = NULL;
1146     int pit_isa_irq = 0;
1147     qemu_irq pit_alt_irq = NULL;
1148     ISADevice *pit = NULL;
1149     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1150     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1151     X86MachineState *x86ms = X86_MACHINE(pcms);
1152 
1153     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1154     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1155 
1156     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1157     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1158 
1159     /*
1160      * Check if an HPET shall be created.
1161      */
1162     if (pcms->hpet_enabled) {
1163         qemu_irq rtc_irq;
1164 
1165         hpet = qdev_try_new(TYPE_HPET);
1166         if (!hpet) {
1167             error_report("couldn't create HPET device");
1168             exit(1);
1169         }
1170         /*
1171          * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*,
1172          * use IRQ16~23, IRQ8 and IRQ2.  If the user has already set
1173          * the property, use whatever mask they specified.
1174          */
1175         uint8_t compat = object_property_get_uint(OBJECT(hpet),
1176                 HPET_INTCAP, NULL);
1177         if (!compat) {
1178             qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1179         }
1180         sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1181         sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1182 
1183         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1184             sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1185         }
1186         pit_isa_irq = -1;
1187         pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1188         rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1189 
1190         /* overwrite connection created by south bridge */
1191         qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq);
1192     }
1193 
1194     object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state),
1195                               "date");
1196 
1197 #ifdef CONFIG_XEN_EMU
1198     if (xen_mode == XEN_EMULATE) {
1199         xen_overlay_create();
1200         xen_evtchn_create(IOAPIC_NUM_PINS, gsi);
1201         xen_gnttab_create();
1202         xen_xenstore_create();
1203         if (pcms->pcibus) {
1204             pci_create_simple(pcms->pcibus, -1, "xen-platform");
1205         }
1206         xen_bus_init();
1207     }
1208 #endif
1209 
1210     qemu_register_boot_set(pc_boot_set, pcms);
1211     set_boot_dev(pcms, MC146818_RTC(rtc_state),
1212                  MACHINE(pcms)->boot_config.order, &error_fatal);
1213 
1214     if (!xen_enabled() &&
1215         (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1216         if (kvm_pit_in_kernel()) {
1217             pit = kvm_pit_init(isa_bus, 0x40);
1218         } else {
1219             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1220         }
1221         if (hpet) {
1222             /* connect PIT to output control line of the HPET */
1223             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1224         }
1225         object_property_set_link(OBJECT(pcms->pcspk), "pit",
1226                                  OBJECT(pit), &error_fatal);
1227         isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal);
1228     }
1229 
1230     assert(pcms->vmport >= 0 && pcms->vmport < ON_OFF_AUTO__MAX);
1231     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
1232         pcms->vmport = (xen_enabled() || !pcms->i8042_enabled)
1233             ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
1234     }
1235 
1236     /* Super I/O */
1237     pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1238                     pcms->vmport != ON_OFF_AUTO_ON, &error_fatal);
1239 }
1240 
1241 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1242 {
1243     MachineClass *mc = MACHINE_CLASS(pcmc);
1244     bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000);
1245     NICInfo *nd;
1246 
1247     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1248 
1249     while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) {
1250         pc_init_ne2k_isa(isa_bus, nd, &error_fatal);
1251     }
1252 
1253     /* Anything remaining should be a PCI NIC */
1254     pci_init_nic_devices(pci_bus, mc->default_nic);
1255 
1256     rom_reset_order_override();
1257 }
1258 
1259 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1260 {
1261     qemu_irq *i8259;
1262 
1263     if (kvm_pic_in_kernel()) {
1264         i8259 = kvm_i8259_init(isa_bus);
1265     } else if (xen_enabled()) {
1266         i8259 = xen_interrupt_controller_init();
1267     } else {
1268         i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1269     }
1270 
1271     for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1272         i8259_irqs[i] = i8259[i];
1273     }
1274 
1275     g_free(i8259);
1276 }
1277 
1278 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1279                                Error **errp)
1280 {
1281     const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1282     const MachineState *ms = MACHINE(hotplug_dev);
1283     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1284     Error *local_err = NULL;
1285 
1286     /*
1287      * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1288      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1289      * addition to cover this case.
1290      */
1291     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1292         error_setg(errp,
1293                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1294         return;
1295     }
1296 
1297     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1298         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1299         return;
1300     }
1301 
1302     hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1303     if (local_err) {
1304         error_propagate(errp, local_err);
1305         return;
1306     }
1307 
1308     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
1309 }
1310 
1311 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1312                            DeviceState *dev, Error **errp)
1313 {
1314     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1315     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1316     MachineState *ms = MACHINE(hotplug_dev);
1317     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1318 
1319     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1320 
1321     if (is_nvdimm) {
1322         nvdimm_plug(ms->nvdimms_state);
1323     }
1324 
1325     hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1326 }
1327 
1328 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1329                                      DeviceState *dev, Error **errp)
1330 {
1331     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1332 
1333     /*
1334      * When "acpi=off" is used with the Q35 machine type, no ACPI is built,
1335      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1336      * addition to cover this case.
1337      */
1338     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1339         error_setg(errp,
1340                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1341         return;
1342     }
1343 
1344     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1345         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1346         return;
1347     }
1348 
1349     hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1350                                    errp);
1351 }
1352 
1353 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1354                              DeviceState *dev, Error **errp)
1355 {
1356     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1357     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1358     Error *local_err = NULL;
1359 
1360     hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1361     if (local_err) {
1362         goto out;
1363     }
1364 
1365     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1366     qdev_unrealize(dev);
1367  out:
1368     error_propagate(errp, local_err);
1369 }
1370 
1371 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev,
1372                                    DeviceState *dev, Error **errp)
1373 {
1374     /* The vmbus handler has no hotplug handler; we should never end up here. */
1375     g_assert(!dev->hotplugged);
1376     memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp);
1377 }
1378 
1379 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev,
1380                                DeviceState *dev, Error **errp)
1381 {
1382     memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1383 }
1384 
1385 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1386                                           DeviceState *dev, Error **errp)
1387 {
1388     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1389         pc_memory_pre_plug(hotplug_dev, dev, errp);
1390     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1391         x86_cpu_pre_plug(hotplug_dev, dev, errp);
1392     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1393         virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1394     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1395         /* Declare the APIC range as the reserved MSI region */
1396         char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1397                                               VIRTIO_IOMMU_RESV_MEM_T_MSI);
1398         QList *reserved_regions = qlist_new();
1399 
1400         qlist_append_str(reserved_regions, resv_prop_str);
1401         qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
1402 
1403         g_free(resv_prop_str);
1404     }
1405 
1406     if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1407         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1408         PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1409 
1410         if (pcms->iommu) {
1411             error_setg(errp, "QEMU does not support multiple vIOMMUs "
1412                        "for x86 yet.");
1413             return;
1414         }
1415         pcms->iommu = dev;
1416     } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1417         pc_hv_balloon_pre_plug(hotplug_dev, dev, errp);
1418     }
1419 }
1420 
1421 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1422                                       DeviceState *dev, Error **errp)
1423 {
1424     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1425         pc_memory_plug(hotplug_dev, dev, errp);
1426     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1427         x86_cpu_plug(hotplug_dev, dev, errp);
1428     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1429         virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1430     } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) {
1431         pc_hv_balloon_plug(hotplug_dev, dev, errp);
1432     }
1433 }
1434 
1435 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1436                                                 DeviceState *dev, Error **errp)
1437 {
1438     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1439         pc_memory_unplug_request(hotplug_dev, dev, errp);
1440     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1441         x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1442     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1443         virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
1444                                      errp);
1445     } else {
1446         error_setg(errp, "acpi: device unplug request for not supported device"
1447                    " type: %s", object_get_typename(OBJECT(dev)));
1448     }
1449 }
1450 
1451 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1452                                         DeviceState *dev, Error **errp)
1453 {
1454     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1455         pc_memory_unplug(hotplug_dev, dev, errp);
1456     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1457         x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1458     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
1459         virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
1460     } else {
1461         error_setg(errp, "acpi: device unplug for not supported device"
1462                    " type: %s", object_get_typename(OBJECT(dev)));
1463     }
1464 }
1465 
1466 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1467                                              DeviceState *dev)
1468 {
1469     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1470         object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1471         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
1472         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1473         object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) ||
1474         object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1475         return HOTPLUG_HANDLER(machine);
1476     }
1477 
1478     return NULL;
1479 }
1480 
1481 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1482                                   void *opaque, Error **errp)
1483 {
1484     PCMachineState *pcms = PC_MACHINE(obj);
1485     OnOffAuto vmport = pcms->vmport;
1486 
1487     visit_type_OnOffAuto(v, name, &vmport, errp);
1488 }
1489 
1490 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1491                                   void *opaque, Error **errp)
1492 {
1493     PCMachineState *pcms = PC_MACHINE(obj);
1494 
1495     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1496 }
1497 
1498 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp)
1499 {
1500     PCMachineState *pcms = PC_MACHINE(obj);
1501 
1502     return pcms->fd_bootchk;
1503 }
1504 
1505 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp)
1506 {
1507     PCMachineState *pcms = PC_MACHINE(obj);
1508 
1509     pcms->fd_bootchk = value;
1510 }
1511 
1512 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1513 {
1514     PCMachineState *pcms = PC_MACHINE(obj);
1515 
1516     return pcms->smbus_enabled;
1517 }
1518 
1519 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1520 {
1521     PCMachineState *pcms = PC_MACHINE(obj);
1522 
1523     pcms->smbus_enabled = value;
1524 }
1525 
1526 static bool pc_machine_get_sata(Object *obj, Error **errp)
1527 {
1528     PCMachineState *pcms = PC_MACHINE(obj);
1529 
1530     return pcms->sata_enabled;
1531 }
1532 
1533 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1534 {
1535     PCMachineState *pcms = PC_MACHINE(obj);
1536 
1537     pcms->sata_enabled = value;
1538 }
1539 
1540 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1541 {
1542     PCMachineState *pcms = PC_MACHINE(obj);
1543 
1544     return pcms->hpet_enabled;
1545 }
1546 
1547 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1548 {
1549     PCMachineState *pcms = PC_MACHINE(obj);
1550 
1551     pcms->hpet_enabled = value;
1552 }
1553 
1554 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1555 {
1556     PCMachineState *pcms = PC_MACHINE(obj);
1557 
1558     return pcms->i8042_enabled;
1559 }
1560 
1561 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1562 {
1563     PCMachineState *pcms = PC_MACHINE(obj);
1564 
1565     pcms->i8042_enabled = value;
1566 }
1567 
1568 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1569 {
1570     PCMachineState *pcms = PC_MACHINE(obj);
1571 
1572     return pcms->default_bus_bypass_iommu;
1573 }
1574 
1575 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1576                                                     Error **errp)
1577 {
1578     PCMachineState *pcms = PC_MACHINE(obj);
1579 
1580     pcms->default_bus_bypass_iommu = value;
1581 }
1582 
1583 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1584                                      void *opaque, Error **errp)
1585 {
1586     PCMachineState *pcms = PC_MACHINE(obj);
1587     SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1588 
1589     visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1590 }
1591 
1592 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1593                                      void *opaque, Error **errp)
1594 {
1595     PCMachineState *pcms = PC_MACHINE(obj);
1596 
1597     visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1598 }
1599 
1600 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1601                                             const char *name, void *opaque,
1602                                             Error **errp)
1603 {
1604     PCMachineState *pcms = PC_MACHINE(obj);
1605     uint64_t value = pcms->max_ram_below_4g;
1606 
1607     visit_type_size(v, name, &value, errp);
1608 }
1609 
1610 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1611                                             const char *name, void *opaque,
1612                                             Error **errp)
1613 {
1614     PCMachineState *pcms = PC_MACHINE(obj);
1615     uint64_t value;
1616 
1617     if (!visit_type_size(v, name, &value, errp)) {
1618         return;
1619     }
1620     if (value > 4 * GiB) {
1621         error_setg(errp,
1622                    "Machine option 'max-ram-below-4g=%"PRIu64
1623                    "' expects size less than or equal to 4G", value);
1624         return;
1625     }
1626 
1627     if (value < 1 * MiB) {
1628         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1629                     "BIOS may not work with less than 1MiB", value);
1630     }
1631 
1632     pcms->max_ram_below_4g = value;
1633 }
1634 
1635 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1636                                        const char *name, void *opaque,
1637                                        Error **errp)
1638 {
1639     PCMachineState *pcms = PC_MACHINE(obj);
1640     uint64_t value = pcms->max_fw_size;
1641 
1642     visit_type_size(v, name, &value, errp);
1643 }
1644 
1645 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1646                                        const char *name, void *opaque,
1647                                        Error **errp)
1648 {
1649     PCMachineState *pcms = PC_MACHINE(obj);
1650     uint64_t value;
1651 
1652     if (!visit_type_size(v, name, &value, errp)) {
1653         return;
1654     }
1655 
1656     /*
1657      * We don't have a theoretically justifiable exact lower bound on the base
1658      * address of any flash mapping. In practice, the IO-APIC MMIO range is
1659      * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1660      * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to
1661      * 16MiB in size.
1662      */
1663     if (value > 16 * MiB) {
1664         error_setg(errp,
1665                    "User specified max allowed firmware size %" PRIu64 " is "
1666                    "greater than 16MiB. If combined firmware size exceeds "
1667                    "16MiB the system may not boot, or experience intermittent"
1668                    "stability issues.",
1669                    value);
1670         return;
1671     }
1672 
1673     pcms->max_fw_size = value;
1674 }
1675 
1676 
1677 static void pc_machine_initfn(Object *obj)
1678 {
1679     PCMachineState *pcms = PC_MACHINE(obj);
1680     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1681 
1682 #ifdef CONFIG_VMPORT
1683     pcms->vmport = ON_OFF_AUTO_AUTO;
1684 #else
1685     pcms->vmport = ON_OFF_AUTO_OFF;
1686 #endif /* CONFIG_VMPORT */
1687     pcms->max_ram_below_4g = 0; /* use default */
1688     pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type;
1689     pcms->south_bridge = pcmc->default_south_bridge;
1690 
1691     /* acpi build is enabled by default if machine supports it */
1692     pcms->acpi_build_enabled = pcmc->has_acpi_build;
1693     pcms->smbus_enabled = true;
1694     pcms->sata_enabled = true;
1695     pcms->i8042_enabled = true;
1696     pcms->max_fw_size = 8 * MiB;
1697 #ifdef CONFIG_HPET
1698     pcms->hpet_enabled = true;
1699 #endif
1700     pcms->fd_bootchk = true;
1701     pcms->default_bus_bypass_iommu = false;
1702 
1703     pc_system_flash_create(pcms);
1704     pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1705     object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1706                               OBJECT(pcms->pcspk), "audiodev");
1707     if (pcmc->pci_enabled) {
1708         cxl_machine_init(obj, &pcms->cxl_devices_state);
1709     }
1710 
1711     pcms->machine_done.notify = pc_machine_done;
1712     qemu_add_machine_init_done_notifier(&pcms->machine_done);
1713 }
1714 
1715 static void pc_machine_reset(MachineState *machine, ResetType type)
1716 {
1717     CPUState *cs;
1718     X86CPU *cpu;
1719 
1720     qemu_devices_reset(type);
1721 
1722     /* Reset APIC after devices have been reset to cancel
1723      * any changes that qemu_devices_reset() might have done.
1724      */
1725     CPU_FOREACH(cs) {
1726         cpu = X86_CPU(cs);
1727 
1728         x86_cpu_after_reset(cpu);
1729     }
1730 }
1731 
1732 static void pc_machine_wakeup(MachineState *machine)
1733 {
1734     cpu_synchronize_all_states();
1735     pc_machine_reset(machine, RESET_TYPE_WAKEUP);
1736     cpu_synchronize_all_post_reset();
1737 }
1738 
1739 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1740 {
1741     X86IOMMUState *iommu = x86_iommu_get_default();
1742     IntelIOMMUState *intel_iommu;
1743 
1744     if (iommu &&
1745         object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1746         object_dynamic_cast((Object *)dev, "vfio-pci")) {
1747         intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1748         if (!intel_iommu->caching_mode) {
1749             error_setg(errp, "Device assignment is not allowed without "
1750                        "enabling caching-mode=on for Intel IOMMU.");
1751             return false;
1752         }
1753     }
1754 
1755     return true;
1756 }
1757 
1758 static void pc_machine_class_init(ObjectClass *oc, void *data)
1759 {
1760     MachineClass *mc = MACHINE_CLASS(oc);
1761     X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
1762     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1763     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1764 
1765     pcmc->pci_enabled = true;
1766     pcmc->has_acpi_build = true;
1767     pcmc->smbios_defaults = true;
1768     pcmc->gigabyte_align = true;
1769     pcmc->has_reserved_memory = true;
1770     pcmc->enforce_amd_1tb_hole = true;
1771     pcmc->isa_bios_alias = true;
1772     pcmc->pvh_enabled = true;
1773     pcmc->kvmclock_create_always = true;
1774     x86mc->apic_xrupt_override = true;
1775     assert(!mc->get_hotplug_handler);
1776     mc->get_hotplug_handler = pc_get_hotplug_handler;
1777     mc->hotplug_allowed = pc_hotplug_allowed;
1778     mc->auto_enable_numa_with_memhp = true;
1779     mc->auto_enable_numa_with_memdev = true;
1780     mc->has_hotpluggable_cpus = true;
1781     mc->default_boot_order = "cad";
1782     mc->block_default_type = IF_IDE;
1783     mc->max_cpus = 255;
1784     mc->reset = pc_machine_reset;
1785     mc->wakeup = pc_machine_wakeup;
1786     hc->pre_plug = pc_machine_device_pre_plug_cb;
1787     hc->plug = pc_machine_device_plug_cb;
1788     hc->unplug_request = pc_machine_device_unplug_request_cb;
1789     hc->unplug = pc_machine_device_unplug_cb;
1790     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1791     mc->nvdimm_supported = true;
1792     mc->smp_props.dies_supported = true;
1793     mc->smp_props.modules_supported = true;
1794     mc->default_ram_id = "pc.ram";
1795     pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;
1796 
1797     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1798         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1799         NULL, NULL);
1800     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1801         "Maximum ram below the 4G boundary (32bit boundary)");
1802 
1803     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1804         pc_machine_get_vmport, pc_machine_set_vmport,
1805         NULL, NULL);
1806     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1807         "Enable vmport (pc & q35)");
1808 
1809     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1810         pc_machine_get_smbus, pc_machine_set_smbus);
1811     object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1812         "Enable/disable system management bus");
1813 
1814     object_class_property_add_bool(oc, PC_MACHINE_SATA,
1815         pc_machine_get_sata, pc_machine_set_sata);
1816     object_class_property_set_description(oc, PC_MACHINE_SATA,
1817         "Enable/disable Serial ATA bus");
1818 
1819     object_class_property_add_bool(oc, "hpet",
1820         pc_machine_get_hpet, pc_machine_set_hpet);
1821     object_class_property_set_description(oc, "hpet",
1822         "Enable/disable high precision event timer emulation");
1823 
1824     object_class_property_add_bool(oc, PC_MACHINE_I8042,
1825         pc_machine_get_i8042, pc_machine_set_i8042);
1826     object_class_property_set_description(oc, PC_MACHINE_I8042,
1827         "Enable/disable Intel 8042 PS/2 controller emulation");
1828 
1829     object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1830         pc_machine_get_default_bus_bypass_iommu,
1831         pc_machine_set_default_bus_bypass_iommu);
1832 
1833     object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1834         pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1835         NULL, NULL);
1836     object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1837         "Maximum combined firmware size");
1838 
1839     object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1840         pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1841         NULL, NULL);
1842     object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1843         "SMBIOS Entry Point type [32, 64]");
1844 
1845     object_class_property_add_bool(oc, "fd-bootchk",
1846         pc_machine_get_fd_bootchk,
1847         pc_machine_set_fd_bootchk);
1848 }
1849 
1850 static const TypeInfo pc_machine_info = {
1851     .name = TYPE_PC_MACHINE,
1852     .parent = TYPE_X86_MACHINE,
1853     .abstract = true,
1854     .instance_size = sizeof(PCMachineState),
1855     .instance_init = pc_machine_initfn,
1856     .class_size = sizeof(PCMachineClass),
1857     .class_init = pc_machine_class_init,
1858     .interfaces = (InterfaceInfo[]) {
1859          { TYPE_HOTPLUG_HANDLER },
1860          { }
1861     },
1862 };
1863 
1864 static void pc_machine_register_types(void)
1865 {
1866     type_register_static(&pc_machine_info);
1867 }
1868 
1869 type_init(pc_machine_register_types)
1870