1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/block/fdc.h" 29 #include "hw/ide.h" 30 #include "hw/pci/pci.h" 31 #include "monitor/monitor.h" 32 #include "hw/nvram/fw_cfg.h" 33 #include "hw/timer/hpet.h" 34 #include "hw/i386/smbios.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "multiboot.h" 38 #include "hw/timer/mc146818rtc.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/audio/pcspk.h" 41 #include "hw/pci/msi.h" 42 #include "hw/sysbus.h" 43 #include "sysemu/sysemu.h" 44 #include "sysemu/kvm.h" 45 #include "kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "sysemu/blockdev.h" 48 #include "hw/block/block.h" 49 #include "ui/qemu-spice.h" 50 #include "exec/memory.h" 51 #include "exec/address-spaces.h" 52 #include "sysemu/arch_init.h" 53 #include "qemu/bitmap.h" 54 #include "qemu/config-file.h" 55 #include "hw/acpi/acpi.h" 56 #include "hw/acpi/cpu_hotplug.h" 57 #include "hw/cpu/icc_bus.h" 58 #include "hw/boards.h" 59 #include "hw/pci/pci_host.h" 60 #include "acpi-build.h" 61 #include "hw/mem/pc-dimm.h" 62 #include "trace.h" 63 #include "qapi/visitor.h" 64 65 /* debug PC/ISA interrupts */ 66 //#define DEBUG_IRQ 67 68 #ifdef DEBUG_IRQ 69 #define DPRINTF(fmt, ...) \ 70 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 71 #else 72 #define DPRINTF(fmt, ...) 73 #endif 74 75 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */ 76 unsigned acpi_data_size = 0x20000; 77 void pc_set_legacy_acpi_data_size(void) 78 { 79 acpi_data_size = 0x10000; 80 } 81 82 #define BIOS_CFG_IOPORT 0x510 83 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 84 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 85 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 86 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 87 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 88 89 #define E820_NR_ENTRIES 16 90 91 struct e820_entry { 92 uint64_t address; 93 uint64_t length; 94 uint32_t type; 95 } QEMU_PACKED __attribute((__aligned__(4))); 96 97 struct e820_table { 98 uint32_t count; 99 struct e820_entry entry[E820_NR_ENTRIES]; 100 } QEMU_PACKED __attribute((__aligned__(4))); 101 102 static struct e820_table e820_reserve; 103 static struct e820_entry *e820_table; 104 static unsigned e820_entries; 105 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 106 107 void gsi_handler(void *opaque, int n, int level) 108 { 109 GSIState *s = opaque; 110 111 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 112 if (n < ISA_NUM_IRQS) { 113 qemu_set_irq(s->i8259_irq[n], level); 114 } 115 qemu_set_irq(s->ioapic_irq[n], level); 116 } 117 118 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 119 unsigned size) 120 { 121 } 122 123 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 124 { 125 return 0xffffffffffffffffULL; 126 } 127 128 /* MSDOS compatibility mode FPU exception support */ 129 static qemu_irq ferr_irq; 130 131 void pc_register_ferr_irq(qemu_irq irq) 132 { 133 ferr_irq = irq; 134 } 135 136 /* XXX: add IGNNE support */ 137 void cpu_set_ferr(CPUX86State *s) 138 { 139 qemu_irq_raise(ferr_irq); 140 } 141 142 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 143 unsigned size) 144 { 145 qemu_irq_lower(ferr_irq); 146 } 147 148 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 149 { 150 return 0xffffffffffffffffULL; 151 } 152 153 /* TSC handling */ 154 uint64_t cpu_get_tsc(CPUX86State *env) 155 { 156 return cpu_get_ticks(); 157 } 158 159 /* SMM support */ 160 161 static cpu_set_smm_t smm_set; 162 static void *smm_arg; 163 164 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 165 { 166 assert(smm_set == NULL); 167 assert(smm_arg == NULL); 168 smm_set = callback; 169 smm_arg = arg; 170 } 171 172 void cpu_smm_update(CPUX86State *env) 173 { 174 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 175 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 176 } 177 } 178 179 180 /* IRQ handling */ 181 int cpu_get_pic_interrupt(CPUX86State *env) 182 { 183 X86CPU *cpu = x86_env_get_cpu(env); 184 int intno; 185 186 intno = apic_get_interrupt(cpu->apic_state); 187 if (intno >= 0) { 188 return intno; 189 } 190 /* read the irq from the PIC */ 191 if (!apic_accept_pic_intr(cpu->apic_state)) { 192 return -1; 193 } 194 195 intno = pic_read_irq(isa_pic); 196 return intno; 197 } 198 199 static void pic_irq_request(void *opaque, int irq, int level) 200 { 201 CPUState *cs = first_cpu; 202 X86CPU *cpu = X86_CPU(cs); 203 204 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 205 if (cpu->apic_state) { 206 CPU_FOREACH(cs) { 207 cpu = X86_CPU(cs); 208 if (apic_accept_pic_intr(cpu->apic_state)) { 209 apic_deliver_pic_intr(cpu->apic_state, level); 210 } 211 } 212 } else { 213 if (level) { 214 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 215 } else { 216 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 217 } 218 } 219 } 220 221 /* PC cmos mappings */ 222 223 #define REG_EQUIPMENT_BYTE 0x14 224 225 static int cmos_get_fd_drive_type(FDriveType fd0) 226 { 227 int val; 228 229 switch (fd0) { 230 case FDRIVE_DRV_144: 231 /* 1.44 Mb 3"5 drive */ 232 val = 4; 233 break; 234 case FDRIVE_DRV_288: 235 /* 2.88 Mb 3"5 drive */ 236 val = 5; 237 break; 238 case FDRIVE_DRV_120: 239 /* 1.2 Mb 5"5 drive */ 240 val = 2; 241 break; 242 case FDRIVE_DRV_NONE: 243 default: 244 val = 0; 245 break; 246 } 247 return val; 248 } 249 250 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 251 int16_t cylinders, int8_t heads, int8_t sectors) 252 { 253 rtc_set_memory(s, type_ofs, 47); 254 rtc_set_memory(s, info_ofs, cylinders); 255 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 256 rtc_set_memory(s, info_ofs + 2, heads); 257 rtc_set_memory(s, info_ofs + 3, 0xff); 258 rtc_set_memory(s, info_ofs + 4, 0xff); 259 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 260 rtc_set_memory(s, info_ofs + 6, cylinders); 261 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 262 rtc_set_memory(s, info_ofs + 8, sectors); 263 } 264 265 /* convert boot_device letter to something recognizable by the bios */ 266 static int boot_device2nibble(char boot_device) 267 { 268 switch(boot_device) { 269 case 'a': 270 case 'b': 271 return 0x01; /* floppy boot */ 272 case 'c': 273 return 0x02; /* hard drive boot */ 274 case 'd': 275 return 0x03; /* CD-ROM boot */ 276 case 'n': 277 return 0x04; /* Network boot */ 278 } 279 return 0; 280 } 281 282 static int set_boot_dev(ISADevice *s, const char *boot_device) 283 { 284 #define PC_MAX_BOOT_DEVICES 3 285 int nbds, bds[3] = { 0, }; 286 int i; 287 288 nbds = strlen(boot_device); 289 if (nbds > PC_MAX_BOOT_DEVICES) { 290 error_report("Too many boot devices for PC"); 291 return(1); 292 } 293 for (i = 0; i < nbds; i++) { 294 bds[i] = boot_device2nibble(boot_device[i]); 295 if (bds[i] == 0) { 296 error_report("Invalid boot device for PC: '%c'", 297 boot_device[i]); 298 return(1); 299 } 300 } 301 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 302 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 303 return(0); 304 } 305 306 static int pc_boot_set(void *opaque, const char *boot_device) 307 { 308 return set_boot_dev(opaque, boot_device); 309 } 310 311 typedef struct pc_cmos_init_late_arg { 312 ISADevice *rtc_state; 313 BusState *idebus[2]; 314 } pc_cmos_init_late_arg; 315 316 static void pc_cmos_init_late(void *opaque) 317 { 318 pc_cmos_init_late_arg *arg = opaque; 319 ISADevice *s = arg->rtc_state; 320 int16_t cylinders; 321 int8_t heads, sectors; 322 int val; 323 int i, trans; 324 325 val = 0; 326 if (ide_get_geometry(arg->idebus[0], 0, 327 &cylinders, &heads, §ors) >= 0) { 328 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 329 val |= 0xf0; 330 } 331 if (ide_get_geometry(arg->idebus[0], 1, 332 &cylinders, &heads, §ors) >= 0) { 333 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 334 val |= 0x0f; 335 } 336 rtc_set_memory(s, 0x12, val); 337 338 val = 0; 339 for (i = 0; i < 4; i++) { 340 /* NOTE: ide_get_geometry() returns the physical 341 geometry. It is always such that: 1 <= sects <= 63, 1 342 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 343 geometry can be different if a translation is done. */ 344 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 345 &cylinders, &heads, §ors) >= 0) { 346 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 347 assert((trans & ~3) == 0); 348 val |= trans << (i * 2); 349 } 350 } 351 rtc_set_memory(s, 0x39, val); 352 353 qemu_unregister_reset(pc_cmos_init_late, opaque); 354 } 355 356 typedef struct RTCCPUHotplugArg { 357 Notifier cpu_added_notifier; 358 ISADevice *rtc_state; 359 } RTCCPUHotplugArg; 360 361 static void rtc_notify_cpu_added(Notifier *notifier, void *data) 362 { 363 RTCCPUHotplugArg *arg = container_of(notifier, RTCCPUHotplugArg, 364 cpu_added_notifier); 365 ISADevice *s = arg->rtc_state; 366 367 /* increment the number of CPUs */ 368 rtc_set_memory(s, 0x5f, rtc_get_memory(s, 0x5f) + 1); 369 } 370 371 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 372 const char *boot_device, 373 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 374 ISADevice *s) 375 { 376 int val, nb, i; 377 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 378 static pc_cmos_init_late_arg arg; 379 static RTCCPUHotplugArg cpu_hotplug_cb; 380 381 /* various important CMOS locations needed by PC/Bochs bios */ 382 383 /* memory size */ 384 /* base memory (first MiB) */ 385 val = MIN(ram_size / 1024, 640); 386 rtc_set_memory(s, 0x15, val); 387 rtc_set_memory(s, 0x16, val >> 8); 388 /* extended memory (next 64MiB) */ 389 if (ram_size > 1024 * 1024) { 390 val = (ram_size - 1024 * 1024) / 1024; 391 } else { 392 val = 0; 393 } 394 if (val > 65535) 395 val = 65535; 396 rtc_set_memory(s, 0x17, val); 397 rtc_set_memory(s, 0x18, val >> 8); 398 rtc_set_memory(s, 0x30, val); 399 rtc_set_memory(s, 0x31, val >> 8); 400 /* memory between 16MiB and 4GiB */ 401 if (ram_size > 16 * 1024 * 1024) { 402 val = (ram_size - 16 * 1024 * 1024) / 65536; 403 } else { 404 val = 0; 405 } 406 if (val > 65535) 407 val = 65535; 408 rtc_set_memory(s, 0x34, val); 409 rtc_set_memory(s, 0x35, val >> 8); 410 /* memory above 4GiB */ 411 val = above_4g_mem_size / 65536; 412 rtc_set_memory(s, 0x5b, val); 413 rtc_set_memory(s, 0x5c, val >> 8); 414 rtc_set_memory(s, 0x5d, val >> 16); 415 416 /* set the number of CPU */ 417 rtc_set_memory(s, 0x5f, smp_cpus - 1); 418 /* init CPU hotplug notifier */ 419 cpu_hotplug_cb.rtc_state = s; 420 cpu_hotplug_cb.cpu_added_notifier.notify = rtc_notify_cpu_added; 421 qemu_register_cpu_added_notifier(&cpu_hotplug_cb.cpu_added_notifier); 422 423 if (set_boot_dev(s, boot_device)) { 424 exit(1); 425 } 426 427 /* floppy type */ 428 if (floppy) { 429 for (i = 0; i < 2; i++) { 430 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 431 } 432 } 433 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 434 cmos_get_fd_drive_type(fd_type[1]); 435 rtc_set_memory(s, 0x10, val); 436 437 val = 0; 438 nb = 0; 439 if (fd_type[0] < FDRIVE_DRV_NONE) { 440 nb++; 441 } 442 if (fd_type[1] < FDRIVE_DRV_NONE) { 443 nb++; 444 } 445 switch (nb) { 446 case 0: 447 break; 448 case 1: 449 val |= 0x01; /* 1 drive, ready for boot */ 450 break; 451 case 2: 452 val |= 0x41; /* 2 drives, ready for boot */ 453 break; 454 } 455 val |= 0x02; /* FPU is there */ 456 val |= 0x04; /* PS/2 mouse installed */ 457 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 458 459 /* hard drives */ 460 arg.rtc_state = s; 461 arg.idebus[0] = idebus0; 462 arg.idebus[1] = idebus1; 463 qemu_register_reset(pc_cmos_init_late, &arg); 464 } 465 466 #define TYPE_PORT92 "port92" 467 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 468 469 /* port 92 stuff: could be split off */ 470 typedef struct Port92State { 471 ISADevice parent_obj; 472 473 MemoryRegion io; 474 uint8_t outport; 475 qemu_irq *a20_out; 476 } Port92State; 477 478 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 479 unsigned size) 480 { 481 Port92State *s = opaque; 482 int oldval = s->outport; 483 484 DPRINTF("port92: write 0x%02x\n", val); 485 s->outport = val; 486 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 487 if ((val & 1) && !(oldval & 1)) { 488 qemu_system_reset_request(); 489 } 490 } 491 492 static uint64_t port92_read(void *opaque, hwaddr addr, 493 unsigned size) 494 { 495 Port92State *s = opaque; 496 uint32_t ret; 497 498 ret = s->outport; 499 DPRINTF("port92: read 0x%02x\n", ret); 500 return ret; 501 } 502 503 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 504 { 505 Port92State *s = PORT92(dev); 506 507 s->a20_out = a20_out; 508 } 509 510 static const VMStateDescription vmstate_port92_isa = { 511 .name = "port92", 512 .version_id = 1, 513 .minimum_version_id = 1, 514 .fields = (VMStateField[]) { 515 VMSTATE_UINT8(outport, Port92State), 516 VMSTATE_END_OF_LIST() 517 } 518 }; 519 520 static void port92_reset(DeviceState *d) 521 { 522 Port92State *s = PORT92(d); 523 524 s->outport &= ~1; 525 } 526 527 static const MemoryRegionOps port92_ops = { 528 .read = port92_read, 529 .write = port92_write, 530 .impl = { 531 .min_access_size = 1, 532 .max_access_size = 1, 533 }, 534 .endianness = DEVICE_LITTLE_ENDIAN, 535 }; 536 537 static void port92_initfn(Object *obj) 538 { 539 Port92State *s = PORT92(obj); 540 541 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 542 543 s->outport = 0; 544 } 545 546 static void port92_realizefn(DeviceState *dev, Error **errp) 547 { 548 ISADevice *isadev = ISA_DEVICE(dev); 549 Port92State *s = PORT92(dev); 550 551 isa_register_ioport(isadev, &s->io, 0x92); 552 } 553 554 static void port92_class_initfn(ObjectClass *klass, void *data) 555 { 556 DeviceClass *dc = DEVICE_CLASS(klass); 557 558 dc->realize = port92_realizefn; 559 dc->reset = port92_reset; 560 dc->vmsd = &vmstate_port92_isa; 561 /* 562 * Reason: unlike ordinary ISA devices, this one needs additional 563 * wiring: its A20 output line needs to be wired up by 564 * port92_init(). 565 */ 566 dc->cannot_instantiate_with_device_add_yet = true; 567 } 568 569 static const TypeInfo port92_info = { 570 .name = TYPE_PORT92, 571 .parent = TYPE_ISA_DEVICE, 572 .instance_size = sizeof(Port92State), 573 .instance_init = port92_initfn, 574 .class_init = port92_class_initfn, 575 }; 576 577 static void port92_register_types(void) 578 { 579 type_register_static(&port92_info); 580 } 581 582 type_init(port92_register_types) 583 584 static void handle_a20_line_change(void *opaque, int irq, int level) 585 { 586 X86CPU *cpu = opaque; 587 588 /* XXX: send to all CPUs ? */ 589 /* XXX: add logic to handle multiple A20 line sources */ 590 x86_cpu_set_a20(cpu, level); 591 } 592 593 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 594 { 595 int index = le32_to_cpu(e820_reserve.count); 596 struct e820_entry *entry; 597 598 if (type != E820_RAM) { 599 /* old FW_CFG_E820_TABLE entry -- reservations only */ 600 if (index >= E820_NR_ENTRIES) { 601 return -EBUSY; 602 } 603 entry = &e820_reserve.entry[index++]; 604 605 entry->address = cpu_to_le64(address); 606 entry->length = cpu_to_le64(length); 607 entry->type = cpu_to_le32(type); 608 609 e820_reserve.count = cpu_to_le32(index); 610 } 611 612 /* new "etc/e820" file -- include ram too */ 613 e820_table = g_realloc(e820_table, 614 sizeof(struct e820_entry) * (e820_entries+1)); 615 e820_table[e820_entries].address = cpu_to_le64(address); 616 e820_table[e820_entries].length = cpu_to_le64(length); 617 e820_table[e820_entries].type = cpu_to_le32(type); 618 e820_entries++; 619 620 return e820_entries; 621 } 622 623 int e820_get_num_entries(void) 624 { 625 return e820_entries; 626 } 627 628 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 629 { 630 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 631 *address = le64_to_cpu(e820_table[idx].address); 632 *length = le64_to_cpu(e820_table[idx].length); 633 return true; 634 } 635 return false; 636 } 637 638 /* Calculates the limit to CPU APIC ID values 639 * 640 * This function returns the limit for the APIC ID value, so that all 641 * CPU APIC IDs are < pc_apic_id_limit(). 642 * 643 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 644 */ 645 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 646 { 647 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 648 } 649 650 static FWCfgState *bochs_bios_init(void) 651 { 652 FWCfgState *fw_cfg; 653 uint8_t *smbios_tables, *smbios_anchor; 654 size_t smbios_tables_len, smbios_anchor_len; 655 uint64_t *numa_fw_cfg; 656 int i, j; 657 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 658 659 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 660 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 661 * 662 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 663 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 664 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 665 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 666 * may see". 667 * 668 * So, this means we must not use max_cpus, here, but the maximum possible 669 * APIC ID value, plus one. 670 * 671 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 672 * the APIC ID, not the "CPU index" 673 */ 674 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 675 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 676 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 677 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 678 acpi_tables, acpi_tables_len); 679 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 680 681 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 682 if (smbios_tables) { 683 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 684 smbios_tables, smbios_tables_len); 685 } 686 687 smbios_get_tables(&smbios_tables, &smbios_tables_len, 688 &smbios_anchor, &smbios_anchor_len); 689 if (smbios_anchor) { 690 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 691 smbios_tables, smbios_tables_len); 692 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 693 smbios_anchor, smbios_anchor_len); 694 } 695 696 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 697 &e820_reserve, sizeof(e820_reserve)); 698 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 699 sizeof(struct e820_entry) * e820_entries); 700 701 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 702 /* allocate memory for the NUMA channel: one (64bit) word for the number 703 * of nodes, one word for each VCPU->node and one word for each node to 704 * hold the amount of memory. 705 */ 706 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 707 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 708 for (i = 0; i < max_cpus; i++) { 709 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 710 assert(apic_id < apic_id_limit); 711 for (j = 0; j < nb_numa_nodes; j++) { 712 if (test_bit(i, numa_info[j].node_cpu)) { 713 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 714 break; 715 } 716 } 717 } 718 for (i = 0; i < nb_numa_nodes; i++) { 719 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 720 } 721 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 722 (1 + apic_id_limit + nb_numa_nodes) * 723 sizeof(*numa_fw_cfg)); 724 725 return fw_cfg; 726 } 727 728 static long get_file_size(FILE *f) 729 { 730 long where, size; 731 732 /* XXX: on Unix systems, using fstat() probably makes more sense */ 733 734 where = ftell(f); 735 fseek(f, 0, SEEK_END); 736 size = ftell(f); 737 fseek(f, where, SEEK_SET); 738 739 return size; 740 } 741 742 static void load_linux(FWCfgState *fw_cfg, 743 const char *kernel_filename, 744 const char *initrd_filename, 745 const char *kernel_cmdline, 746 hwaddr max_ram_size) 747 { 748 uint16_t protocol; 749 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 750 uint32_t initrd_max; 751 uint8_t header[8192], *setup, *kernel, *initrd_data; 752 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 753 FILE *f; 754 char *vmode; 755 756 /* Align to 16 bytes as a paranoia measure */ 757 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 758 759 /* load the kernel header */ 760 f = fopen(kernel_filename, "rb"); 761 if (!f || !(kernel_size = get_file_size(f)) || 762 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 763 MIN(ARRAY_SIZE(header), kernel_size)) { 764 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 765 kernel_filename, strerror(errno)); 766 exit(1); 767 } 768 769 /* kernel protocol version */ 770 #if 0 771 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 772 #endif 773 if (ldl_p(header+0x202) == 0x53726448) { 774 protocol = lduw_p(header+0x206); 775 } else { 776 /* This looks like a multiboot kernel. If it is, let's stop 777 treating it like a Linux kernel. */ 778 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 779 kernel_cmdline, kernel_size, header)) { 780 return; 781 } 782 protocol = 0; 783 } 784 785 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 786 /* Low kernel */ 787 real_addr = 0x90000; 788 cmdline_addr = 0x9a000 - cmdline_size; 789 prot_addr = 0x10000; 790 } else if (protocol < 0x202) { 791 /* High but ancient kernel */ 792 real_addr = 0x90000; 793 cmdline_addr = 0x9a000 - cmdline_size; 794 prot_addr = 0x100000; 795 } else { 796 /* High and recent kernel */ 797 real_addr = 0x10000; 798 cmdline_addr = 0x20000; 799 prot_addr = 0x100000; 800 } 801 802 #if 0 803 fprintf(stderr, 804 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 805 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 806 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 807 real_addr, 808 cmdline_addr, 809 prot_addr); 810 #endif 811 812 /* highest address for loading the initrd */ 813 if (protocol >= 0x203) { 814 initrd_max = ldl_p(header+0x22c); 815 } else { 816 initrd_max = 0x37ffffff; 817 } 818 819 if (initrd_max >= max_ram_size - acpi_data_size) { 820 initrd_max = max_ram_size - acpi_data_size - 1; 821 } 822 823 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 824 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 825 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 826 827 if (protocol >= 0x202) { 828 stl_p(header+0x228, cmdline_addr); 829 } else { 830 stw_p(header+0x20, 0xA33F); 831 stw_p(header+0x22, cmdline_addr-real_addr); 832 } 833 834 /* handle vga= parameter */ 835 vmode = strstr(kernel_cmdline, "vga="); 836 if (vmode) { 837 unsigned int video_mode; 838 /* skip "vga=" */ 839 vmode += 4; 840 if (!strncmp(vmode, "normal", 6)) { 841 video_mode = 0xffff; 842 } else if (!strncmp(vmode, "ext", 3)) { 843 video_mode = 0xfffe; 844 } else if (!strncmp(vmode, "ask", 3)) { 845 video_mode = 0xfffd; 846 } else { 847 video_mode = strtol(vmode, NULL, 0); 848 } 849 stw_p(header+0x1fa, video_mode); 850 } 851 852 /* loader type */ 853 /* High nybble = B reserved for QEMU; low nybble is revision number. 854 If this code is substantially changed, you may want to consider 855 incrementing the revision. */ 856 if (protocol >= 0x200) { 857 header[0x210] = 0xB0; 858 } 859 /* heap */ 860 if (protocol >= 0x201) { 861 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 862 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 863 } 864 865 /* load initrd */ 866 if (initrd_filename) { 867 if (protocol < 0x200) { 868 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 869 exit(1); 870 } 871 872 initrd_size = get_image_size(initrd_filename); 873 if (initrd_size < 0) { 874 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 875 initrd_filename, strerror(errno)); 876 exit(1); 877 } 878 879 initrd_addr = (initrd_max-initrd_size) & ~4095; 880 881 initrd_data = g_malloc(initrd_size); 882 load_image(initrd_filename, initrd_data); 883 884 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 885 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 886 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 887 888 stl_p(header+0x218, initrd_addr); 889 stl_p(header+0x21c, initrd_size); 890 } 891 892 /* load kernel and setup */ 893 setup_size = header[0x1f1]; 894 if (setup_size == 0) { 895 setup_size = 4; 896 } 897 setup_size = (setup_size+1)*512; 898 kernel_size -= setup_size; 899 900 setup = g_malloc(setup_size); 901 kernel = g_malloc(kernel_size); 902 fseek(f, 0, SEEK_SET); 903 if (fread(setup, 1, setup_size, f) != setup_size) { 904 fprintf(stderr, "fread() failed\n"); 905 exit(1); 906 } 907 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 908 fprintf(stderr, "fread() failed\n"); 909 exit(1); 910 } 911 fclose(f); 912 memcpy(setup, header, MIN(sizeof(header), setup_size)); 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 916 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 917 918 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 919 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 920 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 921 922 option_rom[nb_option_roms].name = "linuxboot.bin"; 923 option_rom[nb_option_roms].bootindex = 0; 924 nb_option_roms++; 925 } 926 927 #define NE2000_NB_MAX 6 928 929 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 930 0x280, 0x380 }; 931 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 932 933 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 934 { 935 static int nb_ne2k = 0; 936 937 if (nb_ne2k == NE2000_NB_MAX) 938 return; 939 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 940 ne2000_irq[nb_ne2k], nd); 941 nb_ne2k++; 942 } 943 944 DeviceState *cpu_get_current_apic(void) 945 { 946 if (current_cpu) { 947 X86CPU *cpu = X86_CPU(current_cpu); 948 return cpu->apic_state; 949 } else { 950 return NULL; 951 } 952 } 953 954 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 955 { 956 X86CPU *cpu = opaque; 957 958 if (level) { 959 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 960 } 961 } 962 963 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 964 DeviceState *icc_bridge, Error **errp) 965 { 966 X86CPU *cpu; 967 Error *local_err = NULL; 968 969 cpu = cpu_x86_create(cpu_model, icc_bridge, &local_err); 970 if (local_err != NULL) { 971 error_propagate(errp, local_err); 972 return NULL; 973 } 974 975 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 976 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 977 978 if (local_err) { 979 error_propagate(errp, local_err); 980 object_unref(OBJECT(cpu)); 981 cpu = NULL; 982 } 983 return cpu; 984 } 985 986 static const char *current_cpu_model; 987 988 void pc_hot_add_cpu(const int64_t id, Error **errp) 989 { 990 DeviceState *icc_bridge; 991 int64_t apic_id = x86_cpu_apic_id_from_index(id); 992 993 if (id < 0) { 994 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 995 return; 996 } 997 998 if (cpu_exists(apic_id)) { 999 error_setg(errp, "Unable to add CPU: %" PRIi64 1000 ", it already exists", id); 1001 return; 1002 } 1003 1004 if (id >= max_cpus) { 1005 error_setg(errp, "Unable to add CPU: %" PRIi64 1006 ", max allowed: %d", id, max_cpus - 1); 1007 return; 1008 } 1009 1010 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1011 error_setg(errp, "Unable to add CPU: %" PRIi64 1012 ", resulting APIC ID (%" PRIi64 ") is too large", 1013 id, apic_id); 1014 return; 1015 } 1016 1017 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1018 TYPE_ICC_BRIDGE, NULL)); 1019 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1020 } 1021 1022 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1023 { 1024 int i; 1025 X86CPU *cpu = NULL; 1026 Error *error = NULL; 1027 unsigned long apic_id_limit; 1028 1029 /* init CPUs */ 1030 if (cpu_model == NULL) { 1031 #ifdef TARGET_X86_64 1032 cpu_model = "qemu64"; 1033 #else 1034 cpu_model = "qemu32"; 1035 #endif 1036 } 1037 current_cpu_model = cpu_model; 1038 1039 apic_id_limit = pc_apic_id_limit(max_cpus); 1040 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1041 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1042 apic_id_limit - 1); 1043 exit(1); 1044 } 1045 1046 for (i = 0; i < smp_cpus; i++) { 1047 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1048 icc_bridge, &error); 1049 if (error) { 1050 error_report("%s", error_get_pretty(error)); 1051 error_free(error); 1052 exit(1); 1053 } 1054 } 1055 1056 /* map APIC MMIO area if CPU has APIC */ 1057 if (cpu && cpu->apic_state) { 1058 /* XXX: what if the base changes? */ 1059 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1060 APIC_DEFAULT_ADDRESS, 0x1000); 1061 } 1062 1063 /* tell smbios about cpuid version and features */ 1064 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1065 } 1066 1067 /* pci-info ROM file. Little endian format */ 1068 typedef struct PcRomPciInfo { 1069 uint64_t w32_min; 1070 uint64_t w32_max; 1071 uint64_t w64_min; 1072 uint64_t w64_max; 1073 } PcRomPciInfo; 1074 1075 typedef struct PcGuestInfoState { 1076 PcGuestInfo info; 1077 Notifier machine_done; 1078 } PcGuestInfoState; 1079 1080 static 1081 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1082 { 1083 PcGuestInfoState *guest_info_state = container_of(notifier, 1084 PcGuestInfoState, 1085 machine_done); 1086 acpi_setup(&guest_info_state->info); 1087 } 1088 1089 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1090 ram_addr_t above_4g_mem_size) 1091 { 1092 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1093 PcGuestInfo *guest_info = &guest_info_state->info; 1094 int i, j; 1095 1096 guest_info->ram_size_below_4g = below_4g_mem_size; 1097 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1098 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1099 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1100 guest_info->numa_nodes = nb_numa_nodes; 1101 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1102 sizeof *guest_info->node_mem); 1103 for (i = 0; i < nb_numa_nodes; i++) { 1104 guest_info->node_mem[i] = numa_info[i].node_mem; 1105 } 1106 1107 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1108 sizeof *guest_info->node_cpu); 1109 1110 for (i = 0; i < max_cpus; i++) { 1111 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1112 assert(apic_id < guest_info->apic_id_limit); 1113 for (j = 0; j < nb_numa_nodes; j++) { 1114 if (test_bit(i, numa_info[j].node_cpu)) { 1115 guest_info->node_cpu[apic_id] = j; 1116 break; 1117 } 1118 } 1119 } 1120 1121 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1122 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1123 return guest_info; 1124 } 1125 1126 /* setup pci memory address space mapping into system address space */ 1127 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1128 MemoryRegion *pci_address_space) 1129 { 1130 /* Set to lower priority than RAM */ 1131 memory_region_add_subregion_overlap(system_memory, 0x0, 1132 pci_address_space, -1); 1133 } 1134 1135 void pc_acpi_init(const char *default_dsdt) 1136 { 1137 char *filename; 1138 1139 if (acpi_tables != NULL) { 1140 /* manually set via -acpitable, leave it alone */ 1141 return; 1142 } 1143 1144 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1145 if (filename == NULL) { 1146 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1147 } else { 1148 char *arg; 1149 QemuOpts *opts; 1150 Error *err = NULL; 1151 1152 arg = g_strdup_printf("file=%s", filename); 1153 1154 /* creates a deep copy of "arg" */ 1155 opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0); 1156 g_assert(opts != NULL); 1157 1158 acpi_table_add_builtin(opts, &err); 1159 if (err) { 1160 error_report("WARNING: failed to load %s: %s", filename, 1161 error_get_pretty(err)); 1162 error_free(err); 1163 } 1164 g_free(arg); 1165 g_free(filename); 1166 } 1167 } 1168 1169 FWCfgState *xen_load_linux(const char *kernel_filename, 1170 const char *kernel_cmdline, 1171 const char *initrd_filename, 1172 ram_addr_t below_4g_mem_size, 1173 PcGuestInfo *guest_info) 1174 { 1175 int i; 1176 FWCfgState *fw_cfg; 1177 1178 assert(kernel_filename != NULL); 1179 1180 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); 1181 rom_set_fw(fw_cfg); 1182 1183 load_linux(fw_cfg, kernel_filename, initrd_filename, 1184 kernel_cmdline, below_4g_mem_size); 1185 for (i = 0; i < nb_option_roms; i++) { 1186 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1187 !strcmp(option_rom[i].name, "multiboot.bin")); 1188 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1189 } 1190 guest_info->fw_cfg = fw_cfg; 1191 return fw_cfg; 1192 } 1193 1194 FWCfgState *pc_memory_init(MachineState *machine, 1195 MemoryRegion *system_memory, 1196 ram_addr_t below_4g_mem_size, 1197 ram_addr_t above_4g_mem_size, 1198 MemoryRegion *rom_memory, 1199 MemoryRegion **ram_memory, 1200 PcGuestInfo *guest_info) 1201 { 1202 int linux_boot, i; 1203 MemoryRegion *ram, *option_rom_mr; 1204 MemoryRegion *ram_below_4g, *ram_above_4g; 1205 FWCfgState *fw_cfg; 1206 PCMachineState *pcms = PC_MACHINE(machine); 1207 1208 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1209 1210 linux_boot = (machine->kernel_filename != NULL); 1211 1212 /* Allocate RAM. We allocate it as a single memory region and use 1213 * aliases to address portions of it, mostly for backwards compatibility 1214 * with older qemus that used qemu_ram_alloc(). 1215 */ 1216 ram = g_malloc(sizeof(*ram)); 1217 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1218 machine->ram_size); 1219 *ram_memory = ram; 1220 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1221 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1222 0, below_4g_mem_size); 1223 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1224 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1225 if (above_4g_mem_size > 0) { 1226 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1227 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1228 below_4g_mem_size, above_4g_mem_size); 1229 memory_region_add_subregion(system_memory, 0x100000000ULL, 1230 ram_above_4g); 1231 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1232 } 1233 1234 if (!guest_info->has_reserved_memory && 1235 (machine->ram_slots || 1236 (machine->maxram_size > machine->ram_size))) { 1237 MachineClass *mc = MACHINE_GET_CLASS(machine); 1238 1239 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1240 mc->name); 1241 exit(EXIT_FAILURE); 1242 } 1243 1244 /* initialize hotplug memory address space */ 1245 if (guest_info->has_reserved_memory && 1246 (machine->ram_size < machine->maxram_size)) { 1247 ram_addr_t hotplug_mem_size = 1248 machine->maxram_size - machine->ram_size; 1249 1250 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1251 error_report("unsupported amount of memory slots: %"PRIu64, 1252 machine->ram_slots); 1253 exit(EXIT_FAILURE); 1254 } 1255 1256 pcms->hotplug_memory_base = 1257 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1258 1259 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1260 hotplug_mem_size) { 1261 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1262 machine->maxram_size); 1263 exit(EXIT_FAILURE); 1264 } 1265 1266 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1267 "hotplug-memory", hotplug_mem_size); 1268 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1269 &pcms->hotplug_memory); 1270 } 1271 1272 /* Initialize PC system firmware */ 1273 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1274 1275 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1276 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE); 1277 vmstate_register_ram_global(option_rom_mr); 1278 memory_region_add_subregion_overlap(rom_memory, 1279 PC_ROM_MIN_VGA, 1280 option_rom_mr, 1281 1); 1282 1283 fw_cfg = bochs_bios_init(); 1284 rom_set_fw(fw_cfg); 1285 1286 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1287 uint64_t *val = g_malloc(sizeof(*val)); 1288 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1289 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1290 } 1291 1292 if (linux_boot) { 1293 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1294 machine->kernel_cmdline, below_4g_mem_size); 1295 } 1296 1297 for (i = 0; i < nb_option_roms; i++) { 1298 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1299 } 1300 guest_info->fw_cfg = fw_cfg; 1301 return fw_cfg; 1302 } 1303 1304 qemu_irq *pc_allocate_cpu_irq(void) 1305 { 1306 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1307 } 1308 1309 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1310 { 1311 DeviceState *dev = NULL; 1312 1313 if (pci_bus) { 1314 PCIDevice *pcidev = pci_vga_init(pci_bus); 1315 dev = pcidev ? &pcidev->qdev : NULL; 1316 } else if (isa_bus) { 1317 ISADevice *isadev = isa_vga_init(isa_bus); 1318 dev = isadev ? DEVICE(isadev) : NULL; 1319 } 1320 return dev; 1321 } 1322 1323 static void cpu_request_exit(void *opaque, int irq, int level) 1324 { 1325 CPUState *cpu = current_cpu; 1326 1327 if (cpu && level) { 1328 cpu_exit(cpu); 1329 } 1330 } 1331 1332 static const MemoryRegionOps ioport80_io_ops = { 1333 .write = ioport80_write, 1334 .read = ioport80_read, 1335 .endianness = DEVICE_NATIVE_ENDIAN, 1336 .impl = { 1337 .min_access_size = 1, 1338 .max_access_size = 1, 1339 }, 1340 }; 1341 1342 static const MemoryRegionOps ioportF0_io_ops = { 1343 .write = ioportF0_write, 1344 .read = ioportF0_read, 1345 .endianness = DEVICE_NATIVE_ENDIAN, 1346 .impl = { 1347 .min_access_size = 1, 1348 .max_access_size = 1, 1349 }, 1350 }; 1351 1352 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1353 ISADevice **rtc_state, 1354 ISADevice **floppy, 1355 bool no_vmport, 1356 uint32 hpet_irqs) 1357 { 1358 int i; 1359 DriveInfo *fd[MAX_FD]; 1360 DeviceState *hpet = NULL; 1361 int pit_isa_irq = 0; 1362 qemu_irq pit_alt_irq = NULL; 1363 qemu_irq rtc_irq = NULL; 1364 qemu_irq *a20_line; 1365 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1366 qemu_irq *cpu_exit_irq; 1367 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1368 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1369 1370 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1371 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1372 1373 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1374 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1375 1376 /* 1377 * Check if an HPET shall be created. 1378 * 1379 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1380 * when the HPET wants to take over. Thus we have to disable the latter. 1381 */ 1382 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1383 /* In order to set property, here not using sysbus_try_create_simple */ 1384 hpet = qdev_try_create(NULL, TYPE_HPET); 1385 if (hpet) { 1386 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1387 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1388 * IRQ8 and IRQ2. 1389 */ 1390 uint8_t compat = object_property_get_int(OBJECT(hpet), 1391 HPET_INTCAP, NULL); 1392 if (!compat) { 1393 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1394 } 1395 qdev_init_nofail(hpet); 1396 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1397 1398 for (i = 0; i < GSI_NUM_PINS; i++) { 1399 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1400 } 1401 pit_isa_irq = -1; 1402 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1403 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1404 } 1405 } 1406 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1407 1408 qemu_register_boot_set(pc_boot_set, *rtc_state); 1409 1410 if (!xen_enabled()) { 1411 if (kvm_irqchip_in_kernel()) { 1412 pit = kvm_pit_init(isa_bus, 0x40); 1413 } else { 1414 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1415 } 1416 if (hpet) { 1417 /* connect PIT to output control line of the HPET */ 1418 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1419 } 1420 pcspk_init(isa_bus, pit); 1421 } 1422 1423 for(i = 0; i < MAX_SERIAL_PORTS; i++) { 1424 if (serial_hds[i]) { 1425 serial_isa_init(isa_bus, i, serial_hds[i]); 1426 } 1427 } 1428 1429 for(i = 0; i < MAX_PARALLEL_PORTS; i++) { 1430 if (parallel_hds[i]) { 1431 parallel_init(isa_bus, i, parallel_hds[i]); 1432 } 1433 } 1434 1435 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1436 i8042 = isa_create_simple(isa_bus, "i8042"); 1437 i8042_setup_a20_line(i8042, &a20_line[0]); 1438 if (!no_vmport) { 1439 vmport_init(isa_bus); 1440 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1441 } else { 1442 vmmouse = NULL; 1443 } 1444 if (vmmouse) { 1445 DeviceState *dev = DEVICE(vmmouse); 1446 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1447 qdev_init_nofail(dev); 1448 } 1449 port92 = isa_create_simple(isa_bus, "port92"); 1450 port92_init(port92, &a20_line[1]); 1451 1452 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1453 DMA_init(0, cpu_exit_irq); 1454 1455 for(i = 0; i < MAX_FD; i++) { 1456 fd[i] = drive_get(IF_FLOPPY, 0, i); 1457 } 1458 *floppy = fdctrl_init_isa(isa_bus, fd); 1459 } 1460 1461 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1462 { 1463 int i; 1464 1465 for (i = 0; i < nb_nics; i++) { 1466 NICInfo *nd = &nd_table[i]; 1467 1468 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1469 pc_init_ne2k_isa(isa_bus, nd); 1470 } else { 1471 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1472 } 1473 } 1474 } 1475 1476 void pc_pci_device_init(PCIBus *pci_bus) 1477 { 1478 int max_bus; 1479 int bus; 1480 1481 max_bus = drive_get_max_bus(IF_SCSI); 1482 for (bus = 0; bus <= max_bus; bus++) { 1483 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1484 } 1485 } 1486 1487 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1488 { 1489 DeviceState *dev; 1490 SysBusDevice *d; 1491 unsigned int i; 1492 1493 if (kvm_irqchip_in_kernel()) { 1494 dev = qdev_create(NULL, "kvm-ioapic"); 1495 } else { 1496 dev = qdev_create(NULL, "ioapic"); 1497 } 1498 if (parent_name) { 1499 object_property_add_child(object_resolve_path(parent_name, NULL), 1500 "ioapic", OBJECT(dev), NULL); 1501 } 1502 qdev_init_nofail(dev); 1503 d = SYS_BUS_DEVICE(dev); 1504 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1505 1506 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1507 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1508 } 1509 } 1510 1511 static void pc_generic_machine_class_init(ObjectClass *oc, void *data) 1512 { 1513 MachineClass *mc = MACHINE_CLASS(oc); 1514 QEMUMachine *qm = data; 1515 1516 mc->name = qm->name; 1517 mc->alias = qm->alias; 1518 mc->desc = qm->desc; 1519 mc->init = qm->init; 1520 mc->reset = qm->reset; 1521 mc->hot_add_cpu = qm->hot_add_cpu; 1522 mc->kvm_type = qm->kvm_type; 1523 mc->block_default_type = qm->block_default_type; 1524 mc->max_cpus = qm->max_cpus; 1525 mc->no_serial = qm->no_serial; 1526 mc->no_parallel = qm->no_parallel; 1527 mc->use_virtcon = qm->use_virtcon; 1528 mc->use_sclp = qm->use_sclp; 1529 mc->no_floppy = qm->no_floppy; 1530 mc->no_cdrom = qm->no_cdrom; 1531 mc->no_sdcard = qm->no_sdcard; 1532 mc->is_default = qm->is_default; 1533 mc->default_machine_opts = qm->default_machine_opts; 1534 mc->default_boot_order = qm->default_boot_order; 1535 mc->compat_props = qm->compat_props; 1536 mc->hw_version = qm->hw_version; 1537 } 1538 1539 void qemu_register_pc_machine(QEMUMachine *m) 1540 { 1541 char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); 1542 TypeInfo ti = { 1543 .name = name, 1544 .parent = TYPE_PC_MACHINE, 1545 .class_init = pc_generic_machine_class_init, 1546 .class_data = (void *)m, 1547 }; 1548 1549 type_register(&ti); 1550 g_free(name); 1551 } 1552 1553 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1554 DeviceState *dev, Error **errp) 1555 { 1556 int slot; 1557 HotplugHandlerClass *hhc; 1558 Error *local_err = NULL; 1559 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1560 MachineState *machine = MACHINE(hotplug_dev); 1561 PCDIMMDevice *dimm = PC_DIMM(dev); 1562 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1563 MemoryRegion *mr = ddc->get_memory_region(dimm); 1564 uint64_t addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 1565 &local_err); 1566 if (local_err) { 1567 goto out; 1568 } 1569 1570 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1571 memory_region_size(&pcms->hotplug_memory), 1572 !addr ? NULL : &addr, 1573 memory_region_size(mr), &local_err); 1574 if (local_err) { 1575 goto out; 1576 } 1577 1578 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1579 if (local_err) { 1580 goto out; 1581 } 1582 trace_mhp_pc_dimm_assigned_address(addr); 1583 1584 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1585 if (local_err) { 1586 goto out; 1587 } 1588 1589 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1590 machine->ram_slots, &local_err); 1591 if (local_err) { 1592 goto out; 1593 } 1594 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1595 if (local_err) { 1596 goto out; 1597 } 1598 trace_mhp_pc_dimm_assigned_slot(slot); 1599 1600 if (!pcms->acpi_dev) { 1601 error_setg(&local_err, 1602 "memory hotplug is not enabled: missing acpi device"); 1603 goto out; 1604 } 1605 1606 memory_region_add_subregion(&pcms->hotplug_memory, 1607 addr - pcms->hotplug_memory_base, mr); 1608 vmstate_register_ram(mr, dev); 1609 1610 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1611 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1612 out: 1613 error_propagate(errp, local_err); 1614 } 1615 1616 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1617 DeviceState *dev, Error **errp) 1618 { 1619 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1620 pc_dimm_plug(hotplug_dev, dev, errp); 1621 } 1622 } 1623 1624 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1625 DeviceState *dev) 1626 { 1627 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1628 1629 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1630 return HOTPLUG_HANDLER(machine); 1631 } 1632 1633 return pcmc->get_hotplug_handler ? 1634 pcmc->get_hotplug_handler(machine, dev) : NULL; 1635 } 1636 1637 static void 1638 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1639 const char *name, Error **errp) 1640 { 1641 PCMachineState *pcms = PC_MACHINE(obj); 1642 int64_t value = memory_region_size(&pcms->hotplug_memory); 1643 1644 visit_type_int(v, &value, name, errp); 1645 } 1646 1647 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1648 void *opaque, const char *name, 1649 Error **errp) 1650 { 1651 PCMachineState *pcms = PC_MACHINE(obj); 1652 uint64_t value = pcms->max_ram_below_4g; 1653 1654 visit_type_size(v, &value, name, errp); 1655 } 1656 1657 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1658 void *opaque, const char *name, 1659 Error **errp) 1660 { 1661 PCMachineState *pcms = PC_MACHINE(obj); 1662 Error *error = NULL; 1663 uint64_t value; 1664 1665 visit_type_size(v, &value, name, &error); 1666 if (error) { 1667 error_propagate(errp, error); 1668 return; 1669 } 1670 if (value > (1ULL << 32)) { 1671 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1672 "Machine option 'max-ram-below-4g=%"PRIu64 1673 "' expects size less than or equal to 4G", value); 1674 error_propagate(errp, error); 1675 return; 1676 } 1677 1678 if (value < (1ULL << 20)) { 1679 error_report("Warning: small max_ram_below_4g(%"PRIu64 1680 ") less than 1M. BIOS may not work..", 1681 value); 1682 } 1683 1684 pcms->max_ram_below_4g = value; 1685 } 1686 1687 static void pc_machine_initfn(Object *obj) 1688 { 1689 PCMachineState *pcms = PC_MACHINE(obj); 1690 1691 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1692 pc_machine_get_hotplug_memory_region_size, 1693 NULL, NULL, NULL, NULL); 1694 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1695 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1696 pc_machine_get_max_ram_below_4g, 1697 pc_machine_set_max_ram_below_4g, 1698 NULL, NULL, NULL); 1699 } 1700 1701 static void pc_machine_class_init(ObjectClass *oc, void *data) 1702 { 1703 MachineClass *mc = MACHINE_CLASS(oc); 1704 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1705 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1706 1707 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1708 mc->get_hotplug_handler = pc_get_hotpug_handler; 1709 hc->plug = pc_machine_device_plug_cb; 1710 } 1711 1712 static const TypeInfo pc_machine_info = { 1713 .name = TYPE_PC_MACHINE, 1714 .parent = TYPE_MACHINE, 1715 .abstract = true, 1716 .instance_size = sizeof(PCMachineState), 1717 .instance_init = pc_machine_initfn, 1718 .class_size = sizeof(PCMachineClass), 1719 .class_init = pc_machine_class_init, 1720 .interfaces = (InterfaceInfo[]) { 1721 { TYPE_HOTPLUG_HANDLER }, 1722 { } 1723 }, 1724 }; 1725 1726 static void pc_machine_register_types(void) 1727 { 1728 type_register_static(&pc_machine_info); 1729 } 1730 1731 type_init(pc_machine_register_types) 1732