xref: /openbmc/qemu/hw/i386/pc.c (revision 701bff24)
1 /*
2  * QEMU PC System Emulator
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "hw/i386/x86.h"
28 #include "hw/i386/pc.h"
29 #include "hw/char/serial.h"
30 #include "hw/char/parallel.h"
31 #include "hw/i386/apic.h"
32 #include "hw/i386/topology.h"
33 #include "hw/i386/fw_cfg.h"
34 #include "hw/i386/vmport.h"
35 #include "sysemu/cpus.h"
36 #include "hw/block/fdc.h"
37 #include "hw/ide.h"
38 #include "hw/pci/pci.h"
39 #include "hw/pci/pci_bus.h"
40 #include "hw/pci-bridge/pci_expander_bridge.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/timer/hpet.h"
43 #include "hw/firmware/smbios.h"
44 #include "hw/loader.h"
45 #include "elf.h"
46 #include "migration/vmstate.h"
47 #include "multiboot.h"
48 #include "hw/rtc/mc146818rtc.h"
49 #include "hw/intc/i8259.h"
50 #include "hw/dma/i8257.h"
51 #include "hw/timer/i8254.h"
52 #include "hw/input/i8042.h"
53 #include "hw/irq.h"
54 #include "hw/audio/pcspk.h"
55 #include "hw/pci/msi.h"
56 #include "hw/sysbus.h"
57 #include "sysemu/sysemu.h"
58 #include "sysemu/tcg.h"
59 #include "sysemu/numa.h"
60 #include "sysemu/kvm.h"
61 #include "sysemu/xen.h"
62 #include "sysemu/reset.h"
63 #include "sysemu/runstate.h"
64 #include "kvm/kvm_i386.h"
65 #include "hw/xen/xen.h"
66 #include "hw/xen/start_info.h"
67 #include "ui/qemu-spice.h"
68 #include "exec/memory.h"
69 #include "qemu/bitmap.h"
70 #include "qemu/config-file.h"
71 #include "qemu/error-report.h"
72 #include "qemu/option.h"
73 #include "qemu/cutils.h"
74 #include "hw/acpi/acpi.h"
75 #include "hw/acpi/cpu_hotplug.h"
76 #include "acpi-build.h"
77 #include "hw/mem/pc-dimm.h"
78 #include "hw/mem/nvdimm.h"
79 #include "hw/cxl/cxl.h"
80 #include "hw/cxl/cxl_host.h"
81 #include "qapi/error.h"
82 #include "qapi/qapi-visit-common.h"
83 #include "qapi/qapi-visit-machine.h"
84 #include "qapi/visitor.h"
85 #include "hw/core/cpu.h"
86 #include "hw/usb.h"
87 #include "hw/i386/intel_iommu.h"
88 #include "hw/net/ne2000-isa.h"
89 #include "standard-headers/asm-x86/bootparam.h"
90 #include "hw/virtio/virtio-iommu.h"
91 #include "hw/virtio/virtio-pmem-pci.h"
92 #include "hw/virtio/virtio-mem-pci.h"
93 #include "hw/mem/memory-device.h"
94 #include "sysemu/replay.h"
95 #include "target/i386/cpu.h"
96 #include "qapi/qmp/qerror.h"
97 #include "e820_memory_layout.h"
98 #include "fw_cfg.h"
99 #include "trace.h"
100 #include CONFIG_DEVICES
101 
102 /*
103  * Helper for setting model-id for CPU models that changed model-id
104  * depending on QEMU versions up to QEMU 2.4.
105  */
106 #define PC_CPU_MODEL_IDS(v) \
107     { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
108     { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
109     { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
110 
111 GlobalProperty pc_compat_7_1[] = {};
112 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1);
113 
114 GlobalProperty pc_compat_7_0[] = {};
115 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0);
116 
117 GlobalProperty pc_compat_6_2[] = {
118     { "virtio-mem", "unplugged-inaccessible", "off" },
119 };
120 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2);
121 
122 GlobalProperty pc_compat_6_1[] = {
123     { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" },
124     { TYPE_X86_CPU, "hv-version-id-major", "0x0006" },
125     { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" },
126     { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" },
127 };
128 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1);
129 
130 GlobalProperty pc_compat_6_0[] = {
131     { "qemu64" "-" TYPE_X86_CPU, "family", "6" },
132     { "qemu64" "-" TYPE_X86_CPU, "model", "6" },
133     { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" },
134     { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" },
135     { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
136     { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" },
137 };
138 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0);
139 
140 GlobalProperty pc_compat_5_2[] = {
141     { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" },
142 };
143 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2);
144 
145 GlobalProperty pc_compat_5_1[] = {
146     { "ICH9-LPC", "x-smi-cpu-hotplug", "off" },
147     { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" },
148 };
149 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1);
150 
151 GlobalProperty pc_compat_5_0[] = {
152 };
153 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0);
154 
155 GlobalProperty pc_compat_4_2[] = {
156     { "mch", "smbase-smram", "off" },
157 };
158 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2);
159 
160 GlobalProperty pc_compat_4_1[] = {};
161 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
162 
163 GlobalProperty pc_compat_4_0[] = {};
164 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
165 
166 GlobalProperty pc_compat_3_1[] = {
167     { "intel-iommu", "dma-drain", "off" },
168     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
169     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
170     { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
171     { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
172     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
173     { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
174     { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
175     { "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
176     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
177     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
178     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
179     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
180     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
181     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
182     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
183     { "Cascadelake-Server" "-" TYPE_X86_CPU,  "mpx", "on" },
184     { "Icelake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
185     { "Icelake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
186     { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
187     { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
188 };
189 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
190 
191 GlobalProperty pc_compat_3_0[] = {
192     { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
193     { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
194     { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
195 };
196 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
197 
198 GlobalProperty pc_compat_2_12[] = {
199     { TYPE_X86_CPU, "legacy-cache", "on" },
200     { TYPE_X86_CPU, "topoext", "off" },
201     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
202     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
203 };
204 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
205 
206 GlobalProperty pc_compat_2_11[] = {
207     { TYPE_X86_CPU, "x-migrate-smi-count", "off" },
208     { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
209 };
210 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
211 
212 GlobalProperty pc_compat_2_10[] = {
213     { TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
214     { "i440FX-pcihost", "x-pci-hole64-fix", "off" },
215     { "q35-pcihost", "x-pci-hole64-fix", "off" },
216 };
217 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
218 
219 GlobalProperty pc_compat_2_9[] = {
220     { "mch", "extended-tseg-mbytes", "0" },
221 };
222 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
223 
224 GlobalProperty pc_compat_2_8[] = {
225     { TYPE_X86_CPU, "tcg-cpuid", "off" },
226     { "kvmclock", "x-mach-use-reliable-get-clock", "off" },
227     { "ICH9-LPC", "x-smi-broadcast", "off" },
228     { TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
229     { "Haswell-" TYPE_X86_CPU, "stepping", "1" },
230 };
231 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
232 
233 GlobalProperty pc_compat_2_7[] = {
234     { TYPE_X86_CPU, "l3-cache", "off" },
235     { TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
236     { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
237     { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
238     { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
239     { "isa-pcspk", "migrate", "off" },
240 };
241 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
242 
243 GlobalProperty pc_compat_2_6[] = {
244     { TYPE_X86_CPU, "cpuid-0xb", "off" },
245     { "vmxnet3", "romfile", "" },
246     { TYPE_X86_CPU, "fill-mtrr-mask", "off" },
247     { "apic-common", "legacy-instance-id", "on", }
248 };
249 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
250 
251 GlobalProperty pc_compat_2_5[] = {};
252 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
253 
254 GlobalProperty pc_compat_2_4[] = {
255     PC_CPU_MODEL_IDS("2.4.0")
256     { "Haswell-" TYPE_X86_CPU, "abm", "off" },
257     { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
258     { "Broadwell-" TYPE_X86_CPU, "abm", "off" },
259     { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
260     { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
261     { TYPE_X86_CPU, "check", "off" },
262     { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
263     { "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
264     { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
265     { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
266     { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
267     { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
268     { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
269     { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
270 };
271 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
272 
273 GlobalProperty pc_compat_2_3[] = {
274     PC_CPU_MODEL_IDS("2.3.0")
275     { TYPE_X86_CPU, "arat", "off" },
276     { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
277     { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
278     { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
279     { "n270" "-" TYPE_X86_CPU, "min-level", "5" },
280     { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
281     { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
282     { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
283     { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
284     { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
285     { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
286     { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
287     { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
288     { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
289     { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
290     { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
291     { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
292     { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
293     { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
294     { TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
295 };
296 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
297 
298 GlobalProperty pc_compat_2_2[] = {
299     PC_CPU_MODEL_IDS("2.2.0")
300     { "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
301     { "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
302     { "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
303     { "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
304     { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
305     { "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
306     { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
307     { "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
308     { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
309     { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
310     { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
311     { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
312     { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
313     { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
314     { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
315     { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
316     { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
317     { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
318 };
319 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
320 
321 GlobalProperty pc_compat_2_1[] = {
322     PC_CPU_MODEL_IDS("2.1.0")
323     { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
324     { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
325 };
326 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
327 
328 GlobalProperty pc_compat_2_0[] = {
329     PC_CPU_MODEL_IDS("2.0.0")
330     { "virtio-scsi-pci", "any_layout", "off" },
331     { "PIIX4_PM", "memory-hotplug-support", "off" },
332     { "apic", "version", "0x11" },
333     { "nec-usb-xhci", "superspeed-ports-first", "off" },
334     { "nec-usb-xhci", "force-pcie-endcap", "on" },
335     { "pci-serial", "prog_if", "0" },
336     { "pci-serial-2x", "prog_if", "0" },
337     { "pci-serial-4x", "prog_if", "0" },
338     { "virtio-net-pci", "guest_announce", "off" },
339     { "ICH9-LPC", "memory-hotplug-support", "off" },
340 };
341 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
342 
343 GlobalProperty pc_compat_1_7[] = {
344     PC_CPU_MODEL_IDS("1.7.0")
345     { TYPE_USB_DEVICE, "msos-desc", "no" },
346     { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" },
347     { "hpet", HPET_INTCAP, "4" },
348 };
349 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
350 
351 GlobalProperty pc_compat_1_6[] = {
352     PC_CPU_MODEL_IDS("1.6.0")
353     { "e1000", "mitigation", "off" },
354     { "qemu64-" TYPE_X86_CPU, "model", "2" },
355     { "qemu32-" TYPE_X86_CPU, "model", "3" },
356     { "i440FX-pcihost", "short_root_bus", "1" },
357     { "q35-pcihost", "short_root_bus", "1" },
358 };
359 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
360 
361 GlobalProperty pc_compat_1_5[] = {
362     PC_CPU_MODEL_IDS("1.5.0")
363     { "Conroe-" TYPE_X86_CPU, "model", "2" },
364     { "Conroe-" TYPE_X86_CPU, "min-level", "2" },
365     { "Penryn-" TYPE_X86_CPU, "model", "2" },
366     { "Penryn-" TYPE_X86_CPU, "min-level", "2" },
367     { "Nehalem-" TYPE_X86_CPU, "model", "2" },
368     { "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
369     { "virtio-net-pci", "any_layout", "off" },
370     { TYPE_X86_CPU, "pmu", "on" },
371     { "i440FX-pcihost", "short_root_bus", "0" },
372     { "q35-pcihost", "short_root_bus", "0" },
373 };
374 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
375 
376 GlobalProperty pc_compat_1_4[] = {
377     PC_CPU_MODEL_IDS("1.4.0")
378     { "scsi-hd", "discard_granularity", "0" },
379     { "scsi-cd", "discard_granularity", "0" },
380     { "ide-hd", "discard_granularity", "0" },
381     { "ide-cd", "discard_granularity", "0" },
382     { "virtio-blk-pci", "discard_granularity", "0" },
383     /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
384     { "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
385     { "virtio-net-pci", "ctrl_guest_offloads", "off" },
386     { "e1000", "romfile", "pxe-e1000.rom" },
387     { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
388     { "pcnet", "romfile", "pxe-pcnet.rom" },
389     { "rtl8139", "romfile", "pxe-rtl8139.rom" },
390     { "virtio-net-pci", "romfile", "pxe-virtio.rom" },
391     { "486-" TYPE_X86_CPU, "model", "0" },
392     { "n270" "-" TYPE_X86_CPU, "movbe", "off" },
393     { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
394 };
395 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
396 
397 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
398 {
399     GSIState *s;
400 
401     s = g_new0(GSIState, 1);
402     if (kvm_ioapic_in_kernel()) {
403         kvm_pc_setup_irq_routing(pci_enabled);
404     }
405     *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
406 
407     return s;
408 }
409 
410 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
411                            unsigned size)
412 {
413 }
414 
415 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
416 {
417     return 0xffffffffffffffffULL;
418 }
419 
420 /* MSDOS compatibility mode FPU exception support */
421 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
422                            unsigned size)
423 {
424     if (tcg_enabled()) {
425         cpu_set_ignne();
426     }
427 }
428 
429 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
430 {
431     return 0xffffffffffffffffULL;
432 }
433 
434 /* PC cmos mappings */
435 
436 #define REG_EQUIPMENT_BYTE          0x14
437 
438 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
439                          int16_t cylinders, int8_t heads, int8_t sectors)
440 {
441     rtc_set_memory(s, type_ofs, 47);
442     rtc_set_memory(s, info_ofs, cylinders);
443     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
444     rtc_set_memory(s, info_ofs + 2, heads);
445     rtc_set_memory(s, info_ofs + 3, 0xff);
446     rtc_set_memory(s, info_ofs + 4, 0xff);
447     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
448     rtc_set_memory(s, info_ofs + 6, cylinders);
449     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
450     rtc_set_memory(s, info_ofs + 8, sectors);
451 }
452 
453 /* convert boot_device letter to something recognizable by the bios */
454 static int boot_device2nibble(char boot_device)
455 {
456     switch(boot_device) {
457     case 'a':
458     case 'b':
459         return 0x01; /* floppy boot */
460     case 'c':
461         return 0x02; /* hard drive boot */
462     case 'd':
463         return 0x03; /* CD-ROM boot */
464     case 'n':
465         return 0x04; /* Network boot */
466     }
467     return 0;
468 }
469 
470 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
471 {
472 #define PC_MAX_BOOT_DEVICES 3
473     int nbds, bds[3] = { 0, };
474     int i;
475 
476     nbds = strlen(boot_device);
477     if (nbds > PC_MAX_BOOT_DEVICES) {
478         error_setg(errp, "Too many boot devices for PC");
479         return;
480     }
481     for (i = 0; i < nbds; i++) {
482         bds[i] = boot_device2nibble(boot_device[i]);
483         if (bds[i] == 0) {
484             error_setg(errp, "Invalid boot device for PC: '%c'",
485                        boot_device[i]);
486             return;
487         }
488     }
489     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
490     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
491 }
492 
493 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
494 {
495     set_boot_dev(opaque, boot_device, errp);
496 }
497 
498 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
499 {
500     int val, nb, i;
501     FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
502                                    FLOPPY_DRIVE_TYPE_NONE };
503 
504     /* floppy type */
505     if (floppy) {
506         for (i = 0; i < 2; i++) {
507             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
508         }
509     }
510     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
511         cmos_get_fd_drive_type(fd_type[1]);
512     rtc_set_memory(rtc_state, 0x10, val);
513 
514     val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
515     nb = 0;
516     if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
517         nb++;
518     }
519     if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
520         nb++;
521     }
522     switch (nb) {
523     case 0:
524         break;
525     case 1:
526         val |= 0x01; /* 1 drive, ready for boot */
527         break;
528     case 2:
529         val |= 0x41; /* 2 drives, ready for boot */
530         break;
531     }
532     rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
533 }
534 
535 typedef struct pc_cmos_init_late_arg {
536     ISADevice *rtc_state;
537     BusState *idebus[2];
538 } pc_cmos_init_late_arg;
539 
540 typedef struct check_fdc_state {
541     ISADevice *floppy;
542     bool multiple;
543 } CheckFdcState;
544 
545 static int check_fdc(Object *obj, void *opaque)
546 {
547     CheckFdcState *state = opaque;
548     Object *fdc;
549     uint32_t iobase;
550     Error *local_err = NULL;
551 
552     fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
553     if (!fdc) {
554         return 0;
555     }
556 
557     iobase = object_property_get_uint(obj, "iobase", &local_err);
558     if (local_err || iobase != 0x3f0) {
559         error_free(local_err);
560         return 0;
561     }
562 
563     if (state->floppy) {
564         state->multiple = true;
565     } else {
566         state->floppy = ISA_DEVICE(obj);
567     }
568     return 0;
569 }
570 
571 static const char * const fdc_container_path[] = {
572     "/unattached", "/peripheral", "/peripheral-anon"
573 };
574 
575 /*
576  * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
577  * and ACPI objects.
578  */
579 static ISADevice *pc_find_fdc0(void)
580 {
581     int i;
582     Object *container;
583     CheckFdcState state = { 0 };
584 
585     for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
586         container = container_get(qdev_get_machine(), fdc_container_path[i]);
587         object_child_foreach(container, check_fdc, &state);
588     }
589 
590     if (state.multiple) {
591         warn_report("multiple floppy disk controllers with "
592                     "iobase=0x3f0 have been found");
593         error_printf("the one being picked for CMOS setup might not reflect "
594                      "your intent");
595     }
596 
597     return state.floppy;
598 }
599 
600 static void pc_cmos_init_late(void *opaque)
601 {
602     pc_cmos_init_late_arg *arg = opaque;
603     ISADevice *s = arg->rtc_state;
604     int16_t cylinders;
605     int8_t heads, sectors;
606     int val;
607     int i, trans;
608 
609     val = 0;
610     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
611                                            &cylinders, &heads, &sectors) >= 0) {
612         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
613         val |= 0xf0;
614     }
615     if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
616                                            &cylinders, &heads, &sectors) >= 0) {
617         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
618         val |= 0x0f;
619     }
620     rtc_set_memory(s, 0x12, val);
621 
622     val = 0;
623     for (i = 0; i < 4; i++) {
624         /* NOTE: ide_get_geometry() returns the physical
625            geometry.  It is always such that: 1 <= sects <= 63, 1
626            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
627            geometry can be different if a translation is done. */
628         if (arg->idebus[i / 2] &&
629             ide_get_geometry(arg->idebus[i / 2], i % 2,
630                              &cylinders, &heads, &sectors) >= 0) {
631             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
632             assert((trans & ~3) == 0);
633             val |= trans << (i * 2);
634         }
635     }
636     rtc_set_memory(s, 0x39, val);
637 
638     pc_cmos_init_floppy(s, pc_find_fdc0());
639 
640     qemu_unregister_reset(pc_cmos_init_late, opaque);
641 }
642 
643 void pc_cmos_init(PCMachineState *pcms,
644                   BusState *idebus0, BusState *idebus1,
645                   ISADevice *s)
646 {
647     int val;
648     static pc_cmos_init_late_arg arg;
649     X86MachineState *x86ms = X86_MACHINE(pcms);
650 
651     /* various important CMOS locations needed by PC/Bochs bios */
652 
653     /* memory size */
654     /* base memory (first MiB) */
655     val = MIN(x86ms->below_4g_mem_size / KiB, 640);
656     rtc_set_memory(s, 0x15, val);
657     rtc_set_memory(s, 0x16, val >> 8);
658     /* extended memory (next 64MiB) */
659     if (x86ms->below_4g_mem_size > 1 * MiB) {
660         val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB;
661     } else {
662         val = 0;
663     }
664     if (val > 65535)
665         val = 65535;
666     rtc_set_memory(s, 0x17, val);
667     rtc_set_memory(s, 0x18, val >> 8);
668     rtc_set_memory(s, 0x30, val);
669     rtc_set_memory(s, 0x31, val >> 8);
670     /* memory between 16MiB and 4GiB */
671     if (x86ms->below_4g_mem_size > 16 * MiB) {
672         val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
673     } else {
674         val = 0;
675     }
676     if (val > 65535)
677         val = 65535;
678     rtc_set_memory(s, 0x34, val);
679     rtc_set_memory(s, 0x35, val >> 8);
680     /* memory above 4GiB */
681     val = x86ms->above_4g_mem_size / 65536;
682     rtc_set_memory(s, 0x5b, val);
683     rtc_set_memory(s, 0x5c, val >> 8);
684     rtc_set_memory(s, 0x5d, val >> 16);
685 
686     object_property_add_link(OBJECT(pcms), "rtc_state",
687                              TYPE_ISA_DEVICE,
688                              (Object **)&x86ms->rtc,
689                              object_property_allow_set_link,
690                              OBJ_PROP_LINK_STRONG);
691     object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s),
692                              &error_abort);
693 
694     set_boot_dev(s, MACHINE(pcms)->boot_config.order, &error_fatal);
695 
696     val = 0;
697     val |= 0x02; /* FPU is there */
698     val |= 0x04; /* PS/2 mouse installed */
699     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
700 
701     /* hard drives and FDC */
702     arg.rtc_state = s;
703     arg.idebus[0] = idebus0;
704     arg.idebus[1] = idebus1;
705     qemu_register_reset(pc_cmos_init_late, &arg);
706 }
707 
708 static void handle_a20_line_change(void *opaque, int irq, int level)
709 {
710     X86CPU *cpu = opaque;
711 
712     /* XXX: send to all CPUs ? */
713     /* XXX: add logic to handle multiple A20 line sources */
714     x86_cpu_set_a20(cpu, level);
715 }
716 
717 #define NE2000_NB_MAX 6
718 
719 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
720                                               0x280, 0x380 };
721 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
722 
723 static void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
724 {
725     static int nb_ne2k = 0;
726 
727     if (nb_ne2k == NE2000_NB_MAX)
728         return;
729     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
730                     ne2000_irq[nb_ne2k], nd);
731     nb_ne2k++;
732 }
733 
734 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
735 {
736     X86CPU *cpu = opaque;
737 
738     if (level) {
739         cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
740     }
741 }
742 
743 static
744 void pc_machine_done(Notifier *notifier, void *data)
745 {
746     PCMachineState *pcms = container_of(notifier,
747                                         PCMachineState, machine_done);
748     X86MachineState *x86ms = X86_MACHINE(pcms);
749 
750     cxl_hook_up_pxb_registers(pcms->bus, &pcms->cxl_devices_state,
751                               &error_fatal);
752 
753     if (pcms->cxl_devices_state.is_enabled) {
754         cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal);
755     }
756 
757     /* set the number of CPUs */
758     x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus);
759 
760     fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg);
761 
762     acpi_setup();
763     if (x86ms->fw_cfg) {
764         fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg);
765         fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg);
766         /* update FW_CFG_NB_CPUS to account for -device added CPUs */
767         fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
768     }
769 }
770 
771 void pc_guest_info_init(PCMachineState *pcms)
772 {
773     X86MachineState *x86ms = X86_MACHINE(pcms);
774 
775     x86ms->apic_xrupt_override = true;
776     pcms->machine_done.notify = pc_machine_done;
777     qemu_add_machine_init_done_notifier(&pcms->machine_done);
778 }
779 
780 /* setup pci memory address space mapping into system address space */
781 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
782                             MemoryRegion *pci_address_space)
783 {
784     /* Set to lower priority than RAM */
785     memory_region_add_subregion_overlap(system_memory, 0x0,
786                                         pci_address_space, -1);
787 }
788 
789 void xen_load_linux(PCMachineState *pcms)
790 {
791     int i;
792     FWCfgState *fw_cfg;
793     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
794     X86MachineState *x86ms = X86_MACHINE(pcms);
795 
796     assert(MACHINE(pcms)->kernel_filename != NULL);
797 
798     fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE);
799     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus);
800     rom_set_fw(fw_cfg);
801 
802     x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
803                    pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
804     for (i = 0; i < nb_option_roms; i++) {
805         assert(!strcmp(option_rom[i].name, "linuxboot.bin") ||
806                !strcmp(option_rom[i].name, "linuxboot_dma.bin") ||
807                !strcmp(option_rom[i].name, "pvh.bin") ||
808                !strcmp(option_rom[i].name, "multiboot.bin") ||
809                !strcmp(option_rom[i].name, "multiboot_dma.bin"));
810         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
811     }
812     x86ms->fw_cfg = fw_cfg;
813 }
814 
815 #define PC_ROM_MIN_VGA     0xc0000
816 #define PC_ROM_MIN_OPTION  0xc8000
817 #define PC_ROM_MAX         0xe0000
818 #define PC_ROM_ALIGN       0x800
819 #define PC_ROM_SIZE        (PC_ROM_MAX - PC_ROM_MIN_VGA)
820 
821 static hwaddr pc_above_4g_end(PCMachineState *pcms)
822 {
823     X86MachineState *x86ms = X86_MACHINE(pcms);
824 
825     if (pcms->sgx_epc.size != 0) {
826         return sgx_epc_above_4g_end(&pcms->sgx_epc);
827     }
828 
829     return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size;
830 }
831 
832 static void pc_get_device_memory_range(PCMachineState *pcms,
833                                        hwaddr *base,
834                                        ram_addr_t *device_mem_size)
835 {
836     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
837     MachineState *machine = MACHINE(pcms);
838     ram_addr_t size;
839     hwaddr addr;
840 
841     size = machine->maxram_size - machine->ram_size;
842     addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB);
843 
844     if (pcmc->enforce_aligned_dimm) {
845         /* size device region assuming 1G page max alignment per slot */
846         size += (1 * GiB) * machine->ram_slots;
847     }
848 
849     *base = addr;
850     *device_mem_size = size;
851 }
852 
853 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms)
854 {
855     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
856     hwaddr cxl_base;
857     ram_addr_t size;
858 
859     if (pcmc->has_reserved_memory) {
860         pc_get_device_memory_range(pcms, &cxl_base, &size);
861         cxl_base += size;
862     } else {
863         cxl_base = pc_above_4g_end(pcms);
864     }
865 
866     return cxl_base;
867 }
868 
869 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms)
870 {
871     uint64_t start = pc_get_cxl_range_start(pcms) + MiB;
872 
873     if (pcms->cxl_devices_state.fixed_windows) {
874         GList *it;
875 
876         start = ROUND_UP(start, 256 * MiB);
877         for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
878             CXLFixedWindow *fw = it->data;
879             start += fw->size;
880         }
881     }
882 
883     return start;
884 }
885 
886 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size)
887 {
888     X86CPU *cpu = X86_CPU(first_cpu);
889 
890     /* 32-bit systems don't have hole64 thus return max CPU address */
891     if (cpu->phys_bits <= 32) {
892         return ((hwaddr)1 << cpu->phys_bits) - 1;
893     }
894 
895     return pc_pci_hole64_start() + pci_hole64_size - 1;
896 }
897 
898 /*
899  * AMD systems with an IOMMU have an additional hole close to the
900  * 1Tb, which are special GPAs that cannot be DMA mapped. Depending
901  * on kernel version, VFIO may or may not let you DMA map those ranges.
902  * Starting Linux v5.4 we validate it, and can't create guests on AMD machines
903  * with certain memory sizes. It's also wrong to use those IOVA ranges
904  * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse.
905  * The ranges reserved for Hyper-Transport are:
906  *
907  * FD_0000_0000h - FF_FFFF_FFFFh
908  *
909  * The ranges represent the following:
910  *
911  * Base Address   Top Address  Use
912  *
913  * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space
914  * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl
915  * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK
916  * FD_F910_0000h FD_F91F_FFFFh System Management
917  * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables
918  * FD_FB00_0000h FD_FBFF_FFFFh Address Translation
919  * FD_FC00_0000h FD_FDFF_FFFFh I/O Space
920  * FD_FE00_0000h FD_FFFF_FFFFh Configuration
921  * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages
922  * FE_2000_0000h FF_FFFF_FFFFh Reserved
923  *
924  * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology",
925  * Table 3: Special Address Controls (GPA) for more information.
926  */
927 #define AMD_HT_START         0xfd00000000UL
928 #define AMD_HT_END           0xffffffffffUL
929 #define AMD_ABOVE_1TB_START  (AMD_HT_END + 1)
930 #define AMD_HT_SIZE          (AMD_ABOVE_1TB_START - AMD_HT_START)
931 
932 void pc_memory_init(PCMachineState *pcms,
933                     MemoryRegion *system_memory,
934                     MemoryRegion *rom_memory,
935                     MemoryRegion **ram_memory,
936                     uint64_t pci_hole64_size)
937 {
938     int linux_boot, i;
939     MemoryRegion *option_rom_mr;
940     MemoryRegion *ram_below_4g, *ram_above_4g;
941     FWCfgState *fw_cfg;
942     MachineState *machine = MACHINE(pcms);
943     MachineClass *mc = MACHINE_GET_CLASS(machine);
944     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
945     X86MachineState *x86ms = X86_MACHINE(pcms);
946     hwaddr maxphysaddr, maxusedaddr;
947     hwaddr cxl_base, cxl_resv_end = 0;
948     X86CPU *cpu = X86_CPU(first_cpu);
949 
950     assert(machine->ram_size == x86ms->below_4g_mem_size +
951                                 x86ms->above_4g_mem_size);
952 
953     linux_boot = (machine->kernel_filename != NULL);
954 
955     /*
956      * The HyperTransport range close to the 1T boundary is unique to AMD
957      * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation
958      * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in
959      * older machine types (<= 7.0) for compatibility purposes.
960      */
961     if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) {
962         /* Bail out if max possible address does not cross HT range */
963         if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) {
964             x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START;
965         }
966 
967         /*
968          * Advertise the HT region if address space covers the reserved
969          * region or if we relocate.
970          */
971         if (cpu->phys_bits >= 40) {
972             e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED);
973         }
974     }
975 
976     /*
977      * phys-bits is required to be appropriately configured
978      * to make sure max used GPA is reachable.
979      */
980     maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size);
981     maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1;
982     if (maxphysaddr < maxusedaddr) {
983         error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64
984                      " phys-bits too low (%u)",
985                      maxphysaddr, maxusedaddr, cpu->phys_bits);
986         exit(EXIT_FAILURE);
987     }
988 
989     /*
990      * Split single memory region and use aliases to address portions of it,
991      * done for backwards compatibility with older qemus.
992      */
993     *ram_memory = machine->ram;
994     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
995     memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram,
996                              0, x86ms->below_4g_mem_size);
997     memory_region_add_subregion(system_memory, 0, ram_below_4g);
998     e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM);
999     if (x86ms->above_4g_mem_size > 0) {
1000         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1001         memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g",
1002                                  machine->ram,
1003                                  x86ms->below_4g_mem_size,
1004                                  x86ms->above_4g_mem_size);
1005         memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start,
1006                                     ram_above_4g);
1007         e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size,
1008                        E820_RAM);
1009     }
1010 
1011     if (pcms->sgx_epc.size != 0) {
1012         e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED);
1013     }
1014 
1015     if (!pcmc->has_reserved_memory &&
1016         (machine->ram_slots ||
1017          (machine->maxram_size > machine->ram_size))) {
1018 
1019         error_report("\"-memory 'slots|maxmem'\" is not supported by: %s",
1020                      mc->name);
1021         exit(EXIT_FAILURE);
1022     }
1023 
1024     /* always allocate the device memory information */
1025     machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
1026 
1027     /* initialize device memory address space */
1028     if (pcmc->has_reserved_memory &&
1029         (machine->ram_size < machine->maxram_size)) {
1030         ram_addr_t device_mem_size;
1031 
1032         if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) {
1033             error_report("unsupported amount of memory slots: %"PRIu64,
1034                          machine->ram_slots);
1035             exit(EXIT_FAILURE);
1036         }
1037 
1038         if (QEMU_ALIGN_UP(machine->maxram_size,
1039                           TARGET_PAGE_SIZE) != machine->maxram_size) {
1040             error_report("maximum memory size must by aligned to multiple of "
1041                          "%d bytes", TARGET_PAGE_SIZE);
1042             exit(EXIT_FAILURE);
1043         }
1044 
1045         pc_get_device_memory_range(pcms, &machine->device_memory->base, &device_mem_size);
1046 
1047         if ((machine->device_memory->base + device_mem_size) <
1048             device_mem_size) {
1049             error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT,
1050                          machine->maxram_size);
1051             exit(EXIT_FAILURE);
1052         }
1053 
1054         memory_region_init(&machine->device_memory->mr, OBJECT(pcms),
1055                            "device-memory", device_mem_size);
1056         memory_region_add_subregion(system_memory, machine->device_memory->base,
1057                                     &machine->device_memory->mr);
1058     }
1059 
1060     if (pcms->cxl_devices_state.is_enabled) {
1061         MemoryRegion *mr = &pcms->cxl_devices_state.host_mr;
1062         hwaddr cxl_size = MiB;
1063 
1064         cxl_base = pc_get_cxl_range_start(pcms);
1065         e820_add_entry(cxl_base, cxl_size, E820_RESERVED);
1066         memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size);
1067         memory_region_add_subregion(system_memory, cxl_base, mr);
1068         cxl_resv_end = cxl_base + cxl_size;
1069         if (pcms->cxl_devices_state.fixed_windows) {
1070             hwaddr cxl_fmw_base;
1071             GList *it;
1072 
1073             cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB);
1074             for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) {
1075                 CXLFixedWindow *fw = it->data;
1076 
1077                 fw->base = cxl_fmw_base;
1078                 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw,
1079                                       "cxl-fixed-memory-region", fw->size);
1080                 memory_region_add_subregion(system_memory, fw->base, &fw->mr);
1081                 e820_add_entry(fw->base, fw->size, E820_RESERVED);
1082                 cxl_fmw_base += fw->size;
1083                 cxl_resv_end = cxl_fmw_base;
1084             }
1085         }
1086     }
1087 
1088     /* Initialize PC system firmware */
1089     pc_system_firmware_init(pcms, rom_memory);
1090 
1091     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1092     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE,
1093                            &error_fatal);
1094     if (pcmc->pci_enabled) {
1095         memory_region_set_readonly(option_rom_mr, true);
1096     }
1097     memory_region_add_subregion_overlap(rom_memory,
1098                                         PC_ROM_MIN_VGA,
1099                                         option_rom_mr,
1100                                         1);
1101 
1102     fw_cfg = fw_cfg_arch_create(machine,
1103                                 x86ms->boot_cpus, x86ms->apic_id_limit);
1104 
1105     rom_set_fw(fw_cfg);
1106 
1107     if (pcmc->has_reserved_memory && machine->device_memory->base) {
1108         uint64_t *val = g_malloc(sizeof(*val));
1109         PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1110         uint64_t res_mem_end = machine->device_memory->base;
1111 
1112         if (!pcmc->broken_reserved_end) {
1113             res_mem_end += memory_region_size(&machine->device_memory->mr);
1114         }
1115 
1116         if (pcms->cxl_devices_state.is_enabled) {
1117             res_mem_end = cxl_resv_end;
1118         }
1119         *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB));
1120         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
1121     }
1122 
1123     if (linux_boot) {
1124         x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size,
1125                        pcmc->pvh_enabled, pcmc->legacy_no_rng_seed);
1126     }
1127 
1128     for (i = 0; i < nb_option_roms; i++) {
1129         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1130     }
1131     x86ms->fw_cfg = fw_cfg;
1132 
1133     /* Init default IOAPIC address space */
1134     x86ms->ioapic_as = &address_space_memory;
1135 
1136     /* Init ACPI memory hotplug IO base address */
1137     pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
1138 }
1139 
1140 /*
1141  * The 64bit pci hole starts after "above 4G RAM" and
1142  * potentially the space reserved for memory hotplug.
1143  */
1144 uint64_t pc_pci_hole64_start(void)
1145 {
1146     PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1147     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1148     MachineState *ms = MACHINE(pcms);
1149     uint64_t hole64_start = 0;
1150     ram_addr_t size = 0;
1151 
1152     if (pcms->cxl_devices_state.is_enabled) {
1153         hole64_start = pc_get_cxl_range_end(pcms);
1154     } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) {
1155         pc_get_device_memory_range(pcms, &hole64_start, &size);
1156         if (!pcmc->broken_reserved_end) {
1157             hole64_start += size;
1158         }
1159     } else {
1160         hole64_start = pc_above_4g_end(pcms);
1161     }
1162 
1163     return ROUND_UP(hole64_start, 1 * GiB);
1164 }
1165 
1166 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1167 {
1168     DeviceState *dev = NULL;
1169 
1170     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA);
1171     if (pci_bus) {
1172         PCIDevice *pcidev = pci_vga_init(pci_bus);
1173         dev = pcidev ? &pcidev->qdev : NULL;
1174     } else if (isa_bus) {
1175         ISADevice *isadev = isa_vga_init(isa_bus);
1176         dev = isadev ? DEVICE(isadev) : NULL;
1177     }
1178     rom_reset_order_override();
1179     return dev;
1180 }
1181 
1182 static const MemoryRegionOps ioport80_io_ops = {
1183     .write = ioport80_write,
1184     .read = ioport80_read,
1185     .endianness = DEVICE_NATIVE_ENDIAN,
1186     .impl = {
1187         .min_access_size = 1,
1188         .max_access_size = 1,
1189     },
1190 };
1191 
1192 static const MemoryRegionOps ioportF0_io_ops = {
1193     .write = ioportF0_write,
1194     .read = ioportF0_read,
1195     .endianness = DEVICE_NATIVE_ENDIAN,
1196     .impl = {
1197         .min_access_size = 1,
1198         .max_access_size = 1,
1199     },
1200 };
1201 
1202 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl,
1203                             bool create_i8042, bool no_vmport)
1204 {
1205     int i;
1206     DriveInfo *fd[MAX_FD];
1207     qemu_irq *a20_line;
1208     ISADevice *fdc, *i8042, *port92, *vmmouse;
1209 
1210     serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS);
1211     parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
1212 
1213     for (i = 0; i < MAX_FD; i++) {
1214         fd[i] = drive_get(IF_FLOPPY, 0, i);
1215         create_fdctrl |= !!fd[i];
1216     }
1217     if (create_fdctrl) {
1218         fdc = isa_new(TYPE_ISA_FDC);
1219         if (fdc) {
1220             isa_realize_and_unref(fdc, isa_bus, &error_fatal);
1221             isa_fdc_init_drives(fdc, fd);
1222         }
1223     }
1224 
1225     if (!create_i8042) {
1226         return;
1227     }
1228 
1229     i8042 = isa_create_simple(isa_bus, TYPE_I8042);
1230     if (!no_vmport) {
1231         isa_create_simple(isa_bus, TYPE_VMPORT);
1232         vmmouse = isa_try_new("vmmouse");
1233     } else {
1234         vmmouse = NULL;
1235     }
1236     if (vmmouse) {
1237         object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042),
1238                                  &error_abort);
1239         isa_realize_and_unref(vmmouse, isa_bus, &error_fatal);
1240     }
1241     port92 = isa_create_simple(isa_bus, TYPE_PORT92);
1242 
1243     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1244     i8042_setup_a20_line(i8042, a20_line[0]);
1245     qdev_connect_gpio_out_named(DEVICE(port92),
1246                                 PORT92_A20_LINE, 0, a20_line[1]);
1247     g_free(a20_line);
1248 }
1249 
1250 void pc_basic_device_init(struct PCMachineState *pcms,
1251                           ISABus *isa_bus, qemu_irq *gsi,
1252                           ISADevice **rtc_state,
1253                           bool create_fdctrl,
1254                           uint32_t hpet_irqs)
1255 {
1256     int i;
1257     DeviceState *hpet = NULL;
1258     int pit_isa_irq = 0;
1259     qemu_irq pit_alt_irq = NULL;
1260     qemu_irq rtc_irq = NULL;
1261     ISADevice *pit = NULL;
1262     MemoryRegion *ioport80_io = g_new(MemoryRegion, 1);
1263     MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1);
1264     X86MachineState *x86ms = X86_MACHINE(pcms);
1265 
1266     memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1);
1267     memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io);
1268 
1269     memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1);
1270     memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io);
1271 
1272     /*
1273      * Check if an HPET shall be created.
1274      *
1275      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1276      * when the HPET wants to take over. Thus we have to disable the latter.
1277      */
1278     if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() ||
1279                                kvm_has_pit_state2())) {
1280         hpet = qdev_try_new(TYPE_HPET);
1281         if (!hpet) {
1282             error_report("couldn't create HPET device");
1283             exit(1);
1284         }
1285         /*
1286          * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and
1287          * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and
1288          * IRQ2.
1289          */
1290         uint8_t compat = object_property_get_uint(OBJECT(hpet),
1291                 HPET_INTCAP, NULL);
1292         if (!compat) {
1293             qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs);
1294         }
1295         sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal);
1296         sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE);
1297 
1298         for (i = 0; i < GSI_NUM_PINS; i++) {
1299             sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]);
1300         }
1301         pit_isa_irq = -1;
1302         pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1303         rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1304     }
1305     *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
1306 
1307     qemu_register_boot_set(pc_boot_set, *rtc_state);
1308 
1309     if (!xen_enabled() &&
1310         (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
1311         if (kvm_pit_in_kernel()) {
1312             pit = kvm_pit_init(isa_bus, 0x40);
1313         } else {
1314             pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1315         }
1316         if (hpet) {
1317             /* connect PIT to output control line of the HPET */
1318             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0));
1319         }
1320         pcspk_init(pcms->pcspk, isa_bus, pit);
1321     }
1322 
1323     i8257_dma_init(isa_bus, 0);
1324 
1325     /* Super I/O */
1326     pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled,
1327                     pcms->vmport != ON_OFF_AUTO_ON);
1328 }
1329 
1330 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus)
1331 {
1332     int i;
1333 
1334     rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC);
1335     for (i = 0; i < nb_nics; i++) {
1336         NICInfo *nd = &nd_table[i];
1337         const char *model = nd->model ? nd->model : pcmc->default_nic_model;
1338 
1339         if (g_str_equal(model, "ne2k_isa")) {
1340             pc_init_ne2k_isa(isa_bus, nd);
1341         } else {
1342             pci_nic_init_nofail(nd, pci_bus, model, NULL);
1343         }
1344     }
1345     rom_reset_order_override();
1346 }
1347 
1348 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs)
1349 {
1350     qemu_irq *i8259;
1351 
1352     if (kvm_pic_in_kernel()) {
1353         i8259 = kvm_i8259_init(isa_bus);
1354     } else if (xen_enabled()) {
1355         i8259 = xen_interrupt_controller_init();
1356     } else {
1357         i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq());
1358     }
1359 
1360     for (size_t i = 0; i < ISA_NUM_IRQS; i++) {
1361         i8259_irqs[i] = i8259[i];
1362     }
1363 
1364     g_free(i8259);
1365 }
1366 
1367 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
1368                                Error **errp)
1369 {
1370     const PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1371     const X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1372     const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
1373     const MachineState *ms = MACHINE(hotplug_dev);
1374     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1375     const uint64_t legacy_align = TARGET_PAGE_SIZE;
1376     Error *local_err = NULL;
1377 
1378     /*
1379      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1380      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1381      * addition to cover this case.
1382      */
1383     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1384         error_setg(errp,
1385                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1386         return;
1387     }
1388 
1389     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
1390         error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'");
1391         return;
1392     }
1393 
1394     hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err);
1395     if (local_err) {
1396         error_propagate(errp, local_err);
1397         return;
1398     }
1399 
1400     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev),
1401                      pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp);
1402 }
1403 
1404 static void pc_memory_plug(HotplugHandler *hotplug_dev,
1405                            DeviceState *dev, Error **errp)
1406 {
1407     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1408     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1409     MachineState *ms = MACHINE(hotplug_dev);
1410     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
1411 
1412     pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms));
1413 
1414     if (is_nvdimm) {
1415         nvdimm_plug(ms->nvdimms_state);
1416     }
1417 
1418     hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort);
1419 }
1420 
1421 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev,
1422                                      DeviceState *dev, Error **errp)
1423 {
1424     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1425 
1426     /*
1427      * When -no-acpi is used with Q35 machine type, no ACPI is built,
1428      * but pcms->acpi_dev is still created. Check !acpi_enabled in
1429      * addition to cover this case.
1430      */
1431     if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) {
1432         error_setg(errp,
1433                    "memory hotplug is not enabled: missing acpi device or acpi disabled");
1434         return;
1435     }
1436 
1437     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
1438         error_setg(errp, "nvdimm device hot unplug is not supported yet.");
1439         return;
1440     }
1441 
1442     hotplug_handler_unplug_request(x86ms->acpi_dev, dev,
1443                                    errp);
1444 }
1445 
1446 static void pc_memory_unplug(HotplugHandler *hotplug_dev,
1447                              DeviceState *dev, Error **errp)
1448 {
1449     PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1450     X86MachineState *x86ms = X86_MACHINE(hotplug_dev);
1451     Error *local_err = NULL;
1452 
1453     hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err);
1454     if (local_err) {
1455         goto out;
1456     }
1457 
1458     pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms));
1459     qdev_unrealize(dev);
1460  out:
1461     error_propagate(errp, local_err);
1462 }
1463 
1464 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev,
1465                                       DeviceState *dev, Error **errp)
1466 {
1467     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1468     Error *local_err = NULL;
1469 
1470     if (!hotplug_dev2 && dev->hotplugged) {
1471         /*
1472          * Without a bus hotplug handler, we cannot control the plug/unplug
1473          * order. We should never reach this point when hotplugging on x86,
1474          * however, better add a safety net.
1475          */
1476         error_setg(errp, "hotplug of virtio based memory devices not supported"
1477                    " on this bus.");
1478         return;
1479     }
1480     /*
1481      * First, see if we can plug this memory device at all. If that
1482      * succeeds, branch of to the actual hotplug handler.
1483      */
1484     memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL,
1485                            &local_err);
1486     if (!local_err && hotplug_dev2) {
1487         hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err);
1488     }
1489     error_propagate(errp, local_err);
1490 }
1491 
1492 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev,
1493                                   DeviceState *dev, Error **errp)
1494 {
1495     HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev);
1496     Error *local_err = NULL;
1497 
1498     /*
1499      * Plug the memory device first and then branch off to the actual
1500      * hotplug handler. If that one fails, we can easily undo the memory
1501      * device bits.
1502      */
1503     memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1504     if (hotplug_dev2) {
1505         hotplug_handler_plug(hotplug_dev2, dev, &local_err);
1506         if (local_err) {
1507             memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev));
1508         }
1509     }
1510     error_propagate(errp, local_err);
1511 }
1512 
1513 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev,
1514                                             DeviceState *dev, Error **errp)
1515 {
1516     /* We don't support hot unplug of virtio based memory devices */
1517     error_setg(errp, "virtio based memory devices cannot be unplugged.");
1518 }
1519 
1520 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev,
1521                                     DeviceState *dev, Error **errp)
1522 {
1523     /* We don't support hot unplug of virtio based memory devices */
1524 }
1525 
1526 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
1527                                           DeviceState *dev, Error **errp)
1528 {
1529     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1530         pc_memory_pre_plug(hotplug_dev, dev, errp);
1531     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1532         x86_cpu_pre_plug(hotplug_dev, dev, errp);
1533     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1534                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1535         pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp);
1536     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1537         /* Declare the APIC range as the reserved MSI region */
1538         char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d",
1539                                               VIRTIO_IOMMU_RESV_MEM_T_MSI);
1540 
1541         object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
1542         object_property_set_str(OBJECT(dev), "reserved-regions[0]",
1543                                 resv_prop_str, errp);
1544         g_free(resv_prop_str);
1545     }
1546 
1547     if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) ||
1548         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
1549         PCMachineState *pcms = PC_MACHINE(hotplug_dev);
1550 
1551         if (pcms->iommu) {
1552             error_setg(errp, "QEMU does not support multiple vIOMMUs "
1553                        "for x86 yet.");
1554             return;
1555         }
1556         pcms->iommu = dev;
1557     }
1558 }
1559 
1560 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1561                                       DeviceState *dev, Error **errp)
1562 {
1563     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1564         pc_memory_plug(hotplug_dev, dev, errp);
1565     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1566         x86_cpu_plug(hotplug_dev, dev, errp);
1567     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1568                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1569         pc_virtio_md_pci_plug(hotplug_dev, dev, errp);
1570     }
1571 }
1572 
1573 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
1574                                                 DeviceState *dev, Error **errp)
1575 {
1576     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1577         pc_memory_unplug_request(hotplug_dev, dev, errp);
1578     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1579         x86_cpu_unplug_request_cb(hotplug_dev, dev, errp);
1580     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1581                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1582         pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp);
1583     } else {
1584         error_setg(errp, "acpi: device unplug request for not supported device"
1585                    " type: %s", object_get_typename(OBJECT(dev)));
1586     }
1587 }
1588 
1589 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
1590                                         DeviceState *dev, Error **errp)
1591 {
1592     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
1593         pc_memory_unplug(hotplug_dev, dev, errp);
1594     } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
1595         x86_cpu_unplug_cb(hotplug_dev, dev, errp);
1596     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1597                object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) {
1598         pc_virtio_md_pci_unplug(hotplug_dev, dev, errp);
1599     } else {
1600         error_setg(errp, "acpi: device unplug for not supported device"
1601                    " type: %s", object_get_typename(OBJECT(dev)));
1602     }
1603 }
1604 
1605 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine,
1606                                              DeviceState *dev)
1607 {
1608     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
1609         object_dynamic_cast(OBJECT(dev), TYPE_CPU) ||
1610         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) ||
1611         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) ||
1612         object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) ||
1613         object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) {
1614         return HOTPLUG_HANDLER(machine);
1615     }
1616 
1617     return NULL;
1618 }
1619 
1620 static void
1621 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v,
1622                                          const char *name, void *opaque,
1623                                          Error **errp)
1624 {
1625     MachineState *ms = MACHINE(obj);
1626     int64_t value = 0;
1627 
1628     if (ms->device_memory) {
1629         value = memory_region_size(&ms->device_memory->mr);
1630     }
1631 
1632     visit_type_int(v, name, &value, errp);
1633 }
1634 
1635 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name,
1636                                   void *opaque, Error **errp)
1637 {
1638     PCMachineState *pcms = PC_MACHINE(obj);
1639     OnOffAuto vmport = pcms->vmport;
1640 
1641     visit_type_OnOffAuto(v, name, &vmport, errp);
1642 }
1643 
1644 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name,
1645                                   void *opaque, Error **errp)
1646 {
1647     PCMachineState *pcms = PC_MACHINE(obj);
1648 
1649     visit_type_OnOffAuto(v, name, &pcms->vmport, errp);
1650 }
1651 
1652 static bool pc_machine_get_smbus(Object *obj, Error **errp)
1653 {
1654     PCMachineState *pcms = PC_MACHINE(obj);
1655 
1656     return pcms->smbus_enabled;
1657 }
1658 
1659 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp)
1660 {
1661     PCMachineState *pcms = PC_MACHINE(obj);
1662 
1663     pcms->smbus_enabled = value;
1664 }
1665 
1666 static bool pc_machine_get_sata(Object *obj, Error **errp)
1667 {
1668     PCMachineState *pcms = PC_MACHINE(obj);
1669 
1670     return pcms->sata_enabled;
1671 }
1672 
1673 static void pc_machine_set_sata(Object *obj, bool value, Error **errp)
1674 {
1675     PCMachineState *pcms = PC_MACHINE(obj);
1676 
1677     pcms->sata_enabled = value;
1678 }
1679 
1680 static bool pc_machine_get_hpet(Object *obj, Error **errp)
1681 {
1682     PCMachineState *pcms = PC_MACHINE(obj);
1683 
1684     return pcms->hpet_enabled;
1685 }
1686 
1687 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp)
1688 {
1689     PCMachineState *pcms = PC_MACHINE(obj);
1690 
1691     pcms->hpet_enabled = value;
1692 }
1693 
1694 static bool pc_machine_get_i8042(Object *obj, Error **errp)
1695 {
1696     PCMachineState *pcms = PC_MACHINE(obj);
1697 
1698     return pcms->i8042_enabled;
1699 }
1700 
1701 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp)
1702 {
1703     PCMachineState *pcms = PC_MACHINE(obj);
1704 
1705     pcms->i8042_enabled = value;
1706 }
1707 
1708 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp)
1709 {
1710     PCMachineState *pcms = PC_MACHINE(obj);
1711 
1712     return pcms->default_bus_bypass_iommu;
1713 }
1714 
1715 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value,
1716                                                     Error **errp)
1717 {
1718     PCMachineState *pcms = PC_MACHINE(obj);
1719 
1720     pcms->default_bus_bypass_iommu = value;
1721 }
1722 
1723 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name,
1724                                      void *opaque, Error **errp)
1725 {
1726     PCMachineState *pcms = PC_MACHINE(obj);
1727     SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type;
1728 
1729     visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp);
1730 }
1731 
1732 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name,
1733                                      void *opaque, Error **errp)
1734 {
1735     PCMachineState *pcms = PC_MACHINE(obj);
1736 
1737     visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp);
1738 }
1739 
1740 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v,
1741                                             const char *name, void *opaque,
1742                                             Error **errp)
1743 {
1744     PCMachineState *pcms = PC_MACHINE(obj);
1745     uint64_t value = pcms->max_ram_below_4g;
1746 
1747     visit_type_size(v, name, &value, errp);
1748 }
1749 
1750 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
1751                                             const char *name, void *opaque,
1752                                             Error **errp)
1753 {
1754     PCMachineState *pcms = PC_MACHINE(obj);
1755     uint64_t value;
1756 
1757     if (!visit_type_size(v, name, &value, errp)) {
1758         return;
1759     }
1760     if (value > 4 * GiB) {
1761         error_setg(errp,
1762                    "Machine option 'max-ram-below-4g=%"PRIu64
1763                    "' expects size less than or equal to 4G", value);
1764         return;
1765     }
1766 
1767     if (value < 1 * MiB) {
1768         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
1769                     "BIOS may not work with less than 1MiB", value);
1770     }
1771 
1772     pcms->max_ram_below_4g = value;
1773 }
1774 
1775 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v,
1776                                        const char *name, void *opaque,
1777                                        Error **errp)
1778 {
1779     PCMachineState *pcms = PC_MACHINE(obj);
1780     uint64_t value = pcms->max_fw_size;
1781 
1782     visit_type_size(v, name, &value, errp);
1783 }
1784 
1785 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v,
1786                                        const char *name, void *opaque,
1787                                        Error **errp)
1788 {
1789     PCMachineState *pcms = PC_MACHINE(obj);
1790     Error *error = NULL;
1791     uint64_t value;
1792 
1793     visit_type_size(v, name, &value, &error);
1794     if (error) {
1795         error_propagate(errp, error);
1796         return;
1797     }
1798 
1799     /*
1800     * We don't have a theoretically justifiable exact lower bound on the base
1801     * address of any flash mapping. In practice, the IO-APIC MMIO range is
1802     * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free
1803     * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
1804     * size.
1805     */
1806     if (value > 16 * MiB) {
1807         error_setg(errp,
1808                    "User specified max allowed firmware size %" PRIu64 " is "
1809                    "greater than 16MiB. If combined firwmare size exceeds "
1810                    "16MiB the system may not boot, or experience intermittent"
1811                    "stability issues.",
1812                    value);
1813         return;
1814     }
1815 
1816     pcms->max_fw_size = value;
1817 }
1818 
1819 
1820 static void pc_machine_initfn(Object *obj)
1821 {
1822     PCMachineState *pcms = PC_MACHINE(obj);
1823 
1824 #ifdef CONFIG_VMPORT
1825     pcms->vmport = ON_OFF_AUTO_AUTO;
1826 #else
1827     pcms->vmport = ON_OFF_AUTO_OFF;
1828 #endif /* CONFIG_VMPORT */
1829     pcms->max_ram_below_4g = 0; /* use default */
1830     pcms->smbios_entry_point_type = SMBIOS_ENTRY_POINT_TYPE_32;
1831 
1832     /* acpi build is enabled by default if machine supports it */
1833     pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build;
1834     pcms->smbus_enabled = true;
1835     pcms->sata_enabled = true;
1836     pcms->i8042_enabled = true;
1837     pcms->max_fw_size = 8 * MiB;
1838 #ifdef CONFIG_HPET
1839     pcms->hpet_enabled = true;
1840 #endif
1841     pcms->default_bus_bypass_iommu = false;
1842 
1843     pc_system_flash_create(pcms);
1844     pcms->pcspk = isa_new(TYPE_PC_SPEAKER);
1845     object_property_add_alias(OBJECT(pcms), "pcspk-audiodev",
1846                               OBJECT(pcms->pcspk), "audiodev");
1847     cxl_machine_init(obj, &pcms->cxl_devices_state);
1848 }
1849 
1850 static void pc_machine_reset(MachineState *machine)
1851 {
1852     CPUState *cs;
1853     X86CPU *cpu;
1854 
1855     qemu_devices_reset();
1856 
1857     /* Reset APIC after devices have been reset to cancel
1858      * any changes that qemu_devices_reset() might have done.
1859      */
1860     CPU_FOREACH(cs) {
1861         cpu = X86_CPU(cs);
1862 
1863         x86_cpu_after_reset(cpu);
1864     }
1865 }
1866 
1867 static void pc_machine_wakeup(MachineState *machine)
1868 {
1869     cpu_synchronize_all_states();
1870     pc_machine_reset(machine);
1871     cpu_synchronize_all_post_reset();
1872 }
1873 
1874 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp)
1875 {
1876     X86IOMMUState *iommu = x86_iommu_get_default();
1877     IntelIOMMUState *intel_iommu;
1878 
1879     if (iommu &&
1880         object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) &&
1881         object_dynamic_cast((Object *)dev, "vfio-pci")) {
1882         intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1883         if (!intel_iommu->caching_mode) {
1884             error_setg(errp, "Device assignment is not allowed without "
1885                        "enabling caching-mode=on for Intel IOMMU.");
1886             return false;
1887         }
1888     }
1889 
1890     return true;
1891 }
1892 
1893 static void pc_machine_class_init(ObjectClass *oc, void *data)
1894 {
1895     MachineClass *mc = MACHINE_CLASS(oc);
1896     PCMachineClass *pcmc = PC_MACHINE_CLASS(oc);
1897     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1898 
1899     pcmc->pci_enabled = true;
1900     pcmc->has_acpi_build = true;
1901     pcmc->rsdp_in_ram = true;
1902     pcmc->smbios_defaults = true;
1903     pcmc->smbios_uuid_encoded = true;
1904     pcmc->gigabyte_align = true;
1905     pcmc->has_reserved_memory = true;
1906     pcmc->kvmclock_enabled = true;
1907     pcmc->enforce_aligned_dimm = true;
1908     pcmc->enforce_amd_1tb_hole = true;
1909     /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported
1910      * to be used at the moment, 32K should be enough for a while.  */
1911     pcmc->acpi_data_size = 0x20000 + 0x8000;
1912     pcmc->pvh_enabled = true;
1913     pcmc->kvmclock_create_always = true;
1914     assert(!mc->get_hotplug_handler);
1915     mc->get_hotplug_handler = pc_get_hotplug_handler;
1916     mc->hotplug_allowed = pc_hotplug_allowed;
1917     mc->cpu_index_to_instance_props = x86_cpu_index_to_props;
1918     mc->get_default_cpu_node_id = x86_get_default_cpu_node_id;
1919     mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids;
1920     mc->auto_enable_numa_with_memhp = true;
1921     mc->auto_enable_numa_with_memdev = true;
1922     mc->has_hotpluggable_cpus = true;
1923     mc->default_boot_order = "cad";
1924     mc->block_default_type = IF_IDE;
1925     mc->max_cpus = 255;
1926     mc->reset = pc_machine_reset;
1927     mc->wakeup = pc_machine_wakeup;
1928     hc->pre_plug = pc_machine_device_pre_plug_cb;
1929     hc->plug = pc_machine_device_plug_cb;
1930     hc->unplug_request = pc_machine_device_unplug_request_cb;
1931     hc->unplug = pc_machine_device_unplug_cb;
1932     mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE;
1933     mc->nvdimm_supported = true;
1934     mc->smp_props.dies_supported = true;
1935     mc->default_ram_id = "pc.ram";
1936 
1937     object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size",
1938         pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g,
1939         NULL, NULL);
1940     object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G,
1941         "Maximum ram below the 4G boundary (32bit boundary)");
1942 
1943     object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int",
1944         pc_machine_get_device_memory_region_size, NULL,
1945         NULL, NULL);
1946 
1947     object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto",
1948         pc_machine_get_vmport, pc_machine_set_vmport,
1949         NULL, NULL);
1950     object_class_property_set_description(oc, PC_MACHINE_VMPORT,
1951         "Enable vmport (pc & q35)");
1952 
1953     object_class_property_add_bool(oc, PC_MACHINE_SMBUS,
1954         pc_machine_get_smbus, pc_machine_set_smbus);
1955     object_class_property_set_description(oc, PC_MACHINE_SMBUS,
1956         "Enable/disable system management bus");
1957 
1958     object_class_property_add_bool(oc, PC_MACHINE_SATA,
1959         pc_machine_get_sata, pc_machine_set_sata);
1960     object_class_property_set_description(oc, PC_MACHINE_SATA,
1961         "Enable/disable Serial ATA bus");
1962 
1963     object_class_property_add_bool(oc, "hpet",
1964         pc_machine_get_hpet, pc_machine_set_hpet);
1965     object_class_property_set_description(oc, "hpet",
1966         "Enable/disable high precision event timer emulation");
1967 
1968     object_class_property_add_bool(oc, PC_MACHINE_I8042,
1969         pc_machine_get_i8042, pc_machine_set_i8042);
1970 
1971     object_class_property_add_bool(oc, "default-bus-bypass-iommu",
1972         pc_machine_get_default_bus_bypass_iommu,
1973         pc_machine_set_default_bus_bypass_iommu);
1974 
1975     object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size",
1976         pc_machine_get_max_fw_size, pc_machine_set_max_fw_size,
1977         NULL, NULL);
1978     object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE,
1979         "Maximum combined firmware size");
1980 
1981     object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str",
1982         pc_machine_get_smbios_ep, pc_machine_set_smbios_ep,
1983         NULL, NULL);
1984     object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP,
1985         "SMBIOS Entry Point type [32, 64]");
1986 }
1987 
1988 static const TypeInfo pc_machine_info = {
1989     .name = TYPE_PC_MACHINE,
1990     .parent = TYPE_X86_MACHINE,
1991     .abstract = true,
1992     .instance_size = sizeof(PCMachineState),
1993     .instance_init = pc_machine_initfn,
1994     .class_size = sizeof(PCMachineClass),
1995     .class_init = pc_machine_class_init,
1996     .interfaces = (InterfaceInfo[]) {
1997          { TYPE_HOTPLUG_HANDLER },
1998          { }
1999     },
2000 };
2001 
2002 static void pc_machine_register_types(void)
2003 {
2004     type_register_static(&pc_machine_info);
2005 }
2006 
2007 type_init(pc_machine_register_types)
2008