1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_9_0[] = { 83 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 84 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 85 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 86 { "sev-guest", "legacy-vm-type", "on" }, 87 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 88 }; 89 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 90 91 GlobalProperty pc_compat_8_2[] = {}; 92 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 93 94 GlobalProperty pc_compat_8_1[] = {}; 95 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 96 97 GlobalProperty pc_compat_8_0[] = { 98 { "virtio-mem", "unplugged-inaccessible", "auto" }, 99 }; 100 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 101 102 GlobalProperty pc_compat_7_2[] = { 103 { "ICH9-LPC", "noreboot", "true" }, 104 }; 105 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 106 107 GlobalProperty pc_compat_7_1[] = {}; 108 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 109 110 GlobalProperty pc_compat_7_0[] = {}; 111 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 112 113 GlobalProperty pc_compat_6_2[] = { 114 { "virtio-mem", "unplugged-inaccessible", "off" }, 115 }; 116 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 117 118 GlobalProperty pc_compat_6_1[] = { 119 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 120 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 121 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 122 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 123 }; 124 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 125 126 GlobalProperty pc_compat_6_0[] = { 127 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 128 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 129 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 130 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 131 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 132 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 133 }; 134 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 135 136 GlobalProperty pc_compat_5_2[] = { 137 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 138 }; 139 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 140 141 GlobalProperty pc_compat_5_1[] = { 142 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 143 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 144 }; 145 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 146 147 GlobalProperty pc_compat_5_0[] = { 148 }; 149 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 150 151 GlobalProperty pc_compat_4_2[] = { 152 { "mch", "smbase-smram", "off" }, 153 }; 154 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 155 156 GlobalProperty pc_compat_4_1[] = {}; 157 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 158 159 GlobalProperty pc_compat_4_0[] = {}; 160 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 161 162 GlobalProperty pc_compat_3_1[] = { 163 { "intel-iommu", "dma-drain", "off" }, 164 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 165 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 166 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 167 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 168 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 169 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 170 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 171 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 172 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 173 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 174 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 175 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 176 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 177 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 178 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 179 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 180 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 181 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 182 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 183 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 184 }; 185 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 186 187 GlobalProperty pc_compat_3_0[] = { 188 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 189 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 190 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 191 }; 192 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 193 194 GlobalProperty pc_compat_2_12[] = { 195 { TYPE_X86_CPU, "legacy-cache", "on" }, 196 { TYPE_X86_CPU, "topoext", "off" }, 197 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 198 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 199 }; 200 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 201 202 GlobalProperty pc_compat_2_11[] = { 203 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 204 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 205 }; 206 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 207 208 GlobalProperty pc_compat_2_10[] = { 209 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 210 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 211 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 212 }; 213 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 214 215 GlobalProperty pc_compat_2_9[] = { 216 { "mch", "extended-tseg-mbytes", "0" }, 217 }; 218 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 219 220 GlobalProperty pc_compat_2_8[] = { 221 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 222 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 223 { "ICH9-LPC", "x-smi-broadcast", "off" }, 224 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 225 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 226 }; 227 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 228 229 GlobalProperty pc_compat_2_7[] = { 230 { TYPE_X86_CPU, "l3-cache", "off" }, 231 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 232 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 233 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 234 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 235 { "isa-pcspk", "migrate", "off" }, 236 }; 237 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 238 239 GlobalProperty pc_compat_2_6[] = { 240 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 241 { "vmxnet3", "romfile", "" }, 242 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 243 { "apic-common", "legacy-instance-id", "on", } 244 }; 245 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 246 247 GlobalProperty pc_compat_2_5[] = {}; 248 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 249 250 GlobalProperty pc_compat_2_4[] = { 251 PC_CPU_MODEL_IDS("2.4.0") 252 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 253 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 254 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 255 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 256 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 257 { TYPE_X86_CPU, "check", "off" }, 258 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 259 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 260 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 261 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 262 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 263 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 264 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 265 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 266 }; 267 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 268 269 /* 270 * @PC_FW_DATA: 271 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 272 * and other BIOS datastructures. 273 * 274 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 275 * reported to be used at the moment, 32K should be enough for a while. 276 */ 277 #define PC_FW_DATA (0x20000 + 0x8000) 278 279 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 280 { 281 GSIState *s; 282 283 s = g_new0(GSIState, 1); 284 if (kvm_ioapic_in_kernel()) { 285 kvm_pc_setup_irq_routing(pci_enabled); 286 } 287 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 288 289 return s; 290 } 291 292 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 293 unsigned size) 294 { 295 } 296 297 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 298 { 299 return 0xffffffffffffffffULL; 300 } 301 302 /* MS-DOS compatibility mode FPU exception support */ 303 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 304 unsigned size) 305 { 306 if (tcg_enabled()) { 307 cpu_set_ignne(); 308 } 309 } 310 311 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 312 { 313 return 0xffffffffffffffffULL; 314 } 315 316 /* PC cmos mappings */ 317 318 #define REG_EQUIPMENT_BYTE 0x14 319 320 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 321 int16_t cylinders, int8_t heads, int8_t sectors) 322 { 323 mc146818rtc_set_cmos_data(s, type_ofs, 47); 324 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 325 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 326 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 327 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 328 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 329 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 330 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 331 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 332 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 333 } 334 335 /* convert boot_device letter to something recognizable by the bios */ 336 static int boot_device2nibble(char boot_device) 337 { 338 switch(boot_device) { 339 case 'a': 340 case 'b': 341 return 0x01; /* floppy boot */ 342 case 'c': 343 return 0x02; /* hard drive boot */ 344 case 'd': 345 return 0x03; /* CD-ROM boot */ 346 case 'n': 347 return 0x04; /* Network boot */ 348 } 349 return 0; 350 } 351 352 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 353 const char *boot_device, Error **errp) 354 { 355 #define PC_MAX_BOOT_DEVICES 3 356 int nbds, bds[3] = { 0, }; 357 int i; 358 359 nbds = strlen(boot_device); 360 if (nbds > PC_MAX_BOOT_DEVICES) { 361 error_setg(errp, "Too many boot devices for PC"); 362 return; 363 } 364 for (i = 0; i < nbds; i++) { 365 bds[i] = boot_device2nibble(boot_device[i]); 366 if (bds[i] == 0) { 367 error_setg(errp, "Invalid boot device for PC: '%c'", 368 boot_device[i]); 369 return; 370 } 371 } 372 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 373 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 374 } 375 376 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 377 { 378 PCMachineState *pcms = opaque; 379 X86MachineState *x86ms = X86_MACHINE(pcms); 380 381 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 382 } 383 384 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 385 { 386 int val, nb; 387 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 388 FLOPPY_DRIVE_TYPE_NONE }; 389 390 #ifdef CONFIG_FDC_ISA 391 /* floppy type */ 392 if (floppy) { 393 for (int i = 0; i < 2; i++) { 394 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 395 } 396 } 397 #endif 398 399 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 400 cmos_get_fd_drive_type(fd_type[1]); 401 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 402 403 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 404 nb = 0; 405 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 406 nb++; 407 } 408 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 409 nb++; 410 } 411 switch (nb) { 412 case 0: 413 break; 414 case 1: 415 val |= 0x01; /* 1 drive, ready for boot */ 416 break; 417 case 2: 418 val |= 0x41; /* 2 drives, ready for boot */ 419 break; 420 } 421 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 422 } 423 424 typedef struct check_fdc_state { 425 ISADevice *floppy; 426 bool multiple; 427 } CheckFdcState; 428 429 static int check_fdc(Object *obj, void *opaque) 430 { 431 CheckFdcState *state = opaque; 432 Object *fdc; 433 uint32_t iobase; 434 Error *local_err = NULL; 435 436 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 437 if (!fdc) { 438 return 0; 439 } 440 441 iobase = object_property_get_uint(obj, "iobase", &local_err); 442 if (local_err || iobase != 0x3f0) { 443 error_free(local_err); 444 return 0; 445 } 446 447 if (state->floppy) { 448 state->multiple = true; 449 } else { 450 state->floppy = ISA_DEVICE(obj); 451 } 452 return 0; 453 } 454 455 static const char * const fdc_container_path[] = { 456 "/unattached", "/peripheral", "/peripheral-anon" 457 }; 458 459 /* 460 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 461 * and ACPI objects. 462 */ 463 static ISADevice *pc_find_fdc0(void) 464 { 465 int i; 466 Object *container; 467 CheckFdcState state = { 0 }; 468 469 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 470 container = container_get(qdev_get_machine(), fdc_container_path[i]); 471 object_child_foreach(container, check_fdc, &state); 472 } 473 474 if (state.multiple) { 475 warn_report("multiple floppy disk controllers with " 476 "iobase=0x3f0 have been found"); 477 error_printf("the one being picked for CMOS setup might not reflect " 478 "your intent"); 479 } 480 481 return state.floppy; 482 } 483 484 static void pc_cmos_init_late(PCMachineState *pcms) 485 { 486 X86MachineState *x86ms = X86_MACHINE(pcms); 487 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 488 int16_t cylinders; 489 int8_t heads, sectors; 490 int val; 491 int i, trans; 492 493 val = 0; 494 if (pcms->idebus[0] && 495 ide_get_geometry(pcms->idebus[0], 0, 496 &cylinders, &heads, §ors) >= 0) { 497 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 498 val |= 0xf0; 499 } 500 if (pcms->idebus[0] && 501 ide_get_geometry(pcms->idebus[0], 1, 502 &cylinders, &heads, §ors) >= 0) { 503 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 504 val |= 0x0f; 505 } 506 mc146818rtc_set_cmos_data(s, 0x12, val); 507 508 val = 0; 509 for (i = 0; i < 4; i++) { 510 /* NOTE: ide_get_geometry() returns the physical 511 geometry. It is always such that: 1 <= sects <= 63, 1 512 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 513 geometry can be different if a translation is done. */ 514 BusState *idebus = pcms->idebus[i / 2]; 515 if (idebus && 516 ide_get_geometry(idebus, i % 2, 517 &cylinders, &heads, §ors) >= 0) { 518 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 519 assert((trans & ~3) == 0); 520 val |= trans << (i * 2); 521 } 522 } 523 mc146818rtc_set_cmos_data(s, 0x39, val); 524 525 pc_cmos_init_floppy(s, pc_find_fdc0()); 526 527 /* various important CMOS locations needed by PC/Bochs bios */ 528 529 /* memory size */ 530 /* base memory (first MiB) */ 531 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 532 mc146818rtc_set_cmos_data(s, 0x15, val); 533 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 534 /* extended memory (next 64MiB) */ 535 if (x86ms->below_4g_mem_size > 1 * MiB) { 536 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 537 } else { 538 val = 0; 539 } 540 if (val > 65535) 541 val = 65535; 542 mc146818rtc_set_cmos_data(s, 0x17, val); 543 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 544 mc146818rtc_set_cmos_data(s, 0x30, val); 545 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 546 /* memory between 16MiB and 4GiB */ 547 if (x86ms->below_4g_mem_size > 16 * MiB) { 548 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 549 } else { 550 val = 0; 551 } 552 if (val > 65535) 553 val = 65535; 554 mc146818rtc_set_cmos_data(s, 0x34, val); 555 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 556 /* memory above 4GiB */ 557 val = x86ms->above_4g_mem_size / 65536; 558 mc146818rtc_set_cmos_data(s, 0x5b, val); 559 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 560 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 561 562 val = 0; 563 val |= 0x02; /* FPU is there */ 564 val |= 0x04; /* PS/2 mouse installed */ 565 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 566 } 567 568 static void handle_a20_line_change(void *opaque, int irq, int level) 569 { 570 X86CPU *cpu = opaque; 571 572 /* XXX: send to all CPUs ? */ 573 /* XXX: add logic to handle multiple A20 line sources */ 574 x86_cpu_set_a20(cpu, level); 575 } 576 577 #define NE2000_NB_MAX 6 578 579 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 580 0x280, 0x380 }; 581 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 582 583 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 584 { 585 static int nb_ne2k = 0; 586 587 if (nb_ne2k == NE2000_NB_MAX) { 588 error_setg(errp, 589 "maximum number of ISA NE2000 devices exceeded"); 590 return false; 591 } 592 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 593 ne2000_irq[nb_ne2k], nd); 594 nb_ne2k++; 595 return true; 596 } 597 598 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 599 { 600 X86CPU *cpu = opaque; 601 602 if (level) { 603 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 604 } 605 } 606 607 static 608 void pc_machine_done(Notifier *notifier, void *data) 609 { 610 PCMachineState *pcms = container_of(notifier, 611 PCMachineState, machine_done); 612 X86MachineState *x86ms = X86_MACHINE(pcms); 613 614 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 615 &error_fatal); 616 617 if (pcms->cxl_devices_state.is_enabled) { 618 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 619 } 620 621 /* set the number of CPUs */ 622 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 623 624 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 625 626 acpi_setup(); 627 if (x86ms->fw_cfg) { 628 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 629 fw_cfg_add_e820(x86ms->fw_cfg); 630 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 631 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 632 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 633 } 634 635 pc_cmos_init_late(pcms); 636 } 637 638 /* setup pci memory address space mapping into system address space */ 639 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 640 MemoryRegion *pci_address_space) 641 { 642 /* Set to lower priority than RAM */ 643 memory_region_add_subregion_overlap(system_memory, 0x0, 644 pci_address_space, -1); 645 } 646 647 void xen_load_linux(PCMachineState *pcms) 648 { 649 int i; 650 FWCfgState *fw_cfg; 651 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 652 X86MachineState *x86ms = X86_MACHINE(pcms); 653 654 assert(MACHINE(pcms)->kernel_filename != NULL); 655 656 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 657 &address_space_memory); 658 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 659 rom_set_fw(fw_cfg); 660 661 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 662 for (i = 0; i < nb_option_roms; i++) { 663 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 664 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 665 !strcmp(option_rom[i].name, "pvh.bin") || 666 !strcmp(option_rom[i].name, "multiboot.bin") || 667 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 668 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 669 } 670 x86ms->fw_cfg = fw_cfg; 671 } 672 673 #define PC_ROM_MIN_VGA 0xc0000 674 #define PC_ROM_MIN_OPTION 0xc8000 675 #define PC_ROM_MAX 0xe0000 676 #define PC_ROM_ALIGN 0x800 677 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 678 679 static hwaddr pc_above_4g_end(PCMachineState *pcms) 680 { 681 X86MachineState *x86ms = X86_MACHINE(pcms); 682 683 if (pcms->sgx_epc.size != 0) { 684 return sgx_epc_above_4g_end(&pcms->sgx_epc); 685 } 686 687 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 688 } 689 690 static void pc_get_device_memory_range(PCMachineState *pcms, 691 hwaddr *base, 692 ram_addr_t *device_mem_size) 693 { 694 MachineState *machine = MACHINE(pcms); 695 ram_addr_t size; 696 hwaddr addr; 697 698 size = machine->maxram_size - machine->ram_size; 699 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 700 701 /* size device region assuming 1G page max alignment per slot */ 702 size += (1 * GiB) * machine->ram_slots; 703 704 *base = addr; 705 *device_mem_size = size; 706 } 707 708 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 709 { 710 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 711 MachineState *ms = MACHINE(pcms); 712 hwaddr cxl_base; 713 ram_addr_t size; 714 715 if (pcmc->has_reserved_memory && 716 (ms->ram_size < ms->maxram_size)) { 717 pc_get_device_memory_range(pcms, &cxl_base, &size); 718 cxl_base += size; 719 } else { 720 cxl_base = pc_above_4g_end(pcms); 721 } 722 723 return cxl_base; 724 } 725 726 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 727 { 728 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 729 730 if (pcms->cxl_devices_state.fixed_windows) { 731 GList *it; 732 733 start = ROUND_UP(start, 256 * MiB); 734 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 735 CXLFixedWindow *fw = it->data; 736 start += fw->size; 737 } 738 } 739 740 return start; 741 } 742 743 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 744 { 745 X86CPU *cpu = X86_CPU(first_cpu); 746 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 747 MachineState *ms = MACHINE(pcms); 748 749 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 750 /* 64-bit systems */ 751 return pc_pci_hole64_start() + pci_hole64_size - 1; 752 } 753 754 /* 32-bit systems */ 755 if (pcmc->broken_32bit_mem_addr_check) { 756 /* old value for compatibility reasons */ 757 return ((hwaddr)1 << cpu->phys_bits) - 1; 758 } 759 760 /* 761 * 32-bit systems don't have hole64 but they might have a region for 762 * memory devices. Even if additional hotplugged memory devices might 763 * not be usable by most guest OSes, we need to still consider them for 764 * calculating the highest possible GPA so that we can properly report 765 * if someone configures them on a CPU that cannot possibly address them. 766 */ 767 if (pcmc->has_reserved_memory && 768 (ms->ram_size < ms->maxram_size)) { 769 hwaddr devmem_start; 770 ram_addr_t devmem_size; 771 772 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 773 devmem_start += devmem_size; 774 return devmem_start - 1; 775 } 776 777 /* configuration without any memory hotplug */ 778 return pc_above_4g_end(pcms) - 1; 779 } 780 781 /* 782 * AMD systems with an IOMMU have an additional hole close to the 783 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 784 * on kernel version, VFIO may or may not let you DMA map those ranges. 785 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 786 * with certain memory sizes. It's also wrong to use those IOVA ranges 787 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 788 * The ranges reserved for Hyper-Transport are: 789 * 790 * FD_0000_0000h - FF_FFFF_FFFFh 791 * 792 * The ranges represent the following: 793 * 794 * Base Address Top Address Use 795 * 796 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 797 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 798 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 799 * FD_F910_0000h FD_F91F_FFFFh System Management 800 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 801 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 802 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 803 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 804 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 805 * FE_2000_0000h FF_FFFF_FFFFh Reserved 806 * 807 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 808 * Table 3: Special Address Controls (GPA) for more information. 809 */ 810 #define AMD_HT_START 0xfd00000000UL 811 #define AMD_HT_END 0xffffffffffUL 812 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 813 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 814 815 void pc_memory_init(PCMachineState *pcms, 816 MemoryRegion *system_memory, 817 MemoryRegion *rom_memory, 818 uint64_t pci_hole64_size) 819 { 820 int linux_boot, i; 821 MemoryRegion *option_rom_mr; 822 MemoryRegion *ram_below_4g, *ram_above_4g; 823 FWCfgState *fw_cfg; 824 MachineState *machine = MACHINE(pcms); 825 MachineClass *mc = MACHINE_GET_CLASS(machine); 826 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 827 X86MachineState *x86ms = X86_MACHINE(pcms); 828 hwaddr maxphysaddr, maxusedaddr; 829 hwaddr cxl_base, cxl_resv_end = 0; 830 X86CPU *cpu = X86_CPU(first_cpu); 831 832 assert(machine->ram_size == x86ms->below_4g_mem_size + 833 x86ms->above_4g_mem_size); 834 835 linux_boot = (machine->kernel_filename != NULL); 836 837 /* 838 * The HyperTransport range close to the 1T boundary is unique to AMD 839 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 840 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 841 * older machine types (<= 7.0) for compatibility purposes. 842 */ 843 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 844 /* Bail out if max possible address does not cross HT range */ 845 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 846 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 847 } 848 849 /* 850 * Advertise the HT region if address space covers the reserved 851 * region or if we relocate. 852 */ 853 if (cpu->phys_bits >= 40) { 854 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 855 } 856 } 857 858 /* 859 * phys-bits is required to be appropriately configured 860 * to make sure max used GPA is reachable. 861 */ 862 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 863 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 864 if (maxphysaddr < maxusedaddr) { 865 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 866 " phys-bits too low (%u)", 867 maxphysaddr, maxusedaddr, cpu->phys_bits); 868 exit(EXIT_FAILURE); 869 } 870 871 /* 872 * Split single memory region and use aliases to address portions of it, 873 * done for backwards compatibility with older qemus. 874 */ 875 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 876 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 877 0, x86ms->below_4g_mem_size); 878 memory_region_add_subregion(system_memory, 0, ram_below_4g); 879 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 880 if (x86ms->above_4g_mem_size > 0) { 881 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 882 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 883 machine->ram, 884 x86ms->below_4g_mem_size, 885 x86ms->above_4g_mem_size); 886 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 887 ram_above_4g); 888 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 889 E820_RAM); 890 } 891 892 if (pcms->sgx_epc.size != 0) { 893 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 894 } 895 896 if (!pcmc->has_reserved_memory && 897 (machine->ram_slots || 898 (machine->maxram_size > machine->ram_size))) { 899 900 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 901 mc->name); 902 exit(EXIT_FAILURE); 903 } 904 905 /* initialize device memory address space */ 906 if (pcmc->has_reserved_memory && 907 (machine->ram_size < machine->maxram_size)) { 908 ram_addr_t device_mem_size; 909 hwaddr device_mem_base; 910 911 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 912 error_report("unsupported amount of memory slots: %"PRIu64, 913 machine->ram_slots); 914 exit(EXIT_FAILURE); 915 } 916 917 if (QEMU_ALIGN_UP(machine->maxram_size, 918 TARGET_PAGE_SIZE) != machine->maxram_size) { 919 error_report("maximum memory size must by aligned to multiple of " 920 "%d bytes", TARGET_PAGE_SIZE); 921 exit(EXIT_FAILURE); 922 } 923 924 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 925 926 if (device_mem_base + device_mem_size < device_mem_size) { 927 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 928 machine->maxram_size); 929 exit(EXIT_FAILURE); 930 } 931 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 932 } 933 934 if (pcms->cxl_devices_state.is_enabled) { 935 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 936 hwaddr cxl_size = MiB; 937 938 cxl_base = pc_get_cxl_range_start(pcms); 939 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 940 memory_region_add_subregion(system_memory, cxl_base, mr); 941 cxl_resv_end = cxl_base + cxl_size; 942 if (pcms->cxl_devices_state.fixed_windows) { 943 hwaddr cxl_fmw_base; 944 GList *it; 945 946 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 947 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 948 CXLFixedWindow *fw = it->data; 949 950 fw->base = cxl_fmw_base; 951 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 952 "cxl-fixed-memory-region", fw->size); 953 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 954 cxl_fmw_base += fw->size; 955 cxl_resv_end = cxl_fmw_base; 956 } 957 } 958 } 959 960 /* Initialize PC system firmware */ 961 pc_system_firmware_init(pcms, rom_memory); 962 963 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 964 if (machine_require_guest_memfd(machine)) { 965 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 966 PC_ROM_SIZE, &error_fatal); 967 } else { 968 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 969 &error_fatal); 970 if (pcmc->pci_enabled) { 971 memory_region_set_readonly(option_rom_mr, true); 972 } 973 } 974 memory_region_add_subregion_overlap(rom_memory, 975 PC_ROM_MIN_VGA, 976 option_rom_mr, 977 1); 978 979 fw_cfg = fw_cfg_arch_create(machine, 980 x86ms->boot_cpus, x86ms->apic_id_limit); 981 982 rom_set_fw(fw_cfg); 983 984 if (machine->device_memory) { 985 uint64_t *val = g_malloc(sizeof(*val)); 986 uint64_t res_mem_end = machine->device_memory->base; 987 988 if (!pcmc->broken_reserved_end) { 989 res_mem_end += memory_region_size(&machine->device_memory->mr); 990 } 991 992 if (pcms->cxl_devices_state.is_enabled) { 993 res_mem_end = cxl_resv_end; 994 } 995 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 996 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 997 } 998 999 if (linux_boot) { 1000 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1001 } 1002 1003 for (i = 0; i < nb_option_roms; i++) { 1004 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1005 } 1006 x86ms->fw_cfg = fw_cfg; 1007 1008 /* Init default IOAPIC address space */ 1009 x86ms->ioapic_as = &address_space_memory; 1010 1011 /* Init ACPI memory hotplug IO base address */ 1012 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1013 } 1014 1015 /* 1016 * The 64bit pci hole starts after "above 4G RAM" and 1017 * potentially the space reserved for memory hotplug. 1018 */ 1019 uint64_t pc_pci_hole64_start(void) 1020 { 1021 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1022 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1023 MachineState *ms = MACHINE(pcms); 1024 uint64_t hole64_start = 0; 1025 ram_addr_t size = 0; 1026 1027 if (pcms->cxl_devices_state.is_enabled) { 1028 hole64_start = pc_get_cxl_range_end(pcms); 1029 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1030 pc_get_device_memory_range(pcms, &hole64_start, &size); 1031 if (!pcmc->broken_reserved_end) { 1032 hole64_start += size; 1033 } 1034 } else { 1035 hole64_start = pc_above_4g_end(pcms); 1036 } 1037 1038 return ROUND_UP(hole64_start, 1 * GiB); 1039 } 1040 1041 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1042 { 1043 DeviceState *dev = NULL; 1044 1045 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1046 if (pci_bus) { 1047 PCIDevice *pcidev = pci_vga_init(pci_bus); 1048 dev = pcidev ? &pcidev->qdev : NULL; 1049 } else if (isa_bus) { 1050 ISADevice *isadev = isa_vga_init(isa_bus); 1051 dev = isadev ? DEVICE(isadev) : NULL; 1052 } 1053 rom_reset_order_override(); 1054 return dev; 1055 } 1056 1057 static const MemoryRegionOps ioport80_io_ops = { 1058 .write = ioport80_write, 1059 .read = ioport80_read, 1060 .endianness = DEVICE_NATIVE_ENDIAN, 1061 .impl = { 1062 .min_access_size = 1, 1063 .max_access_size = 1, 1064 }, 1065 }; 1066 1067 static const MemoryRegionOps ioportF0_io_ops = { 1068 .write = ioportF0_write, 1069 .read = ioportF0_read, 1070 .endianness = DEVICE_NATIVE_ENDIAN, 1071 .impl = { 1072 .min_access_size = 1, 1073 .max_access_size = 1, 1074 }, 1075 }; 1076 1077 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1078 bool create_i8042, bool no_vmport, Error **errp) 1079 { 1080 int i; 1081 DriveInfo *fd[MAX_FD]; 1082 qemu_irq *a20_line; 1083 ISADevice *i8042, *port92, *vmmouse; 1084 1085 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1086 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1087 1088 for (i = 0; i < MAX_FD; i++) { 1089 fd[i] = drive_get(IF_FLOPPY, 0, i); 1090 create_fdctrl |= !!fd[i]; 1091 } 1092 if (create_fdctrl) { 1093 #ifdef CONFIG_FDC_ISA 1094 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1095 if (fdc) { 1096 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1097 isa_fdc_init_drives(fdc, fd); 1098 } 1099 #endif 1100 } 1101 1102 if (!create_i8042) { 1103 if (!no_vmport) { 1104 error_setg(errp, 1105 "vmport requires the i8042 controller to be enabled"); 1106 } 1107 return; 1108 } 1109 1110 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1111 if (!no_vmport) { 1112 isa_create_simple(isa_bus, TYPE_VMPORT); 1113 vmmouse = isa_try_new("vmmouse"); 1114 } else { 1115 vmmouse = NULL; 1116 } 1117 if (vmmouse) { 1118 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1119 &error_abort); 1120 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1121 } 1122 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1123 1124 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1125 qdev_connect_gpio_out_named(DEVICE(i8042), 1126 I8042_A20_LINE, 0, a20_line[0]); 1127 qdev_connect_gpio_out_named(DEVICE(port92), 1128 PORT92_A20_LINE, 0, a20_line[1]); 1129 g_free(a20_line); 1130 } 1131 1132 void pc_basic_device_init(struct PCMachineState *pcms, 1133 ISABus *isa_bus, qemu_irq *gsi, 1134 ISADevice *rtc_state, 1135 bool create_fdctrl, 1136 uint32_t hpet_irqs) 1137 { 1138 int i; 1139 DeviceState *hpet = NULL; 1140 int pit_isa_irq = 0; 1141 qemu_irq pit_alt_irq = NULL; 1142 ISADevice *pit = NULL; 1143 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1144 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1145 X86MachineState *x86ms = X86_MACHINE(pcms); 1146 1147 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1148 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1149 1150 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1151 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1152 1153 /* 1154 * Check if an HPET shall be created. 1155 */ 1156 if (pcms->hpet_enabled) { 1157 qemu_irq rtc_irq; 1158 1159 hpet = qdev_try_new(TYPE_HPET); 1160 if (!hpet) { 1161 error_report("couldn't create HPET device"); 1162 exit(1); 1163 } 1164 /* 1165 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1166 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1167 * the property, use whatever mask they specified. 1168 */ 1169 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1170 HPET_INTCAP, NULL); 1171 if (!compat) { 1172 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1173 } 1174 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1175 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1176 1177 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1178 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1179 } 1180 pit_isa_irq = -1; 1181 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1182 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1183 1184 /* overwrite connection created by south bridge */ 1185 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1186 } 1187 1188 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1189 "date"); 1190 1191 #ifdef CONFIG_XEN_EMU 1192 if (xen_mode == XEN_EMULATE) { 1193 xen_overlay_create(); 1194 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1195 xen_gnttab_create(); 1196 xen_xenstore_create(); 1197 if (pcms->pcibus) { 1198 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1199 } 1200 xen_bus_init(); 1201 } 1202 #endif 1203 1204 qemu_register_boot_set(pc_boot_set, pcms); 1205 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1206 MACHINE(pcms)->boot_config.order, &error_fatal); 1207 1208 if (!xen_enabled() && 1209 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1210 if (kvm_pit_in_kernel()) { 1211 pit = kvm_pit_init(isa_bus, 0x40); 1212 } else { 1213 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1214 } 1215 if (hpet) { 1216 /* connect PIT to output control line of the HPET */ 1217 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1218 } 1219 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1220 OBJECT(pit), &error_fatal); 1221 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1222 } 1223 1224 assert(pcms->vmport >= 0 && pcms->vmport < ON_OFF_AUTO__MAX); 1225 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1226 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1227 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1228 } 1229 1230 /* Super I/O */ 1231 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1232 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1233 } 1234 1235 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1236 { 1237 MachineClass *mc = MACHINE_CLASS(pcmc); 1238 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1239 NICInfo *nd; 1240 1241 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1242 1243 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1244 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1245 } 1246 1247 /* Anything remaining should be a PCI NIC */ 1248 if (pci_bus) { 1249 pci_init_nic_devices(pci_bus, mc->default_nic); 1250 } 1251 1252 rom_reset_order_override(); 1253 } 1254 1255 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1256 { 1257 qemu_irq *i8259; 1258 1259 if (kvm_pic_in_kernel()) { 1260 i8259 = kvm_i8259_init(isa_bus); 1261 } else if (xen_enabled()) { 1262 i8259 = xen_interrupt_controller_init(); 1263 } else { 1264 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1265 } 1266 1267 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1268 i8259_irqs[i] = i8259[i]; 1269 } 1270 1271 g_free(i8259); 1272 } 1273 1274 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1275 Error **errp) 1276 { 1277 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1278 const MachineState *ms = MACHINE(hotplug_dev); 1279 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1280 Error *local_err = NULL; 1281 1282 /* 1283 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1284 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1285 * addition to cover this case. 1286 */ 1287 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1288 error_setg(errp, 1289 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1290 return; 1291 } 1292 1293 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1294 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1295 return; 1296 } 1297 1298 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1299 if (local_err) { 1300 error_propagate(errp, local_err); 1301 return; 1302 } 1303 1304 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1305 } 1306 1307 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1308 DeviceState *dev, Error **errp) 1309 { 1310 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1311 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1312 MachineState *ms = MACHINE(hotplug_dev); 1313 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1314 1315 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1316 1317 if (is_nvdimm) { 1318 nvdimm_plug(ms->nvdimms_state); 1319 } 1320 1321 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1322 } 1323 1324 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1325 DeviceState *dev, Error **errp) 1326 { 1327 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1328 1329 /* 1330 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1331 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1332 * addition to cover this case. 1333 */ 1334 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1335 error_setg(errp, 1336 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1337 return; 1338 } 1339 1340 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1341 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1342 return; 1343 } 1344 1345 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1346 errp); 1347 } 1348 1349 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1350 DeviceState *dev, Error **errp) 1351 { 1352 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1353 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1354 Error *local_err = NULL; 1355 1356 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1357 if (local_err) { 1358 goto out; 1359 } 1360 1361 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1362 qdev_unrealize(dev); 1363 out: 1364 error_propagate(errp, local_err); 1365 } 1366 1367 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1368 DeviceState *dev, Error **errp) 1369 { 1370 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1371 g_assert(!dev->hotplugged); 1372 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1373 } 1374 1375 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1376 DeviceState *dev, Error **errp) 1377 { 1378 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1379 } 1380 1381 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1382 DeviceState *dev, Error **errp) 1383 { 1384 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1385 pc_memory_pre_plug(hotplug_dev, dev, errp); 1386 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1387 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1388 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1389 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1390 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1391 /* Declare the APIC range as the reserved MSI region */ 1392 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1393 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1394 QList *reserved_regions = qlist_new(); 1395 1396 qlist_append_str(reserved_regions, resv_prop_str); 1397 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1398 1399 g_free(resv_prop_str); 1400 } 1401 1402 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1403 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1404 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1405 1406 if (pcms->iommu) { 1407 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1408 "for x86 yet."); 1409 return; 1410 } 1411 pcms->iommu = dev; 1412 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1413 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1414 } 1415 } 1416 1417 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1418 DeviceState *dev, Error **errp) 1419 { 1420 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1421 pc_memory_plug(hotplug_dev, dev, errp); 1422 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1423 x86_cpu_plug(hotplug_dev, dev, errp); 1424 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1425 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1426 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1427 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1428 } 1429 } 1430 1431 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1432 DeviceState *dev, Error **errp) 1433 { 1434 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1435 pc_memory_unplug_request(hotplug_dev, dev, errp); 1436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1437 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1439 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1440 errp); 1441 } else { 1442 error_setg(errp, "acpi: device unplug request for not supported device" 1443 " type: %s", object_get_typename(OBJECT(dev))); 1444 } 1445 } 1446 1447 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1448 DeviceState *dev, Error **errp) 1449 { 1450 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1451 pc_memory_unplug(hotplug_dev, dev, errp); 1452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1453 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1455 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1456 } else { 1457 error_setg(errp, "acpi: device unplug for not supported device" 1458 " type: %s", object_get_typename(OBJECT(dev))); 1459 } 1460 } 1461 1462 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1463 DeviceState *dev) 1464 { 1465 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1466 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1467 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1468 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1469 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1470 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1471 return HOTPLUG_HANDLER(machine); 1472 } 1473 1474 return NULL; 1475 } 1476 1477 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1478 void *opaque, Error **errp) 1479 { 1480 PCMachineState *pcms = PC_MACHINE(obj); 1481 OnOffAuto vmport = pcms->vmport; 1482 1483 visit_type_OnOffAuto(v, name, &vmport, errp); 1484 } 1485 1486 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1487 void *opaque, Error **errp) 1488 { 1489 PCMachineState *pcms = PC_MACHINE(obj); 1490 1491 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1492 } 1493 1494 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1495 { 1496 PCMachineState *pcms = PC_MACHINE(obj); 1497 1498 return pcms->fd_bootchk; 1499 } 1500 1501 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1502 { 1503 PCMachineState *pcms = PC_MACHINE(obj); 1504 1505 pcms->fd_bootchk = value; 1506 } 1507 1508 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1509 { 1510 PCMachineState *pcms = PC_MACHINE(obj); 1511 1512 return pcms->smbus_enabled; 1513 } 1514 1515 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1516 { 1517 PCMachineState *pcms = PC_MACHINE(obj); 1518 1519 pcms->smbus_enabled = value; 1520 } 1521 1522 static bool pc_machine_get_sata(Object *obj, Error **errp) 1523 { 1524 PCMachineState *pcms = PC_MACHINE(obj); 1525 1526 return pcms->sata_enabled; 1527 } 1528 1529 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1530 { 1531 PCMachineState *pcms = PC_MACHINE(obj); 1532 1533 pcms->sata_enabled = value; 1534 } 1535 1536 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 1540 return pcms->hpet_enabled; 1541 } 1542 1543 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1544 { 1545 PCMachineState *pcms = PC_MACHINE(obj); 1546 1547 pcms->hpet_enabled = value; 1548 } 1549 1550 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1551 { 1552 PCMachineState *pcms = PC_MACHINE(obj); 1553 1554 return pcms->i8042_enabled; 1555 } 1556 1557 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1558 { 1559 PCMachineState *pcms = PC_MACHINE(obj); 1560 1561 pcms->i8042_enabled = value; 1562 } 1563 1564 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1565 { 1566 PCMachineState *pcms = PC_MACHINE(obj); 1567 1568 return pcms->default_bus_bypass_iommu; 1569 } 1570 1571 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1572 Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 1576 pcms->default_bus_bypass_iommu = value; 1577 } 1578 1579 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1580 void *opaque, Error **errp) 1581 { 1582 PCMachineState *pcms = PC_MACHINE(obj); 1583 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1584 1585 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1586 } 1587 1588 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1589 void *opaque, Error **errp) 1590 { 1591 PCMachineState *pcms = PC_MACHINE(obj); 1592 1593 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1594 } 1595 1596 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1597 const char *name, void *opaque, 1598 Error **errp) 1599 { 1600 PCMachineState *pcms = PC_MACHINE(obj); 1601 uint64_t value = pcms->max_ram_below_4g; 1602 1603 visit_type_size(v, name, &value, errp); 1604 } 1605 1606 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1607 const char *name, void *opaque, 1608 Error **errp) 1609 { 1610 PCMachineState *pcms = PC_MACHINE(obj); 1611 uint64_t value; 1612 1613 if (!visit_type_size(v, name, &value, errp)) { 1614 return; 1615 } 1616 if (value > 4 * GiB) { 1617 error_setg(errp, 1618 "Machine option 'max-ram-below-4g=%"PRIu64 1619 "' expects size less than or equal to 4G", value); 1620 return; 1621 } 1622 1623 if (value < 1 * MiB) { 1624 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1625 "BIOS may not work with less than 1MiB", value); 1626 } 1627 1628 pcms->max_ram_below_4g = value; 1629 } 1630 1631 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1632 const char *name, void *opaque, 1633 Error **errp) 1634 { 1635 PCMachineState *pcms = PC_MACHINE(obj); 1636 uint64_t value = pcms->max_fw_size; 1637 1638 visit_type_size(v, name, &value, errp); 1639 } 1640 1641 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1642 const char *name, void *opaque, 1643 Error **errp) 1644 { 1645 PCMachineState *pcms = PC_MACHINE(obj); 1646 uint64_t value; 1647 1648 if (!visit_type_size(v, name, &value, errp)) { 1649 return; 1650 } 1651 1652 /* 1653 * We don't have a theoretically justifiable exact lower bound on the base 1654 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1655 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1656 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1657 * 16MiB in size. 1658 */ 1659 if (value > 16 * MiB) { 1660 error_setg(errp, 1661 "User specified max allowed firmware size %" PRIu64 " is " 1662 "greater than 16MiB. If combined firmware size exceeds " 1663 "16MiB the system may not boot, or experience intermittent" 1664 "stability issues.", 1665 value); 1666 return; 1667 } 1668 1669 pcms->max_fw_size = value; 1670 } 1671 1672 1673 static void pc_machine_initfn(Object *obj) 1674 { 1675 PCMachineState *pcms = PC_MACHINE(obj); 1676 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1677 1678 #ifdef CONFIG_VMPORT 1679 pcms->vmport = ON_OFF_AUTO_AUTO; 1680 #else 1681 pcms->vmport = ON_OFF_AUTO_OFF; 1682 #endif /* CONFIG_VMPORT */ 1683 pcms->max_ram_below_4g = 0; /* use default */ 1684 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1685 pcms->south_bridge = pcmc->default_south_bridge; 1686 1687 /* acpi build is enabled by default if machine supports it */ 1688 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1689 pcms->smbus_enabled = true; 1690 pcms->sata_enabled = true; 1691 pcms->i8042_enabled = true; 1692 pcms->max_fw_size = 8 * MiB; 1693 #ifdef CONFIG_HPET 1694 pcms->hpet_enabled = true; 1695 #endif 1696 pcms->fd_bootchk = true; 1697 pcms->default_bus_bypass_iommu = false; 1698 1699 pc_system_flash_create(pcms); 1700 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1701 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1702 OBJECT(pcms->pcspk), "audiodev"); 1703 if (pcmc->pci_enabled) { 1704 cxl_machine_init(obj, &pcms->cxl_devices_state); 1705 } 1706 1707 pcms->machine_done.notify = pc_machine_done; 1708 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1709 } 1710 1711 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1712 { 1713 CPUState *cs; 1714 X86CPU *cpu; 1715 1716 qemu_devices_reset(reason); 1717 1718 /* Reset APIC after devices have been reset to cancel 1719 * any changes that qemu_devices_reset() might have done. 1720 */ 1721 CPU_FOREACH(cs) { 1722 cpu = X86_CPU(cs); 1723 1724 x86_cpu_after_reset(cpu); 1725 } 1726 } 1727 1728 static void pc_machine_wakeup(MachineState *machine) 1729 { 1730 cpu_synchronize_all_states(); 1731 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1732 cpu_synchronize_all_post_reset(); 1733 } 1734 1735 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1736 { 1737 X86IOMMUState *iommu = x86_iommu_get_default(); 1738 IntelIOMMUState *intel_iommu; 1739 1740 if (iommu && 1741 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1742 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1743 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1744 if (!intel_iommu->caching_mode) { 1745 error_setg(errp, "Device assignment is not allowed without " 1746 "enabling caching-mode=on for Intel IOMMU."); 1747 return false; 1748 } 1749 } 1750 1751 return true; 1752 } 1753 1754 static void pc_machine_class_init(ObjectClass *oc, void *data) 1755 { 1756 MachineClass *mc = MACHINE_CLASS(oc); 1757 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1758 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1759 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1760 1761 pcmc->pci_enabled = true; 1762 pcmc->has_acpi_build = true; 1763 pcmc->smbios_defaults = true; 1764 pcmc->gigabyte_align = true; 1765 pcmc->has_reserved_memory = true; 1766 pcmc->enforce_amd_1tb_hole = true; 1767 pcmc->isa_bios_alias = true; 1768 pcmc->pvh_enabled = true; 1769 pcmc->kvmclock_create_always = true; 1770 x86mc->apic_xrupt_override = true; 1771 assert(!mc->get_hotplug_handler); 1772 mc->get_hotplug_handler = pc_get_hotplug_handler; 1773 mc->hotplug_allowed = pc_hotplug_allowed; 1774 mc->auto_enable_numa_with_memhp = true; 1775 mc->auto_enable_numa_with_memdev = true; 1776 mc->has_hotpluggable_cpus = true; 1777 mc->default_boot_order = "cad"; 1778 mc->block_default_type = IF_IDE; 1779 mc->max_cpus = 255; 1780 mc->reset = pc_machine_reset; 1781 mc->wakeup = pc_machine_wakeup; 1782 hc->pre_plug = pc_machine_device_pre_plug_cb; 1783 hc->plug = pc_machine_device_plug_cb; 1784 hc->unplug_request = pc_machine_device_unplug_request_cb; 1785 hc->unplug = pc_machine_device_unplug_cb; 1786 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1787 mc->nvdimm_supported = true; 1788 mc->smp_props.dies_supported = true; 1789 mc->smp_props.modules_supported = true; 1790 mc->default_ram_id = "pc.ram"; 1791 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1792 1793 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1794 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1795 NULL, NULL); 1796 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1797 "Maximum ram below the 4G boundary (32bit boundary)"); 1798 1799 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1800 pc_machine_get_vmport, pc_machine_set_vmport, 1801 NULL, NULL); 1802 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1803 "Enable vmport (pc & q35)"); 1804 1805 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1806 pc_machine_get_smbus, pc_machine_set_smbus); 1807 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1808 "Enable/disable system management bus"); 1809 1810 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1811 pc_machine_get_sata, pc_machine_set_sata); 1812 object_class_property_set_description(oc, PC_MACHINE_SATA, 1813 "Enable/disable Serial ATA bus"); 1814 1815 object_class_property_add_bool(oc, "hpet", 1816 pc_machine_get_hpet, pc_machine_set_hpet); 1817 object_class_property_set_description(oc, "hpet", 1818 "Enable/disable high precision event timer emulation"); 1819 1820 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1821 pc_machine_get_i8042, pc_machine_set_i8042); 1822 1823 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1824 pc_machine_get_default_bus_bypass_iommu, 1825 pc_machine_set_default_bus_bypass_iommu); 1826 1827 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1828 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1829 NULL, NULL); 1830 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1831 "Maximum combined firmware size"); 1832 1833 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1834 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1835 NULL, NULL); 1836 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1837 "SMBIOS Entry Point type [32, 64]"); 1838 1839 object_class_property_add_bool(oc, "fd-bootchk", 1840 pc_machine_get_fd_bootchk, 1841 pc_machine_set_fd_bootchk); 1842 } 1843 1844 static const TypeInfo pc_machine_info = { 1845 .name = TYPE_PC_MACHINE, 1846 .parent = TYPE_X86_MACHINE, 1847 .abstract = true, 1848 .instance_size = sizeof(PCMachineState), 1849 .instance_init = pc_machine_initfn, 1850 .class_size = sizeof(PCMachineClass), 1851 .class_init = pc_machine_class_init, 1852 .interfaces = (InterfaceInfo[]) { 1853 { TYPE_HOTPLUG_HANDLER }, 1854 { } 1855 }, 1856 }; 1857 1858 static void pc_machine_register_types(void) 1859 { 1860 type_register_static(&pc_machine_info); 1861 } 1862 1863 type_init(pc_machine_register_types) 1864