1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/i386/apic.h" 31 #include "hw/i386/topology.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "sysemu/cpus.h" 34 #include "hw/block/fdc.h" 35 #include "hw/ide.h" 36 #include "hw/pci/pci.h" 37 #include "hw/pci/pci_bus.h" 38 #include "hw/nvram/fw_cfg.h" 39 #include "hw/timer/hpet.h" 40 #include "hw/firmware/smbios.h" 41 #include "hw/loader.h" 42 #include "elf.h" 43 #include "migration/vmstate.h" 44 #include "multiboot.h" 45 #include "hw/timer/mc146818rtc.h" 46 #include "hw/dma/i8257.h" 47 #include "hw/timer/i8254.h" 48 #include "hw/input/i8042.h" 49 #include "hw/irq.h" 50 #include "hw/audio/pcspk.h" 51 #include "hw/pci/msi.h" 52 #include "hw/sysbus.h" 53 #include "sysemu/sysemu.h" 54 #include "sysemu/tcg.h" 55 #include "sysemu/numa.h" 56 #include "sysemu/kvm.h" 57 #include "sysemu/qtest.h" 58 #include "sysemu/reset.h" 59 #include "sysemu/runstate.h" 60 #include "kvm_i386.h" 61 #include "hw/xen/xen.h" 62 #include "hw/xen/start_info.h" 63 #include "ui/qemu-spice.h" 64 #include "exec/memory.h" 65 #include "exec/address-spaces.h" 66 #include "sysemu/arch_init.h" 67 #include "qemu/bitmap.h" 68 #include "qemu/config-file.h" 69 #include "qemu/error-report.h" 70 #include "qemu/option.h" 71 #include "hw/acpi/acpi.h" 72 #include "hw/acpi/cpu_hotplug.h" 73 #include "hw/boards.h" 74 #include "acpi-build.h" 75 #include "hw/mem/pc-dimm.h" 76 #include "qapi/error.h" 77 #include "qapi/qapi-visit-common.h" 78 #include "qapi/visitor.h" 79 #include "hw/core/cpu.h" 80 #include "hw/nmi.h" 81 #include "hw/usb.h" 82 #include "hw/i386/intel_iommu.h" 83 #include "hw/net/ne2000-isa.h" 84 #include "standard-headers/asm-x86/bootparam.h" 85 #include "hw/virtio/virtio-pmem-pci.h" 86 #include "hw/mem/memory-device.h" 87 #include "sysemu/replay.h" 88 #include "qapi/qmp/qerror.h" 89 #include "config-devices.h" 90 #include "e820_memory_layout.h" 91 #include "fw_cfg.h" 92 93 /* debug PC/ISA interrupts */ 94 //#define DEBUG_IRQ 95 96 #ifdef DEBUG_IRQ 97 #define DPRINTF(fmt, ...) \ 98 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 99 #else 100 #define DPRINTF(fmt, ...) 101 #endif 102 103 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 104 105 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 106 static size_t pvh_start_addr; 107 108 GlobalProperty pc_compat_4_1[] = {}; 109 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 110 111 GlobalProperty pc_compat_4_0[] = {}; 112 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 113 114 GlobalProperty pc_compat_3_1[] = { 115 { "intel-iommu", "dma-drain", "off" }, 116 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 117 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 118 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 119 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 120 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 121 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 122 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 123 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 124 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 125 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 126 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 127 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 128 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 129 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 130 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 131 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 132 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 133 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 135 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 136 }; 137 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 138 139 GlobalProperty pc_compat_3_0[] = { 140 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 141 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 142 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 143 }; 144 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 145 146 GlobalProperty pc_compat_2_12[] = { 147 { TYPE_X86_CPU, "legacy-cache", "on" }, 148 { TYPE_X86_CPU, "topoext", "off" }, 149 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 150 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 151 }; 152 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 153 154 GlobalProperty pc_compat_2_11[] = { 155 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 156 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 157 }; 158 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 159 160 GlobalProperty pc_compat_2_10[] = { 161 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 162 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 163 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 164 }; 165 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 166 167 GlobalProperty pc_compat_2_9[] = { 168 { "mch", "extended-tseg-mbytes", "0" }, 169 }; 170 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 171 172 GlobalProperty pc_compat_2_8[] = { 173 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 174 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 175 { "ICH9-LPC", "x-smi-broadcast", "off" }, 176 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 177 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 178 }; 179 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 180 181 GlobalProperty pc_compat_2_7[] = { 182 { TYPE_X86_CPU, "l3-cache", "off" }, 183 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 184 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 185 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 186 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 187 { "isa-pcspk", "migrate", "off" }, 188 }; 189 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 190 191 GlobalProperty pc_compat_2_6[] = { 192 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 193 { "vmxnet3", "romfile", "" }, 194 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 195 { "apic-common", "legacy-instance-id", "on", } 196 }; 197 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 198 199 GlobalProperty pc_compat_2_5[] = {}; 200 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 201 202 GlobalProperty pc_compat_2_4[] = { 203 PC_CPU_MODEL_IDS("2.4.0") 204 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 205 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 206 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 207 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 208 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 209 { TYPE_X86_CPU, "check", "off" }, 210 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 211 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 212 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 213 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 214 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 215 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 216 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 217 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 218 }; 219 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 220 221 GlobalProperty pc_compat_2_3[] = { 222 PC_CPU_MODEL_IDS("2.3.0") 223 { TYPE_X86_CPU, "arat", "off" }, 224 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 225 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 226 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 227 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 228 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 229 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 230 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 231 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 232 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 233 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 234 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 235 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 236 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 237 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 243 }; 244 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 245 246 GlobalProperty pc_compat_2_2[] = { 247 PC_CPU_MODEL_IDS("2.2.0") 248 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 249 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 250 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 251 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 252 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 253 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 254 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 263 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 264 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 265 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 266 }; 267 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 268 269 GlobalProperty pc_compat_2_1[] = { 270 PC_CPU_MODEL_IDS("2.1.0") 271 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 272 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 273 }; 274 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 275 276 GlobalProperty pc_compat_2_0[] = { 277 PC_CPU_MODEL_IDS("2.0.0") 278 { "virtio-scsi-pci", "any_layout", "off" }, 279 { "PIIX4_PM", "memory-hotplug-support", "off" }, 280 { "apic", "version", "0x11" }, 281 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 282 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 283 { "pci-serial", "prog_if", "0" }, 284 { "pci-serial-2x", "prog_if", "0" }, 285 { "pci-serial-4x", "prog_if", "0" }, 286 { "virtio-net-pci", "guest_announce", "off" }, 287 { "ICH9-LPC", "memory-hotplug-support", "off" }, 288 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 289 { "ioh3420", COMPAT_PROP_PCP, "off" }, 290 }; 291 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 292 293 GlobalProperty pc_compat_1_7[] = { 294 PC_CPU_MODEL_IDS("1.7.0") 295 { TYPE_USB_DEVICE, "msos-desc", "no" }, 296 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 297 { "hpet", HPET_INTCAP, "4" }, 298 }; 299 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 300 301 GlobalProperty pc_compat_1_6[] = { 302 PC_CPU_MODEL_IDS("1.6.0") 303 { "e1000", "mitigation", "off" }, 304 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 305 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 306 { "i440FX-pcihost", "short_root_bus", "1" }, 307 { "q35-pcihost", "short_root_bus", "1" }, 308 }; 309 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 310 311 GlobalProperty pc_compat_1_5[] = { 312 PC_CPU_MODEL_IDS("1.5.0") 313 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 314 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 315 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 316 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 317 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 318 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 319 { "virtio-net-pci", "any_layout", "off" }, 320 { TYPE_X86_CPU, "pmu", "on" }, 321 { "i440FX-pcihost", "short_root_bus", "0" }, 322 { "q35-pcihost", "short_root_bus", "0" }, 323 }; 324 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 325 326 GlobalProperty pc_compat_1_4[] = { 327 PC_CPU_MODEL_IDS("1.4.0") 328 { "scsi-hd", "discard_granularity", "0" }, 329 { "scsi-cd", "discard_granularity", "0" }, 330 { "scsi-disk", "discard_granularity", "0" }, 331 { "ide-hd", "discard_granularity", "0" }, 332 { "ide-cd", "discard_granularity", "0" }, 333 { "ide-drive", "discard_granularity", "0" }, 334 { "virtio-blk-pci", "discard_granularity", "0" }, 335 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 336 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 337 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 338 { "e1000", "romfile", "pxe-e1000.rom" }, 339 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 340 { "pcnet", "romfile", "pxe-pcnet.rom" }, 341 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 342 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 343 { "486-" TYPE_X86_CPU, "model", "0" }, 344 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 345 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 346 }; 347 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 348 349 void gsi_handler(void *opaque, int n, int level) 350 { 351 GSIState *s = opaque; 352 353 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 354 if (n < ISA_NUM_IRQS) { 355 qemu_set_irq(s->i8259_irq[n], level); 356 } 357 qemu_set_irq(s->ioapic_irq[n], level); 358 } 359 360 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 361 unsigned size) 362 { 363 } 364 365 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 366 { 367 return 0xffffffffffffffffULL; 368 } 369 370 /* MSDOS compatibility mode FPU exception support */ 371 static qemu_irq ferr_irq; 372 373 void pc_register_ferr_irq(qemu_irq irq) 374 { 375 ferr_irq = irq; 376 } 377 378 /* XXX: add IGNNE support */ 379 void cpu_set_ferr(CPUX86State *s) 380 { 381 qemu_irq_raise(ferr_irq); 382 } 383 384 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 385 unsigned size) 386 { 387 qemu_irq_lower(ferr_irq); 388 } 389 390 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 391 { 392 return 0xffffffffffffffffULL; 393 } 394 395 /* TSC handling */ 396 uint64_t cpu_get_tsc(CPUX86State *env) 397 { 398 return cpu_get_ticks(); 399 } 400 401 /* IRQ handling */ 402 int cpu_get_pic_interrupt(CPUX86State *env) 403 { 404 X86CPU *cpu = env_archcpu(env); 405 int intno; 406 407 if (!kvm_irqchip_in_kernel()) { 408 intno = apic_get_interrupt(cpu->apic_state); 409 if (intno >= 0) { 410 return intno; 411 } 412 /* read the irq from the PIC */ 413 if (!apic_accept_pic_intr(cpu->apic_state)) { 414 return -1; 415 } 416 } 417 418 intno = pic_read_irq(isa_pic); 419 return intno; 420 } 421 422 static void pic_irq_request(void *opaque, int irq, int level) 423 { 424 CPUState *cs = first_cpu; 425 X86CPU *cpu = X86_CPU(cs); 426 427 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 428 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 429 CPU_FOREACH(cs) { 430 cpu = X86_CPU(cs); 431 if (apic_accept_pic_intr(cpu->apic_state)) { 432 apic_deliver_pic_intr(cpu->apic_state, level); 433 } 434 } 435 } else { 436 if (level) { 437 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 438 } else { 439 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 440 } 441 } 442 } 443 444 /* PC cmos mappings */ 445 446 #define REG_EQUIPMENT_BYTE 0x14 447 448 int cmos_get_fd_drive_type(FloppyDriveType fd0) 449 { 450 int val; 451 452 switch (fd0) { 453 case FLOPPY_DRIVE_TYPE_144: 454 /* 1.44 Mb 3"5 drive */ 455 val = 4; 456 break; 457 case FLOPPY_DRIVE_TYPE_288: 458 /* 2.88 Mb 3"5 drive */ 459 val = 5; 460 break; 461 case FLOPPY_DRIVE_TYPE_120: 462 /* 1.2 Mb 5"5 drive */ 463 val = 2; 464 break; 465 case FLOPPY_DRIVE_TYPE_NONE: 466 default: 467 val = 0; 468 break; 469 } 470 return val; 471 } 472 473 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 474 int16_t cylinders, int8_t heads, int8_t sectors) 475 { 476 rtc_set_memory(s, type_ofs, 47); 477 rtc_set_memory(s, info_ofs, cylinders); 478 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 479 rtc_set_memory(s, info_ofs + 2, heads); 480 rtc_set_memory(s, info_ofs + 3, 0xff); 481 rtc_set_memory(s, info_ofs + 4, 0xff); 482 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 483 rtc_set_memory(s, info_ofs + 6, cylinders); 484 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 485 rtc_set_memory(s, info_ofs + 8, sectors); 486 } 487 488 /* convert boot_device letter to something recognizable by the bios */ 489 static int boot_device2nibble(char boot_device) 490 { 491 switch(boot_device) { 492 case 'a': 493 case 'b': 494 return 0x01; /* floppy boot */ 495 case 'c': 496 return 0x02; /* hard drive boot */ 497 case 'd': 498 return 0x03; /* CD-ROM boot */ 499 case 'n': 500 return 0x04; /* Network boot */ 501 } 502 return 0; 503 } 504 505 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 506 { 507 #define PC_MAX_BOOT_DEVICES 3 508 int nbds, bds[3] = { 0, }; 509 int i; 510 511 nbds = strlen(boot_device); 512 if (nbds > PC_MAX_BOOT_DEVICES) { 513 error_setg(errp, "Too many boot devices for PC"); 514 return; 515 } 516 for (i = 0; i < nbds; i++) { 517 bds[i] = boot_device2nibble(boot_device[i]); 518 if (bds[i] == 0) { 519 error_setg(errp, "Invalid boot device for PC: '%c'", 520 boot_device[i]); 521 return; 522 } 523 } 524 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 525 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 526 } 527 528 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 529 { 530 set_boot_dev(opaque, boot_device, errp); 531 } 532 533 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 534 { 535 int val, nb, i; 536 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 537 FLOPPY_DRIVE_TYPE_NONE }; 538 539 /* floppy type */ 540 if (floppy) { 541 for (i = 0; i < 2; i++) { 542 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 543 } 544 } 545 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 546 cmos_get_fd_drive_type(fd_type[1]); 547 rtc_set_memory(rtc_state, 0x10, val); 548 549 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 550 nb = 0; 551 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 552 nb++; 553 } 554 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 555 nb++; 556 } 557 switch (nb) { 558 case 0: 559 break; 560 case 1: 561 val |= 0x01; /* 1 drive, ready for boot */ 562 break; 563 case 2: 564 val |= 0x41; /* 2 drives, ready for boot */ 565 break; 566 } 567 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 568 } 569 570 typedef struct pc_cmos_init_late_arg { 571 ISADevice *rtc_state; 572 BusState *idebus[2]; 573 } pc_cmos_init_late_arg; 574 575 typedef struct check_fdc_state { 576 ISADevice *floppy; 577 bool multiple; 578 } CheckFdcState; 579 580 static int check_fdc(Object *obj, void *opaque) 581 { 582 CheckFdcState *state = opaque; 583 Object *fdc; 584 uint32_t iobase; 585 Error *local_err = NULL; 586 587 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 588 if (!fdc) { 589 return 0; 590 } 591 592 iobase = object_property_get_uint(obj, "iobase", &local_err); 593 if (local_err || iobase != 0x3f0) { 594 error_free(local_err); 595 return 0; 596 } 597 598 if (state->floppy) { 599 state->multiple = true; 600 } else { 601 state->floppy = ISA_DEVICE(obj); 602 } 603 return 0; 604 } 605 606 static const char * const fdc_container_path[] = { 607 "/unattached", "/peripheral", "/peripheral-anon" 608 }; 609 610 /* 611 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 612 * and ACPI objects. 613 */ 614 ISADevice *pc_find_fdc0(void) 615 { 616 int i; 617 Object *container; 618 CheckFdcState state = { 0 }; 619 620 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 621 container = container_get(qdev_get_machine(), fdc_container_path[i]); 622 object_child_foreach(container, check_fdc, &state); 623 } 624 625 if (state.multiple) { 626 warn_report("multiple floppy disk controllers with " 627 "iobase=0x3f0 have been found"); 628 error_printf("the one being picked for CMOS setup might not reflect " 629 "your intent"); 630 } 631 632 return state.floppy; 633 } 634 635 static void pc_cmos_init_late(void *opaque) 636 { 637 pc_cmos_init_late_arg *arg = opaque; 638 ISADevice *s = arg->rtc_state; 639 int16_t cylinders; 640 int8_t heads, sectors; 641 int val; 642 int i, trans; 643 644 val = 0; 645 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 646 &cylinders, &heads, §ors) >= 0) { 647 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 648 val |= 0xf0; 649 } 650 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 651 &cylinders, &heads, §ors) >= 0) { 652 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 653 val |= 0x0f; 654 } 655 rtc_set_memory(s, 0x12, val); 656 657 val = 0; 658 for (i = 0; i < 4; i++) { 659 /* NOTE: ide_get_geometry() returns the physical 660 geometry. It is always such that: 1 <= sects <= 63, 1 661 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 662 geometry can be different if a translation is done. */ 663 if (arg->idebus[i / 2] && 664 ide_get_geometry(arg->idebus[i / 2], i % 2, 665 &cylinders, &heads, §ors) >= 0) { 666 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 667 assert((trans & ~3) == 0); 668 val |= trans << (i * 2); 669 } 670 } 671 rtc_set_memory(s, 0x39, val); 672 673 pc_cmos_init_floppy(s, pc_find_fdc0()); 674 675 qemu_unregister_reset(pc_cmos_init_late, opaque); 676 } 677 678 void pc_cmos_init(PCMachineState *pcms, 679 BusState *idebus0, BusState *idebus1, 680 ISADevice *s) 681 { 682 int val; 683 static pc_cmos_init_late_arg arg; 684 685 /* various important CMOS locations needed by PC/Bochs bios */ 686 687 /* memory size */ 688 /* base memory (first MiB) */ 689 val = MIN(pcms->below_4g_mem_size / KiB, 640); 690 rtc_set_memory(s, 0x15, val); 691 rtc_set_memory(s, 0x16, val >> 8); 692 /* extended memory (next 64MiB) */ 693 if (pcms->below_4g_mem_size > 1 * MiB) { 694 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 695 } else { 696 val = 0; 697 } 698 if (val > 65535) 699 val = 65535; 700 rtc_set_memory(s, 0x17, val); 701 rtc_set_memory(s, 0x18, val >> 8); 702 rtc_set_memory(s, 0x30, val); 703 rtc_set_memory(s, 0x31, val >> 8); 704 /* memory between 16MiB and 4GiB */ 705 if (pcms->below_4g_mem_size > 16 * MiB) { 706 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 707 } else { 708 val = 0; 709 } 710 if (val > 65535) 711 val = 65535; 712 rtc_set_memory(s, 0x34, val); 713 rtc_set_memory(s, 0x35, val >> 8); 714 /* memory above 4GiB */ 715 val = pcms->above_4g_mem_size / 65536; 716 rtc_set_memory(s, 0x5b, val); 717 rtc_set_memory(s, 0x5c, val >> 8); 718 rtc_set_memory(s, 0x5d, val >> 16); 719 720 object_property_add_link(OBJECT(pcms), "rtc_state", 721 TYPE_ISA_DEVICE, 722 (Object **)&pcms->rtc, 723 object_property_allow_set_link, 724 OBJ_PROP_LINK_STRONG, &error_abort); 725 object_property_set_link(OBJECT(pcms), OBJECT(s), 726 "rtc_state", &error_abort); 727 728 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 729 730 val = 0; 731 val |= 0x02; /* FPU is there */ 732 val |= 0x04; /* PS/2 mouse installed */ 733 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 734 735 /* hard drives and FDC */ 736 arg.rtc_state = s; 737 arg.idebus[0] = idebus0; 738 arg.idebus[1] = idebus1; 739 qemu_register_reset(pc_cmos_init_late, &arg); 740 } 741 742 #define TYPE_PORT92 "port92" 743 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 744 745 /* port 92 stuff: could be split off */ 746 typedef struct Port92State { 747 ISADevice parent_obj; 748 749 MemoryRegion io; 750 uint8_t outport; 751 qemu_irq a20_out; 752 } Port92State; 753 754 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 755 unsigned size) 756 { 757 Port92State *s = opaque; 758 int oldval = s->outport; 759 760 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 761 s->outport = val; 762 qemu_set_irq(s->a20_out, (val >> 1) & 1); 763 if ((val & 1) && !(oldval & 1)) { 764 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 765 } 766 } 767 768 static uint64_t port92_read(void *opaque, hwaddr addr, 769 unsigned size) 770 { 771 Port92State *s = opaque; 772 uint32_t ret; 773 774 ret = s->outport; 775 DPRINTF("port92: read 0x%02x\n", ret); 776 return ret; 777 } 778 779 static void port92_init(ISADevice *dev, qemu_irq a20_out) 780 { 781 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 782 } 783 784 static const VMStateDescription vmstate_port92_isa = { 785 .name = "port92", 786 .version_id = 1, 787 .minimum_version_id = 1, 788 .fields = (VMStateField[]) { 789 VMSTATE_UINT8(outport, Port92State), 790 VMSTATE_END_OF_LIST() 791 } 792 }; 793 794 static void port92_reset(DeviceState *d) 795 { 796 Port92State *s = PORT92(d); 797 798 s->outport &= ~1; 799 } 800 801 static const MemoryRegionOps port92_ops = { 802 .read = port92_read, 803 .write = port92_write, 804 .impl = { 805 .min_access_size = 1, 806 .max_access_size = 1, 807 }, 808 .endianness = DEVICE_LITTLE_ENDIAN, 809 }; 810 811 static void port92_initfn(Object *obj) 812 { 813 Port92State *s = PORT92(obj); 814 815 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 816 817 s->outport = 0; 818 819 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 820 } 821 822 static void port92_realizefn(DeviceState *dev, Error **errp) 823 { 824 ISADevice *isadev = ISA_DEVICE(dev); 825 Port92State *s = PORT92(dev); 826 827 isa_register_ioport(isadev, &s->io, 0x92); 828 } 829 830 static void port92_class_initfn(ObjectClass *klass, void *data) 831 { 832 DeviceClass *dc = DEVICE_CLASS(klass); 833 834 dc->realize = port92_realizefn; 835 dc->reset = port92_reset; 836 dc->vmsd = &vmstate_port92_isa; 837 /* 838 * Reason: unlike ordinary ISA devices, this one needs additional 839 * wiring: its A20 output line needs to be wired up by 840 * port92_init(). 841 */ 842 dc->user_creatable = false; 843 } 844 845 static const TypeInfo port92_info = { 846 .name = TYPE_PORT92, 847 .parent = TYPE_ISA_DEVICE, 848 .instance_size = sizeof(Port92State), 849 .instance_init = port92_initfn, 850 .class_init = port92_class_initfn, 851 }; 852 853 static void port92_register_types(void) 854 { 855 type_register_static(&port92_info); 856 } 857 858 type_init(port92_register_types) 859 860 static void handle_a20_line_change(void *opaque, int irq, int level) 861 { 862 X86CPU *cpu = opaque; 863 864 /* XXX: send to all CPUs ? */ 865 /* XXX: add logic to handle multiple A20 line sources */ 866 x86_cpu_set_a20(cpu, level); 867 } 868 869 /* Calculates initial APIC ID for a specific CPU index 870 * 871 * Currently we need to be able to calculate the APIC ID from the CPU index 872 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 873 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 874 * all CPUs up to max_cpus. 875 */ 876 static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, 877 unsigned int cpu_index) 878 { 879 MachineState *ms = MACHINE(pcms); 880 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 881 uint32_t correct_id; 882 static bool warned; 883 884 correct_id = x86_apicid_from_cpu_idx(pcms->smp_dies, ms->smp.cores, 885 ms->smp.threads, cpu_index); 886 if (pcmc->compat_apic_id_mode) { 887 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 888 error_report("APIC IDs set in compatibility mode, " 889 "CPU topology won't match the configuration"); 890 warned = true; 891 } 892 return cpu_index; 893 } else { 894 return correct_id; 895 } 896 } 897 898 static long get_file_size(FILE *f) 899 { 900 long where, size; 901 902 /* XXX: on Unix systems, using fstat() probably makes more sense */ 903 904 where = ftell(f); 905 fseek(f, 0, SEEK_END); 906 size = ftell(f); 907 fseek(f, where, SEEK_SET); 908 909 return size; 910 } 911 912 struct setup_data { 913 uint64_t next; 914 uint32_t type; 915 uint32_t len; 916 uint8_t data[0]; 917 } __attribute__((packed)); 918 919 920 /* 921 * The entry point into the kernel for PVH boot is different from 922 * the native entry point. The PVH entry is defined by the x86/HVM 923 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 924 * 925 * This function is passed to load_elf() when it is called from 926 * load_elfboot() which then additionally checks for an ELF Note of 927 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 928 * parse the PVH entry address from the ELF Note. 929 * 930 * Due to trickery in elf_opts.h, load_elf() is actually available as 931 * load_elf32() or load_elf64() and this routine needs to be able 932 * to deal with being called as 32 or 64 bit. 933 * 934 * The address of the PVH entry point is saved to the 'pvh_start_addr' 935 * global variable. (although the entry point is 32-bit, the kernel 936 * binary can be either 32-bit or 64-bit). 937 */ 938 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 939 { 940 size_t *elf_note_data_addr; 941 942 /* Check if ELF Note header passed in is valid */ 943 if (arg1 == NULL) { 944 return 0; 945 } 946 947 if (is64) { 948 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 949 uint64_t nhdr_size64 = sizeof(struct elf64_note); 950 uint64_t phdr_align = *(uint64_t *)arg2; 951 uint64_t nhdr_namesz = nhdr64->n_namesz; 952 953 elf_note_data_addr = 954 ((void *)nhdr64) + nhdr_size64 + 955 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 956 } else { 957 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 958 uint32_t nhdr_size32 = sizeof(struct elf32_note); 959 uint32_t phdr_align = *(uint32_t *)arg2; 960 uint32_t nhdr_namesz = nhdr32->n_namesz; 961 962 elf_note_data_addr = 963 ((void *)nhdr32) + nhdr_size32 + 964 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 965 } 966 967 pvh_start_addr = *elf_note_data_addr; 968 969 return pvh_start_addr; 970 } 971 972 static bool load_elfboot(const char *kernel_filename, 973 int kernel_file_size, 974 uint8_t *header, 975 size_t pvh_xen_start_addr, 976 FWCfgState *fw_cfg) 977 { 978 uint32_t flags = 0; 979 uint32_t mh_load_addr = 0; 980 uint32_t elf_kernel_size = 0; 981 uint64_t elf_entry; 982 uint64_t elf_low, elf_high; 983 int kernel_size; 984 985 if (ldl_p(header) != 0x464c457f) { 986 return false; /* no elfboot */ 987 } 988 989 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 990 flags = elf_is64 ? 991 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 992 993 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 994 error_report("elfboot unsupported flags = %x", flags); 995 exit(1); 996 } 997 998 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 999 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1000 NULL, &elf_note_type, &elf_entry, 1001 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1002 0, 0); 1003 1004 if (kernel_size < 0) { 1005 error_report("Error while loading elf kernel"); 1006 exit(1); 1007 } 1008 mh_load_addr = elf_low; 1009 elf_kernel_size = elf_high - elf_low; 1010 1011 if (pvh_start_addr == 0) { 1012 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1013 exit(1); 1014 } 1015 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1016 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1017 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1018 1019 return true; 1020 } 1021 1022 static void load_linux(PCMachineState *pcms, 1023 FWCfgState *fw_cfg) 1024 { 1025 uint16_t protocol; 1026 int setup_size, kernel_size, cmdline_size; 1027 int dtb_size, setup_data_offset; 1028 uint32_t initrd_max; 1029 uint8_t header[8192], *setup, *kernel; 1030 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1031 FILE *f; 1032 char *vmode; 1033 MachineState *machine = MACHINE(pcms); 1034 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1035 struct setup_data *setup_data; 1036 const char *kernel_filename = machine->kernel_filename; 1037 const char *initrd_filename = machine->initrd_filename; 1038 const char *dtb_filename = machine->dtb; 1039 const char *kernel_cmdline = machine->kernel_cmdline; 1040 1041 /* Align to 16 bytes as a paranoia measure */ 1042 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1043 1044 /* load the kernel header */ 1045 f = fopen(kernel_filename, "rb"); 1046 if (!f || !(kernel_size = get_file_size(f)) || 1047 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1048 MIN(ARRAY_SIZE(header), kernel_size)) { 1049 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1050 kernel_filename, strerror(errno)); 1051 exit(1); 1052 } 1053 1054 /* kernel protocol version */ 1055 #if 0 1056 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1057 #endif 1058 if (ldl_p(header+0x202) == 0x53726448) { 1059 protocol = lduw_p(header+0x206); 1060 } else { 1061 /* 1062 * This could be a multiboot kernel. If it is, let's stop treating it 1063 * like a Linux kernel. 1064 * Note: some multiboot images could be in the ELF format (the same of 1065 * PVH), so we try multiboot first since we check the multiboot magic 1066 * header before to load it. 1067 */ 1068 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1069 kernel_cmdline, kernel_size, header)) { 1070 return; 1071 } 1072 /* 1073 * Check if the file is an uncompressed kernel file (ELF) and load it, 1074 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1075 * If load_elfboot() is successful, populate the fw_cfg info. 1076 */ 1077 if (pcmc->pvh_enabled && 1078 load_elfboot(kernel_filename, kernel_size, 1079 header, pvh_start_addr, fw_cfg)) { 1080 fclose(f); 1081 1082 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1083 strlen(kernel_cmdline) + 1); 1084 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1085 1086 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1087 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1088 header, sizeof(header)); 1089 1090 /* load initrd */ 1091 if (initrd_filename) { 1092 GMappedFile *mapped_file; 1093 gsize initrd_size; 1094 gchar *initrd_data; 1095 GError *gerr = NULL; 1096 1097 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1098 if (!mapped_file) { 1099 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1100 initrd_filename, gerr->message); 1101 exit(1); 1102 } 1103 pcms->initrd_mapped_file = mapped_file; 1104 1105 initrd_data = g_mapped_file_get_contents(mapped_file); 1106 initrd_size = g_mapped_file_get_length(mapped_file); 1107 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1108 if (initrd_size >= initrd_max) { 1109 fprintf(stderr, "qemu: initrd is too large, cannot support." 1110 "(max: %"PRIu32", need %"PRId64")\n", 1111 initrd_max, (uint64_t)initrd_size); 1112 exit(1); 1113 } 1114 1115 initrd_addr = (initrd_max - initrd_size) & ~4095; 1116 1117 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1118 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1119 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1120 initrd_size); 1121 } 1122 1123 option_rom[nb_option_roms].bootindex = 0; 1124 option_rom[nb_option_roms].name = "pvh.bin"; 1125 nb_option_roms++; 1126 1127 return; 1128 } 1129 protocol = 0; 1130 } 1131 1132 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1133 /* Low kernel */ 1134 real_addr = 0x90000; 1135 cmdline_addr = 0x9a000 - cmdline_size; 1136 prot_addr = 0x10000; 1137 } else if (protocol < 0x202) { 1138 /* High but ancient kernel */ 1139 real_addr = 0x90000; 1140 cmdline_addr = 0x9a000 - cmdline_size; 1141 prot_addr = 0x100000; 1142 } else { 1143 /* High and recent kernel */ 1144 real_addr = 0x10000; 1145 cmdline_addr = 0x20000; 1146 prot_addr = 0x100000; 1147 } 1148 1149 #if 0 1150 fprintf(stderr, 1151 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1152 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1153 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1154 real_addr, 1155 cmdline_addr, 1156 prot_addr); 1157 #endif 1158 1159 /* highest address for loading the initrd */ 1160 if (protocol >= 0x20c && 1161 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1162 /* 1163 * Linux has supported initrd up to 4 GB for a very long time (2007, 1164 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1165 * though it only sets initrd_max to 2 GB to "work around bootloader 1166 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1167 * has supported this. 1168 * 1169 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1170 * be loaded into any address. 1171 * 1172 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1173 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1174 * field). 1175 * 1176 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1177 */ 1178 initrd_max = UINT32_MAX; 1179 } else if (protocol >= 0x203) { 1180 initrd_max = ldl_p(header+0x22c); 1181 } else { 1182 initrd_max = 0x37ffffff; 1183 } 1184 1185 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1186 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1187 } 1188 1189 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1190 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1191 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1192 1193 if (protocol >= 0x202) { 1194 stl_p(header+0x228, cmdline_addr); 1195 } else { 1196 stw_p(header+0x20, 0xA33F); 1197 stw_p(header+0x22, cmdline_addr-real_addr); 1198 } 1199 1200 /* handle vga= parameter */ 1201 vmode = strstr(kernel_cmdline, "vga="); 1202 if (vmode) { 1203 unsigned int video_mode; 1204 /* skip "vga=" */ 1205 vmode += 4; 1206 if (!strncmp(vmode, "normal", 6)) { 1207 video_mode = 0xffff; 1208 } else if (!strncmp(vmode, "ext", 3)) { 1209 video_mode = 0xfffe; 1210 } else if (!strncmp(vmode, "ask", 3)) { 1211 video_mode = 0xfffd; 1212 } else { 1213 video_mode = strtol(vmode, NULL, 0); 1214 } 1215 stw_p(header+0x1fa, video_mode); 1216 } 1217 1218 /* loader type */ 1219 /* High nybble = B reserved for QEMU; low nybble is revision number. 1220 If this code is substantially changed, you may want to consider 1221 incrementing the revision. */ 1222 if (protocol >= 0x200) { 1223 header[0x210] = 0xB0; 1224 } 1225 /* heap */ 1226 if (protocol >= 0x201) { 1227 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1228 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1229 } 1230 1231 /* load initrd */ 1232 if (initrd_filename) { 1233 GMappedFile *mapped_file; 1234 gsize initrd_size; 1235 gchar *initrd_data; 1236 GError *gerr = NULL; 1237 1238 if (protocol < 0x200) { 1239 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1240 exit(1); 1241 } 1242 1243 mapped_file = g_mapped_file_new(initrd_filename, false, &gerr); 1244 if (!mapped_file) { 1245 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1246 initrd_filename, gerr->message); 1247 exit(1); 1248 } 1249 pcms->initrd_mapped_file = mapped_file; 1250 1251 initrd_data = g_mapped_file_get_contents(mapped_file); 1252 initrd_size = g_mapped_file_get_length(mapped_file); 1253 if (initrd_size >= initrd_max) { 1254 fprintf(stderr, "qemu: initrd is too large, cannot support." 1255 "(max: %"PRIu32", need %"PRId64")\n", 1256 initrd_max, (uint64_t)initrd_size); 1257 exit(1); 1258 } 1259 1260 initrd_addr = (initrd_max-initrd_size) & ~4095; 1261 1262 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1263 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1264 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1265 1266 stl_p(header+0x218, initrd_addr); 1267 stl_p(header+0x21c, initrd_size); 1268 } 1269 1270 /* load kernel and setup */ 1271 setup_size = header[0x1f1]; 1272 if (setup_size == 0) { 1273 setup_size = 4; 1274 } 1275 setup_size = (setup_size+1)*512; 1276 if (setup_size > kernel_size) { 1277 fprintf(stderr, "qemu: invalid kernel header\n"); 1278 exit(1); 1279 } 1280 kernel_size -= setup_size; 1281 1282 setup = g_malloc(setup_size); 1283 kernel = g_malloc(kernel_size); 1284 fseek(f, 0, SEEK_SET); 1285 if (fread(setup, 1, setup_size, f) != setup_size) { 1286 fprintf(stderr, "fread() failed\n"); 1287 exit(1); 1288 } 1289 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1290 fprintf(stderr, "fread() failed\n"); 1291 exit(1); 1292 } 1293 fclose(f); 1294 1295 /* append dtb to kernel */ 1296 if (dtb_filename) { 1297 if (protocol < 0x209) { 1298 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1299 exit(1); 1300 } 1301 1302 dtb_size = get_image_size(dtb_filename); 1303 if (dtb_size <= 0) { 1304 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1305 dtb_filename, strerror(errno)); 1306 exit(1); 1307 } 1308 1309 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1310 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1311 kernel = g_realloc(kernel, kernel_size); 1312 1313 stq_p(header+0x250, prot_addr + setup_data_offset); 1314 1315 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1316 setup_data->next = 0; 1317 setup_data->type = cpu_to_le32(SETUP_DTB); 1318 setup_data->len = cpu_to_le32(dtb_size); 1319 1320 load_image_size(dtb_filename, setup_data->data, dtb_size); 1321 } 1322 1323 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1324 1325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1326 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1327 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1328 1329 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1330 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1331 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1332 1333 option_rom[nb_option_roms].bootindex = 0; 1334 option_rom[nb_option_roms].name = "linuxboot.bin"; 1335 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1336 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1337 } 1338 nb_option_roms++; 1339 } 1340 1341 #define NE2000_NB_MAX 6 1342 1343 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1344 0x280, 0x380 }; 1345 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1346 1347 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1348 { 1349 static int nb_ne2k = 0; 1350 1351 if (nb_ne2k == NE2000_NB_MAX) 1352 return; 1353 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1354 ne2000_irq[nb_ne2k], nd); 1355 nb_ne2k++; 1356 } 1357 1358 DeviceState *cpu_get_current_apic(void) 1359 { 1360 if (current_cpu) { 1361 X86CPU *cpu = X86_CPU(current_cpu); 1362 return cpu->apic_state; 1363 } else { 1364 return NULL; 1365 } 1366 } 1367 1368 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1369 { 1370 X86CPU *cpu = opaque; 1371 1372 if (level) { 1373 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1374 } 1375 } 1376 1377 static void pc_new_cpu(PCMachineState *pcms, int64_t apic_id, Error **errp) 1378 { 1379 Object *cpu = NULL; 1380 Error *local_err = NULL; 1381 CPUX86State *env = NULL; 1382 1383 cpu = object_new(MACHINE(pcms)->cpu_type); 1384 1385 env = &X86_CPU(cpu)->env; 1386 env->nr_dies = pcms->smp_dies; 1387 1388 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1389 object_property_set_bool(cpu, true, "realized", &local_err); 1390 1391 object_unref(cpu); 1392 error_propagate(errp, local_err); 1393 } 1394 1395 /* 1396 * This function is very similar to smp_parse() 1397 * in hw/core/machine.c but includes CPU die support. 1398 */ 1399 void pc_smp_parse(MachineState *ms, QemuOpts *opts) 1400 { 1401 PCMachineState *pcms = PC_MACHINE(ms); 1402 1403 if (opts) { 1404 unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); 1405 unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); 1406 unsigned dies = qemu_opt_get_number(opts, "dies", 1); 1407 unsigned cores = qemu_opt_get_number(opts, "cores", 0); 1408 unsigned threads = qemu_opt_get_number(opts, "threads", 0); 1409 1410 /* compute missing values, prefer sockets over cores over threads */ 1411 if (cpus == 0 || sockets == 0) { 1412 cores = cores > 0 ? cores : 1; 1413 threads = threads > 0 ? threads : 1; 1414 if (cpus == 0) { 1415 sockets = sockets > 0 ? sockets : 1; 1416 cpus = cores * threads * dies * sockets; 1417 } else { 1418 ms->smp.max_cpus = 1419 qemu_opt_get_number(opts, "maxcpus", cpus); 1420 sockets = ms->smp.max_cpus / (cores * threads * dies); 1421 } 1422 } else if (cores == 0) { 1423 threads = threads > 0 ? threads : 1; 1424 cores = cpus / (sockets * dies * threads); 1425 cores = cores > 0 ? cores : 1; 1426 } else if (threads == 0) { 1427 threads = cpus / (cores * dies * sockets); 1428 threads = threads > 0 ? threads : 1; 1429 } else if (sockets * dies * cores * threads < cpus) { 1430 error_report("cpu topology: " 1431 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 1432 "smp_cpus (%u)", 1433 sockets, dies, cores, threads, cpus); 1434 exit(1); 1435 } 1436 1437 ms->smp.max_cpus = 1438 qemu_opt_get_number(opts, "maxcpus", cpus); 1439 1440 if (ms->smp.max_cpus < cpus) { 1441 error_report("maxcpus must be equal to or greater than smp"); 1442 exit(1); 1443 } 1444 1445 if (sockets * dies * cores * threads > ms->smp.max_cpus) { 1446 error_report("cpu topology: " 1447 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) > " 1448 "maxcpus (%u)", 1449 sockets, dies, cores, threads, 1450 ms->smp.max_cpus); 1451 exit(1); 1452 } 1453 1454 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 1455 warn_report("Invalid CPU topology deprecated: " 1456 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 1457 "!= maxcpus (%u)", 1458 sockets, dies, cores, threads, 1459 ms->smp.max_cpus); 1460 } 1461 1462 ms->smp.cpus = cpus; 1463 ms->smp.cores = cores; 1464 ms->smp.threads = threads; 1465 pcms->smp_dies = dies; 1466 } 1467 1468 if (ms->smp.cpus > 1) { 1469 Error *blocker = NULL; 1470 error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); 1471 replay_add_blocker(blocker); 1472 } 1473 } 1474 1475 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) 1476 { 1477 PCMachineState *pcms = PC_MACHINE(ms); 1478 int64_t apic_id = x86_cpu_apic_id_from_index(pcms, id); 1479 Error *local_err = NULL; 1480 1481 if (id < 0) { 1482 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1483 return; 1484 } 1485 1486 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1487 error_setg(errp, "Unable to add CPU: %" PRIi64 1488 ", resulting APIC ID (%" PRIi64 ") is too large", 1489 id, apic_id); 1490 return; 1491 } 1492 1493 pc_new_cpu(PC_MACHINE(ms), apic_id, &local_err); 1494 if (local_err) { 1495 error_propagate(errp, local_err); 1496 return; 1497 } 1498 } 1499 1500 void pc_cpus_init(PCMachineState *pcms) 1501 { 1502 int i; 1503 const CPUArchIdList *possible_cpus; 1504 MachineState *ms = MACHINE(pcms); 1505 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1506 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc); 1507 1508 x86_cpu_set_default_version(pcmc->default_cpu_version); 1509 1510 /* Calculates the limit to CPU APIC ID values 1511 * 1512 * Limit for the APIC ID value, so that all 1513 * CPU APIC IDs are < pcms->apic_id_limit. 1514 * 1515 * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). 1516 */ 1517 pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, 1518 ms->smp.max_cpus - 1) + 1; 1519 possible_cpus = mc->possible_cpu_arch_ids(ms); 1520 for (i = 0; i < ms->smp.cpus; i++) { 1521 pc_new_cpu(pcms, possible_cpus->cpus[i].arch_id, &error_fatal); 1522 } 1523 } 1524 1525 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1526 { 1527 if (cpus_count > 0xff) { 1528 /* If the number of CPUs can't be represented in 8 bits, the 1529 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1530 * to make old BIOSes fail more predictably. 1531 */ 1532 rtc_set_memory(rtc, 0x5f, 0); 1533 } else { 1534 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1535 } 1536 } 1537 1538 static 1539 void pc_machine_done(Notifier *notifier, void *data) 1540 { 1541 PCMachineState *pcms = container_of(notifier, 1542 PCMachineState, machine_done); 1543 PCIBus *bus = pcms->bus; 1544 1545 /* set the number of CPUs */ 1546 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1547 1548 if (bus) { 1549 int extra_hosts = 0; 1550 1551 QLIST_FOREACH(bus, &bus->child, sibling) { 1552 /* look for expander root buses */ 1553 if (pci_bus_is_root(bus)) { 1554 extra_hosts++; 1555 } 1556 } 1557 if (extra_hosts && pcms->fw_cfg) { 1558 uint64_t *val = g_malloc(sizeof(*val)); 1559 *val = cpu_to_le64(extra_hosts); 1560 fw_cfg_add_file(pcms->fw_cfg, 1561 "etc/extra-pci-roots", val, sizeof(*val)); 1562 } 1563 } 1564 1565 acpi_setup(); 1566 if (pcms->fw_cfg) { 1567 fw_cfg_build_smbios(MACHINE(pcms), pcms->fw_cfg); 1568 fw_cfg_build_feature_control(MACHINE(pcms), pcms->fw_cfg); 1569 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1570 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1571 } 1572 1573 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1574 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1575 1576 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1577 iommu->intr_eim != ON_OFF_AUTO_ON) { 1578 error_report("current -smp configuration requires " 1579 "Extended Interrupt Mode enabled. " 1580 "You can add an IOMMU using: " 1581 "-device intel-iommu,intremap=on,eim=on"); 1582 exit(EXIT_FAILURE); 1583 } 1584 } 1585 } 1586 1587 void pc_guest_info_init(PCMachineState *pcms) 1588 { 1589 int i; 1590 MachineState *ms = MACHINE(pcms); 1591 1592 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1593 pcms->numa_nodes = ms->numa_state->num_nodes; 1594 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1595 sizeof *pcms->node_mem); 1596 for (i = 0; i < ms->numa_state->num_nodes; i++) { 1597 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 1598 } 1599 1600 pcms->machine_done.notify = pc_machine_done; 1601 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1602 } 1603 1604 /* setup pci memory address space mapping into system address space */ 1605 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1606 MemoryRegion *pci_address_space) 1607 { 1608 /* Set to lower priority than RAM */ 1609 memory_region_add_subregion_overlap(system_memory, 0x0, 1610 pci_address_space, -1); 1611 } 1612 1613 void xen_load_linux(PCMachineState *pcms) 1614 { 1615 int i; 1616 FWCfgState *fw_cfg; 1617 1618 assert(MACHINE(pcms)->kernel_filename != NULL); 1619 1620 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1621 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1622 rom_set_fw(fw_cfg); 1623 1624 load_linux(pcms, fw_cfg); 1625 for (i = 0; i < nb_option_roms; i++) { 1626 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1627 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1628 !strcmp(option_rom[i].name, "pvh.bin") || 1629 !strcmp(option_rom[i].name, "multiboot.bin")); 1630 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1631 } 1632 pcms->fw_cfg = fw_cfg; 1633 } 1634 1635 void pc_memory_init(PCMachineState *pcms, 1636 MemoryRegion *system_memory, 1637 MemoryRegion *rom_memory, 1638 MemoryRegion **ram_memory) 1639 { 1640 int linux_boot, i; 1641 MemoryRegion *ram, *option_rom_mr; 1642 MemoryRegion *ram_below_4g, *ram_above_4g; 1643 FWCfgState *fw_cfg; 1644 MachineState *machine = MACHINE(pcms); 1645 MachineClass *mc = MACHINE_GET_CLASS(machine); 1646 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1647 1648 assert(machine->ram_size == pcms->below_4g_mem_size + 1649 pcms->above_4g_mem_size); 1650 1651 linux_boot = (machine->kernel_filename != NULL); 1652 1653 /* Allocate RAM. We allocate it as a single memory region and use 1654 * aliases to address portions of it, mostly for backwards compatibility 1655 * with older qemus that used qemu_ram_alloc(). 1656 */ 1657 ram = g_malloc(sizeof(*ram)); 1658 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1659 machine->ram_size); 1660 *ram_memory = ram; 1661 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1662 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1663 0, pcms->below_4g_mem_size); 1664 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1665 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1666 if (pcms->above_4g_mem_size > 0) { 1667 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1668 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1669 pcms->below_4g_mem_size, 1670 pcms->above_4g_mem_size); 1671 memory_region_add_subregion(system_memory, 0x100000000ULL, 1672 ram_above_4g); 1673 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1674 } 1675 1676 if (!pcmc->has_reserved_memory && 1677 (machine->ram_slots || 1678 (machine->maxram_size > machine->ram_size))) { 1679 1680 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1681 mc->name); 1682 exit(EXIT_FAILURE); 1683 } 1684 1685 /* always allocate the device memory information */ 1686 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1687 1688 /* initialize device memory address space */ 1689 if (pcmc->has_reserved_memory && 1690 (machine->ram_size < machine->maxram_size)) { 1691 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1692 1693 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1694 error_report("unsupported amount of memory slots: %"PRIu64, 1695 machine->ram_slots); 1696 exit(EXIT_FAILURE); 1697 } 1698 1699 if (QEMU_ALIGN_UP(machine->maxram_size, 1700 TARGET_PAGE_SIZE) != machine->maxram_size) { 1701 error_report("maximum memory size must by aligned to multiple of " 1702 "%d bytes", TARGET_PAGE_SIZE); 1703 exit(EXIT_FAILURE); 1704 } 1705 1706 machine->device_memory->base = 1707 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1708 1709 if (pcmc->enforce_aligned_dimm) { 1710 /* size device region assuming 1G page max alignment per slot */ 1711 device_mem_size += (1 * GiB) * machine->ram_slots; 1712 } 1713 1714 if ((machine->device_memory->base + device_mem_size) < 1715 device_mem_size) { 1716 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1717 machine->maxram_size); 1718 exit(EXIT_FAILURE); 1719 } 1720 1721 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1722 "device-memory", device_mem_size); 1723 memory_region_add_subregion(system_memory, machine->device_memory->base, 1724 &machine->device_memory->mr); 1725 } 1726 1727 /* Initialize PC system firmware */ 1728 pc_system_firmware_init(pcms, rom_memory); 1729 1730 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1731 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1732 &error_fatal); 1733 if (pcmc->pci_enabled) { 1734 memory_region_set_readonly(option_rom_mr, true); 1735 } 1736 memory_region_add_subregion_overlap(rom_memory, 1737 PC_ROM_MIN_VGA, 1738 option_rom_mr, 1739 1); 1740 1741 fw_cfg = fw_cfg_arch_create(machine, 1742 pcms->boot_cpus, pcms->apic_id_limit); 1743 1744 rom_set_fw(fw_cfg); 1745 1746 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1747 uint64_t *val = g_malloc(sizeof(*val)); 1748 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1749 uint64_t res_mem_end = machine->device_memory->base; 1750 1751 if (!pcmc->broken_reserved_end) { 1752 res_mem_end += memory_region_size(&machine->device_memory->mr); 1753 } 1754 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1755 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1756 } 1757 1758 if (linux_boot) { 1759 load_linux(pcms, fw_cfg); 1760 } 1761 1762 for (i = 0; i < nb_option_roms; i++) { 1763 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1764 } 1765 pcms->fw_cfg = fw_cfg; 1766 1767 /* Init default IOAPIC address space */ 1768 pcms->ioapic_as = &address_space_memory; 1769 1770 /* Init ACPI memory hotplug IO base address */ 1771 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1772 } 1773 1774 /* 1775 * The 64bit pci hole starts after "above 4G RAM" and 1776 * potentially the space reserved for memory hotplug. 1777 */ 1778 uint64_t pc_pci_hole64_start(void) 1779 { 1780 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1781 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1782 MachineState *ms = MACHINE(pcms); 1783 uint64_t hole64_start = 0; 1784 1785 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1786 hole64_start = ms->device_memory->base; 1787 if (!pcmc->broken_reserved_end) { 1788 hole64_start += memory_region_size(&ms->device_memory->mr); 1789 } 1790 } else { 1791 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1792 } 1793 1794 return ROUND_UP(hole64_start, 1 * GiB); 1795 } 1796 1797 qemu_irq pc_allocate_cpu_irq(void) 1798 { 1799 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1800 } 1801 1802 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1803 { 1804 DeviceState *dev = NULL; 1805 1806 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1807 if (pci_bus) { 1808 PCIDevice *pcidev = pci_vga_init(pci_bus); 1809 dev = pcidev ? &pcidev->qdev : NULL; 1810 } else if (isa_bus) { 1811 ISADevice *isadev = isa_vga_init(isa_bus); 1812 dev = isadev ? DEVICE(isadev) : NULL; 1813 } 1814 rom_reset_order_override(); 1815 return dev; 1816 } 1817 1818 static const MemoryRegionOps ioport80_io_ops = { 1819 .write = ioport80_write, 1820 .read = ioport80_read, 1821 .endianness = DEVICE_NATIVE_ENDIAN, 1822 .impl = { 1823 .min_access_size = 1, 1824 .max_access_size = 1, 1825 }, 1826 }; 1827 1828 static const MemoryRegionOps ioportF0_io_ops = { 1829 .write = ioportF0_write, 1830 .read = ioportF0_read, 1831 .endianness = DEVICE_NATIVE_ENDIAN, 1832 .impl = { 1833 .min_access_size = 1, 1834 .max_access_size = 1, 1835 }, 1836 }; 1837 1838 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1839 { 1840 int i; 1841 DriveInfo *fd[MAX_FD]; 1842 qemu_irq *a20_line; 1843 ISADevice *i8042, *port92, *vmmouse; 1844 1845 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1846 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1847 1848 for (i = 0; i < MAX_FD; i++) { 1849 fd[i] = drive_get(IF_FLOPPY, 0, i); 1850 create_fdctrl |= !!fd[i]; 1851 } 1852 if (create_fdctrl) { 1853 fdctrl_init_isa(isa_bus, fd); 1854 } 1855 1856 i8042 = isa_create_simple(isa_bus, "i8042"); 1857 if (!no_vmport) { 1858 vmport_init(isa_bus); 1859 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1860 } else { 1861 vmmouse = NULL; 1862 } 1863 if (vmmouse) { 1864 DeviceState *dev = DEVICE(vmmouse); 1865 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1866 qdev_init_nofail(dev); 1867 } 1868 port92 = isa_create_simple(isa_bus, "port92"); 1869 1870 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1871 i8042_setup_a20_line(i8042, a20_line[0]); 1872 port92_init(port92, a20_line[1]); 1873 g_free(a20_line); 1874 } 1875 1876 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1877 ISADevice **rtc_state, 1878 bool create_fdctrl, 1879 bool no_vmport, 1880 bool has_pit, 1881 uint32_t hpet_irqs) 1882 { 1883 int i; 1884 DeviceState *hpet = NULL; 1885 int pit_isa_irq = 0; 1886 qemu_irq pit_alt_irq = NULL; 1887 qemu_irq rtc_irq = NULL; 1888 ISADevice *pit = NULL; 1889 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1890 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1891 1892 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1893 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1894 1895 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1896 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1897 1898 /* 1899 * Check if an HPET shall be created. 1900 * 1901 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1902 * when the HPET wants to take over. Thus we have to disable the latter. 1903 */ 1904 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1905 /* In order to set property, here not using sysbus_try_create_simple */ 1906 hpet = qdev_try_create(NULL, TYPE_HPET); 1907 if (hpet) { 1908 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1909 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1910 * IRQ8 and IRQ2. 1911 */ 1912 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1913 HPET_INTCAP, NULL); 1914 if (!compat) { 1915 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1916 } 1917 qdev_init_nofail(hpet); 1918 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1919 1920 for (i = 0; i < GSI_NUM_PINS; i++) { 1921 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1922 } 1923 pit_isa_irq = -1; 1924 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1925 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1926 } 1927 } 1928 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1929 1930 qemu_register_boot_set(pc_boot_set, *rtc_state); 1931 1932 if (!xen_enabled() && has_pit) { 1933 if (kvm_pit_in_kernel()) { 1934 pit = kvm_pit_init(isa_bus, 0x40); 1935 } else { 1936 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1937 } 1938 if (hpet) { 1939 /* connect PIT to output control line of the HPET */ 1940 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1941 } 1942 pcspk_init(isa_bus, pit); 1943 } 1944 1945 i8257_dma_init(isa_bus, 0); 1946 1947 /* Super I/O */ 1948 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 1949 } 1950 1951 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1952 { 1953 int i; 1954 1955 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1956 for (i = 0; i < nb_nics; i++) { 1957 NICInfo *nd = &nd_table[i]; 1958 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1959 1960 if (g_str_equal(model, "ne2k_isa")) { 1961 pc_init_ne2k_isa(isa_bus, nd); 1962 } else { 1963 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1964 } 1965 } 1966 rom_reset_order_override(); 1967 } 1968 1969 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1970 { 1971 DeviceState *dev; 1972 SysBusDevice *d; 1973 unsigned int i; 1974 1975 if (kvm_ioapic_in_kernel()) { 1976 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 1977 } else { 1978 dev = qdev_create(NULL, TYPE_IOAPIC); 1979 } 1980 if (parent_name) { 1981 object_property_add_child(object_resolve_path(parent_name, NULL), 1982 "ioapic", OBJECT(dev), NULL); 1983 } 1984 qdev_init_nofail(dev); 1985 d = SYS_BUS_DEVICE(dev); 1986 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1987 1988 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1989 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1990 } 1991 } 1992 1993 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1994 Error **errp) 1995 { 1996 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1997 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1998 const MachineState *ms = MACHINE(hotplug_dev); 1999 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2000 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2001 Error *local_err = NULL; 2002 2003 /* 2004 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2005 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2006 * addition to cover this case. 2007 */ 2008 if (!pcms->acpi_dev || !acpi_enabled) { 2009 error_setg(errp, 2010 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2011 return; 2012 } 2013 2014 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2015 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2016 return; 2017 } 2018 2019 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 2020 if (local_err) { 2021 error_propagate(errp, local_err); 2022 return; 2023 } 2024 2025 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2026 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2027 } 2028 2029 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2030 DeviceState *dev, Error **errp) 2031 { 2032 Error *local_err = NULL; 2033 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2034 MachineState *ms = MACHINE(hotplug_dev); 2035 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2036 2037 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2038 if (local_err) { 2039 goto out; 2040 } 2041 2042 if (is_nvdimm) { 2043 nvdimm_plug(ms->nvdimms_state); 2044 } 2045 2046 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2047 out: 2048 error_propagate(errp, local_err); 2049 } 2050 2051 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2052 DeviceState *dev, Error **errp) 2053 { 2054 Error *local_err = NULL; 2055 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2056 2057 /* 2058 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2059 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2060 * addition to cover this case. 2061 */ 2062 if (!pcms->acpi_dev || !acpi_enabled) { 2063 error_setg(&local_err, 2064 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2065 goto out; 2066 } 2067 2068 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2069 error_setg(&local_err, 2070 "nvdimm device hot unplug is not supported yet."); 2071 goto out; 2072 } 2073 2074 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2075 &local_err); 2076 out: 2077 error_propagate(errp, local_err); 2078 } 2079 2080 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2081 DeviceState *dev, Error **errp) 2082 { 2083 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2084 Error *local_err = NULL; 2085 2086 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2087 if (local_err) { 2088 goto out; 2089 } 2090 2091 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2092 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2093 out: 2094 error_propagate(errp, local_err); 2095 } 2096 2097 static int pc_apic_cmp(const void *a, const void *b) 2098 { 2099 CPUArchId *apic_a = (CPUArchId *)a; 2100 CPUArchId *apic_b = (CPUArchId *)b; 2101 2102 return apic_a->arch_id - apic_b->arch_id; 2103 } 2104 2105 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2106 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2107 * entry corresponding to CPU's apic_id returns NULL. 2108 */ 2109 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2110 { 2111 CPUArchId apic_id, *found_cpu; 2112 2113 apic_id.arch_id = id; 2114 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2115 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2116 pc_apic_cmp); 2117 if (found_cpu && idx) { 2118 *idx = found_cpu - ms->possible_cpus->cpus; 2119 } 2120 return found_cpu; 2121 } 2122 2123 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2124 DeviceState *dev, Error **errp) 2125 { 2126 CPUArchId *found_cpu; 2127 Error *local_err = NULL; 2128 X86CPU *cpu = X86_CPU(dev); 2129 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2130 2131 if (pcms->acpi_dev) { 2132 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2133 if (local_err) { 2134 goto out; 2135 } 2136 } 2137 2138 /* increment the number of CPUs */ 2139 pcms->boot_cpus++; 2140 if (pcms->rtc) { 2141 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2142 } 2143 if (pcms->fw_cfg) { 2144 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2145 } 2146 2147 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2148 found_cpu->cpu = OBJECT(dev); 2149 out: 2150 error_propagate(errp, local_err); 2151 } 2152 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2153 DeviceState *dev, Error **errp) 2154 { 2155 int idx = -1; 2156 Error *local_err = NULL; 2157 X86CPU *cpu = X86_CPU(dev); 2158 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2159 2160 if (!pcms->acpi_dev) { 2161 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2162 goto out; 2163 } 2164 2165 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2166 assert(idx != -1); 2167 if (idx == 0) { 2168 error_setg(&local_err, "Boot CPU is unpluggable"); 2169 goto out; 2170 } 2171 2172 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2173 &local_err); 2174 if (local_err) { 2175 goto out; 2176 } 2177 2178 out: 2179 error_propagate(errp, local_err); 2180 2181 } 2182 2183 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2184 DeviceState *dev, Error **errp) 2185 { 2186 CPUArchId *found_cpu; 2187 Error *local_err = NULL; 2188 X86CPU *cpu = X86_CPU(dev); 2189 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2190 2191 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2192 if (local_err) { 2193 goto out; 2194 } 2195 2196 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2197 found_cpu->cpu = NULL; 2198 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2199 2200 /* decrement the number of CPUs */ 2201 pcms->boot_cpus--; 2202 /* Update the number of CPUs in CMOS */ 2203 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2204 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2205 out: 2206 error_propagate(errp, local_err); 2207 } 2208 2209 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2210 DeviceState *dev, Error **errp) 2211 { 2212 int idx; 2213 CPUState *cs; 2214 CPUArchId *cpu_slot; 2215 X86CPUTopoInfo topo; 2216 X86CPU *cpu = X86_CPU(dev); 2217 CPUX86State *env = &cpu->env; 2218 MachineState *ms = MACHINE(hotplug_dev); 2219 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2220 unsigned int smp_cores = ms->smp.cores; 2221 unsigned int smp_threads = ms->smp.threads; 2222 2223 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2224 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2225 ms->cpu_type); 2226 return; 2227 } 2228 2229 env->nr_dies = pcms->smp_dies; 2230 2231 /* 2232 * If APIC ID is not set, 2233 * set it based on socket/die/core/thread properties. 2234 */ 2235 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2236 int max_socket = (ms->smp.max_cpus - 1) / 2237 smp_threads / smp_cores / pcms->smp_dies; 2238 2239 /* 2240 * die-id was optional in QEMU 4.0 and older, so keep it optional 2241 * if there's only one die per socket. 2242 */ 2243 if (cpu->die_id < 0 && pcms->smp_dies == 1) { 2244 cpu->die_id = 0; 2245 } 2246 2247 if (cpu->socket_id < 0) { 2248 error_setg(errp, "CPU socket-id is not set"); 2249 return; 2250 } else if (cpu->socket_id > max_socket) { 2251 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2252 cpu->socket_id, max_socket); 2253 return; 2254 } 2255 if (cpu->die_id < 0) { 2256 error_setg(errp, "CPU die-id is not set"); 2257 return; 2258 } else if (cpu->die_id > pcms->smp_dies - 1) { 2259 error_setg(errp, "Invalid CPU die-id: %u must be in range 0:%u", 2260 cpu->die_id, pcms->smp_dies - 1); 2261 return; 2262 } 2263 if (cpu->core_id < 0) { 2264 error_setg(errp, "CPU core-id is not set"); 2265 return; 2266 } else if (cpu->core_id > (smp_cores - 1)) { 2267 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2268 cpu->core_id, smp_cores - 1); 2269 return; 2270 } 2271 if (cpu->thread_id < 0) { 2272 error_setg(errp, "CPU thread-id is not set"); 2273 return; 2274 } else if (cpu->thread_id > (smp_threads - 1)) { 2275 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2276 cpu->thread_id, smp_threads - 1); 2277 return; 2278 } 2279 2280 topo.pkg_id = cpu->socket_id; 2281 topo.die_id = cpu->die_id; 2282 topo.core_id = cpu->core_id; 2283 topo.smt_id = cpu->thread_id; 2284 cpu->apic_id = apicid_from_topo_ids(pcms->smp_dies, smp_cores, 2285 smp_threads, &topo); 2286 } 2287 2288 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2289 if (!cpu_slot) { 2290 MachineState *ms = MACHINE(pcms); 2291 2292 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2293 smp_cores, smp_threads, &topo); 2294 error_setg(errp, 2295 "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" 2296 " APIC ID %" PRIu32 ", valid index range 0:%d", 2297 topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, 2298 cpu->apic_id, ms->possible_cpus->len - 1); 2299 return; 2300 } 2301 2302 if (cpu_slot->cpu) { 2303 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2304 idx, cpu->apic_id); 2305 return; 2306 } 2307 2308 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2309 * so that machine_query_hotpluggable_cpus would show correct values 2310 */ 2311 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2312 * once -smp refactoring is complete and there will be CPU private 2313 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2314 x86_topo_ids_from_apicid(cpu->apic_id, pcms->smp_dies, 2315 smp_cores, smp_threads, &topo); 2316 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2317 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2318 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2319 return; 2320 } 2321 cpu->socket_id = topo.pkg_id; 2322 2323 if (cpu->die_id != -1 && cpu->die_id != topo.die_id) { 2324 error_setg(errp, "property die-id: %u doesn't match set apic-id:" 2325 " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); 2326 return; 2327 } 2328 cpu->die_id = topo.die_id; 2329 2330 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2331 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2332 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2333 return; 2334 } 2335 cpu->core_id = topo.core_id; 2336 2337 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2338 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2339 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2340 return; 2341 } 2342 cpu->thread_id = topo.smt_id; 2343 2344 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && 2345 !kvm_hv_vpindex_settable()) { 2346 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2347 return; 2348 } 2349 2350 cs = CPU(cpu); 2351 cs->cpu_index = idx; 2352 2353 numa_cpu_pre_plug(cpu_slot, dev, errp); 2354 } 2355 2356 static void pc_virtio_pmem_pci_pre_plug(HotplugHandler *hotplug_dev, 2357 DeviceState *dev, Error **errp) 2358 { 2359 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2360 Error *local_err = NULL; 2361 2362 if (!hotplug_dev2) { 2363 /* 2364 * Without a bus hotplug handler, we cannot control the plug/unplug 2365 * order. This should never be the case on x86, however better add 2366 * a safety net. 2367 */ 2368 error_setg(errp, "virtio-pmem-pci not supported on this bus."); 2369 return; 2370 } 2371 /* 2372 * First, see if we can plug this memory device at all. If that 2373 * succeeds, branch of to the actual hotplug handler. 2374 */ 2375 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 2376 &local_err); 2377 if (!local_err) { 2378 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 2379 } 2380 error_propagate(errp, local_err); 2381 } 2382 2383 static void pc_virtio_pmem_pci_plug(HotplugHandler *hotplug_dev, 2384 DeviceState *dev, Error **errp) 2385 { 2386 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 2387 Error *local_err = NULL; 2388 2389 /* 2390 * Plug the memory device first and then branch off to the actual 2391 * hotplug handler. If that one fails, we can easily undo the memory 2392 * device bits. 2393 */ 2394 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2395 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 2396 if (local_err) { 2397 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 2398 } 2399 error_propagate(errp, local_err); 2400 } 2401 2402 static void pc_virtio_pmem_pci_unplug_request(HotplugHandler *hotplug_dev, 2403 DeviceState *dev, Error **errp) 2404 { 2405 /* We don't support virtio pmem hot unplug */ 2406 error_setg(errp, "virtio pmem device unplug not supported."); 2407 } 2408 2409 static void pc_virtio_pmem_pci_unplug(HotplugHandler *hotplug_dev, 2410 DeviceState *dev, Error **errp) 2411 { 2412 /* We don't support virtio pmem hot unplug */ 2413 } 2414 2415 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2416 DeviceState *dev, Error **errp) 2417 { 2418 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2419 pc_memory_pre_plug(hotplug_dev, dev, errp); 2420 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2421 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2422 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2423 pc_virtio_pmem_pci_pre_plug(hotplug_dev, dev, errp); 2424 } 2425 } 2426 2427 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2428 DeviceState *dev, Error **errp) 2429 { 2430 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2431 pc_memory_plug(hotplug_dev, dev, errp); 2432 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2433 pc_cpu_plug(hotplug_dev, dev, errp); 2434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2435 pc_virtio_pmem_pci_plug(hotplug_dev, dev, errp); 2436 } 2437 } 2438 2439 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2440 DeviceState *dev, Error **errp) 2441 { 2442 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2443 pc_memory_unplug_request(hotplug_dev, dev, errp); 2444 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2445 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2446 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2447 pc_virtio_pmem_pci_unplug_request(hotplug_dev, dev, errp); 2448 } else { 2449 error_setg(errp, "acpi: device unplug request for not supported device" 2450 " type: %s", object_get_typename(OBJECT(dev))); 2451 } 2452 } 2453 2454 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2455 DeviceState *dev, Error **errp) 2456 { 2457 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2458 pc_memory_unplug(hotplug_dev, dev, errp); 2459 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2460 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2461 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2462 pc_virtio_pmem_pci_unplug(hotplug_dev, dev, errp); 2463 } else { 2464 error_setg(errp, "acpi: device unplug for not supported device" 2465 " type: %s", object_get_typename(OBJECT(dev))); 2466 } 2467 } 2468 2469 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2470 DeviceState *dev) 2471 { 2472 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2473 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 2474 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI)) { 2475 return HOTPLUG_HANDLER(machine); 2476 } 2477 2478 return NULL; 2479 } 2480 2481 static void 2482 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2483 const char *name, void *opaque, 2484 Error **errp) 2485 { 2486 MachineState *ms = MACHINE(obj); 2487 int64_t value = 0; 2488 2489 if (ms->device_memory) { 2490 value = memory_region_size(&ms->device_memory->mr); 2491 } 2492 2493 visit_type_int(v, name, &value, errp); 2494 } 2495 2496 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2497 const char *name, void *opaque, 2498 Error **errp) 2499 { 2500 PCMachineState *pcms = PC_MACHINE(obj); 2501 uint64_t value = pcms->max_ram_below_4g; 2502 2503 visit_type_size(v, name, &value, errp); 2504 } 2505 2506 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2507 const char *name, void *opaque, 2508 Error **errp) 2509 { 2510 PCMachineState *pcms = PC_MACHINE(obj); 2511 Error *error = NULL; 2512 uint64_t value; 2513 2514 visit_type_size(v, name, &value, &error); 2515 if (error) { 2516 error_propagate(errp, error); 2517 return; 2518 } 2519 if (value > 4 * GiB) { 2520 error_setg(&error, 2521 "Machine option 'max-ram-below-4g=%"PRIu64 2522 "' expects size less than or equal to 4G", value); 2523 error_propagate(errp, error); 2524 return; 2525 } 2526 2527 if (value < 1 * MiB) { 2528 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2529 "BIOS may not work with less than 1MiB", value); 2530 } 2531 2532 pcms->max_ram_below_4g = value; 2533 } 2534 2535 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2536 void *opaque, Error **errp) 2537 { 2538 PCMachineState *pcms = PC_MACHINE(obj); 2539 OnOffAuto vmport = pcms->vmport; 2540 2541 visit_type_OnOffAuto(v, name, &vmport, errp); 2542 } 2543 2544 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2545 void *opaque, Error **errp) 2546 { 2547 PCMachineState *pcms = PC_MACHINE(obj); 2548 2549 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2550 } 2551 2552 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2553 { 2554 bool smm_available = false; 2555 2556 if (pcms->smm == ON_OFF_AUTO_OFF) { 2557 return false; 2558 } 2559 2560 if (tcg_enabled() || qtest_enabled()) { 2561 smm_available = true; 2562 } else if (kvm_enabled()) { 2563 smm_available = kvm_has_smm(); 2564 } 2565 2566 if (smm_available) { 2567 return true; 2568 } 2569 2570 if (pcms->smm == ON_OFF_AUTO_ON) { 2571 error_report("System Management Mode not supported by this hypervisor."); 2572 exit(1); 2573 } 2574 return false; 2575 } 2576 2577 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2578 void *opaque, Error **errp) 2579 { 2580 PCMachineState *pcms = PC_MACHINE(obj); 2581 OnOffAuto smm = pcms->smm; 2582 2583 visit_type_OnOffAuto(v, name, &smm, errp); 2584 } 2585 2586 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2587 void *opaque, Error **errp) 2588 { 2589 PCMachineState *pcms = PC_MACHINE(obj); 2590 2591 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2592 } 2593 2594 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2595 { 2596 PCMachineState *pcms = PC_MACHINE(obj); 2597 2598 return pcms->smbus_enabled; 2599 } 2600 2601 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2602 { 2603 PCMachineState *pcms = PC_MACHINE(obj); 2604 2605 pcms->smbus_enabled = value; 2606 } 2607 2608 static bool pc_machine_get_sata(Object *obj, Error **errp) 2609 { 2610 PCMachineState *pcms = PC_MACHINE(obj); 2611 2612 return pcms->sata_enabled; 2613 } 2614 2615 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2616 { 2617 PCMachineState *pcms = PC_MACHINE(obj); 2618 2619 pcms->sata_enabled = value; 2620 } 2621 2622 static bool pc_machine_get_pit(Object *obj, Error **errp) 2623 { 2624 PCMachineState *pcms = PC_MACHINE(obj); 2625 2626 return pcms->pit_enabled; 2627 } 2628 2629 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2630 { 2631 PCMachineState *pcms = PC_MACHINE(obj); 2632 2633 pcms->pit_enabled = value; 2634 } 2635 2636 static void pc_machine_initfn(Object *obj) 2637 { 2638 PCMachineState *pcms = PC_MACHINE(obj); 2639 2640 pcms->max_ram_below_4g = 0; /* use default */ 2641 pcms->smm = ON_OFF_AUTO_AUTO; 2642 #ifdef CONFIG_VMPORT 2643 pcms->vmport = ON_OFF_AUTO_AUTO; 2644 #else 2645 pcms->vmport = ON_OFF_AUTO_OFF; 2646 #endif /* CONFIG_VMPORT */ 2647 /* acpi build is enabled by default if machine supports it */ 2648 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2649 pcms->smbus_enabled = true; 2650 pcms->sata_enabled = true; 2651 pcms->pit_enabled = true; 2652 pcms->smp_dies = 1; 2653 2654 pc_system_flash_create(pcms); 2655 } 2656 2657 static void pc_machine_reset(MachineState *machine) 2658 { 2659 CPUState *cs; 2660 X86CPU *cpu; 2661 2662 qemu_devices_reset(); 2663 2664 /* Reset APIC after devices have been reset to cancel 2665 * any changes that qemu_devices_reset() might have done. 2666 */ 2667 CPU_FOREACH(cs) { 2668 cpu = X86_CPU(cs); 2669 2670 if (cpu->apic_state) { 2671 device_reset(cpu->apic_state); 2672 } 2673 } 2674 } 2675 2676 static void pc_machine_wakeup(MachineState *machine) 2677 { 2678 cpu_synchronize_all_states(); 2679 pc_machine_reset(machine); 2680 cpu_synchronize_all_post_reset(); 2681 } 2682 2683 static CpuInstanceProperties 2684 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2685 { 2686 MachineClass *mc = MACHINE_GET_CLASS(ms); 2687 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2688 2689 assert(cpu_index < possible_cpus->len); 2690 return possible_cpus->cpus[cpu_index].props; 2691 } 2692 2693 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2694 { 2695 X86CPUTopoInfo topo; 2696 PCMachineState *pcms = PC_MACHINE(ms); 2697 2698 assert(idx < ms->possible_cpus->len); 2699 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2700 pcms->smp_dies, ms->smp.cores, 2701 ms->smp.threads, &topo); 2702 return topo.pkg_id % ms->numa_state->num_nodes; 2703 } 2704 2705 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2706 { 2707 PCMachineState *pcms = PC_MACHINE(ms); 2708 int i; 2709 unsigned int max_cpus = ms->smp.max_cpus; 2710 2711 if (ms->possible_cpus) { 2712 /* 2713 * make sure that max_cpus hasn't changed since the first use, i.e. 2714 * -smp hasn't been parsed after it 2715 */ 2716 assert(ms->possible_cpus->len == max_cpus); 2717 return ms->possible_cpus; 2718 } 2719 2720 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2721 sizeof(CPUArchId) * max_cpus); 2722 ms->possible_cpus->len = max_cpus; 2723 for (i = 0; i < ms->possible_cpus->len; i++) { 2724 X86CPUTopoInfo topo; 2725 2726 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2727 ms->possible_cpus->cpus[i].vcpus_count = 1; 2728 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(pcms, i); 2729 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2730 pcms->smp_dies, ms->smp.cores, 2731 ms->smp.threads, &topo); 2732 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2733 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2734 if (pcms->smp_dies > 1) { 2735 ms->possible_cpus->cpus[i].props.has_die_id = true; 2736 ms->possible_cpus->cpus[i].props.die_id = topo.die_id; 2737 } 2738 ms->possible_cpus->cpus[i].props.has_core_id = true; 2739 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2740 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2741 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2742 } 2743 return ms->possible_cpus; 2744 } 2745 2746 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2747 { 2748 /* cpu index isn't used */ 2749 CPUState *cs; 2750 2751 CPU_FOREACH(cs) { 2752 X86CPU *cpu = X86_CPU(cs); 2753 2754 if (!cpu->apic_state) { 2755 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2756 } else { 2757 apic_deliver_nmi(cpu->apic_state); 2758 } 2759 } 2760 } 2761 2762 2763 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 2764 { 2765 X86IOMMUState *iommu = x86_iommu_get_default(); 2766 IntelIOMMUState *intel_iommu; 2767 2768 if (iommu && 2769 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 2770 object_dynamic_cast((Object *)dev, "vfio-pci")) { 2771 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 2772 if (!intel_iommu->caching_mode) { 2773 error_setg(errp, "Device assignment is not allowed without " 2774 "enabling caching-mode=on for Intel IOMMU."); 2775 return false; 2776 } 2777 } 2778 2779 return true; 2780 } 2781 2782 static void pc_machine_class_init(ObjectClass *oc, void *data) 2783 { 2784 MachineClass *mc = MACHINE_CLASS(oc); 2785 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2786 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2787 NMIClass *nc = NMI_CLASS(oc); 2788 2789 pcmc->pci_enabled = true; 2790 pcmc->has_acpi_build = true; 2791 pcmc->rsdp_in_ram = true; 2792 pcmc->smbios_defaults = true; 2793 pcmc->smbios_uuid_encoded = true; 2794 pcmc->gigabyte_align = true; 2795 pcmc->has_reserved_memory = true; 2796 pcmc->kvmclock_enabled = true; 2797 pcmc->enforce_aligned_dimm = true; 2798 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2799 * to be used at the moment, 32K should be enough for a while. */ 2800 pcmc->acpi_data_size = 0x20000 + 0x8000; 2801 pcmc->save_tsc_khz = true; 2802 pcmc->linuxboot_dma_enabled = true; 2803 pcmc->pvh_enabled = true; 2804 assert(!mc->get_hotplug_handler); 2805 mc->get_hotplug_handler = pc_get_hotplug_handler; 2806 mc->hotplug_allowed = pc_hotplug_allowed; 2807 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2808 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2809 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2810 mc->auto_enable_numa_with_memhp = true; 2811 mc->has_hotpluggable_cpus = true; 2812 mc->default_boot_order = "cad"; 2813 mc->hot_add_cpu = pc_hot_add_cpu; 2814 mc->smp_parse = pc_smp_parse; 2815 mc->block_default_type = IF_IDE; 2816 mc->max_cpus = 255; 2817 mc->reset = pc_machine_reset; 2818 mc->wakeup = pc_machine_wakeup; 2819 hc->pre_plug = pc_machine_device_pre_plug_cb; 2820 hc->plug = pc_machine_device_plug_cb; 2821 hc->unplug_request = pc_machine_device_unplug_request_cb; 2822 hc->unplug = pc_machine_device_unplug_cb; 2823 nc->nmi_monitor_handler = x86_nmi; 2824 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2825 mc->nvdimm_supported = true; 2826 mc->numa_mem_supported = true; 2827 2828 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2829 pc_machine_get_device_memory_region_size, NULL, 2830 NULL, NULL, &error_abort); 2831 2832 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2833 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2834 NULL, NULL, &error_abort); 2835 2836 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2837 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2838 2839 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2840 pc_machine_get_smm, pc_machine_set_smm, 2841 NULL, NULL, &error_abort); 2842 object_class_property_set_description(oc, PC_MACHINE_SMM, 2843 "Enable SMM (pc & q35)", &error_abort); 2844 2845 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2846 pc_machine_get_vmport, pc_machine_set_vmport, 2847 NULL, NULL, &error_abort); 2848 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2849 "Enable vmport (pc & q35)", &error_abort); 2850 2851 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2852 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2853 2854 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2855 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2856 2857 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2858 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2859 } 2860 2861 static const TypeInfo pc_machine_info = { 2862 .name = TYPE_PC_MACHINE, 2863 .parent = TYPE_MACHINE, 2864 .abstract = true, 2865 .instance_size = sizeof(PCMachineState), 2866 .instance_init = pc_machine_initfn, 2867 .class_size = sizeof(PCMachineClass), 2868 .class_init = pc_machine_class_init, 2869 .interfaces = (InterfaceInfo[]) { 2870 { TYPE_HOTPLUG_HANDLER }, 2871 { TYPE_NMI }, 2872 { } 2873 }, 2874 }; 2875 2876 static void pc_machine_register_types(void) 2877 { 2878 type_register_static(&pc_machine_info); 2879 } 2880 2881 type_init(pc_machine_register_types) 2882