1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/char/parallel.h" 30 #include "hw/hyperv/hv-balloon.h" 31 #include "hw/i386/fw_cfg.h" 32 #include "hw/i386/vmport.h" 33 #include "sysemu/cpus.h" 34 #include "hw/ide/ide-bus.h" 35 #include "hw/timer/hpet.h" 36 #include "hw/loader.h" 37 #include "hw/rtc/mc146818rtc.h" 38 #include "hw/intc/i8259.h" 39 #include "hw/timer/i8254.h" 40 #include "hw/input/i8042.h" 41 #include "hw/audio/pcspk.h" 42 #include "sysemu/sysemu.h" 43 #include "sysemu/xen.h" 44 #include "sysemu/reset.h" 45 #include "kvm/kvm_i386.h" 46 #include "hw/xen/xen.h" 47 #include "qapi/qmp/qlist.h" 48 #include "qemu/error-report.h" 49 #include "hw/acpi/cpu_hotplug.h" 50 #include "acpi-build.h" 51 #include "hw/mem/nvdimm.h" 52 #include "hw/cxl/cxl_host.h" 53 #include "hw/usb.h" 54 #include "hw/i386/intel_iommu.h" 55 #include "hw/net/ne2000-isa.h" 56 #include "hw/virtio/virtio-iommu.h" 57 #include "hw/virtio/virtio-md-pci.h" 58 #include "hw/i386/kvm/xen_overlay.h" 59 #include "hw/i386/kvm/xen_evtchn.h" 60 #include "hw/i386/kvm/xen_gnttab.h" 61 #include "hw/i386/kvm/xen_xenstore.h" 62 #include "hw/mem/memory-device.h" 63 #include "e820_memory_layout.h" 64 #include "trace.h" 65 #include "sev.h" 66 #include CONFIG_DEVICES 67 68 #ifdef CONFIG_XEN_EMU 69 #include "hw/xen/xen-legacy-backend.h" 70 #include "hw/xen/xen-bus.h" 71 #endif 72 73 /* 74 * Helper for setting model-id for CPU models that changed model-id 75 * depending on QEMU versions up to QEMU 2.4. 76 */ 77 #define PC_CPU_MODEL_IDS(v) \ 78 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 79 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 80 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 81 82 GlobalProperty pc_compat_9_1[] = {}; 83 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 84 85 GlobalProperty pc_compat_9_0[] = { 86 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 87 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 88 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 89 { "sev-guest", "legacy-vm-type", "on" }, 90 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 91 }; 92 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 93 94 GlobalProperty pc_compat_8_2[] = {}; 95 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 96 97 GlobalProperty pc_compat_8_1[] = {}; 98 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 99 100 GlobalProperty pc_compat_8_0[] = { 101 { "virtio-mem", "unplugged-inaccessible", "auto" }, 102 }; 103 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 104 105 GlobalProperty pc_compat_7_2[] = { 106 { "ICH9-LPC", "noreboot", "true" }, 107 }; 108 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 109 110 GlobalProperty pc_compat_7_1[] = {}; 111 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 112 113 GlobalProperty pc_compat_7_0[] = {}; 114 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 115 116 GlobalProperty pc_compat_6_2[] = { 117 { "virtio-mem", "unplugged-inaccessible", "off" }, 118 }; 119 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 120 121 GlobalProperty pc_compat_6_1[] = { 122 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 123 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 124 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 125 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 126 }; 127 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 128 129 GlobalProperty pc_compat_6_0[] = { 130 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 131 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 132 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 133 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 134 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 135 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 136 }; 137 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 138 139 GlobalProperty pc_compat_5_2[] = { 140 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 141 }; 142 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 143 144 GlobalProperty pc_compat_5_1[] = { 145 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 146 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 147 }; 148 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 149 150 GlobalProperty pc_compat_5_0[] = { 151 }; 152 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 153 154 GlobalProperty pc_compat_4_2[] = { 155 { "mch", "smbase-smram", "off" }, 156 }; 157 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 158 159 GlobalProperty pc_compat_4_1[] = {}; 160 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 161 162 GlobalProperty pc_compat_4_0[] = {}; 163 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 164 165 GlobalProperty pc_compat_3_1[] = { 166 { "intel-iommu", "dma-drain", "off" }, 167 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 168 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 169 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 170 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 171 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 172 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 173 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 174 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 175 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 176 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 177 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 178 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 179 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 180 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 181 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 182 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 183 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 184 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 185 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 186 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 187 }; 188 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 189 190 GlobalProperty pc_compat_3_0[] = { 191 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 192 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 193 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 194 }; 195 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 196 197 GlobalProperty pc_compat_2_12[] = { 198 { TYPE_X86_CPU, "legacy-cache", "on" }, 199 { TYPE_X86_CPU, "topoext", "off" }, 200 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 201 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 202 }; 203 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 204 205 GlobalProperty pc_compat_2_11[] = { 206 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 207 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 208 }; 209 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 210 211 GlobalProperty pc_compat_2_10[] = { 212 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 213 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 214 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 215 }; 216 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 217 218 GlobalProperty pc_compat_2_9[] = { 219 { "mch", "extended-tseg-mbytes", "0" }, 220 }; 221 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 222 223 GlobalProperty pc_compat_2_8[] = { 224 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 225 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 226 { "ICH9-LPC", "x-smi-broadcast", "off" }, 227 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 228 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 229 }; 230 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 231 232 GlobalProperty pc_compat_2_7[] = { 233 { TYPE_X86_CPU, "l3-cache", "off" }, 234 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 235 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 236 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 237 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 238 { "isa-pcspk", "migrate", "off" }, 239 }; 240 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 241 242 GlobalProperty pc_compat_2_6[] = { 243 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 244 { "vmxnet3", "romfile", "" }, 245 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 246 { "apic-common", "legacy-instance-id", "on", } 247 }; 248 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 249 250 GlobalProperty pc_compat_2_5[] = {}; 251 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 252 253 GlobalProperty pc_compat_2_4[] = { 254 PC_CPU_MODEL_IDS("2.4.0") 255 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 256 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 257 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 258 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 259 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 260 { TYPE_X86_CPU, "check", "off" }, 261 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 262 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 263 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 264 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 265 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 266 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 267 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 268 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 269 }; 270 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 271 272 /* 273 * @PC_FW_DATA: 274 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 275 * and other BIOS datastructures. 276 * 277 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 278 * reported to be used at the moment, 32K should be enough for a while. 279 */ 280 #define PC_FW_DATA (0x20000 + 0x8000) 281 282 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 283 { 284 GSIState *s; 285 286 s = g_new0(GSIState, 1); 287 if (kvm_ioapic_in_kernel()) { 288 kvm_pc_setup_irq_routing(pci_enabled); 289 } 290 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 291 292 return s; 293 } 294 295 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 296 unsigned size) 297 { 298 } 299 300 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 301 { 302 return 0xffffffffffffffffULL; 303 } 304 305 /* MS-DOS compatibility mode FPU exception support */ 306 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 307 unsigned size) 308 { 309 if (tcg_enabled()) { 310 cpu_set_ignne(); 311 } 312 } 313 314 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 315 { 316 return 0xffffffffffffffffULL; 317 } 318 319 /* PC cmos mappings */ 320 321 #define REG_EQUIPMENT_BYTE 0x14 322 323 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 324 int16_t cylinders, int8_t heads, int8_t sectors) 325 { 326 mc146818rtc_set_cmos_data(s, type_ofs, 47); 327 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 328 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 329 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 330 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 331 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 332 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 333 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 334 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 335 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 336 } 337 338 /* convert boot_device letter to something recognizable by the bios */ 339 static int boot_device2nibble(char boot_device) 340 { 341 switch(boot_device) { 342 case 'a': 343 case 'b': 344 return 0x01; /* floppy boot */ 345 case 'c': 346 return 0x02; /* hard drive boot */ 347 case 'd': 348 return 0x03; /* CD-ROM boot */ 349 case 'n': 350 return 0x04; /* Network boot */ 351 } 352 return 0; 353 } 354 355 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 356 const char *boot_device, Error **errp) 357 { 358 #define PC_MAX_BOOT_DEVICES 3 359 int nbds, bds[3] = { 0, }; 360 int i; 361 362 nbds = strlen(boot_device); 363 if (nbds > PC_MAX_BOOT_DEVICES) { 364 error_setg(errp, "Too many boot devices for PC"); 365 return; 366 } 367 for (i = 0; i < nbds; i++) { 368 bds[i] = boot_device2nibble(boot_device[i]); 369 if (bds[i] == 0) { 370 error_setg(errp, "Invalid boot device for PC: '%c'", 371 boot_device[i]); 372 return; 373 } 374 } 375 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 376 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 377 } 378 379 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 380 { 381 PCMachineState *pcms = opaque; 382 X86MachineState *x86ms = X86_MACHINE(pcms); 383 384 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 385 } 386 387 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 388 { 389 int val, nb; 390 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 391 FLOPPY_DRIVE_TYPE_NONE }; 392 393 #ifdef CONFIG_FDC_ISA 394 /* floppy type */ 395 if (floppy) { 396 for (int i = 0; i < 2; i++) { 397 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 398 } 399 } 400 #endif 401 402 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 403 cmos_get_fd_drive_type(fd_type[1]); 404 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 405 406 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 407 nb = 0; 408 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 409 nb++; 410 } 411 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 412 nb++; 413 } 414 switch (nb) { 415 case 0: 416 break; 417 case 1: 418 val |= 0x01; /* 1 drive, ready for boot */ 419 break; 420 case 2: 421 val |= 0x41; /* 2 drives, ready for boot */ 422 break; 423 } 424 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 425 } 426 427 typedef struct check_fdc_state { 428 ISADevice *floppy; 429 bool multiple; 430 } CheckFdcState; 431 432 static int check_fdc(Object *obj, void *opaque) 433 { 434 CheckFdcState *state = opaque; 435 Object *fdc; 436 uint32_t iobase; 437 Error *local_err = NULL; 438 439 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 440 if (!fdc) { 441 return 0; 442 } 443 444 iobase = object_property_get_uint(obj, "iobase", &local_err); 445 if (local_err || iobase != 0x3f0) { 446 error_free(local_err); 447 return 0; 448 } 449 450 if (state->floppy) { 451 state->multiple = true; 452 } else { 453 state->floppy = ISA_DEVICE(obj); 454 } 455 return 0; 456 } 457 458 static const char * const fdc_container_path[] = { 459 "/unattached", "/peripheral", "/peripheral-anon" 460 }; 461 462 /* 463 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 464 * and ACPI objects. 465 */ 466 static ISADevice *pc_find_fdc0(void) 467 { 468 int i; 469 Object *container; 470 CheckFdcState state = { 0 }; 471 472 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 473 container = container_get(qdev_get_machine(), fdc_container_path[i]); 474 object_child_foreach(container, check_fdc, &state); 475 } 476 477 if (state.multiple) { 478 warn_report("multiple floppy disk controllers with " 479 "iobase=0x3f0 have been found"); 480 error_printf("the one being picked for CMOS setup might not reflect " 481 "your intent"); 482 } 483 484 return state.floppy; 485 } 486 487 static void pc_cmos_init_late(PCMachineState *pcms) 488 { 489 X86MachineState *x86ms = X86_MACHINE(pcms); 490 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 491 int16_t cylinders; 492 int8_t heads, sectors; 493 int val; 494 int i, trans; 495 496 val = 0; 497 if (pcms->idebus[0] && 498 ide_get_geometry(pcms->idebus[0], 0, 499 &cylinders, &heads, §ors) >= 0) { 500 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 501 val |= 0xf0; 502 } 503 if (pcms->idebus[0] && 504 ide_get_geometry(pcms->idebus[0], 1, 505 &cylinders, &heads, §ors) >= 0) { 506 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 507 val |= 0x0f; 508 } 509 mc146818rtc_set_cmos_data(s, 0x12, val); 510 511 val = 0; 512 for (i = 0; i < 4; i++) { 513 /* NOTE: ide_get_geometry() returns the physical 514 geometry. It is always such that: 1 <= sects <= 63, 1 515 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 516 geometry can be different if a translation is done. */ 517 BusState *idebus = pcms->idebus[i / 2]; 518 if (idebus && 519 ide_get_geometry(idebus, i % 2, 520 &cylinders, &heads, §ors) >= 0) { 521 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 522 assert((trans & ~3) == 0); 523 val |= trans << (i * 2); 524 } 525 } 526 mc146818rtc_set_cmos_data(s, 0x39, val); 527 528 pc_cmos_init_floppy(s, pc_find_fdc0()); 529 530 /* various important CMOS locations needed by PC/Bochs bios */ 531 532 /* memory size */ 533 /* base memory (first MiB) */ 534 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 535 mc146818rtc_set_cmos_data(s, 0x15, val); 536 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 537 /* extended memory (next 64MiB) */ 538 if (x86ms->below_4g_mem_size > 1 * MiB) { 539 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 540 } else { 541 val = 0; 542 } 543 if (val > 65535) 544 val = 65535; 545 mc146818rtc_set_cmos_data(s, 0x17, val); 546 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 547 mc146818rtc_set_cmos_data(s, 0x30, val); 548 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 549 /* memory between 16MiB and 4GiB */ 550 if (x86ms->below_4g_mem_size > 16 * MiB) { 551 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 552 } else { 553 val = 0; 554 } 555 if (val > 65535) 556 val = 65535; 557 mc146818rtc_set_cmos_data(s, 0x34, val); 558 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 559 /* memory above 4GiB */ 560 val = x86ms->above_4g_mem_size / 65536; 561 mc146818rtc_set_cmos_data(s, 0x5b, val); 562 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 563 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 564 565 val = 0; 566 val |= 0x02; /* FPU is there */ 567 val |= 0x04; /* PS/2 mouse installed */ 568 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 569 } 570 571 static void handle_a20_line_change(void *opaque, int irq, int level) 572 { 573 X86CPU *cpu = opaque; 574 575 /* XXX: send to all CPUs ? */ 576 /* XXX: add logic to handle multiple A20 line sources */ 577 x86_cpu_set_a20(cpu, level); 578 } 579 580 #define NE2000_NB_MAX 6 581 582 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 583 0x280, 0x380 }; 584 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 585 586 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 587 { 588 static int nb_ne2k = 0; 589 590 if (nb_ne2k == NE2000_NB_MAX) { 591 error_setg(errp, 592 "maximum number of ISA NE2000 devices exceeded"); 593 return false; 594 } 595 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 596 ne2000_irq[nb_ne2k], nd); 597 nb_ne2k++; 598 return true; 599 } 600 601 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 602 { 603 X86CPU *cpu = opaque; 604 605 if (level) { 606 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 607 } 608 } 609 610 static 611 void pc_machine_done(Notifier *notifier, void *data) 612 { 613 PCMachineState *pcms = container_of(notifier, 614 PCMachineState, machine_done); 615 X86MachineState *x86ms = X86_MACHINE(pcms); 616 617 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 618 &error_fatal); 619 620 if (pcms->cxl_devices_state.is_enabled) { 621 cxl_fmws_link_targets(&pcms->cxl_devices_state, &error_fatal); 622 } 623 624 /* set the number of CPUs */ 625 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 626 627 fw_cfg_add_extra_pci_roots(pcms->pcibus, x86ms->fw_cfg); 628 629 acpi_setup(); 630 if (x86ms->fw_cfg) { 631 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 632 fw_cfg_add_e820(x86ms->fw_cfg); 633 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 634 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 635 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 636 } 637 638 pc_cmos_init_late(pcms); 639 } 640 641 /* setup pci memory address space mapping into system address space */ 642 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 643 MemoryRegion *pci_address_space) 644 { 645 /* Set to lower priority than RAM */ 646 memory_region_add_subregion_overlap(system_memory, 0x0, 647 pci_address_space, -1); 648 } 649 650 void xen_load_linux(PCMachineState *pcms) 651 { 652 int i; 653 FWCfgState *fw_cfg; 654 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 655 X86MachineState *x86ms = X86_MACHINE(pcms); 656 657 assert(MACHINE(pcms)->kernel_filename != NULL); 658 659 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 660 &address_space_memory); 661 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 662 rom_set_fw(fw_cfg); 663 664 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 665 for (i = 0; i < nb_option_roms; i++) { 666 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 667 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 668 !strcmp(option_rom[i].name, "pvh.bin") || 669 !strcmp(option_rom[i].name, "multiboot.bin") || 670 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 671 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 672 } 673 x86ms->fw_cfg = fw_cfg; 674 } 675 676 #define PC_ROM_MIN_VGA 0xc0000 677 #define PC_ROM_MIN_OPTION 0xc8000 678 #define PC_ROM_MAX 0xe0000 679 #define PC_ROM_ALIGN 0x800 680 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 681 682 static hwaddr pc_above_4g_end(PCMachineState *pcms) 683 { 684 X86MachineState *x86ms = X86_MACHINE(pcms); 685 686 if (pcms->sgx_epc.size != 0) { 687 return sgx_epc_above_4g_end(&pcms->sgx_epc); 688 } 689 690 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 691 } 692 693 static void pc_get_device_memory_range(PCMachineState *pcms, 694 hwaddr *base, 695 ram_addr_t *device_mem_size) 696 { 697 MachineState *machine = MACHINE(pcms); 698 ram_addr_t size; 699 hwaddr addr; 700 701 size = machine->maxram_size - machine->ram_size; 702 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 703 704 /* size device region assuming 1G page max alignment per slot */ 705 size += (1 * GiB) * machine->ram_slots; 706 707 *base = addr; 708 *device_mem_size = size; 709 } 710 711 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 712 { 713 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 714 MachineState *ms = MACHINE(pcms); 715 hwaddr cxl_base; 716 ram_addr_t size; 717 718 if (pcmc->has_reserved_memory && 719 (ms->ram_size < ms->maxram_size)) { 720 pc_get_device_memory_range(pcms, &cxl_base, &size); 721 cxl_base += size; 722 } else { 723 cxl_base = pc_above_4g_end(pcms); 724 } 725 726 return cxl_base; 727 } 728 729 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 730 { 731 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 732 733 if (pcms->cxl_devices_state.fixed_windows) { 734 GList *it; 735 736 start = ROUND_UP(start, 256 * MiB); 737 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 738 CXLFixedWindow *fw = it->data; 739 start += fw->size; 740 } 741 } 742 743 return start; 744 } 745 746 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 747 { 748 X86CPU *cpu = X86_CPU(first_cpu); 749 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 750 MachineState *ms = MACHINE(pcms); 751 752 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 753 /* 64-bit systems */ 754 return pc_pci_hole64_start() + pci_hole64_size - 1; 755 } 756 757 /* 32-bit systems */ 758 if (pcmc->broken_32bit_mem_addr_check) { 759 /* old value for compatibility reasons */ 760 return ((hwaddr)1 << cpu->phys_bits) - 1; 761 } 762 763 /* 764 * 32-bit systems don't have hole64 but they might have a region for 765 * memory devices. Even if additional hotplugged memory devices might 766 * not be usable by most guest OSes, we need to still consider them for 767 * calculating the highest possible GPA so that we can properly report 768 * if someone configures them on a CPU that cannot possibly address them. 769 */ 770 if (pcmc->has_reserved_memory && 771 (ms->ram_size < ms->maxram_size)) { 772 hwaddr devmem_start; 773 ram_addr_t devmem_size; 774 775 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 776 devmem_start += devmem_size; 777 return devmem_start - 1; 778 } 779 780 /* configuration without any memory hotplug */ 781 return pc_above_4g_end(pcms) - 1; 782 } 783 784 /* 785 * AMD systems with an IOMMU have an additional hole close to the 786 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 787 * on kernel version, VFIO may or may not let you DMA map those ranges. 788 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 789 * with certain memory sizes. It's also wrong to use those IOVA ranges 790 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 791 * The ranges reserved for Hyper-Transport are: 792 * 793 * FD_0000_0000h - FF_FFFF_FFFFh 794 * 795 * The ranges represent the following: 796 * 797 * Base Address Top Address Use 798 * 799 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 800 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 801 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 802 * FD_F910_0000h FD_F91F_FFFFh System Management 803 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 804 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 805 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 806 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 807 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 808 * FE_2000_0000h FF_FFFF_FFFFh Reserved 809 * 810 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 811 * Table 3: Special Address Controls (GPA) for more information. 812 */ 813 #define AMD_HT_START 0xfd00000000UL 814 #define AMD_HT_END 0xffffffffffUL 815 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 816 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 817 818 void pc_memory_init(PCMachineState *pcms, 819 MemoryRegion *system_memory, 820 MemoryRegion *rom_memory, 821 uint64_t pci_hole64_size) 822 { 823 int linux_boot, i; 824 MemoryRegion *option_rom_mr; 825 MemoryRegion *ram_below_4g, *ram_above_4g; 826 FWCfgState *fw_cfg; 827 MachineState *machine = MACHINE(pcms); 828 MachineClass *mc = MACHINE_GET_CLASS(machine); 829 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 830 X86MachineState *x86ms = X86_MACHINE(pcms); 831 hwaddr maxphysaddr, maxusedaddr; 832 hwaddr cxl_base, cxl_resv_end = 0; 833 X86CPU *cpu = X86_CPU(first_cpu); 834 835 assert(machine->ram_size == x86ms->below_4g_mem_size + 836 x86ms->above_4g_mem_size); 837 838 linux_boot = (machine->kernel_filename != NULL); 839 840 /* 841 * The HyperTransport range close to the 1T boundary is unique to AMD 842 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 843 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 844 * older machine types (<= 7.0) for compatibility purposes. 845 */ 846 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 847 /* Bail out if max possible address does not cross HT range */ 848 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 849 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 850 } 851 852 /* 853 * Advertise the HT region if address space covers the reserved 854 * region or if we relocate. 855 */ 856 if (cpu->phys_bits >= 40) { 857 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 858 } 859 } 860 861 /* 862 * phys-bits is required to be appropriately configured 863 * to make sure max used GPA is reachable. 864 */ 865 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 866 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 867 if (maxphysaddr < maxusedaddr) { 868 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 869 " phys-bits too low (%u)", 870 maxphysaddr, maxusedaddr, cpu->phys_bits); 871 exit(EXIT_FAILURE); 872 } 873 874 /* 875 * Split single memory region and use aliases to address portions of it, 876 * done for backwards compatibility with older qemus. 877 */ 878 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 879 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 880 0, x86ms->below_4g_mem_size); 881 memory_region_add_subregion(system_memory, 0, ram_below_4g); 882 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 883 if (x86ms->above_4g_mem_size > 0) { 884 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 885 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 886 machine->ram, 887 x86ms->below_4g_mem_size, 888 x86ms->above_4g_mem_size); 889 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 890 ram_above_4g); 891 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 892 E820_RAM); 893 } 894 895 if (pcms->sgx_epc.size != 0) { 896 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 897 } 898 899 if (!pcmc->has_reserved_memory && 900 (machine->ram_slots || 901 (machine->maxram_size > machine->ram_size))) { 902 903 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 904 mc->name); 905 exit(EXIT_FAILURE); 906 } 907 908 /* initialize device memory address space */ 909 if (pcmc->has_reserved_memory && 910 (machine->ram_size < machine->maxram_size)) { 911 ram_addr_t device_mem_size; 912 hwaddr device_mem_base; 913 914 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 915 error_report("unsupported amount of memory slots: %"PRIu64, 916 machine->ram_slots); 917 exit(EXIT_FAILURE); 918 } 919 920 if (QEMU_ALIGN_UP(machine->maxram_size, 921 TARGET_PAGE_SIZE) != machine->maxram_size) { 922 error_report("maximum memory size must by aligned to multiple of " 923 "%d bytes", TARGET_PAGE_SIZE); 924 exit(EXIT_FAILURE); 925 } 926 927 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 928 929 if (device_mem_base + device_mem_size < device_mem_size) { 930 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 931 machine->maxram_size); 932 exit(EXIT_FAILURE); 933 } 934 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 935 } 936 937 if (pcms->cxl_devices_state.is_enabled) { 938 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 939 hwaddr cxl_size = MiB; 940 941 cxl_base = pc_get_cxl_range_start(pcms); 942 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 943 memory_region_add_subregion(system_memory, cxl_base, mr); 944 cxl_resv_end = cxl_base + cxl_size; 945 if (pcms->cxl_devices_state.fixed_windows) { 946 hwaddr cxl_fmw_base; 947 GList *it; 948 949 cxl_fmw_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 950 for (it = pcms->cxl_devices_state.fixed_windows; it; it = it->next) { 951 CXLFixedWindow *fw = it->data; 952 953 fw->base = cxl_fmw_base; 954 memory_region_init_io(&fw->mr, OBJECT(machine), &cfmws_ops, fw, 955 "cxl-fixed-memory-region", fw->size); 956 memory_region_add_subregion(system_memory, fw->base, &fw->mr); 957 cxl_fmw_base += fw->size; 958 cxl_resv_end = cxl_fmw_base; 959 } 960 } 961 } 962 963 /* Initialize PC system firmware */ 964 pc_system_firmware_init(pcms, rom_memory); 965 966 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 967 if (machine_require_guest_memfd(machine)) { 968 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 969 PC_ROM_SIZE, &error_fatal); 970 } else { 971 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 972 &error_fatal); 973 if (pcmc->pci_enabled) { 974 memory_region_set_readonly(option_rom_mr, true); 975 } 976 } 977 memory_region_add_subregion_overlap(rom_memory, 978 PC_ROM_MIN_VGA, 979 option_rom_mr, 980 1); 981 982 fw_cfg = fw_cfg_arch_create(machine, 983 x86ms->boot_cpus, x86ms->apic_id_limit); 984 985 rom_set_fw(fw_cfg); 986 987 if (machine->device_memory) { 988 uint64_t *val = g_malloc(sizeof(*val)); 989 uint64_t res_mem_end = machine->device_memory->base; 990 991 if (!pcmc->broken_reserved_end) { 992 res_mem_end += memory_region_size(&machine->device_memory->mr); 993 } 994 995 if (pcms->cxl_devices_state.is_enabled) { 996 res_mem_end = cxl_resv_end; 997 } 998 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 999 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1000 } 1001 1002 if (linux_boot) { 1003 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 1004 } 1005 1006 for (i = 0; i < nb_option_roms; i++) { 1007 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1008 } 1009 x86ms->fw_cfg = fw_cfg; 1010 1011 /* Init default IOAPIC address space */ 1012 x86ms->ioapic_as = &address_space_memory; 1013 1014 /* Init ACPI memory hotplug IO base address */ 1015 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1016 } 1017 1018 /* 1019 * The 64bit pci hole starts after "above 4G RAM" and 1020 * potentially the space reserved for memory hotplug. 1021 */ 1022 uint64_t pc_pci_hole64_start(void) 1023 { 1024 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1025 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1026 MachineState *ms = MACHINE(pcms); 1027 uint64_t hole64_start = 0; 1028 ram_addr_t size = 0; 1029 1030 if (pcms->cxl_devices_state.is_enabled) { 1031 hole64_start = pc_get_cxl_range_end(pcms); 1032 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1033 pc_get_device_memory_range(pcms, &hole64_start, &size); 1034 if (!pcmc->broken_reserved_end) { 1035 hole64_start += size; 1036 } 1037 } else { 1038 hole64_start = pc_above_4g_end(pcms); 1039 } 1040 1041 return ROUND_UP(hole64_start, 1 * GiB); 1042 } 1043 1044 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1045 { 1046 DeviceState *dev = NULL; 1047 1048 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1049 if (pci_bus) { 1050 PCIDevice *pcidev = pci_vga_init(pci_bus); 1051 dev = pcidev ? &pcidev->qdev : NULL; 1052 } else if (isa_bus) { 1053 ISADevice *isadev = isa_vga_init(isa_bus); 1054 dev = isadev ? DEVICE(isadev) : NULL; 1055 } 1056 rom_reset_order_override(); 1057 return dev; 1058 } 1059 1060 static const MemoryRegionOps ioport80_io_ops = { 1061 .write = ioport80_write, 1062 .read = ioport80_read, 1063 .endianness = DEVICE_NATIVE_ENDIAN, 1064 .impl = { 1065 .min_access_size = 1, 1066 .max_access_size = 1, 1067 }, 1068 }; 1069 1070 static const MemoryRegionOps ioportF0_io_ops = { 1071 .write = ioportF0_write, 1072 .read = ioportF0_read, 1073 .endianness = DEVICE_NATIVE_ENDIAN, 1074 .impl = { 1075 .min_access_size = 1, 1076 .max_access_size = 1, 1077 }, 1078 }; 1079 1080 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1081 bool create_i8042, bool no_vmport, Error **errp) 1082 { 1083 int i; 1084 DriveInfo *fd[MAX_FD]; 1085 qemu_irq *a20_line; 1086 ISADevice *i8042, *port92, *vmmouse; 1087 1088 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1089 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1090 1091 for (i = 0; i < MAX_FD; i++) { 1092 fd[i] = drive_get(IF_FLOPPY, 0, i); 1093 create_fdctrl |= !!fd[i]; 1094 } 1095 if (create_fdctrl) { 1096 #ifdef CONFIG_FDC_ISA 1097 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1098 if (fdc) { 1099 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1100 isa_fdc_init_drives(fdc, fd); 1101 } 1102 #endif 1103 } 1104 1105 if (!create_i8042) { 1106 if (!no_vmport) { 1107 error_setg(errp, 1108 "vmport requires the i8042 controller to be enabled"); 1109 } 1110 return; 1111 } 1112 1113 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1114 if (!no_vmport) { 1115 isa_create_simple(isa_bus, TYPE_VMPORT); 1116 vmmouse = isa_try_new("vmmouse"); 1117 } else { 1118 vmmouse = NULL; 1119 } 1120 if (vmmouse) { 1121 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1122 &error_abort); 1123 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1124 } 1125 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1126 1127 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1128 qdev_connect_gpio_out_named(DEVICE(i8042), 1129 I8042_A20_LINE, 0, a20_line[0]); 1130 qdev_connect_gpio_out_named(DEVICE(port92), 1131 PORT92_A20_LINE, 0, a20_line[1]); 1132 g_free(a20_line); 1133 } 1134 1135 void pc_basic_device_init(struct PCMachineState *pcms, 1136 ISABus *isa_bus, qemu_irq *gsi, 1137 ISADevice *rtc_state, 1138 bool create_fdctrl, 1139 uint32_t hpet_irqs) 1140 { 1141 int i; 1142 DeviceState *hpet = NULL; 1143 int pit_isa_irq = 0; 1144 qemu_irq pit_alt_irq = NULL; 1145 ISADevice *pit = NULL; 1146 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1147 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1148 X86MachineState *x86ms = X86_MACHINE(pcms); 1149 1150 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1151 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1152 1153 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1154 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1155 1156 /* 1157 * Check if an HPET shall be created. 1158 */ 1159 if (pcms->hpet_enabled) { 1160 qemu_irq rtc_irq; 1161 1162 hpet = qdev_try_new(TYPE_HPET); 1163 if (!hpet) { 1164 error_report("couldn't create HPET device"); 1165 exit(1); 1166 } 1167 /* 1168 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1169 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1170 * the property, use whatever mask they specified. 1171 */ 1172 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1173 HPET_INTCAP, NULL); 1174 if (!compat) { 1175 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1176 } 1177 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1178 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1179 1180 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1181 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1182 } 1183 pit_isa_irq = -1; 1184 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1185 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1186 1187 /* overwrite connection created by south bridge */ 1188 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1189 } 1190 1191 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1192 "date"); 1193 1194 #ifdef CONFIG_XEN_EMU 1195 if (xen_mode == XEN_EMULATE) { 1196 xen_overlay_create(); 1197 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1198 xen_gnttab_create(); 1199 xen_xenstore_create(); 1200 if (pcms->pcibus) { 1201 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1202 } 1203 xen_bus_init(); 1204 } 1205 #endif 1206 1207 qemu_register_boot_set(pc_boot_set, pcms); 1208 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1209 MACHINE(pcms)->boot_config.order, &error_fatal); 1210 1211 if (!xen_enabled() && 1212 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1213 if (kvm_pit_in_kernel()) { 1214 pit = kvm_pit_init(isa_bus, 0x40); 1215 } else { 1216 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1217 } 1218 if (hpet) { 1219 /* connect PIT to output control line of the HPET */ 1220 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1221 } 1222 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1223 OBJECT(pit), &error_fatal); 1224 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1225 } 1226 1227 assert(pcms->vmport >= 0 && pcms->vmport < ON_OFF_AUTO__MAX); 1228 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1229 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1230 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1231 } 1232 1233 /* Super I/O */ 1234 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1235 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1236 } 1237 1238 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1239 { 1240 MachineClass *mc = MACHINE_CLASS(pcmc); 1241 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1242 NICInfo *nd; 1243 1244 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1245 1246 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1247 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1248 } 1249 1250 /* Anything remaining should be a PCI NIC */ 1251 pci_init_nic_devices(pci_bus, mc->default_nic); 1252 1253 rom_reset_order_override(); 1254 } 1255 1256 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1257 { 1258 qemu_irq *i8259; 1259 1260 if (kvm_pic_in_kernel()) { 1261 i8259 = kvm_i8259_init(isa_bus); 1262 } else if (xen_enabled()) { 1263 i8259 = xen_interrupt_controller_init(); 1264 } else { 1265 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1266 } 1267 1268 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1269 i8259_irqs[i] = i8259[i]; 1270 } 1271 1272 g_free(i8259); 1273 } 1274 1275 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1276 Error **errp) 1277 { 1278 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1279 const MachineState *ms = MACHINE(hotplug_dev); 1280 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1281 Error *local_err = NULL; 1282 1283 /* 1284 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1285 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1286 * addition to cover this case. 1287 */ 1288 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1289 error_setg(errp, 1290 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1291 return; 1292 } 1293 1294 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1295 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1296 return; 1297 } 1298 1299 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1300 if (local_err) { 1301 error_propagate(errp, local_err); 1302 return; 1303 } 1304 1305 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1306 } 1307 1308 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1309 DeviceState *dev, Error **errp) 1310 { 1311 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1312 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1313 MachineState *ms = MACHINE(hotplug_dev); 1314 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1315 1316 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1317 1318 if (is_nvdimm) { 1319 nvdimm_plug(ms->nvdimms_state); 1320 } 1321 1322 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1323 } 1324 1325 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1326 DeviceState *dev, Error **errp) 1327 { 1328 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1329 1330 /* 1331 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1332 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1333 * addition to cover this case. 1334 */ 1335 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1336 error_setg(errp, 1337 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1338 return; 1339 } 1340 1341 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1342 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1343 return; 1344 } 1345 1346 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1347 errp); 1348 } 1349 1350 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1351 DeviceState *dev, Error **errp) 1352 { 1353 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1354 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1355 Error *local_err = NULL; 1356 1357 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1358 if (local_err) { 1359 goto out; 1360 } 1361 1362 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1363 qdev_unrealize(dev); 1364 out: 1365 error_propagate(errp, local_err); 1366 } 1367 1368 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1369 DeviceState *dev, Error **errp) 1370 { 1371 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1372 g_assert(!dev->hotplugged); 1373 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1374 } 1375 1376 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1377 DeviceState *dev, Error **errp) 1378 { 1379 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1380 } 1381 1382 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1383 DeviceState *dev, Error **errp) 1384 { 1385 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1386 pc_memory_pre_plug(hotplug_dev, dev, errp); 1387 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1388 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1389 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1390 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1391 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1392 /* Declare the APIC range as the reserved MSI region */ 1393 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1394 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1395 QList *reserved_regions = qlist_new(); 1396 1397 qlist_append_str(reserved_regions, resv_prop_str); 1398 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1399 1400 g_free(resv_prop_str); 1401 } 1402 1403 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1404 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1405 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1406 1407 if (pcms->iommu) { 1408 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1409 "for x86 yet."); 1410 return; 1411 } 1412 pcms->iommu = dev; 1413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1414 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1415 } 1416 } 1417 1418 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1419 DeviceState *dev, Error **errp) 1420 { 1421 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1422 pc_memory_plug(hotplug_dev, dev, errp); 1423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1424 x86_cpu_plug(hotplug_dev, dev, errp); 1425 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1426 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1427 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1428 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1429 } 1430 } 1431 1432 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1433 DeviceState *dev, Error **errp) 1434 { 1435 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1436 pc_memory_unplug_request(hotplug_dev, dev, errp); 1437 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1438 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1439 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1440 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1441 errp); 1442 } else { 1443 error_setg(errp, "acpi: device unplug request for not supported device" 1444 " type: %s", object_get_typename(OBJECT(dev))); 1445 } 1446 } 1447 1448 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1449 DeviceState *dev, Error **errp) 1450 { 1451 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1452 pc_memory_unplug(hotplug_dev, dev, errp); 1453 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1454 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1455 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1456 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1457 } else { 1458 error_setg(errp, "acpi: device unplug for not supported device" 1459 " type: %s", object_get_typename(OBJECT(dev))); 1460 } 1461 } 1462 1463 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1464 DeviceState *dev) 1465 { 1466 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1467 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1468 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1469 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1470 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1471 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1472 return HOTPLUG_HANDLER(machine); 1473 } 1474 1475 return NULL; 1476 } 1477 1478 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1479 void *opaque, Error **errp) 1480 { 1481 PCMachineState *pcms = PC_MACHINE(obj); 1482 OnOffAuto vmport = pcms->vmport; 1483 1484 visit_type_OnOffAuto(v, name, &vmport, errp); 1485 } 1486 1487 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1488 void *opaque, Error **errp) 1489 { 1490 PCMachineState *pcms = PC_MACHINE(obj); 1491 1492 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1493 } 1494 1495 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1496 { 1497 PCMachineState *pcms = PC_MACHINE(obj); 1498 1499 return pcms->fd_bootchk; 1500 } 1501 1502 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1503 { 1504 PCMachineState *pcms = PC_MACHINE(obj); 1505 1506 pcms->fd_bootchk = value; 1507 } 1508 1509 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1510 { 1511 PCMachineState *pcms = PC_MACHINE(obj); 1512 1513 return pcms->smbus_enabled; 1514 } 1515 1516 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1517 { 1518 PCMachineState *pcms = PC_MACHINE(obj); 1519 1520 pcms->smbus_enabled = value; 1521 } 1522 1523 static bool pc_machine_get_sata(Object *obj, Error **errp) 1524 { 1525 PCMachineState *pcms = PC_MACHINE(obj); 1526 1527 return pcms->sata_enabled; 1528 } 1529 1530 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1531 { 1532 PCMachineState *pcms = PC_MACHINE(obj); 1533 1534 pcms->sata_enabled = value; 1535 } 1536 1537 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1538 { 1539 PCMachineState *pcms = PC_MACHINE(obj); 1540 1541 return pcms->hpet_enabled; 1542 } 1543 1544 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 1548 pcms->hpet_enabled = value; 1549 } 1550 1551 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1552 { 1553 PCMachineState *pcms = PC_MACHINE(obj); 1554 1555 return pcms->i8042_enabled; 1556 } 1557 1558 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1559 { 1560 PCMachineState *pcms = PC_MACHINE(obj); 1561 1562 pcms->i8042_enabled = value; 1563 } 1564 1565 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1566 { 1567 PCMachineState *pcms = PC_MACHINE(obj); 1568 1569 return pcms->default_bus_bypass_iommu; 1570 } 1571 1572 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1573 Error **errp) 1574 { 1575 PCMachineState *pcms = PC_MACHINE(obj); 1576 1577 pcms->default_bus_bypass_iommu = value; 1578 } 1579 1580 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1581 void *opaque, Error **errp) 1582 { 1583 PCMachineState *pcms = PC_MACHINE(obj); 1584 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1585 1586 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1587 } 1588 1589 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1590 void *opaque, Error **errp) 1591 { 1592 PCMachineState *pcms = PC_MACHINE(obj); 1593 1594 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1595 } 1596 1597 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1598 const char *name, void *opaque, 1599 Error **errp) 1600 { 1601 PCMachineState *pcms = PC_MACHINE(obj); 1602 uint64_t value = pcms->max_ram_below_4g; 1603 1604 visit_type_size(v, name, &value, errp); 1605 } 1606 1607 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1608 const char *name, void *opaque, 1609 Error **errp) 1610 { 1611 PCMachineState *pcms = PC_MACHINE(obj); 1612 uint64_t value; 1613 1614 if (!visit_type_size(v, name, &value, errp)) { 1615 return; 1616 } 1617 if (value > 4 * GiB) { 1618 error_setg(errp, 1619 "Machine option 'max-ram-below-4g=%"PRIu64 1620 "' expects size less than or equal to 4G", value); 1621 return; 1622 } 1623 1624 if (value < 1 * MiB) { 1625 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1626 "BIOS may not work with less than 1MiB", value); 1627 } 1628 1629 pcms->max_ram_below_4g = value; 1630 } 1631 1632 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1633 const char *name, void *opaque, 1634 Error **errp) 1635 { 1636 PCMachineState *pcms = PC_MACHINE(obj); 1637 uint64_t value = pcms->max_fw_size; 1638 1639 visit_type_size(v, name, &value, errp); 1640 } 1641 1642 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1643 const char *name, void *opaque, 1644 Error **errp) 1645 { 1646 PCMachineState *pcms = PC_MACHINE(obj); 1647 uint64_t value; 1648 1649 if (!visit_type_size(v, name, &value, errp)) { 1650 return; 1651 } 1652 1653 /* 1654 * We don't have a theoretically justifiable exact lower bound on the base 1655 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1656 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1657 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1658 * 16MiB in size. 1659 */ 1660 if (value > 16 * MiB) { 1661 error_setg(errp, 1662 "User specified max allowed firmware size %" PRIu64 " is " 1663 "greater than 16MiB. If combined firmware size exceeds " 1664 "16MiB the system may not boot, or experience intermittent" 1665 "stability issues.", 1666 value); 1667 return; 1668 } 1669 1670 pcms->max_fw_size = value; 1671 } 1672 1673 1674 static void pc_machine_initfn(Object *obj) 1675 { 1676 PCMachineState *pcms = PC_MACHINE(obj); 1677 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1678 1679 #ifdef CONFIG_VMPORT 1680 pcms->vmport = ON_OFF_AUTO_AUTO; 1681 #else 1682 pcms->vmport = ON_OFF_AUTO_OFF; 1683 #endif /* CONFIG_VMPORT */ 1684 pcms->max_ram_below_4g = 0; /* use default */ 1685 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1686 pcms->south_bridge = pcmc->default_south_bridge; 1687 1688 /* acpi build is enabled by default if machine supports it */ 1689 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1690 pcms->smbus_enabled = true; 1691 pcms->sata_enabled = true; 1692 pcms->i8042_enabled = true; 1693 pcms->max_fw_size = 8 * MiB; 1694 #ifdef CONFIG_HPET 1695 pcms->hpet_enabled = true; 1696 #endif 1697 pcms->fd_bootchk = true; 1698 pcms->default_bus_bypass_iommu = false; 1699 1700 pc_system_flash_create(pcms); 1701 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1702 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1703 OBJECT(pcms->pcspk), "audiodev"); 1704 if (pcmc->pci_enabled) { 1705 cxl_machine_init(obj, &pcms->cxl_devices_state); 1706 } 1707 1708 pcms->machine_done.notify = pc_machine_done; 1709 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1710 } 1711 1712 static void pc_machine_reset(MachineState *machine, ShutdownCause reason) 1713 { 1714 CPUState *cs; 1715 X86CPU *cpu; 1716 1717 qemu_devices_reset(reason); 1718 1719 /* Reset APIC after devices have been reset to cancel 1720 * any changes that qemu_devices_reset() might have done. 1721 */ 1722 CPU_FOREACH(cs) { 1723 cpu = X86_CPU(cs); 1724 1725 x86_cpu_after_reset(cpu); 1726 } 1727 } 1728 1729 static void pc_machine_wakeup(MachineState *machine) 1730 { 1731 cpu_synchronize_all_states(); 1732 pc_machine_reset(machine, SHUTDOWN_CAUSE_NONE); 1733 cpu_synchronize_all_post_reset(); 1734 } 1735 1736 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1737 { 1738 X86IOMMUState *iommu = x86_iommu_get_default(); 1739 IntelIOMMUState *intel_iommu; 1740 1741 if (iommu && 1742 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1743 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1744 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1745 if (!intel_iommu->caching_mode) { 1746 error_setg(errp, "Device assignment is not allowed without " 1747 "enabling caching-mode=on for Intel IOMMU."); 1748 return false; 1749 } 1750 } 1751 1752 return true; 1753 } 1754 1755 static void pc_machine_class_init(ObjectClass *oc, void *data) 1756 { 1757 MachineClass *mc = MACHINE_CLASS(oc); 1758 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1759 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1760 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1761 1762 pcmc->pci_enabled = true; 1763 pcmc->has_acpi_build = true; 1764 pcmc->smbios_defaults = true; 1765 pcmc->gigabyte_align = true; 1766 pcmc->has_reserved_memory = true; 1767 pcmc->enforce_amd_1tb_hole = true; 1768 pcmc->isa_bios_alias = true; 1769 pcmc->pvh_enabled = true; 1770 pcmc->kvmclock_create_always = true; 1771 x86mc->apic_xrupt_override = true; 1772 assert(!mc->get_hotplug_handler); 1773 mc->get_hotplug_handler = pc_get_hotplug_handler; 1774 mc->hotplug_allowed = pc_hotplug_allowed; 1775 mc->auto_enable_numa_with_memhp = true; 1776 mc->auto_enable_numa_with_memdev = true; 1777 mc->has_hotpluggable_cpus = true; 1778 mc->default_boot_order = "cad"; 1779 mc->block_default_type = IF_IDE; 1780 mc->max_cpus = 255; 1781 mc->reset = pc_machine_reset; 1782 mc->wakeup = pc_machine_wakeup; 1783 hc->pre_plug = pc_machine_device_pre_plug_cb; 1784 hc->plug = pc_machine_device_plug_cb; 1785 hc->unplug_request = pc_machine_device_unplug_request_cb; 1786 hc->unplug = pc_machine_device_unplug_cb; 1787 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1788 mc->nvdimm_supported = true; 1789 mc->smp_props.dies_supported = true; 1790 mc->smp_props.modules_supported = true; 1791 mc->default_ram_id = "pc.ram"; 1792 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1793 1794 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1795 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1796 NULL, NULL); 1797 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1798 "Maximum ram below the 4G boundary (32bit boundary)"); 1799 1800 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1801 pc_machine_get_vmport, pc_machine_set_vmport, 1802 NULL, NULL); 1803 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1804 "Enable vmport (pc & q35)"); 1805 1806 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1807 pc_machine_get_smbus, pc_machine_set_smbus); 1808 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1809 "Enable/disable system management bus"); 1810 1811 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1812 pc_machine_get_sata, pc_machine_set_sata); 1813 object_class_property_set_description(oc, PC_MACHINE_SATA, 1814 "Enable/disable Serial ATA bus"); 1815 1816 object_class_property_add_bool(oc, "hpet", 1817 pc_machine_get_hpet, pc_machine_set_hpet); 1818 object_class_property_set_description(oc, "hpet", 1819 "Enable/disable high precision event timer emulation"); 1820 1821 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1822 pc_machine_get_i8042, pc_machine_set_i8042); 1823 1824 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1825 pc_machine_get_default_bus_bypass_iommu, 1826 pc_machine_set_default_bus_bypass_iommu); 1827 1828 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1829 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1830 NULL, NULL); 1831 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1832 "Maximum combined firmware size"); 1833 1834 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1835 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1836 NULL, NULL); 1837 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1838 "SMBIOS Entry Point type [32, 64]"); 1839 1840 object_class_property_add_bool(oc, "fd-bootchk", 1841 pc_machine_get_fd_bootchk, 1842 pc_machine_set_fd_bootchk); 1843 } 1844 1845 static const TypeInfo pc_machine_info = { 1846 .name = TYPE_PC_MACHINE, 1847 .parent = TYPE_X86_MACHINE, 1848 .abstract = true, 1849 .instance_size = sizeof(PCMachineState), 1850 .instance_init = pc_machine_initfn, 1851 .class_size = sizeof(PCMachineClass), 1852 .class_init = pc_machine_class_init, 1853 .interfaces = (InterfaceInfo[]) { 1854 { TYPE_HOTPLUG_HANDLER }, 1855 { } 1856 }, 1857 }; 1858 1859 static void pc_machine_register_types(void) 1860 { 1861 type_register_static(&pc_machine_info); 1862 } 1863 1864 type_init(pc_machine_register_types) 1865