1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "sysemu/arch_init.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "qapi/error.h" 80 #include "qapi/qapi-visit-common.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/virtio/virtio-mem-pci.h" 89 #include "hw/mem/memory-device.h" 90 #include "sysemu/replay.h" 91 #include "qapi/qmp/qerror.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 #include CONFIG_DEVICES 96 97 GlobalProperty pc_compat_6_0[] = { 98 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 99 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 100 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 101 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 102 { "ICH9-LPC", "acpi-pci-hotplug-with-bridge-support", "off" }, 103 }; 104 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 105 106 GlobalProperty pc_compat_5_2[] = { 107 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 108 }; 109 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 110 111 GlobalProperty pc_compat_5_1[] = { 112 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 113 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 114 }; 115 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 116 117 GlobalProperty pc_compat_5_0[] = { 118 }; 119 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 120 121 GlobalProperty pc_compat_4_2[] = { 122 { "mch", "smbase-smram", "off" }, 123 }; 124 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 125 126 GlobalProperty pc_compat_4_1[] = {}; 127 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 128 129 GlobalProperty pc_compat_4_0[] = {}; 130 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 131 132 GlobalProperty pc_compat_3_1[] = { 133 { "intel-iommu", "dma-drain", "off" }, 134 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 135 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 136 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 137 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 138 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 139 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 140 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 141 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 142 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 143 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 144 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 145 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 146 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 147 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 148 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 149 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 150 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 151 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 152 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 153 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 154 }; 155 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 156 157 GlobalProperty pc_compat_3_0[] = { 158 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 159 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 160 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 161 }; 162 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 163 164 GlobalProperty pc_compat_2_12[] = { 165 { TYPE_X86_CPU, "legacy-cache", "on" }, 166 { TYPE_X86_CPU, "topoext", "off" }, 167 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 168 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 169 }; 170 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 171 172 GlobalProperty pc_compat_2_11[] = { 173 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 174 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 175 }; 176 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 177 178 GlobalProperty pc_compat_2_10[] = { 179 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 180 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 181 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 182 }; 183 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 184 185 GlobalProperty pc_compat_2_9[] = { 186 { "mch", "extended-tseg-mbytes", "0" }, 187 }; 188 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 189 190 GlobalProperty pc_compat_2_8[] = { 191 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 192 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 193 { "ICH9-LPC", "x-smi-broadcast", "off" }, 194 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 195 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 196 }; 197 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 198 199 GlobalProperty pc_compat_2_7[] = { 200 { TYPE_X86_CPU, "l3-cache", "off" }, 201 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 202 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 203 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 204 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 205 { "isa-pcspk", "migrate", "off" }, 206 }; 207 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 208 209 GlobalProperty pc_compat_2_6[] = { 210 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 211 { "vmxnet3", "romfile", "" }, 212 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 213 { "apic-common", "legacy-instance-id", "on", } 214 }; 215 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 216 217 GlobalProperty pc_compat_2_5[] = {}; 218 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 219 220 GlobalProperty pc_compat_2_4[] = { 221 PC_CPU_MODEL_IDS("2.4.0") 222 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 223 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 224 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 225 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 226 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 227 { TYPE_X86_CPU, "check", "off" }, 228 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 229 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 230 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 231 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 232 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 233 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 234 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 235 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 236 }; 237 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 238 239 GlobalProperty pc_compat_2_3[] = { 240 PC_CPU_MODEL_IDS("2.3.0") 241 { TYPE_X86_CPU, "arat", "off" }, 242 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 243 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 244 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 245 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 246 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 247 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 248 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 249 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 254 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 255 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 256 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 257 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 258 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 259 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 260 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 261 }; 262 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 263 264 GlobalProperty pc_compat_2_2[] = { 265 PC_CPU_MODEL_IDS("2.2.0") 266 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 275 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 276 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 277 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 278 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 279 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 280 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 281 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 282 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 283 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 284 }; 285 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 286 287 GlobalProperty pc_compat_2_1[] = { 288 PC_CPU_MODEL_IDS("2.1.0") 289 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 290 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 291 }; 292 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 293 294 GlobalProperty pc_compat_2_0[] = { 295 PC_CPU_MODEL_IDS("2.0.0") 296 { "virtio-scsi-pci", "any_layout", "off" }, 297 { "PIIX4_PM", "memory-hotplug-support", "off" }, 298 { "apic", "version", "0x11" }, 299 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 300 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 301 { "pci-serial", "prog_if", "0" }, 302 { "pci-serial-2x", "prog_if", "0" }, 303 { "pci-serial-4x", "prog_if", "0" }, 304 { "virtio-net-pci", "guest_announce", "off" }, 305 { "ICH9-LPC", "memory-hotplug-support", "off" }, 306 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 307 { "ioh3420", COMPAT_PROP_PCP, "off" }, 308 }; 309 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 310 311 GlobalProperty pc_compat_1_7[] = { 312 PC_CPU_MODEL_IDS("1.7.0") 313 { TYPE_USB_DEVICE, "msos-desc", "no" }, 314 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 315 { "hpet", HPET_INTCAP, "4" }, 316 }; 317 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 318 319 GlobalProperty pc_compat_1_6[] = { 320 PC_CPU_MODEL_IDS("1.6.0") 321 { "e1000", "mitigation", "off" }, 322 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 323 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 324 { "i440FX-pcihost", "short_root_bus", "1" }, 325 { "q35-pcihost", "short_root_bus", "1" }, 326 }; 327 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 328 329 GlobalProperty pc_compat_1_5[] = { 330 PC_CPU_MODEL_IDS("1.5.0") 331 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 332 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 333 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 334 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 335 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 336 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 337 { "virtio-net-pci", "any_layout", "off" }, 338 { TYPE_X86_CPU, "pmu", "on" }, 339 { "i440FX-pcihost", "short_root_bus", "0" }, 340 { "q35-pcihost", "short_root_bus", "0" }, 341 }; 342 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 343 344 GlobalProperty pc_compat_1_4[] = { 345 PC_CPU_MODEL_IDS("1.4.0") 346 { "scsi-hd", "discard_granularity", "0" }, 347 { "scsi-cd", "discard_granularity", "0" }, 348 { "ide-hd", "discard_granularity", "0" }, 349 { "ide-cd", "discard_granularity", "0" }, 350 { "virtio-blk-pci", "discard_granularity", "0" }, 351 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 352 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 353 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 354 { "e1000", "romfile", "pxe-e1000.rom" }, 355 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 356 { "pcnet", "romfile", "pxe-pcnet.rom" }, 357 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 358 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 359 { "486-" TYPE_X86_CPU, "model", "0" }, 360 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 361 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 362 }; 363 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 364 365 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 366 { 367 GSIState *s; 368 369 s = g_new0(GSIState, 1); 370 if (kvm_ioapic_in_kernel()) { 371 kvm_pc_setup_irq_routing(pci_enabled); 372 } 373 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 374 375 return s; 376 } 377 378 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 379 unsigned size) 380 { 381 } 382 383 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 384 { 385 return 0xffffffffffffffffULL; 386 } 387 388 /* MSDOS compatibility mode FPU exception support */ 389 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 390 unsigned size) 391 { 392 if (tcg_enabled()) { 393 cpu_set_ignne(); 394 } 395 } 396 397 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 398 { 399 return 0xffffffffffffffffULL; 400 } 401 402 /* PC cmos mappings */ 403 404 #define REG_EQUIPMENT_BYTE 0x14 405 406 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 407 int16_t cylinders, int8_t heads, int8_t sectors) 408 { 409 rtc_set_memory(s, type_ofs, 47); 410 rtc_set_memory(s, info_ofs, cylinders); 411 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 412 rtc_set_memory(s, info_ofs + 2, heads); 413 rtc_set_memory(s, info_ofs + 3, 0xff); 414 rtc_set_memory(s, info_ofs + 4, 0xff); 415 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 416 rtc_set_memory(s, info_ofs + 6, cylinders); 417 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 418 rtc_set_memory(s, info_ofs + 8, sectors); 419 } 420 421 /* convert boot_device letter to something recognizable by the bios */ 422 static int boot_device2nibble(char boot_device) 423 { 424 switch(boot_device) { 425 case 'a': 426 case 'b': 427 return 0x01; /* floppy boot */ 428 case 'c': 429 return 0x02; /* hard drive boot */ 430 case 'd': 431 return 0x03; /* CD-ROM boot */ 432 case 'n': 433 return 0x04; /* Network boot */ 434 } 435 return 0; 436 } 437 438 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 439 { 440 #define PC_MAX_BOOT_DEVICES 3 441 int nbds, bds[3] = { 0, }; 442 int i; 443 444 nbds = strlen(boot_device); 445 if (nbds > PC_MAX_BOOT_DEVICES) { 446 error_setg(errp, "Too many boot devices for PC"); 447 return; 448 } 449 for (i = 0; i < nbds; i++) { 450 bds[i] = boot_device2nibble(boot_device[i]); 451 if (bds[i] == 0) { 452 error_setg(errp, "Invalid boot device for PC: '%c'", 453 boot_device[i]); 454 return; 455 } 456 } 457 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 458 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 459 } 460 461 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 462 { 463 set_boot_dev(opaque, boot_device, errp); 464 } 465 466 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 467 { 468 int val, nb, i; 469 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 470 FLOPPY_DRIVE_TYPE_NONE }; 471 472 /* floppy type */ 473 if (floppy) { 474 for (i = 0; i < 2; i++) { 475 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 476 } 477 } 478 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 479 cmos_get_fd_drive_type(fd_type[1]); 480 rtc_set_memory(rtc_state, 0x10, val); 481 482 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 483 nb = 0; 484 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 485 nb++; 486 } 487 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 488 nb++; 489 } 490 switch (nb) { 491 case 0: 492 break; 493 case 1: 494 val |= 0x01; /* 1 drive, ready for boot */ 495 break; 496 case 2: 497 val |= 0x41; /* 2 drives, ready for boot */ 498 break; 499 } 500 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 501 } 502 503 typedef struct pc_cmos_init_late_arg { 504 ISADevice *rtc_state; 505 BusState *idebus[2]; 506 } pc_cmos_init_late_arg; 507 508 typedef struct check_fdc_state { 509 ISADevice *floppy; 510 bool multiple; 511 } CheckFdcState; 512 513 static int check_fdc(Object *obj, void *opaque) 514 { 515 CheckFdcState *state = opaque; 516 Object *fdc; 517 uint32_t iobase; 518 Error *local_err = NULL; 519 520 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 521 if (!fdc) { 522 return 0; 523 } 524 525 iobase = object_property_get_uint(obj, "iobase", &local_err); 526 if (local_err || iobase != 0x3f0) { 527 error_free(local_err); 528 return 0; 529 } 530 531 if (state->floppy) { 532 state->multiple = true; 533 } else { 534 state->floppy = ISA_DEVICE(obj); 535 } 536 return 0; 537 } 538 539 static const char * const fdc_container_path[] = { 540 "/unattached", "/peripheral", "/peripheral-anon" 541 }; 542 543 /* 544 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 545 * and ACPI objects. 546 */ 547 ISADevice *pc_find_fdc0(void) 548 { 549 int i; 550 Object *container; 551 CheckFdcState state = { 0 }; 552 553 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 554 container = container_get(qdev_get_machine(), fdc_container_path[i]); 555 object_child_foreach(container, check_fdc, &state); 556 } 557 558 if (state.multiple) { 559 warn_report("multiple floppy disk controllers with " 560 "iobase=0x3f0 have been found"); 561 error_printf("the one being picked for CMOS setup might not reflect " 562 "your intent"); 563 } 564 565 return state.floppy; 566 } 567 568 static void pc_cmos_init_late(void *opaque) 569 { 570 pc_cmos_init_late_arg *arg = opaque; 571 ISADevice *s = arg->rtc_state; 572 int16_t cylinders; 573 int8_t heads, sectors; 574 int val; 575 int i, trans; 576 577 val = 0; 578 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 579 &cylinders, &heads, §ors) >= 0) { 580 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 581 val |= 0xf0; 582 } 583 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 584 &cylinders, &heads, §ors) >= 0) { 585 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 586 val |= 0x0f; 587 } 588 rtc_set_memory(s, 0x12, val); 589 590 val = 0; 591 for (i = 0; i < 4; i++) { 592 /* NOTE: ide_get_geometry() returns the physical 593 geometry. It is always such that: 1 <= sects <= 63, 1 594 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 595 geometry can be different if a translation is done. */ 596 if (arg->idebus[i / 2] && 597 ide_get_geometry(arg->idebus[i / 2], i % 2, 598 &cylinders, &heads, §ors) >= 0) { 599 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 600 assert((trans & ~3) == 0); 601 val |= trans << (i * 2); 602 } 603 } 604 rtc_set_memory(s, 0x39, val); 605 606 pc_cmos_init_floppy(s, pc_find_fdc0()); 607 608 qemu_unregister_reset(pc_cmos_init_late, opaque); 609 } 610 611 void pc_cmos_init(PCMachineState *pcms, 612 BusState *idebus0, BusState *idebus1, 613 ISADevice *s) 614 { 615 int val; 616 static pc_cmos_init_late_arg arg; 617 X86MachineState *x86ms = X86_MACHINE(pcms); 618 619 /* various important CMOS locations needed by PC/Bochs bios */ 620 621 /* memory size */ 622 /* base memory (first MiB) */ 623 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 624 rtc_set_memory(s, 0x15, val); 625 rtc_set_memory(s, 0x16, val >> 8); 626 /* extended memory (next 64MiB) */ 627 if (x86ms->below_4g_mem_size > 1 * MiB) { 628 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 629 } else { 630 val = 0; 631 } 632 if (val > 65535) 633 val = 65535; 634 rtc_set_memory(s, 0x17, val); 635 rtc_set_memory(s, 0x18, val >> 8); 636 rtc_set_memory(s, 0x30, val); 637 rtc_set_memory(s, 0x31, val >> 8); 638 /* memory between 16MiB and 4GiB */ 639 if (x86ms->below_4g_mem_size > 16 * MiB) { 640 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 641 } else { 642 val = 0; 643 } 644 if (val > 65535) 645 val = 65535; 646 rtc_set_memory(s, 0x34, val); 647 rtc_set_memory(s, 0x35, val >> 8); 648 /* memory above 4GiB */ 649 val = x86ms->above_4g_mem_size / 65536; 650 rtc_set_memory(s, 0x5b, val); 651 rtc_set_memory(s, 0x5c, val >> 8); 652 rtc_set_memory(s, 0x5d, val >> 16); 653 654 object_property_add_link(OBJECT(pcms), "rtc_state", 655 TYPE_ISA_DEVICE, 656 (Object **)&x86ms->rtc, 657 object_property_allow_set_link, 658 OBJ_PROP_LINK_STRONG); 659 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 660 &error_abort); 661 662 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 663 664 val = 0; 665 val |= 0x02; /* FPU is there */ 666 val |= 0x04; /* PS/2 mouse installed */ 667 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 668 669 /* hard drives and FDC */ 670 arg.rtc_state = s; 671 arg.idebus[0] = idebus0; 672 arg.idebus[1] = idebus1; 673 qemu_register_reset(pc_cmos_init_late, &arg); 674 } 675 676 static void handle_a20_line_change(void *opaque, int irq, int level) 677 { 678 X86CPU *cpu = opaque; 679 680 /* XXX: send to all CPUs ? */ 681 /* XXX: add logic to handle multiple A20 line sources */ 682 x86_cpu_set_a20(cpu, level); 683 } 684 685 #define NE2000_NB_MAX 6 686 687 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 688 0x280, 0x380 }; 689 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 690 691 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 692 { 693 static int nb_ne2k = 0; 694 695 if (nb_ne2k == NE2000_NB_MAX) 696 return; 697 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 698 ne2000_irq[nb_ne2k], nd); 699 nb_ne2k++; 700 } 701 702 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 703 { 704 X86CPU *cpu = opaque; 705 706 if (level) { 707 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 708 } 709 } 710 711 /* 712 * This function is very similar to smp_parse() 713 * in hw/core/machine.c but includes CPU die support. 714 */ 715 static void pc_smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp) 716 { 717 unsigned cpus = config->has_cpus ? config->cpus : 0; 718 unsigned sockets = config->has_sockets ? config->sockets : 0; 719 unsigned dies = config->has_dies ? config->dies : 1; 720 unsigned cores = config->has_cores ? config->cores : 0; 721 unsigned threads = config->has_threads ? config->threads : 0; 722 723 /* compute missing values, prefer sockets over cores over threads */ 724 if (cpus == 0 || sockets == 0) { 725 cores = cores > 0 ? cores : 1; 726 threads = threads > 0 ? threads : 1; 727 if (cpus == 0) { 728 sockets = sockets > 0 ? sockets : 1; 729 cpus = cores * threads * dies * sockets; 730 } else { 731 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 732 sockets = ms->smp.max_cpus / (cores * threads * dies); 733 } 734 } else if (cores == 0) { 735 threads = threads > 0 ? threads : 1; 736 cores = cpus / (sockets * dies * threads); 737 cores = cores > 0 ? cores : 1; 738 } else if (threads == 0) { 739 threads = cpus / (cores * dies * sockets); 740 threads = threads > 0 ? threads : 1; 741 } else if (sockets * dies * cores * threads < cpus) { 742 error_setg(errp, "cpu topology: " 743 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 744 "smp_cpus (%u)", 745 sockets, dies, cores, threads, cpus); 746 return; 747 } 748 749 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 750 751 if (ms->smp.max_cpus < cpus) { 752 error_setg(errp, "maxcpus must be equal to or greater than smp"); 753 return; 754 } 755 756 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 757 error_setg(errp, "Invalid CPU topology deprecated: " 758 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 759 "!= maxcpus (%u)", 760 sockets, dies, cores, threads, 761 ms->smp.max_cpus); 762 return; 763 } 764 765 ms->smp.cpus = cpus; 766 ms->smp.cores = cores; 767 ms->smp.threads = threads; 768 ms->smp.sockets = sockets; 769 ms->smp.dies = dies; 770 } 771 772 static 773 void pc_machine_done(Notifier *notifier, void *data) 774 { 775 PCMachineState *pcms = container_of(notifier, 776 PCMachineState, machine_done); 777 X86MachineState *x86ms = X86_MACHINE(pcms); 778 779 /* set the number of CPUs */ 780 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 781 782 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 783 784 acpi_setup(); 785 if (x86ms->fw_cfg) { 786 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 787 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 788 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 789 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 790 } 791 792 793 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 794 !kvm_irqchip_in_kernel()) { 795 error_report("current -smp configuration requires kernel " 796 "irqchip support."); 797 exit(EXIT_FAILURE); 798 } 799 } 800 801 void pc_guest_info_init(PCMachineState *pcms) 802 { 803 int i; 804 MachineState *ms = MACHINE(pcms); 805 X86MachineState *x86ms = X86_MACHINE(pcms); 806 807 x86ms->apic_xrupt_override = true; 808 pcms->numa_nodes = ms->numa_state->num_nodes; 809 pcms->node_mem = g_malloc0(pcms->numa_nodes * 810 sizeof *pcms->node_mem); 811 for (i = 0; i < ms->numa_state->num_nodes; i++) { 812 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 813 } 814 815 pcms->machine_done.notify = pc_machine_done; 816 qemu_add_machine_init_done_notifier(&pcms->machine_done); 817 } 818 819 /* setup pci memory address space mapping into system address space */ 820 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 821 MemoryRegion *pci_address_space) 822 { 823 /* Set to lower priority than RAM */ 824 memory_region_add_subregion_overlap(system_memory, 0x0, 825 pci_address_space, -1); 826 } 827 828 void xen_load_linux(PCMachineState *pcms) 829 { 830 int i; 831 FWCfgState *fw_cfg; 832 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 833 X86MachineState *x86ms = X86_MACHINE(pcms); 834 835 assert(MACHINE(pcms)->kernel_filename != NULL); 836 837 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 838 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 839 rom_set_fw(fw_cfg); 840 841 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 842 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 843 for (i = 0; i < nb_option_roms; i++) { 844 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 845 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 846 !strcmp(option_rom[i].name, "pvh.bin") || 847 !strcmp(option_rom[i].name, "multiboot.bin")); 848 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 849 } 850 x86ms->fw_cfg = fw_cfg; 851 } 852 853 void pc_memory_init(PCMachineState *pcms, 854 MemoryRegion *system_memory, 855 MemoryRegion *rom_memory, 856 MemoryRegion **ram_memory) 857 { 858 int linux_boot, i; 859 MemoryRegion *option_rom_mr; 860 MemoryRegion *ram_below_4g, *ram_above_4g; 861 FWCfgState *fw_cfg; 862 MachineState *machine = MACHINE(pcms); 863 MachineClass *mc = MACHINE_GET_CLASS(machine); 864 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 865 X86MachineState *x86ms = X86_MACHINE(pcms); 866 867 assert(machine->ram_size == x86ms->below_4g_mem_size + 868 x86ms->above_4g_mem_size); 869 870 linux_boot = (machine->kernel_filename != NULL); 871 872 /* 873 * Split single memory region and use aliases to address portions of it, 874 * done for backwards compatibility with older qemus. 875 */ 876 *ram_memory = machine->ram; 877 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 878 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 879 0, x86ms->below_4g_mem_size); 880 memory_region_add_subregion(system_memory, 0, ram_below_4g); 881 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 882 if (x86ms->above_4g_mem_size > 0) { 883 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 884 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 885 machine->ram, 886 x86ms->below_4g_mem_size, 887 x86ms->above_4g_mem_size); 888 memory_region_add_subregion(system_memory, 0x100000000ULL, 889 ram_above_4g); 890 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 891 } 892 893 if (!pcmc->has_reserved_memory && 894 (machine->ram_slots || 895 (machine->maxram_size > machine->ram_size))) { 896 897 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 898 mc->name); 899 exit(EXIT_FAILURE); 900 } 901 902 /* always allocate the device memory information */ 903 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 904 905 /* initialize device memory address space */ 906 if (pcmc->has_reserved_memory && 907 (machine->ram_size < machine->maxram_size)) { 908 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 909 910 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 911 error_report("unsupported amount of memory slots: %"PRIu64, 912 machine->ram_slots); 913 exit(EXIT_FAILURE); 914 } 915 916 if (QEMU_ALIGN_UP(machine->maxram_size, 917 TARGET_PAGE_SIZE) != machine->maxram_size) { 918 error_report("maximum memory size must by aligned to multiple of " 919 "%d bytes", TARGET_PAGE_SIZE); 920 exit(EXIT_FAILURE); 921 } 922 923 machine->device_memory->base = 924 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 925 926 if (pcmc->enforce_aligned_dimm) { 927 /* size device region assuming 1G page max alignment per slot */ 928 device_mem_size += (1 * GiB) * machine->ram_slots; 929 } 930 931 if ((machine->device_memory->base + device_mem_size) < 932 device_mem_size) { 933 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 934 machine->maxram_size); 935 exit(EXIT_FAILURE); 936 } 937 938 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 939 "device-memory", device_mem_size); 940 memory_region_add_subregion(system_memory, machine->device_memory->base, 941 &machine->device_memory->mr); 942 } 943 944 /* Initialize PC system firmware */ 945 pc_system_firmware_init(pcms, rom_memory); 946 947 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 948 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 949 &error_fatal); 950 if (pcmc->pci_enabled) { 951 memory_region_set_readonly(option_rom_mr, true); 952 } 953 memory_region_add_subregion_overlap(rom_memory, 954 PC_ROM_MIN_VGA, 955 option_rom_mr, 956 1); 957 958 fw_cfg = fw_cfg_arch_create(machine, 959 x86ms->boot_cpus, x86ms->apic_id_limit); 960 961 rom_set_fw(fw_cfg); 962 963 if (pcmc->has_reserved_memory && machine->device_memory->base) { 964 uint64_t *val = g_malloc(sizeof(*val)); 965 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 966 uint64_t res_mem_end = machine->device_memory->base; 967 968 if (!pcmc->broken_reserved_end) { 969 res_mem_end += memory_region_size(&machine->device_memory->mr); 970 } 971 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 972 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 973 } 974 975 if (linux_boot) { 976 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 977 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 978 } 979 980 for (i = 0; i < nb_option_roms; i++) { 981 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 982 } 983 x86ms->fw_cfg = fw_cfg; 984 985 /* Init default IOAPIC address space */ 986 x86ms->ioapic_as = &address_space_memory; 987 988 /* Init ACPI memory hotplug IO base address */ 989 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 990 } 991 992 /* 993 * The 64bit pci hole starts after "above 4G RAM" and 994 * potentially the space reserved for memory hotplug. 995 */ 996 uint64_t pc_pci_hole64_start(void) 997 { 998 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 999 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1000 MachineState *ms = MACHINE(pcms); 1001 X86MachineState *x86ms = X86_MACHINE(pcms); 1002 uint64_t hole64_start = 0; 1003 1004 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1005 hole64_start = ms->device_memory->base; 1006 if (!pcmc->broken_reserved_end) { 1007 hole64_start += memory_region_size(&ms->device_memory->mr); 1008 } 1009 } else { 1010 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1011 } 1012 1013 return ROUND_UP(hole64_start, 1 * GiB); 1014 } 1015 1016 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1017 { 1018 DeviceState *dev = NULL; 1019 1020 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1021 if (pci_bus) { 1022 PCIDevice *pcidev = pci_vga_init(pci_bus); 1023 dev = pcidev ? &pcidev->qdev : NULL; 1024 } else if (isa_bus) { 1025 ISADevice *isadev = isa_vga_init(isa_bus); 1026 dev = isadev ? DEVICE(isadev) : NULL; 1027 } 1028 rom_reset_order_override(); 1029 return dev; 1030 } 1031 1032 static const MemoryRegionOps ioport80_io_ops = { 1033 .write = ioport80_write, 1034 .read = ioport80_read, 1035 .endianness = DEVICE_NATIVE_ENDIAN, 1036 .impl = { 1037 .min_access_size = 1, 1038 .max_access_size = 1, 1039 }, 1040 }; 1041 1042 static const MemoryRegionOps ioportF0_io_ops = { 1043 .write = ioportF0_write, 1044 .read = ioportF0_read, 1045 .endianness = DEVICE_NATIVE_ENDIAN, 1046 .impl = { 1047 .min_access_size = 1, 1048 .max_access_size = 1, 1049 }, 1050 }; 1051 1052 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1053 { 1054 int i; 1055 DriveInfo *fd[MAX_FD]; 1056 qemu_irq *a20_line; 1057 ISADevice *fdc, *i8042, *port92, *vmmouse; 1058 1059 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1060 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1061 1062 for (i = 0; i < MAX_FD; i++) { 1063 fd[i] = drive_get(IF_FLOPPY, 0, i); 1064 create_fdctrl |= !!fd[i]; 1065 } 1066 if (create_fdctrl) { 1067 fdc = isa_new(TYPE_ISA_FDC); 1068 if (fdc) { 1069 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1070 isa_fdc_init_drives(fdc, fd); 1071 } 1072 } 1073 1074 i8042 = isa_create_simple(isa_bus, "i8042"); 1075 if (!no_vmport) { 1076 isa_create_simple(isa_bus, TYPE_VMPORT); 1077 vmmouse = isa_try_new("vmmouse"); 1078 } else { 1079 vmmouse = NULL; 1080 } 1081 if (vmmouse) { 1082 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1083 &error_abort); 1084 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1085 } 1086 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1087 1088 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1089 i8042_setup_a20_line(i8042, a20_line[0]); 1090 qdev_connect_gpio_out_named(DEVICE(port92), 1091 PORT92_A20_LINE, 0, a20_line[1]); 1092 g_free(a20_line); 1093 } 1094 1095 void pc_basic_device_init(struct PCMachineState *pcms, 1096 ISABus *isa_bus, qemu_irq *gsi, 1097 ISADevice **rtc_state, 1098 bool create_fdctrl, 1099 uint32_t hpet_irqs) 1100 { 1101 int i; 1102 DeviceState *hpet = NULL; 1103 int pit_isa_irq = 0; 1104 qemu_irq pit_alt_irq = NULL; 1105 qemu_irq rtc_irq = NULL; 1106 ISADevice *pit = NULL; 1107 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1108 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1109 1110 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1111 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1112 1113 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1114 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1115 1116 /* 1117 * Check if an HPET shall be created. 1118 * 1119 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1120 * when the HPET wants to take over. Thus we have to disable the latter. 1121 */ 1122 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1123 kvm_has_pit_state2())) { 1124 hpet = qdev_try_new(TYPE_HPET); 1125 if (!hpet) { 1126 error_report("couldn't create HPET device"); 1127 exit(1); 1128 } 1129 /* 1130 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1131 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1132 * IRQ2. 1133 */ 1134 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1135 HPET_INTCAP, NULL); 1136 if (!compat) { 1137 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1138 } 1139 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1140 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1141 1142 for (i = 0; i < GSI_NUM_PINS; i++) { 1143 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1144 } 1145 pit_isa_irq = -1; 1146 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1147 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1148 } 1149 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1150 1151 qemu_register_boot_set(pc_boot_set, *rtc_state); 1152 1153 if (!xen_enabled() && pcms->pit_enabled) { 1154 if (kvm_pit_in_kernel()) { 1155 pit = kvm_pit_init(isa_bus, 0x40); 1156 } else { 1157 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1158 } 1159 if (hpet) { 1160 /* connect PIT to output control line of the HPET */ 1161 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1162 } 1163 pcspk_init(pcms->pcspk, isa_bus, pit); 1164 } 1165 1166 i8257_dma_init(isa_bus, 0); 1167 1168 /* Super I/O */ 1169 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1170 } 1171 1172 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1173 { 1174 int i; 1175 1176 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1177 for (i = 0; i < nb_nics; i++) { 1178 NICInfo *nd = &nd_table[i]; 1179 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1180 1181 if (g_str_equal(model, "ne2k_isa")) { 1182 pc_init_ne2k_isa(isa_bus, nd); 1183 } else { 1184 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1185 } 1186 } 1187 rom_reset_order_override(); 1188 } 1189 1190 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1191 { 1192 qemu_irq *i8259; 1193 1194 if (kvm_pic_in_kernel()) { 1195 i8259 = kvm_i8259_init(isa_bus); 1196 } else if (xen_enabled()) { 1197 i8259 = xen_interrupt_controller_init(); 1198 } else { 1199 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1200 } 1201 1202 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1203 i8259_irqs[i] = i8259[i]; 1204 } 1205 1206 g_free(i8259); 1207 } 1208 1209 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1210 Error **errp) 1211 { 1212 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1213 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1214 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1215 const MachineState *ms = MACHINE(hotplug_dev); 1216 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1217 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1218 Error *local_err = NULL; 1219 1220 /* 1221 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1222 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1223 * addition to cover this case. 1224 */ 1225 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1226 error_setg(errp, 1227 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1228 return; 1229 } 1230 1231 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1232 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1233 return; 1234 } 1235 1236 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1237 if (local_err) { 1238 error_propagate(errp, local_err); 1239 return; 1240 } 1241 1242 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1243 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1244 } 1245 1246 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1247 DeviceState *dev, Error **errp) 1248 { 1249 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1250 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1251 MachineState *ms = MACHINE(hotplug_dev); 1252 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1253 1254 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1255 1256 if (is_nvdimm) { 1257 nvdimm_plug(ms->nvdimms_state); 1258 } 1259 1260 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1261 } 1262 1263 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1264 DeviceState *dev, Error **errp) 1265 { 1266 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1267 1268 /* 1269 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1270 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1271 * addition to cover this case. 1272 */ 1273 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1274 error_setg(errp, 1275 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1276 return; 1277 } 1278 1279 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1280 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1281 return; 1282 } 1283 1284 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1285 errp); 1286 } 1287 1288 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1289 DeviceState *dev, Error **errp) 1290 { 1291 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1292 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1293 Error *local_err = NULL; 1294 1295 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1296 if (local_err) { 1297 goto out; 1298 } 1299 1300 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1301 qdev_unrealize(dev); 1302 out: 1303 error_propagate(errp, local_err); 1304 } 1305 1306 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1307 DeviceState *dev, Error **errp) 1308 { 1309 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1310 Error *local_err = NULL; 1311 1312 if (!hotplug_dev2 && dev->hotplugged) { 1313 /* 1314 * Without a bus hotplug handler, we cannot control the plug/unplug 1315 * order. We should never reach this point when hotplugging on x86, 1316 * however, better add a safety net. 1317 */ 1318 error_setg(errp, "hotplug of virtio based memory devices not supported" 1319 " on this bus."); 1320 return; 1321 } 1322 /* 1323 * First, see if we can plug this memory device at all. If that 1324 * succeeds, branch of to the actual hotplug handler. 1325 */ 1326 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1327 &local_err); 1328 if (!local_err && hotplug_dev2) { 1329 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1330 } 1331 error_propagate(errp, local_err); 1332 } 1333 1334 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1335 DeviceState *dev, Error **errp) 1336 { 1337 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1338 Error *local_err = NULL; 1339 1340 /* 1341 * Plug the memory device first and then branch off to the actual 1342 * hotplug handler. If that one fails, we can easily undo the memory 1343 * device bits. 1344 */ 1345 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1346 if (hotplug_dev2) { 1347 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1348 if (local_err) { 1349 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1350 } 1351 } 1352 error_propagate(errp, local_err); 1353 } 1354 1355 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1356 DeviceState *dev, Error **errp) 1357 { 1358 /* We don't support hot unplug of virtio based memory devices */ 1359 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1360 } 1361 1362 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1363 DeviceState *dev, Error **errp) 1364 { 1365 /* We don't support hot unplug of virtio based memory devices */ 1366 } 1367 1368 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1369 DeviceState *dev, Error **errp) 1370 { 1371 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1372 pc_memory_pre_plug(hotplug_dev, dev, errp); 1373 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1374 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1375 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1376 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1377 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1378 } 1379 } 1380 1381 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1382 DeviceState *dev, Error **errp) 1383 { 1384 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1385 pc_memory_plug(hotplug_dev, dev, errp); 1386 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1387 x86_cpu_plug(hotplug_dev, dev, errp); 1388 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1389 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1390 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1391 } 1392 } 1393 1394 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1395 DeviceState *dev, Error **errp) 1396 { 1397 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1398 pc_memory_unplug_request(hotplug_dev, dev, errp); 1399 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1400 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1401 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1402 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1403 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1404 } else { 1405 error_setg(errp, "acpi: device unplug request for not supported device" 1406 " type: %s", object_get_typename(OBJECT(dev))); 1407 } 1408 } 1409 1410 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1411 DeviceState *dev, Error **errp) 1412 { 1413 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1414 pc_memory_unplug(hotplug_dev, dev, errp); 1415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1416 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1417 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1418 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1419 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1420 } else { 1421 error_setg(errp, "acpi: device unplug for not supported device" 1422 " type: %s", object_get_typename(OBJECT(dev))); 1423 } 1424 } 1425 1426 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1427 DeviceState *dev) 1428 { 1429 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1430 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1431 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1432 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1433 return HOTPLUG_HANDLER(machine); 1434 } 1435 1436 return NULL; 1437 } 1438 1439 static void 1440 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1441 const char *name, void *opaque, 1442 Error **errp) 1443 { 1444 MachineState *ms = MACHINE(obj); 1445 int64_t value = 0; 1446 1447 if (ms->device_memory) { 1448 value = memory_region_size(&ms->device_memory->mr); 1449 } 1450 1451 visit_type_int(v, name, &value, errp); 1452 } 1453 1454 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1455 void *opaque, Error **errp) 1456 { 1457 PCMachineState *pcms = PC_MACHINE(obj); 1458 OnOffAuto vmport = pcms->vmport; 1459 1460 visit_type_OnOffAuto(v, name, &vmport, errp); 1461 } 1462 1463 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1464 void *opaque, Error **errp) 1465 { 1466 PCMachineState *pcms = PC_MACHINE(obj); 1467 1468 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1469 } 1470 1471 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1472 { 1473 PCMachineState *pcms = PC_MACHINE(obj); 1474 1475 return pcms->smbus_enabled; 1476 } 1477 1478 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1479 { 1480 PCMachineState *pcms = PC_MACHINE(obj); 1481 1482 pcms->smbus_enabled = value; 1483 } 1484 1485 static bool pc_machine_get_sata(Object *obj, Error **errp) 1486 { 1487 PCMachineState *pcms = PC_MACHINE(obj); 1488 1489 return pcms->sata_enabled; 1490 } 1491 1492 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1493 { 1494 PCMachineState *pcms = PC_MACHINE(obj); 1495 1496 pcms->sata_enabled = value; 1497 } 1498 1499 static bool pc_machine_get_pit(Object *obj, Error **errp) 1500 { 1501 PCMachineState *pcms = PC_MACHINE(obj); 1502 1503 return pcms->pit_enabled; 1504 } 1505 1506 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1507 { 1508 PCMachineState *pcms = PC_MACHINE(obj); 1509 1510 pcms->pit_enabled = value; 1511 } 1512 1513 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1514 { 1515 PCMachineState *pcms = PC_MACHINE(obj); 1516 1517 return pcms->hpet_enabled; 1518 } 1519 1520 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1521 { 1522 PCMachineState *pcms = PC_MACHINE(obj); 1523 1524 pcms->hpet_enabled = value; 1525 } 1526 1527 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1528 { 1529 PCMachineState *pcms = PC_MACHINE(obj); 1530 1531 return pcms->default_bus_bypass_iommu; 1532 } 1533 1534 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1535 Error **errp) 1536 { 1537 PCMachineState *pcms = PC_MACHINE(obj); 1538 1539 pcms->default_bus_bypass_iommu = value; 1540 } 1541 1542 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1543 const char *name, void *opaque, 1544 Error **errp) 1545 { 1546 PCMachineState *pcms = PC_MACHINE(obj); 1547 uint64_t value = pcms->max_ram_below_4g; 1548 1549 visit_type_size(v, name, &value, errp); 1550 } 1551 1552 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1553 const char *name, void *opaque, 1554 Error **errp) 1555 { 1556 PCMachineState *pcms = PC_MACHINE(obj); 1557 uint64_t value; 1558 1559 if (!visit_type_size(v, name, &value, errp)) { 1560 return; 1561 } 1562 if (value > 4 * GiB) { 1563 error_setg(errp, 1564 "Machine option 'max-ram-below-4g=%"PRIu64 1565 "' expects size less than or equal to 4G", value); 1566 return; 1567 } 1568 1569 if (value < 1 * MiB) { 1570 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1571 "BIOS may not work with less than 1MiB", value); 1572 } 1573 1574 pcms->max_ram_below_4g = value; 1575 } 1576 1577 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1578 const char *name, void *opaque, 1579 Error **errp) 1580 { 1581 PCMachineState *pcms = PC_MACHINE(obj); 1582 uint64_t value = pcms->max_fw_size; 1583 1584 visit_type_size(v, name, &value, errp); 1585 } 1586 1587 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1588 const char *name, void *opaque, 1589 Error **errp) 1590 { 1591 PCMachineState *pcms = PC_MACHINE(obj); 1592 Error *error = NULL; 1593 uint64_t value; 1594 1595 visit_type_size(v, name, &value, &error); 1596 if (error) { 1597 error_propagate(errp, error); 1598 return; 1599 } 1600 1601 /* 1602 * We don't have a theoretically justifiable exact lower bound on the base 1603 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1604 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1605 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1606 * size. 1607 */ 1608 if (value > 16 * MiB) { 1609 error_setg(errp, 1610 "User specified max allowed firmware size %" PRIu64 " is " 1611 "greater than 16MiB. If combined firwmare size exceeds " 1612 "16MiB the system may not boot, or experience intermittent" 1613 "stability issues.", 1614 value); 1615 return; 1616 } 1617 1618 pcms->max_fw_size = value; 1619 } 1620 1621 1622 static void pc_machine_initfn(Object *obj) 1623 { 1624 PCMachineState *pcms = PC_MACHINE(obj); 1625 1626 #ifdef CONFIG_VMPORT 1627 pcms->vmport = ON_OFF_AUTO_AUTO; 1628 #else 1629 pcms->vmport = ON_OFF_AUTO_OFF; 1630 #endif /* CONFIG_VMPORT */ 1631 pcms->max_ram_below_4g = 0; /* use default */ 1632 /* acpi build is enabled by default if machine supports it */ 1633 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1634 pcms->smbus_enabled = true; 1635 pcms->sata_enabled = true; 1636 pcms->pit_enabled = true; 1637 pcms->max_fw_size = 8 * MiB; 1638 #ifdef CONFIG_HPET 1639 pcms->hpet_enabled = true; 1640 #endif 1641 pcms->default_bus_bypass_iommu = false; 1642 1643 pc_system_flash_create(pcms); 1644 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1645 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1646 OBJECT(pcms->pcspk), "audiodev"); 1647 } 1648 1649 static void pc_machine_reset(MachineState *machine) 1650 { 1651 CPUState *cs; 1652 X86CPU *cpu; 1653 1654 qemu_devices_reset(); 1655 1656 /* Reset APIC after devices have been reset to cancel 1657 * any changes that qemu_devices_reset() might have done. 1658 */ 1659 CPU_FOREACH(cs) { 1660 cpu = X86_CPU(cs); 1661 1662 if (cpu->apic_state) { 1663 device_legacy_reset(cpu->apic_state); 1664 } 1665 } 1666 } 1667 1668 static void pc_machine_wakeup(MachineState *machine) 1669 { 1670 cpu_synchronize_all_states(); 1671 pc_machine_reset(machine); 1672 cpu_synchronize_all_post_reset(); 1673 } 1674 1675 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1676 { 1677 X86IOMMUState *iommu = x86_iommu_get_default(); 1678 IntelIOMMUState *intel_iommu; 1679 1680 if (iommu && 1681 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1682 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1683 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1684 if (!intel_iommu->caching_mode) { 1685 error_setg(errp, "Device assignment is not allowed without " 1686 "enabling caching-mode=on for Intel IOMMU."); 1687 return false; 1688 } 1689 } 1690 1691 return true; 1692 } 1693 1694 static void pc_machine_class_init(ObjectClass *oc, void *data) 1695 { 1696 MachineClass *mc = MACHINE_CLASS(oc); 1697 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1698 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1699 1700 pcmc->pci_enabled = true; 1701 pcmc->has_acpi_build = true; 1702 pcmc->rsdp_in_ram = true; 1703 pcmc->smbios_defaults = true; 1704 pcmc->smbios_uuid_encoded = true; 1705 pcmc->gigabyte_align = true; 1706 pcmc->has_reserved_memory = true; 1707 pcmc->kvmclock_enabled = true; 1708 pcmc->enforce_aligned_dimm = true; 1709 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1710 * to be used at the moment, 32K should be enough for a while. */ 1711 pcmc->acpi_data_size = 0x20000 + 0x8000; 1712 pcmc->linuxboot_dma_enabled = true; 1713 pcmc->pvh_enabled = true; 1714 pcmc->kvmclock_create_always = true; 1715 assert(!mc->get_hotplug_handler); 1716 mc->get_hotplug_handler = pc_get_hotplug_handler; 1717 mc->hotplug_allowed = pc_hotplug_allowed; 1718 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1719 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1720 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1721 mc->auto_enable_numa_with_memhp = true; 1722 mc->auto_enable_numa_with_memdev = true; 1723 mc->has_hotpluggable_cpus = true; 1724 mc->default_boot_order = "cad"; 1725 mc->smp_parse = pc_smp_parse; 1726 mc->block_default_type = IF_IDE; 1727 mc->max_cpus = 255; 1728 mc->reset = pc_machine_reset; 1729 mc->wakeup = pc_machine_wakeup; 1730 hc->pre_plug = pc_machine_device_pre_plug_cb; 1731 hc->plug = pc_machine_device_plug_cb; 1732 hc->unplug_request = pc_machine_device_unplug_request_cb; 1733 hc->unplug = pc_machine_device_unplug_cb; 1734 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1735 mc->nvdimm_supported = true; 1736 mc->default_ram_id = "pc.ram"; 1737 1738 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1739 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1740 NULL, NULL); 1741 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1742 "Maximum ram below the 4G boundary (32bit boundary)"); 1743 1744 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1745 pc_machine_get_device_memory_region_size, NULL, 1746 NULL, NULL); 1747 1748 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1749 pc_machine_get_vmport, pc_machine_set_vmport, 1750 NULL, NULL); 1751 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1752 "Enable vmport (pc & q35)"); 1753 1754 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1755 pc_machine_get_smbus, pc_machine_set_smbus); 1756 1757 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1758 pc_machine_get_sata, pc_machine_set_sata); 1759 1760 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1761 pc_machine_get_pit, pc_machine_set_pit); 1762 1763 object_class_property_add_bool(oc, "hpet", 1764 pc_machine_get_hpet, pc_machine_set_hpet); 1765 1766 object_class_property_add_bool(oc, "default_bus_bypass_iommu", 1767 pc_machine_get_default_bus_bypass_iommu, 1768 pc_machine_set_default_bus_bypass_iommu); 1769 1770 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1771 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1772 NULL, NULL); 1773 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1774 "Maximum combined firmware size"); 1775 } 1776 1777 static const TypeInfo pc_machine_info = { 1778 .name = TYPE_PC_MACHINE, 1779 .parent = TYPE_X86_MACHINE, 1780 .abstract = true, 1781 .instance_size = sizeof(PCMachineState), 1782 .instance_init = pc_machine_initfn, 1783 .class_size = sizeof(PCMachineClass), 1784 .class_init = pc_machine_class_init, 1785 .interfaces = (InterfaceInfo[]) { 1786 { TYPE_HOTPLUG_HANDLER }, 1787 { } 1788 }, 1789 }; 1790 1791 static void pc_machine_register_types(void) 1792 { 1793 type_register_static(&pc_machine_info); 1794 } 1795 1796 type_init(pc_machine_register_types) 1797