1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "qemu/bitmap.h" 69 #include "qemu/config-file.h" 70 #include "qemu/error-report.h" 71 #include "qemu/option.h" 72 #include "qemu/cutils.h" 73 #include "hw/acpi/acpi.h" 74 #include "hw/acpi/cpu_hotplug.h" 75 #include "acpi-build.h" 76 #include "hw/mem/pc-dimm.h" 77 #include "hw/mem/nvdimm.h" 78 #include "qapi/error.h" 79 #include "qapi/qapi-visit-common.h" 80 #include "qapi/visitor.h" 81 #include "hw/core/cpu.h" 82 #include "hw/usb.h" 83 #include "hw/i386/intel_iommu.h" 84 #include "hw/net/ne2000-isa.h" 85 #include "standard-headers/asm-x86/bootparam.h" 86 #include "hw/virtio/virtio-iommu.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/virtio/virtio-mem-pci.h" 89 #include "hw/mem/memory-device.h" 90 #include "sysemu/replay.h" 91 #include "qapi/qmp/qerror.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 #include CONFIG_DEVICES 96 97 GlobalProperty pc_compat_6_1[] = { 98 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 99 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 100 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 101 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 102 }; 103 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 104 105 GlobalProperty pc_compat_6_0[] = { 106 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 107 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 108 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 109 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 110 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 111 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 112 }; 113 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 114 115 GlobalProperty pc_compat_5_2[] = { 116 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 117 }; 118 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 119 120 GlobalProperty pc_compat_5_1[] = { 121 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 122 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 123 }; 124 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 125 126 GlobalProperty pc_compat_5_0[] = { 127 }; 128 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 129 130 GlobalProperty pc_compat_4_2[] = { 131 { "mch", "smbase-smram", "off" }, 132 }; 133 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 134 135 GlobalProperty pc_compat_4_1[] = {}; 136 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 137 138 GlobalProperty pc_compat_4_0[] = {}; 139 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 140 141 GlobalProperty pc_compat_3_1[] = { 142 { "intel-iommu", "dma-drain", "off" }, 143 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 144 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 145 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 146 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 147 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 148 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 149 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 150 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 151 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 152 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 153 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 154 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 155 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 156 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 157 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 158 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 159 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 160 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 161 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 162 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 163 }; 164 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 165 166 GlobalProperty pc_compat_3_0[] = { 167 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 168 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 169 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 170 }; 171 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 172 173 GlobalProperty pc_compat_2_12[] = { 174 { TYPE_X86_CPU, "legacy-cache", "on" }, 175 { TYPE_X86_CPU, "topoext", "off" }, 176 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 177 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 178 }; 179 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 180 181 GlobalProperty pc_compat_2_11[] = { 182 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 183 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 184 }; 185 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 186 187 GlobalProperty pc_compat_2_10[] = { 188 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 189 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 190 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 191 }; 192 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 193 194 GlobalProperty pc_compat_2_9[] = { 195 { "mch", "extended-tseg-mbytes", "0" }, 196 }; 197 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 198 199 GlobalProperty pc_compat_2_8[] = { 200 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 201 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 202 { "ICH9-LPC", "x-smi-broadcast", "off" }, 203 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 204 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 205 }; 206 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 207 208 GlobalProperty pc_compat_2_7[] = { 209 { TYPE_X86_CPU, "l3-cache", "off" }, 210 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 211 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 212 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 213 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 214 { "isa-pcspk", "migrate", "off" }, 215 }; 216 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 217 218 GlobalProperty pc_compat_2_6[] = { 219 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 220 { "vmxnet3", "romfile", "" }, 221 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 222 { "apic-common", "legacy-instance-id", "on", } 223 }; 224 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 225 226 GlobalProperty pc_compat_2_5[] = {}; 227 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 228 229 GlobalProperty pc_compat_2_4[] = { 230 PC_CPU_MODEL_IDS("2.4.0") 231 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 232 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 233 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 234 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 235 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 236 { TYPE_X86_CPU, "check", "off" }, 237 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 238 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 239 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 240 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 241 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 242 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 243 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 244 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 245 }; 246 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 247 248 GlobalProperty pc_compat_2_3[] = { 249 PC_CPU_MODEL_IDS("2.3.0") 250 { TYPE_X86_CPU, "arat", "off" }, 251 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 252 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 253 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 254 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 255 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 256 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 257 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 258 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 259 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 260 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 261 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 262 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 263 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 264 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 265 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 266 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 267 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 268 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 269 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 270 }; 271 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 272 273 GlobalProperty pc_compat_2_2[] = { 274 PC_CPU_MODEL_IDS("2.2.0") 275 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 276 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 277 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 278 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 279 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 280 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 281 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 282 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 283 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 284 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 285 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 286 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 287 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 288 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 289 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 290 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 291 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 292 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 293 }; 294 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 295 296 GlobalProperty pc_compat_2_1[] = { 297 PC_CPU_MODEL_IDS("2.1.0") 298 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 299 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 300 }; 301 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 302 303 GlobalProperty pc_compat_2_0[] = { 304 PC_CPU_MODEL_IDS("2.0.0") 305 { "virtio-scsi-pci", "any_layout", "off" }, 306 { "PIIX4_PM", "memory-hotplug-support", "off" }, 307 { "apic", "version", "0x11" }, 308 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 309 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 310 { "pci-serial", "prog_if", "0" }, 311 { "pci-serial-2x", "prog_if", "0" }, 312 { "pci-serial-4x", "prog_if", "0" }, 313 { "virtio-net-pci", "guest_announce", "off" }, 314 { "ICH9-LPC", "memory-hotplug-support", "off" }, 315 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 316 { "ioh3420", COMPAT_PROP_PCP, "off" }, 317 }; 318 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 319 320 GlobalProperty pc_compat_1_7[] = { 321 PC_CPU_MODEL_IDS("1.7.0") 322 { TYPE_USB_DEVICE, "msos-desc", "no" }, 323 { "PIIX4_PM", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 324 { "hpet", HPET_INTCAP, "4" }, 325 }; 326 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 327 328 GlobalProperty pc_compat_1_6[] = { 329 PC_CPU_MODEL_IDS("1.6.0") 330 { "e1000", "mitigation", "off" }, 331 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 332 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 333 { "i440FX-pcihost", "short_root_bus", "1" }, 334 { "q35-pcihost", "short_root_bus", "1" }, 335 }; 336 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 337 338 GlobalProperty pc_compat_1_5[] = { 339 PC_CPU_MODEL_IDS("1.5.0") 340 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 341 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 342 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 343 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 344 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 345 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 346 { "virtio-net-pci", "any_layout", "off" }, 347 { TYPE_X86_CPU, "pmu", "on" }, 348 { "i440FX-pcihost", "short_root_bus", "0" }, 349 { "q35-pcihost", "short_root_bus", "0" }, 350 }; 351 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 352 353 GlobalProperty pc_compat_1_4[] = { 354 PC_CPU_MODEL_IDS("1.4.0") 355 { "scsi-hd", "discard_granularity", "0" }, 356 { "scsi-cd", "discard_granularity", "0" }, 357 { "ide-hd", "discard_granularity", "0" }, 358 { "ide-cd", "discard_granularity", "0" }, 359 { "virtio-blk-pci", "discard_granularity", "0" }, 360 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 361 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 362 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 363 { "e1000", "romfile", "pxe-e1000.rom" }, 364 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 365 { "pcnet", "romfile", "pxe-pcnet.rom" }, 366 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 367 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 368 { "486-" TYPE_X86_CPU, "model", "0" }, 369 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 370 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 371 }; 372 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 373 374 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 375 { 376 GSIState *s; 377 378 s = g_new0(GSIState, 1); 379 if (kvm_ioapic_in_kernel()) { 380 kvm_pc_setup_irq_routing(pci_enabled); 381 } 382 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 383 384 return s; 385 } 386 387 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 388 unsigned size) 389 { 390 } 391 392 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 393 { 394 return 0xffffffffffffffffULL; 395 } 396 397 /* MSDOS compatibility mode FPU exception support */ 398 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 399 unsigned size) 400 { 401 if (tcg_enabled()) { 402 cpu_set_ignne(); 403 } 404 } 405 406 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 407 { 408 return 0xffffffffffffffffULL; 409 } 410 411 /* PC cmos mappings */ 412 413 #define REG_EQUIPMENT_BYTE 0x14 414 415 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 416 int16_t cylinders, int8_t heads, int8_t sectors) 417 { 418 rtc_set_memory(s, type_ofs, 47); 419 rtc_set_memory(s, info_ofs, cylinders); 420 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 421 rtc_set_memory(s, info_ofs + 2, heads); 422 rtc_set_memory(s, info_ofs + 3, 0xff); 423 rtc_set_memory(s, info_ofs + 4, 0xff); 424 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 425 rtc_set_memory(s, info_ofs + 6, cylinders); 426 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 427 rtc_set_memory(s, info_ofs + 8, sectors); 428 } 429 430 /* convert boot_device letter to something recognizable by the bios */ 431 static int boot_device2nibble(char boot_device) 432 { 433 switch(boot_device) { 434 case 'a': 435 case 'b': 436 return 0x01; /* floppy boot */ 437 case 'c': 438 return 0x02; /* hard drive boot */ 439 case 'd': 440 return 0x03; /* CD-ROM boot */ 441 case 'n': 442 return 0x04; /* Network boot */ 443 } 444 return 0; 445 } 446 447 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 448 { 449 #define PC_MAX_BOOT_DEVICES 3 450 int nbds, bds[3] = { 0, }; 451 int i; 452 453 nbds = strlen(boot_device); 454 if (nbds > PC_MAX_BOOT_DEVICES) { 455 error_setg(errp, "Too many boot devices for PC"); 456 return; 457 } 458 for (i = 0; i < nbds; i++) { 459 bds[i] = boot_device2nibble(boot_device[i]); 460 if (bds[i] == 0) { 461 error_setg(errp, "Invalid boot device for PC: '%c'", 462 boot_device[i]); 463 return; 464 } 465 } 466 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 467 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 468 } 469 470 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 471 { 472 set_boot_dev(opaque, boot_device, errp); 473 } 474 475 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 476 { 477 int val, nb, i; 478 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 479 FLOPPY_DRIVE_TYPE_NONE }; 480 481 /* floppy type */ 482 if (floppy) { 483 for (i = 0; i < 2; i++) { 484 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 485 } 486 } 487 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 488 cmos_get_fd_drive_type(fd_type[1]); 489 rtc_set_memory(rtc_state, 0x10, val); 490 491 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 492 nb = 0; 493 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 494 nb++; 495 } 496 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 497 nb++; 498 } 499 switch (nb) { 500 case 0: 501 break; 502 case 1: 503 val |= 0x01; /* 1 drive, ready for boot */ 504 break; 505 case 2: 506 val |= 0x41; /* 2 drives, ready for boot */ 507 break; 508 } 509 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 510 } 511 512 typedef struct pc_cmos_init_late_arg { 513 ISADevice *rtc_state; 514 BusState *idebus[2]; 515 } pc_cmos_init_late_arg; 516 517 typedef struct check_fdc_state { 518 ISADevice *floppy; 519 bool multiple; 520 } CheckFdcState; 521 522 static int check_fdc(Object *obj, void *opaque) 523 { 524 CheckFdcState *state = opaque; 525 Object *fdc; 526 uint32_t iobase; 527 Error *local_err = NULL; 528 529 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 530 if (!fdc) { 531 return 0; 532 } 533 534 iobase = object_property_get_uint(obj, "iobase", &local_err); 535 if (local_err || iobase != 0x3f0) { 536 error_free(local_err); 537 return 0; 538 } 539 540 if (state->floppy) { 541 state->multiple = true; 542 } else { 543 state->floppy = ISA_DEVICE(obj); 544 } 545 return 0; 546 } 547 548 static const char * const fdc_container_path[] = { 549 "/unattached", "/peripheral", "/peripheral-anon" 550 }; 551 552 /* 553 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 554 * and ACPI objects. 555 */ 556 ISADevice *pc_find_fdc0(void) 557 { 558 int i; 559 Object *container; 560 CheckFdcState state = { 0 }; 561 562 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 563 container = container_get(qdev_get_machine(), fdc_container_path[i]); 564 object_child_foreach(container, check_fdc, &state); 565 } 566 567 if (state.multiple) { 568 warn_report("multiple floppy disk controllers with " 569 "iobase=0x3f0 have been found"); 570 error_printf("the one being picked for CMOS setup might not reflect " 571 "your intent"); 572 } 573 574 return state.floppy; 575 } 576 577 static void pc_cmos_init_late(void *opaque) 578 { 579 pc_cmos_init_late_arg *arg = opaque; 580 ISADevice *s = arg->rtc_state; 581 int16_t cylinders; 582 int8_t heads, sectors; 583 int val; 584 int i, trans; 585 586 val = 0; 587 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 588 &cylinders, &heads, §ors) >= 0) { 589 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 590 val |= 0xf0; 591 } 592 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 593 &cylinders, &heads, §ors) >= 0) { 594 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 595 val |= 0x0f; 596 } 597 rtc_set_memory(s, 0x12, val); 598 599 val = 0; 600 for (i = 0; i < 4; i++) { 601 /* NOTE: ide_get_geometry() returns the physical 602 geometry. It is always such that: 1 <= sects <= 63, 1 603 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 604 geometry can be different if a translation is done. */ 605 if (arg->idebus[i / 2] && 606 ide_get_geometry(arg->idebus[i / 2], i % 2, 607 &cylinders, &heads, §ors) >= 0) { 608 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 609 assert((trans & ~3) == 0); 610 val |= trans << (i * 2); 611 } 612 } 613 rtc_set_memory(s, 0x39, val); 614 615 pc_cmos_init_floppy(s, pc_find_fdc0()); 616 617 qemu_unregister_reset(pc_cmos_init_late, opaque); 618 } 619 620 void pc_cmos_init(PCMachineState *pcms, 621 BusState *idebus0, BusState *idebus1, 622 ISADevice *s) 623 { 624 int val; 625 static pc_cmos_init_late_arg arg; 626 X86MachineState *x86ms = X86_MACHINE(pcms); 627 628 /* various important CMOS locations needed by PC/Bochs bios */ 629 630 /* memory size */ 631 /* base memory (first MiB) */ 632 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 633 rtc_set_memory(s, 0x15, val); 634 rtc_set_memory(s, 0x16, val >> 8); 635 /* extended memory (next 64MiB) */ 636 if (x86ms->below_4g_mem_size > 1 * MiB) { 637 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 638 } else { 639 val = 0; 640 } 641 if (val > 65535) 642 val = 65535; 643 rtc_set_memory(s, 0x17, val); 644 rtc_set_memory(s, 0x18, val >> 8); 645 rtc_set_memory(s, 0x30, val); 646 rtc_set_memory(s, 0x31, val >> 8); 647 /* memory between 16MiB and 4GiB */ 648 if (x86ms->below_4g_mem_size > 16 * MiB) { 649 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 650 } else { 651 val = 0; 652 } 653 if (val > 65535) 654 val = 65535; 655 rtc_set_memory(s, 0x34, val); 656 rtc_set_memory(s, 0x35, val >> 8); 657 /* memory above 4GiB */ 658 val = x86ms->above_4g_mem_size / 65536; 659 rtc_set_memory(s, 0x5b, val); 660 rtc_set_memory(s, 0x5c, val >> 8); 661 rtc_set_memory(s, 0x5d, val >> 16); 662 663 object_property_add_link(OBJECT(pcms), "rtc_state", 664 TYPE_ISA_DEVICE, 665 (Object **)&x86ms->rtc, 666 object_property_allow_set_link, 667 OBJ_PROP_LINK_STRONG); 668 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 669 &error_abort); 670 671 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 672 673 val = 0; 674 val |= 0x02; /* FPU is there */ 675 val |= 0x04; /* PS/2 mouse installed */ 676 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 677 678 /* hard drives and FDC */ 679 arg.rtc_state = s; 680 arg.idebus[0] = idebus0; 681 arg.idebus[1] = idebus1; 682 qemu_register_reset(pc_cmos_init_late, &arg); 683 } 684 685 static void handle_a20_line_change(void *opaque, int irq, int level) 686 { 687 X86CPU *cpu = opaque; 688 689 /* XXX: send to all CPUs ? */ 690 /* XXX: add logic to handle multiple A20 line sources */ 691 x86_cpu_set_a20(cpu, level); 692 } 693 694 #define NE2000_NB_MAX 6 695 696 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 697 0x280, 0x380 }; 698 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 699 700 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 701 { 702 static int nb_ne2k = 0; 703 704 if (nb_ne2k == NE2000_NB_MAX) 705 return; 706 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 707 ne2000_irq[nb_ne2k], nd); 708 nb_ne2k++; 709 } 710 711 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 712 { 713 X86CPU *cpu = opaque; 714 715 if (level) { 716 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 717 } 718 } 719 720 static 721 void pc_machine_done(Notifier *notifier, void *data) 722 { 723 PCMachineState *pcms = container_of(notifier, 724 PCMachineState, machine_done); 725 X86MachineState *x86ms = X86_MACHINE(pcms); 726 727 /* set the number of CPUs */ 728 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 729 730 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 731 732 acpi_setup(); 733 if (x86ms->fw_cfg) { 734 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 735 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 736 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 737 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 738 } 739 740 741 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 742 !kvm_irqchip_in_kernel()) { 743 error_report("current -smp configuration requires kernel " 744 "irqchip support."); 745 exit(EXIT_FAILURE); 746 } 747 } 748 749 void pc_guest_info_init(PCMachineState *pcms) 750 { 751 X86MachineState *x86ms = X86_MACHINE(pcms); 752 753 x86ms->apic_xrupt_override = true; 754 pcms->machine_done.notify = pc_machine_done; 755 qemu_add_machine_init_done_notifier(&pcms->machine_done); 756 } 757 758 /* setup pci memory address space mapping into system address space */ 759 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 760 MemoryRegion *pci_address_space) 761 { 762 /* Set to lower priority than RAM */ 763 memory_region_add_subregion_overlap(system_memory, 0x0, 764 pci_address_space, -1); 765 } 766 767 void xen_load_linux(PCMachineState *pcms) 768 { 769 int i; 770 FWCfgState *fw_cfg; 771 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 772 X86MachineState *x86ms = X86_MACHINE(pcms); 773 774 assert(MACHINE(pcms)->kernel_filename != NULL); 775 776 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 777 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 778 rom_set_fw(fw_cfg); 779 780 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 781 pcmc->pvh_enabled); 782 for (i = 0; i < nb_option_roms; i++) { 783 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 784 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 785 !strcmp(option_rom[i].name, "pvh.bin") || 786 !strcmp(option_rom[i].name, "multiboot.bin") || 787 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 788 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 789 } 790 x86ms->fw_cfg = fw_cfg; 791 } 792 793 #define PC_ROM_MIN_VGA 0xc0000 794 #define PC_ROM_MIN_OPTION 0xc8000 795 #define PC_ROM_MAX 0xe0000 796 #define PC_ROM_ALIGN 0x800 797 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 798 799 void pc_memory_init(PCMachineState *pcms, 800 MemoryRegion *system_memory, 801 MemoryRegion *rom_memory, 802 MemoryRegion **ram_memory) 803 { 804 int linux_boot, i; 805 MemoryRegion *option_rom_mr; 806 MemoryRegion *ram_below_4g, *ram_above_4g; 807 FWCfgState *fw_cfg; 808 MachineState *machine = MACHINE(pcms); 809 MachineClass *mc = MACHINE_GET_CLASS(machine); 810 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 811 X86MachineState *x86ms = X86_MACHINE(pcms); 812 813 assert(machine->ram_size == x86ms->below_4g_mem_size + 814 x86ms->above_4g_mem_size); 815 816 linux_boot = (machine->kernel_filename != NULL); 817 818 /* 819 * Split single memory region and use aliases to address portions of it, 820 * done for backwards compatibility with older qemus. 821 */ 822 *ram_memory = machine->ram; 823 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 824 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 825 0, x86ms->below_4g_mem_size); 826 memory_region_add_subregion(system_memory, 0, ram_below_4g); 827 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 828 if (x86ms->above_4g_mem_size > 0) { 829 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 830 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 831 machine->ram, 832 x86ms->below_4g_mem_size, 833 x86ms->above_4g_mem_size); 834 memory_region_add_subregion(system_memory, 0x100000000ULL, 835 ram_above_4g); 836 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 837 } 838 839 if (pcms->sgx_epc.size != 0) { 840 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 841 } 842 843 if (!pcmc->has_reserved_memory && 844 (machine->ram_slots || 845 (machine->maxram_size > machine->ram_size))) { 846 847 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 848 mc->name); 849 exit(EXIT_FAILURE); 850 } 851 852 /* always allocate the device memory information */ 853 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 854 855 /* initialize device memory address space */ 856 if (pcmc->has_reserved_memory && 857 (machine->ram_size < machine->maxram_size)) { 858 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 859 860 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 861 error_report("unsupported amount of memory slots: %"PRIu64, 862 machine->ram_slots); 863 exit(EXIT_FAILURE); 864 } 865 866 if (QEMU_ALIGN_UP(machine->maxram_size, 867 TARGET_PAGE_SIZE) != machine->maxram_size) { 868 error_report("maximum memory size must by aligned to multiple of " 869 "%d bytes", TARGET_PAGE_SIZE); 870 exit(EXIT_FAILURE); 871 } 872 873 if (pcms->sgx_epc.size != 0) { 874 machine->device_memory->base = sgx_epc_above_4g_end(&pcms->sgx_epc); 875 } else { 876 machine->device_memory->base = 877 0x100000000ULL + x86ms->above_4g_mem_size; 878 } 879 880 machine->device_memory->base = 881 ROUND_UP(machine->device_memory->base, 1 * GiB); 882 883 if (pcmc->enforce_aligned_dimm) { 884 /* size device region assuming 1G page max alignment per slot */ 885 device_mem_size += (1 * GiB) * machine->ram_slots; 886 } 887 888 if ((machine->device_memory->base + device_mem_size) < 889 device_mem_size) { 890 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 891 machine->maxram_size); 892 exit(EXIT_FAILURE); 893 } 894 895 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 896 "device-memory", device_mem_size); 897 memory_region_add_subregion(system_memory, machine->device_memory->base, 898 &machine->device_memory->mr); 899 } 900 901 /* Initialize PC system firmware */ 902 pc_system_firmware_init(pcms, rom_memory); 903 904 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 905 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 906 &error_fatal); 907 if (pcmc->pci_enabled) { 908 memory_region_set_readonly(option_rom_mr, true); 909 } 910 memory_region_add_subregion_overlap(rom_memory, 911 PC_ROM_MIN_VGA, 912 option_rom_mr, 913 1); 914 915 fw_cfg = fw_cfg_arch_create(machine, 916 x86ms->boot_cpus, x86ms->apic_id_limit); 917 918 rom_set_fw(fw_cfg); 919 920 if (pcmc->has_reserved_memory && machine->device_memory->base) { 921 uint64_t *val = g_malloc(sizeof(*val)); 922 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 923 uint64_t res_mem_end = machine->device_memory->base; 924 925 if (!pcmc->broken_reserved_end) { 926 res_mem_end += memory_region_size(&machine->device_memory->mr); 927 } 928 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 929 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 930 } 931 932 if (linux_boot) { 933 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 934 pcmc->pvh_enabled); 935 } 936 937 for (i = 0; i < nb_option_roms; i++) { 938 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 939 } 940 x86ms->fw_cfg = fw_cfg; 941 942 /* Init default IOAPIC address space */ 943 x86ms->ioapic_as = &address_space_memory; 944 945 /* Init ACPI memory hotplug IO base address */ 946 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 947 } 948 949 /* 950 * The 64bit pci hole starts after "above 4G RAM" and 951 * potentially the space reserved for memory hotplug. 952 */ 953 uint64_t pc_pci_hole64_start(void) 954 { 955 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 956 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 957 MachineState *ms = MACHINE(pcms); 958 X86MachineState *x86ms = X86_MACHINE(pcms); 959 uint64_t hole64_start = 0; 960 961 if (pcmc->has_reserved_memory && ms->device_memory->base) { 962 hole64_start = ms->device_memory->base; 963 if (!pcmc->broken_reserved_end) { 964 hole64_start += memory_region_size(&ms->device_memory->mr); 965 } 966 } else if (pcms->sgx_epc.size != 0) { 967 hole64_start = sgx_epc_above_4g_end(&pcms->sgx_epc); 968 } else { 969 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 970 } 971 972 return ROUND_UP(hole64_start, 1 * GiB); 973 } 974 975 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 976 { 977 DeviceState *dev = NULL; 978 979 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 980 if (pci_bus) { 981 PCIDevice *pcidev = pci_vga_init(pci_bus); 982 dev = pcidev ? &pcidev->qdev : NULL; 983 } else if (isa_bus) { 984 ISADevice *isadev = isa_vga_init(isa_bus); 985 dev = isadev ? DEVICE(isadev) : NULL; 986 } 987 rom_reset_order_override(); 988 return dev; 989 } 990 991 static const MemoryRegionOps ioport80_io_ops = { 992 .write = ioport80_write, 993 .read = ioport80_read, 994 .endianness = DEVICE_NATIVE_ENDIAN, 995 .impl = { 996 .min_access_size = 1, 997 .max_access_size = 1, 998 }, 999 }; 1000 1001 static const MemoryRegionOps ioportF0_io_ops = { 1002 .write = ioportF0_write, 1003 .read = ioportF0_read, 1004 .endianness = DEVICE_NATIVE_ENDIAN, 1005 .impl = { 1006 .min_access_size = 1, 1007 .max_access_size = 1, 1008 }, 1009 }; 1010 1011 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1012 { 1013 int i; 1014 DriveInfo *fd[MAX_FD]; 1015 qemu_irq *a20_line; 1016 ISADevice *fdc, *i8042, *port92, *vmmouse; 1017 1018 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1019 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1020 1021 for (i = 0; i < MAX_FD; i++) { 1022 fd[i] = drive_get(IF_FLOPPY, 0, i); 1023 create_fdctrl |= !!fd[i]; 1024 } 1025 if (create_fdctrl) { 1026 fdc = isa_new(TYPE_ISA_FDC); 1027 if (fdc) { 1028 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1029 isa_fdc_init_drives(fdc, fd); 1030 } 1031 } 1032 1033 i8042 = isa_create_simple(isa_bus, "i8042"); 1034 if (!no_vmport) { 1035 isa_create_simple(isa_bus, TYPE_VMPORT); 1036 vmmouse = isa_try_new("vmmouse"); 1037 } else { 1038 vmmouse = NULL; 1039 } 1040 if (vmmouse) { 1041 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1042 &error_abort); 1043 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1044 } 1045 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1046 1047 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1048 i8042_setup_a20_line(i8042, a20_line[0]); 1049 qdev_connect_gpio_out_named(DEVICE(port92), 1050 PORT92_A20_LINE, 0, a20_line[1]); 1051 g_free(a20_line); 1052 } 1053 1054 void pc_basic_device_init(struct PCMachineState *pcms, 1055 ISABus *isa_bus, qemu_irq *gsi, 1056 ISADevice **rtc_state, 1057 bool create_fdctrl, 1058 uint32_t hpet_irqs) 1059 { 1060 int i; 1061 DeviceState *hpet = NULL; 1062 int pit_isa_irq = 0; 1063 qemu_irq pit_alt_irq = NULL; 1064 qemu_irq rtc_irq = NULL; 1065 ISADevice *pit = NULL; 1066 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1067 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1068 1069 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1070 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1071 1072 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1073 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1074 1075 /* 1076 * Check if an HPET shall be created. 1077 * 1078 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1079 * when the HPET wants to take over. Thus we have to disable the latter. 1080 */ 1081 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1082 kvm_has_pit_state2())) { 1083 hpet = qdev_try_new(TYPE_HPET); 1084 if (!hpet) { 1085 error_report("couldn't create HPET device"); 1086 exit(1); 1087 } 1088 /* 1089 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1090 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1091 * IRQ2. 1092 */ 1093 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1094 HPET_INTCAP, NULL); 1095 if (!compat) { 1096 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1097 } 1098 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1099 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1100 1101 for (i = 0; i < GSI_NUM_PINS; i++) { 1102 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1103 } 1104 pit_isa_irq = -1; 1105 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1106 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1107 } 1108 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1109 1110 qemu_register_boot_set(pc_boot_set, *rtc_state); 1111 1112 if (!xen_enabled() && pcms->pit_enabled) { 1113 if (kvm_pit_in_kernel()) { 1114 pit = kvm_pit_init(isa_bus, 0x40); 1115 } else { 1116 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1117 } 1118 if (hpet) { 1119 /* connect PIT to output control line of the HPET */ 1120 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1121 } 1122 pcspk_init(pcms->pcspk, isa_bus, pit); 1123 } 1124 1125 i8257_dma_init(isa_bus, 0); 1126 1127 /* Super I/O */ 1128 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1129 } 1130 1131 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1132 { 1133 int i; 1134 1135 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1136 for (i = 0; i < nb_nics; i++) { 1137 NICInfo *nd = &nd_table[i]; 1138 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1139 1140 if (g_str_equal(model, "ne2k_isa")) { 1141 pc_init_ne2k_isa(isa_bus, nd); 1142 } else { 1143 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1144 } 1145 } 1146 rom_reset_order_override(); 1147 } 1148 1149 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1150 { 1151 qemu_irq *i8259; 1152 1153 if (kvm_pic_in_kernel()) { 1154 i8259 = kvm_i8259_init(isa_bus); 1155 } else if (xen_enabled()) { 1156 i8259 = xen_interrupt_controller_init(); 1157 } else { 1158 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1159 } 1160 1161 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1162 i8259_irqs[i] = i8259[i]; 1163 } 1164 1165 g_free(i8259); 1166 } 1167 1168 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1169 Error **errp) 1170 { 1171 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1172 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1173 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1174 const MachineState *ms = MACHINE(hotplug_dev); 1175 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1176 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1177 Error *local_err = NULL; 1178 1179 /* 1180 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1181 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1182 * addition to cover this case. 1183 */ 1184 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1185 error_setg(errp, 1186 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1187 return; 1188 } 1189 1190 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1191 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1192 return; 1193 } 1194 1195 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1196 if (local_err) { 1197 error_propagate(errp, local_err); 1198 return; 1199 } 1200 1201 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1202 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1203 } 1204 1205 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1206 DeviceState *dev, Error **errp) 1207 { 1208 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1209 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1210 MachineState *ms = MACHINE(hotplug_dev); 1211 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1212 1213 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1214 1215 if (is_nvdimm) { 1216 nvdimm_plug(ms->nvdimms_state); 1217 } 1218 1219 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1220 } 1221 1222 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1223 DeviceState *dev, Error **errp) 1224 { 1225 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1226 1227 /* 1228 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1229 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1230 * addition to cover this case. 1231 */ 1232 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1233 error_setg(errp, 1234 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1235 return; 1236 } 1237 1238 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1239 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1240 return; 1241 } 1242 1243 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1244 errp); 1245 } 1246 1247 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1248 DeviceState *dev, Error **errp) 1249 { 1250 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1251 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1252 Error *local_err = NULL; 1253 1254 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1255 if (local_err) { 1256 goto out; 1257 } 1258 1259 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1260 qdev_unrealize(dev); 1261 out: 1262 error_propagate(errp, local_err); 1263 } 1264 1265 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1266 DeviceState *dev, Error **errp) 1267 { 1268 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1269 Error *local_err = NULL; 1270 1271 if (!hotplug_dev2 && dev->hotplugged) { 1272 /* 1273 * Without a bus hotplug handler, we cannot control the plug/unplug 1274 * order. We should never reach this point when hotplugging on x86, 1275 * however, better add a safety net. 1276 */ 1277 error_setg(errp, "hotplug of virtio based memory devices not supported" 1278 " on this bus."); 1279 return; 1280 } 1281 /* 1282 * First, see if we can plug this memory device at all. If that 1283 * succeeds, branch of to the actual hotplug handler. 1284 */ 1285 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1286 &local_err); 1287 if (!local_err && hotplug_dev2) { 1288 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1289 } 1290 error_propagate(errp, local_err); 1291 } 1292 1293 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1294 DeviceState *dev, Error **errp) 1295 { 1296 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1297 Error *local_err = NULL; 1298 1299 /* 1300 * Plug the memory device first and then branch off to the actual 1301 * hotplug handler. If that one fails, we can easily undo the memory 1302 * device bits. 1303 */ 1304 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1305 if (hotplug_dev2) { 1306 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1307 if (local_err) { 1308 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1309 } 1310 } 1311 error_propagate(errp, local_err); 1312 } 1313 1314 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1315 DeviceState *dev, Error **errp) 1316 { 1317 /* We don't support hot unplug of virtio based memory devices */ 1318 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1319 } 1320 1321 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1322 DeviceState *dev, Error **errp) 1323 { 1324 /* We don't support hot unplug of virtio based memory devices */ 1325 } 1326 1327 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1328 DeviceState *dev, Error **errp) 1329 { 1330 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1331 pc_memory_pre_plug(hotplug_dev, dev, errp); 1332 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1333 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1334 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1335 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1336 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1337 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1338 /* Declare the APIC range as the reserved MSI region */ 1339 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1340 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1341 1342 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); 1343 object_property_set_str(OBJECT(dev), "reserved-regions[0]", 1344 resv_prop_str, errp); 1345 g_free(resv_prop_str); 1346 } 1347 1348 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1349 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1350 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1351 1352 if (pcms->iommu) { 1353 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1354 "for x86 yet."); 1355 return; 1356 } 1357 pcms->iommu = dev; 1358 } 1359 } 1360 1361 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1362 DeviceState *dev, Error **errp) 1363 { 1364 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1365 pc_memory_plug(hotplug_dev, dev, errp); 1366 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1367 x86_cpu_plug(hotplug_dev, dev, errp); 1368 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1369 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1370 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1371 } 1372 } 1373 1374 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1375 DeviceState *dev, Error **errp) 1376 { 1377 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1378 pc_memory_unplug_request(hotplug_dev, dev, errp); 1379 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1380 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1382 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1383 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1384 } else { 1385 error_setg(errp, "acpi: device unplug request for not supported device" 1386 " type: %s", object_get_typename(OBJECT(dev))); 1387 } 1388 } 1389 1390 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1391 DeviceState *dev, Error **errp) 1392 { 1393 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1394 pc_memory_unplug(hotplug_dev, dev, errp); 1395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1396 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1397 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1398 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1399 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1400 } else { 1401 error_setg(errp, "acpi: device unplug for not supported device" 1402 " type: %s", object_get_typename(OBJECT(dev))); 1403 } 1404 } 1405 1406 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1407 DeviceState *dev) 1408 { 1409 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1410 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1411 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1412 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI) || 1413 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1414 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1415 return HOTPLUG_HANDLER(machine); 1416 } 1417 1418 return NULL; 1419 } 1420 1421 static void 1422 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1423 const char *name, void *opaque, 1424 Error **errp) 1425 { 1426 MachineState *ms = MACHINE(obj); 1427 int64_t value = 0; 1428 1429 if (ms->device_memory) { 1430 value = memory_region_size(&ms->device_memory->mr); 1431 } 1432 1433 visit_type_int(v, name, &value, errp); 1434 } 1435 1436 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1437 void *opaque, Error **errp) 1438 { 1439 PCMachineState *pcms = PC_MACHINE(obj); 1440 OnOffAuto vmport = pcms->vmport; 1441 1442 visit_type_OnOffAuto(v, name, &vmport, errp); 1443 } 1444 1445 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1446 void *opaque, Error **errp) 1447 { 1448 PCMachineState *pcms = PC_MACHINE(obj); 1449 1450 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1451 } 1452 1453 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1454 { 1455 PCMachineState *pcms = PC_MACHINE(obj); 1456 1457 return pcms->smbus_enabled; 1458 } 1459 1460 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1461 { 1462 PCMachineState *pcms = PC_MACHINE(obj); 1463 1464 pcms->smbus_enabled = value; 1465 } 1466 1467 static bool pc_machine_get_sata(Object *obj, Error **errp) 1468 { 1469 PCMachineState *pcms = PC_MACHINE(obj); 1470 1471 return pcms->sata_enabled; 1472 } 1473 1474 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1475 { 1476 PCMachineState *pcms = PC_MACHINE(obj); 1477 1478 pcms->sata_enabled = value; 1479 } 1480 1481 static bool pc_machine_get_pit(Object *obj, Error **errp) 1482 { 1483 PCMachineState *pcms = PC_MACHINE(obj); 1484 1485 return pcms->pit_enabled; 1486 } 1487 1488 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1489 { 1490 PCMachineState *pcms = PC_MACHINE(obj); 1491 1492 pcms->pit_enabled = value; 1493 } 1494 1495 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1496 { 1497 PCMachineState *pcms = PC_MACHINE(obj); 1498 1499 return pcms->hpet_enabled; 1500 } 1501 1502 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1503 { 1504 PCMachineState *pcms = PC_MACHINE(obj); 1505 1506 pcms->hpet_enabled = value; 1507 } 1508 1509 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1510 { 1511 PCMachineState *pcms = PC_MACHINE(obj); 1512 1513 return pcms->default_bus_bypass_iommu; 1514 } 1515 1516 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1517 Error **errp) 1518 { 1519 PCMachineState *pcms = PC_MACHINE(obj); 1520 1521 pcms->default_bus_bypass_iommu = value; 1522 } 1523 1524 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1525 const char *name, void *opaque, 1526 Error **errp) 1527 { 1528 PCMachineState *pcms = PC_MACHINE(obj); 1529 uint64_t value = pcms->max_ram_below_4g; 1530 1531 visit_type_size(v, name, &value, errp); 1532 } 1533 1534 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1535 const char *name, void *opaque, 1536 Error **errp) 1537 { 1538 PCMachineState *pcms = PC_MACHINE(obj); 1539 uint64_t value; 1540 1541 if (!visit_type_size(v, name, &value, errp)) { 1542 return; 1543 } 1544 if (value > 4 * GiB) { 1545 error_setg(errp, 1546 "Machine option 'max-ram-below-4g=%"PRIu64 1547 "' expects size less than or equal to 4G", value); 1548 return; 1549 } 1550 1551 if (value < 1 * MiB) { 1552 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1553 "BIOS may not work with less than 1MiB", value); 1554 } 1555 1556 pcms->max_ram_below_4g = value; 1557 } 1558 1559 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1560 const char *name, void *opaque, 1561 Error **errp) 1562 { 1563 PCMachineState *pcms = PC_MACHINE(obj); 1564 uint64_t value = pcms->max_fw_size; 1565 1566 visit_type_size(v, name, &value, errp); 1567 } 1568 1569 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1570 const char *name, void *opaque, 1571 Error **errp) 1572 { 1573 PCMachineState *pcms = PC_MACHINE(obj); 1574 Error *error = NULL; 1575 uint64_t value; 1576 1577 visit_type_size(v, name, &value, &error); 1578 if (error) { 1579 error_propagate(errp, error); 1580 return; 1581 } 1582 1583 /* 1584 * We don't have a theoretically justifiable exact lower bound on the base 1585 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1586 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1587 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1588 * size. 1589 */ 1590 if (value > 16 * MiB) { 1591 error_setg(errp, 1592 "User specified max allowed firmware size %" PRIu64 " is " 1593 "greater than 16MiB. If combined firwmare size exceeds " 1594 "16MiB the system may not boot, or experience intermittent" 1595 "stability issues.", 1596 value); 1597 return; 1598 } 1599 1600 pcms->max_fw_size = value; 1601 } 1602 1603 1604 static void pc_machine_initfn(Object *obj) 1605 { 1606 PCMachineState *pcms = PC_MACHINE(obj); 1607 1608 #ifdef CONFIG_VMPORT 1609 pcms->vmport = ON_OFF_AUTO_AUTO; 1610 #else 1611 pcms->vmport = ON_OFF_AUTO_OFF; 1612 #endif /* CONFIG_VMPORT */ 1613 pcms->max_ram_below_4g = 0; /* use default */ 1614 /* acpi build is enabled by default if machine supports it */ 1615 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1616 pcms->smbus_enabled = true; 1617 pcms->sata_enabled = true; 1618 pcms->pit_enabled = true; 1619 pcms->max_fw_size = 8 * MiB; 1620 #ifdef CONFIG_HPET 1621 pcms->hpet_enabled = true; 1622 #endif 1623 pcms->default_bus_bypass_iommu = false; 1624 1625 pc_system_flash_create(pcms); 1626 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1627 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1628 OBJECT(pcms->pcspk), "audiodev"); 1629 } 1630 1631 static void pc_machine_reset(MachineState *machine) 1632 { 1633 CPUState *cs; 1634 X86CPU *cpu; 1635 1636 qemu_devices_reset(); 1637 1638 /* Reset APIC after devices have been reset to cancel 1639 * any changes that qemu_devices_reset() might have done. 1640 */ 1641 CPU_FOREACH(cs) { 1642 cpu = X86_CPU(cs); 1643 1644 if (cpu->apic_state) { 1645 device_legacy_reset(cpu->apic_state); 1646 } 1647 } 1648 } 1649 1650 static void pc_machine_wakeup(MachineState *machine) 1651 { 1652 cpu_synchronize_all_states(); 1653 pc_machine_reset(machine); 1654 cpu_synchronize_all_post_reset(); 1655 } 1656 1657 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1658 { 1659 X86IOMMUState *iommu = x86_iommu_get_default(); 1660 IntelIOMMUState *intel_iommu; 1661 1662 if (iommu && 1663 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1664 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1665 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1666 if (!intel_iommu->caching_mode) { 1667 error_setg(errp, "Device assignment is not allowed without " 1668 "enabling caching-mode=on for Intel IOMMU."); 1669 return false; 1670 } 1671 } 1672 1673 return true; 1674 } 1675 1676 static void pc_machine_class_init(ObjectClass *oc, void *data) 1677 { 1678 MachineClass *mc = MACHINE_CLASS(oc); 1679 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1680 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1681 1682 pcmc->pci_enabled = true; 1683 pcmc->has_acpi_build = true; 1684 pcmc->rsdp_in_ram = true; 1685 pcmc->smbios_defaults = true; 1686 pcmc->smbios_uuid_encoded = true; 1687 pcmc->gigabyte_align = true; 1688 pcmc->has_reserved_memory = true; 1689 pcmc->kvmclock_enabled = true; 1690 pcmc->enforce_aligned_dimm = true; 1691 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1692 * to be used at the moment, 32K should be enough for a while. */ 1693 pcmc->acpi_data_size = 0x20000 + 0x8000; 1694 pcmc->pvh_enabled = true; 1695 pcmc->kvmclock_create_always = true; 1696 assert(!mc->get_hotplug_handler); 1697 mc->get_hotplug_handler = pc_get_hotplug_handler; 1698 mc->hotplug_allowed = pc_hotplug_allowed; 1699 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1700 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1701 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1702 mc->auto_enable_numa_with_memhp = true; 1703 mc->auto_enable_numa_with_memdev = true; 1704 mc->has_hotpluggable_cpus = true; 1705 mc->default_boot_order = "cad"; 1706 mc->block_default_type = IF_IDE; 1707 mc->max_cpus = 255; 1708 mc->reset = pc_machine_reset; 1709 mc->wakeup = pc_machine_wakeup; 1710 hc->pre_plug = pc_machine_device_pre_plug_cb; 1711 hc->plug = pc_machine_device_plug_cb; 1712 hc->unplug_request = pc_machine_device_unplug_request_cb; 1713 hc->unplug = pc_machine_device_unplug_cb; 1714 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1715 mc->nvdimm_supported = true; 1716 mc->smp_props.dies_supported = true; 1717 mc->default_ram_id = "pc.ram"; 1718 1719 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1720 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1721 NULL, NULL); 1722 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1723 "Maximum ram below the 4G boundary (32bit boundary)"); 1724 1725 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1726 pc_machine_get_device_memory_region_size, NULL, 1727 NULL, NULL); 1728 1729 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1730 pc_machine_get_vmport, pc_machine_set_vmport, 1731 NULL, NULL); 1732 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1733 "Enable vmport (pc & q35)"); 1734 1735 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1736 pc_machine_get_smbus, pc_machine_set_smbus); 1737 1738 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1739 pc_machine_get_sata, pc_machine_set_sata); 1740 1741 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1742 pc_machine_get_pit, pc_machine_set_pit); 1743 1744 object_class_property_add_bool(oc, "hpet", 1745 pc_machine_get_hpet, pc_machine_set_hpet); 1746 1747 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1748 pc_machine_get_default_bus_bypass_iommu, 1749 pc_machine_set_default_bus_bypass_iommu); 1750 1751 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1752 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1753 NULL, NULL); 1754 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1755 "Maximum combined firmware size"); 1756 } 1757 1758 static const TypeInfo pc_machine_info = { 1759 .name = TYPE_PC_MACHINE, 1760 .parent = TYPE_X86_MACHINE, 1761 .abstract = true, 1762 .instance_size = sizeof(PCMachineState), 1763 .instance_init = pc_machine_initfn, 1764 .class_size = sizeof(PCMachineClass), 1765 .class_init = pc_machine_class_init, 1766 .interfaces = (InterfaceInfo[]) { 1767 { TYPE_HOTPLUG_HANDLER }, 1768 { } 1769 }, 1770 }; 1771 1772 static void pc_machine_register_types(void) 1773 { 1774 type_register_static(&pc_machine_info); 1775 } 1776 1777 type_init(pc_machine_register_types) 1778