1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/i386/pc.h" 26 #include "hw/char/serial.h" 27 #include "hw/i386/apic.h" 28 #include "hw/i386/topology.h" 29 #include "sysemu/cpus.h" 30 #include "hw/block/fdc.h" 31 #include "hw/ide.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bus.h" 34 #include "monitor/monitor.h" 35 #include "hw/nvram/fw_cfg.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/i386/smbios.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "multiboot.h" 41 #include "hw/timer/mc146818rtc.h" 42 #include "hw/timer/i8254.h" 43 #include "hw/audio/pcspk.h" 44 #include "hw/pci/msi.h" 45 #include "hw/sysbus.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/numa.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "kvm_i386.h" 51 #include "hw/xen/xen.h" 52 #include "sysemu/block-backend.h" 53 #include "hw/block/block.h" 54 #include "ui/qemu-spice.h" 55 #include "exec/memory.h" 56 #include "exec/address-spaces.h" 57 #include "sysemu/arch_init.h" 58 #include "qemu/bitmap.h" 59 #include "qemu/config-file.h" 60 #include "hw/acpi/acpi.h" 61 #include "hw/acpi/cpu_hotplug.h" 62 #include "hw/cpu/icc_bus.h" 63 #include "hw/boards.h" 64 #include "hw/pci/pci_host.h" 65 #include "acpi-build.h" 66 #include "hw/mem/pc-dimm.h" 67 #include "trace.h" 68 #include "qapi/visitor.h" 69 #include "qapi-visit.h" 70 71 /* debug PC/ISA interrupts */ 72 //#define DEBUG_IRQ 73 74 #ifdef DEBUG_IRQ 75 #define DPRINTF(fmt, ...) \ 76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 77 #else 78 #define DPRINTF(fmt, ...) 79 #endif 80 81 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables 82 * (128K) and other BIOS datastructures (less than 4K reported to be used at 83 * the moment, 32K should be enough for a while). */ 84 static unsigned acpi_data_size = 0x20000 + 0x8000; 85 void pc_set_legacy_acpi_data_size(void) 86 { 87 acpi_data_size = 0x10000; 88 } 89 90 #define BIOS_CFG_IOPORT 0x510 91 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) 92 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) 93 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) 94 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) 95 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) 96 97 #define E820_NR_ENTRIES 16 98 99 struct e820_entry { 100 uint64_t address; 101 uint64_t length; 102 uint32_t type; 103 } QEMU_PACKED __attribute((__aligned__(4))); 104 105 struct e820_table { 106 uint32_t count; 107 struct e820_entry entry[E820_NR_ENTRIES]; 108 } QEMU_PACKED __attribute((__aligned__(4))); 109 110 static struct e820_table e820_reserve; 111 static struct e820_entry *e820_table; 112 static unsigned e820_entries; 113 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 114 115 void gsi_handler(void *opaque, int n, int level) 116 { 117 GSIState *s = opaque; 118 119 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 120 if (n < ISA_NUM_IRQS) { 121 qemu_set_irq(s->i8259_irq[n], level); 122 } 123 qemu_set_irq(s->ioapic_irq[n], level); 124 } 125 126 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 127 unsigned size) 128 { 129 } 130 131 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 132 { 133 return 0xffffffffffffffffULL; 134 } 135 136 /* MSDOS compatibility mode FPU exception support */ 137 static qemu_irq ferr_irq; 138 139 void pc_register_ferr_irq(qemu_irq irq) 140 { 141 ferr_irq = irq; 142 } 143 144 /* XXX: add IGNNE support */ 145 void cpu_set_ferr(CPUX86State *s) 146 { 147 qemu_irq_raise(ferr_irq); 148 } 149 150 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 151 unsigned size) 152 { 153 qemu_irq_lower(ferr_irq); 154 } 155 156 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 157 { 158 return 0xffffffffffffffffULL; 159 } 160 161 /* TSC handling */ 162 uint64_t cpu_get_tsc(CPUX86State *env) 163 { 164 return cpu_get_ticks(); 165 } 166 167 /* SMM support */ 168 169 static cpu_set_smm_t smm_set; 170 static void *smm_arg; 171 172 void cpu_smm_register(cpu_set_smm_t callback, void *arg) 173 { 174 assert(smm_set == NULL); 175 assert(smm_arg == NULL); 176 smm_set = callback; 177 smm_arg = arg; 178 } 179 180 void cpu_smm_update(CPUX86State *env) 181 { 182 if (smm_set && smm_arg && CPU(x86_env_get_cpu(env)) == first_cpu) { 183 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); 184 } 185 } 186 187 188 /* IRQ handling */ 189 int cpu_get_pic_interrupt(CPUX86State *env) 190 { 191 X86CPU *cpu = x86_env_get_cpu(env); 192 int intno; 193 194 intno = apic_get_interrupt(cpu->apic_state); 195 if (intno >= 0) { 196 return intno; 197 } 198 /* read the irq from the PIC */ 199 if (!apic_accept_pic_intr(cpu->apic_state)) { 200 return -1; 201 } 202 203 intno = pic_read_irq(isa_pic); 204 return intno; 205 } 206 207 static void pic_irq_request(void *opaque, int irq, int level) 208 { 209 CPUState *cs = first_cpu; 210 X86CPU *cpu = X86_CPU(cs); 211 212 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 213 if (cpu->apic_state) { 214 CPU_FOREACH(cs) { 215 cpu = X86_CPU(cs); 216 if (apic_accept_pic_intr(cpu->apic_state)) { 217 apic_deliver_pic_intr(cpu->apic_state, level); 218 } 219 } 220 } else { 221 if (level) { 222 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 223 } else { 224 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 225 } 226 } 227 } 228 229 /* PC cmos mappings */ 230 231 #define REG_EQUIPMENT_BYTE 0x14 232 233 static int cmos_get_fd_drive_type(FDriveType fd0) 234 { 235 int val; 236 237 switch (fd0) { 238 case FDRIVE_DRV_144: 239 /* 1.44 Mb 3"5 drive */ 240 val = 4; 241 break; 242 case FDRIVE_DRV_288: 243 /* 2.88 Mb 3"5 drive */ 244 val = 5; 245 break; 246 case FDRIVE_DRV_120: 247 /* 1.2 Mb 5"5 drive */ 248 val = 2; 249 break; 250 case FDRIVE_DRV_NONE: 251 default: 252 val = 0; 253 break; 254 } 255 return val; 256 } 257 258 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 259 int16_t cylinders, int8_t heads, int8_t sectors) 260 { 261 rtc_set_memory(s, type_ofs, 47); 262 rtc_set_memory(s, info_ofs, cylinders); 263 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 264 rtc_set_memory(s, info_ofs + 2, heads); 265 rtc_set_memory(s, info_ofs + 3, 0xff); 266 rtc_set_memory(s, info_ofs + 4, 0xff); 267 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 268 rtc_set_memory(s, info_ofs + 6, cylinders); 269 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 270 rtc_set_memory(s, info_ofs + 8, sectors); 271 } 272 273 /* convert boot_device letter to something recognizable by the bios */ 274 static int boot_device2nibble(char boot_device) 275 { 276 switch(boot_device) { 277 case 'a': 278 case 'b': 279 return 0x01; /* floppy boot */ 280 case 'c': 281 return 0x02; /* hard drive boot */ 282 case 'd': 283 return 0x03; /* CD-ROM boot */ 284 case 'n': 285 return 0x04; /* Network boot */ 286 } 287 return 0; 288 } 289 290 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 291 { 292 #define PC_MAX_BOOT_DEVICES 3 293 int nbds, bds[3] = { 0, }; 294 int i; 295 296 nbds = strlen(boot_device); 297 if (nbds > PC_MAX_BOOT_DEVICES) { 298 error_setg(errp, "Too many boot devices for PC"); 299 return; 300 } 301 for (i = 0; i < nbds; i++) { 302 bds[i] = boot_device2nibble(boot_device[i]); 303 if (bds[i] == 0) { 304 error_setg(errp, "Invalid boot device for PC: '%c'", 305 boot_device[i]); 306 return; 307 } 308 } 309 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 310 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 311 } 312 313 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 314 { 315 set_boot_dev(opaque, boot_device, errp); 316 } 317 318 typedef struct pc_cmos_init_late_arg { 319 ISADevice *rtc_state; 320 BusState *idebus[2]; 321 } pc_cmos_init_late_arg; 322 323 static void pc_cmos_init_late(void *opaque) 324 { 325 pc_cmos_init_late_arg *arg = opaque; 326 ISADevice *s = arg->rtc_state; 327 int16_t cylinders; 328 int8_t heads, sectors; 329 int val; 330 int i, trans; 331 332 val = 0; 333 if (ide_get_geometry(arg->idebus[0], 0, 334 &cylinders, &heads, §ors) >= 0) { 335 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 336 val |= 0xf0; 337 } 338 if (ide_get_geometry(arg->idebus[0], 1, 339 &cylinders, &heads, §ors) >= 0) { 340 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 341 val |= 0x0f; 342 } 343 rtc_set_memory(s, 0x12, val); 344 345 val = 0; 346 for (i = 0; i < 4; i++) { 347 /* NOTE: ide_get_geometry() returns the physical 348 geometry. It is always such that: 1 <= sects <= 63, 1 349 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 350 geometry can be different if a translation is done. */ 351 if (ide_get_geometry(arg->idebus[i / 2], i % 2, 352 &cylinders, &heads, §ors) >= 0) { 353 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 354 assert((trans & ~3) == 0); 355 val |= trans << (i * 2); 356 } 357 } 358 rtc_set_memory(s, 0x39, val); 359 360 qemu_unregister_reset(pc_cmos_init_late, opaque); 361 } 362 363 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 364 const char *boot_device, MachineState *machine, 365 ISADevice *floppy, BusState *idebus0, BusState *idebus1, 366 ISADevice *s) 367 { 368 int val, nb, i; 369 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE }; 370 static pc_cmos_init_late_arg arg; 371 PCMachineState *pc_machine = PC_MACHINE(machine); 372 Error *local_err = NULL; 373 374 /* various important CMOS locations needed by PC/Bochs bios */ 375 376 /* memory size */ 377 /* base memory (first MiB) */ 378 val = MIN(ram_size / 1024, 640); 379 rtc_set_memory(s, 0x15, val); 380 rtc_set_memory(s, 0x16, val >> 8); 381 /* extended memory (next 64MiB) */ 382 if (ram_size > 1024 * 1024) { 383 val = (ram_size - 1024 * 1024) / 1024; 384 } else { 385 val = 0; 386 } 387 if (val > 65535) 388 val = 65535; 389 rtc_set_memory(s, 0x17, val); 390 rtc_set_memory(s, 0x18, val >> 8); 391 rtc_set_memory(s, 0x30, val); 392 rtc_set_memory(s, 0x31, val >> 8); 393 /* memory between 16MiB and 4GiB */ 394 if (ram_size > 16 * 1024 * 1024) { 395 val = (ram_size - 16 * 1024 * 1024) / 65536; 396 } else { 397 val = 0; 398 } 399 if (val > 65535) 400 val = 65535; 401 rtc_set_memory(s, 0x34, val); 402 rtc_set_memory(s, 0x35, val >> 8); 403 /* memory above 4GiB */ 404 val = above_4g_mem_size / 65536; 405 rtc_set_memory(s, 0x5b, val); 406 rtc_set_memory(s, 0x5c, val >> 8); 407 rtc_set_memory(s, 0x5d, val >> 16); 408 409 /* set the number of CPU */ 410 rtc_set_memory(s, 0x5f, smp_cpus - 1); 411 412 object_property_add_link(OBJECT(machine), "rtc_state", 413 TYPE_ISA_DEVICE, 414 (Object **)&pc_machine->rtc, 415 object_property_allow_set_link, 416 OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort); 417 object_property_set_link(OBJECT(machine), OBJECT(s), 418 "rtc_state", &error_abort); 419 420 set_boot_dev(s, boot_device, &local_err); 421 if (local_err) { 422 error_report_err(local_err); 423 exit(1); 424 } 425 426 /* floppy type */ 427 if (floppy) { 428 for (i = 0; i < 2; i++) { 429 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 430 } 431 } 432 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 433 cmos_get_fd_drive_type(fd_type[1]); 434 rtc_set_memory(s, 0x10, val); 435 436 val = 0; 437 nb = 0; 438 if (fd_type[0] < FDRIVE_DRV_NONE) { 439 nb++; 440 } 441 if (fd_type[1] < FDRIVE_DRV_NONE) { 442 nb++; 443 } 444 switch (nb) { 445 case 0: 446 break; 447 case 1: 448 val |= 0x01; /* 1 drive, ready for boot */ 449 break; 450 case 2: 451 val |= 0x41; /* 2 drives, ready for boot */ 452 break; 453 } 454 val |= 0x02; /* FPU is there */ 455 val |= 0x04; /* PS/2 mouse installed */ 456 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 457 458 /* hard drives */ 459 arg.rtc_state = s; 460 arg.idebus[0] = idebus0; 461 arg.idebus[1] = idebus1; 462 qemu_register_reset(pc_cmos_init_late, &arg); 463 } 464 465 #define TYPE_PORT92 "port92" 466 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 467 468 /* port 92 stuff: could be split off */ 469 typedef struct Port92State { 470 ISADevice parent_obj; 471 472 MemoryRegion io; 473 uint8_t outport; 474 qemu_irq *a20_out; 475 } Port92State; 476 477 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 478 unsigned size) 479 { 480 Port92State *s = opaque; 481 int oldval = s->outport; 482 483 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 484 s->outport = val; 485 qemu_set_irq(*s->a20_out, (val >> 1) & 1); 486 if ((val & 1) && !(oldval & 1)) { 487 qemu_system_reset_request(); 488 } 489 } 490 491 static uint64_t port92_read(void *opaque, hwaddr addr, 492 unsigned size) 493 { 494 Port92State *s = opaque; 495 uint32_t ret; 496 497 ret = s->outport; 498 DPRINTF("port92: read 0x%02x\n", ret); 499 return ret; 500 } 501 502 static void port92_init(ISADevice *dev, qemu_irq *a20_out) 503 { 504 Port92State *s = PORT92(dev); 505 506 s->a20_out = a20_out; 507 } 508 509 static const VMStateDescription vmstate_port92_isa = { 510 .name = "port92", 511 .version_id = 1, 512 .minimum_version_id = 1, 513 .fields = (VMStateField[]) { 514 VMSTATE_UINT8(outport, Port92State), 515 VMSTATE_END_OF_LIST() 516 } 517 }; 518 519 static void port92_reset(DeviceState *d) 520 { 521 Port92State *s = PORT92(d); 522 523 s->outport &= ~1; 524 } 525 526 static const MemoryRegionOps port92_ops = { 527 .read = port92_read, 528 .write = port92_write, 529 .impl = { 530 .min_access_size = 1, 531 .max_access_size = 1, 532 }, 533 .endianness = DEVICE_LITTLE_ENDIAN, 534 }; 535 536 static void port92_initfn(Object *obj) 537 { 538 Port92State *s = PORT92(obj); 539 540 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 541 542 s->outport = 0; 543 } 544 545 static void port92_realizefn(DeviceState *dev, Error **errp) 546 { 547 ISADevice *isadev = ISA_DEVICE(dev); 548 Port92State *s = PORT92(dev); 549 550 isa_register_ioport(isadev, &s->io, 0x92); 551 } 552 553 static void port92_class_initfn(ObjectClass *klass, void *data) 554 { 555 DeviceClass *dc = DEVICE_CLASS(klass); 556 557 dc->realize = port92_realizefn; 558 dc->reset = port92_reset; 559 dc->vmsd = &vmstate_port92_isa; 560 /* 561 * Reason: unlike ordinary ISA devices, this one needs additional 562 * wiring: its A20 output line needs to be wired up by 563 * port92_init(). 564 */ 565 dc->cannot_instantiate_with_device_add_yet = true; 566 } 567 568 static const TypeInfo port92_info = { 569 .name = TYPE_PORT92, 570 .parent = TYPE_ISA_DEVICE, 571 .instance_size = sizeof(Port92State), 572 .instance_init = port92_initfn, 573 .class_init = port92_class_initfn, 574 }; 575 576 static void port92_register_types(void) 577 { 578 type_register_static(&port92_info); 579 } 580 581 type_init(port92_register_types) 582 583 static void handle_a20_line_change(void *opaque, int irq, int level) 584 { 585 X86CPU *cpu = opaque; 586 587 /* XXX: send to all CPUs ? */ 588 /* XXX: add logic to handle multiple A20 line sources */ 589 x86_cpu_set_a20(cpu, level); 590 } 591 592 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 593 { 594 int index = le32_to_cpu(e820_reserve.count); 595 struct e820_entry *entry; 596 597 if (type != E820_RAM) { 598 /* old FW_CFG_E820_TABLE entry -- reservations only */ 599 if (index >= E820_NR_ENTRIES) { 600 return -EBUSY; 601 } 602 entry = &e820_reserve.entry[index++]; 603 604 entry->address = cpu_to_le64(address); 605 entry->length = cpu_to_le64(length); 606 entry->type = cpu_to_le32(type); 607 608 e820_reserve.count = cpu_to_le32(index); 609 } 610 611 /* new "etc/e820" file -- include ram too */ 612 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 613 e820_table[e820_entries].address = cpu_to_le64(address); 614 e820_table[e820_entries].length = cpu_to_le64(length); 615 e820_table[e820_entries].type = cpu_to_le32(type); 616 e820_entries++; 617 618 return e820_entries; 619 } 620 621 int e820_get_num_entries(void) 622 { 623 return e820_entries; 624 } 625 626 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 627 { 628 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 629 *address = le64_to_cpu(e820_table[idx].address); 630 *length = le64_to_cpu(e820_table[idx].length); 631 return true; 632 } 633 return false; 634 } 635 636 /* Enables contiguous-apic-ID mode, for compatibility */ 637 static bool compat_apic_id_mode; 638 639 void enable_compat_apic_id_mode(void) 640 { 641 compat_apic_id_mode = true; 642 } 643 644 /* Calculates initial APIC ID for a specific CPU index 645 * 646 * Currently we need to be able to calculate the APIC ID from the CPU index 647 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 648 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 649 * all CPUs up to max_cpus. 650 */ 651 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 652 { 653 uint32_t correct_id; 654 static bool warned; 655 656 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 657 if (compat_apic_id_mode) { 658 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 659 error_report("APIC IDs set in compatibility mode, " 660 "CPU topology won't match the configuration"); 661 warned = true; 662 } 663 return cpu_index; 664 } else { 665 return correct_id; 666 } 667 } 668 669 /* Calculates the limit to CPU APIC ID values 670 * 671 * This function returns the limit for the APIC ID value, so that all 672 * CPU APIC IDs are < pc_apic_id_limit(). 673 * 674 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 675 */ 676 static unsigned int pc_apic_id_limit(unsigned int max_cpus) 677 { 678 return x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 679 } 680 681 static FWCfgState *bochs_bios_init(void) 682 { 683 FWCfgState *fw_cfg; 684 uint8_t *smbios_tables, *smbios_anchor; 685 size_t smbios_tables_len, smbios_anchor_len; 686 uint64_t *numa_fw_cfg; 687 int i, j; 688 unsigned int apic_id_limit = pc_apic_id_limit(max_cpus); 689 690 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 691 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 692 * 693 * SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug 694 * QEMU<->SeaBIOS interface is not based on the "CPU index", but on the APIC 695 * ID of hotplugged CPUs[1]. This means that FW_CFG_MAX_CPUS is not the 696 * "maximum number of CPUs", but the "limit to the APIC ID values SeaBIOS 697 * may see". 698 * 699 * So, this means we must not use max_cpus, here, but the maximum possible 700 * APIC ID value, plus one. 701 * 702 * [1] The only kind of "CPU identifier" used between SeaBIOS and QEMU is 703 * the APIC ID, not the "CPU index" 704 */ 705 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)apic_id_limit); 706 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 707 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 708 acpi_tables, acpi_tables_len); 709 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 710 711 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 712 if (smbios_tables) { 713 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, 714 smbios_tables, smbios_tables_len); 715 } 716 717 smbios_get_tables(&smbios_tables, &smbios_tables_len, 718 &smbios_anchor, &smbios_anchor_len); 719 if (smbios_anchor) { 720 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", 721 smbios_tables, smbios_tables_len); 722 fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", 723 smbios_anchor, smbios_anchor_len); 724 } 725 726 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 727 &e820_reserve, sizeof(e820_reserve)); 728 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 729 sizeof(struct e820_entry) * e820_entries); 730 731 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 732 /* allocate memory for the NUMA channel: one (64bit) word for the number 733 * of nodes, one word for each VCPU->node and one word for each node to 734 * hold the amount of memory. 735 */ 736 numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); 737 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 738 for (i = 0; i < max_cpus; i++) { 739 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 740 assert(apic_id < apic_id_limit); 741 for (j = 0; j < nb_numa_nodes; j++) { 742 if (test_bit(i, numa_info[j].node_cpu)) { 743 numa_fw_cfg[apic_id + 1] = cpu_to_le64(j); 744 break; 745 } 746 } 747 } 748 for (i = 0; i < nb_numa_nodes; i++) { 749 numa_fw_cfg[apic_id_limit + 1 + i] = cpu_to_le64(numa_info[i].node_mem); 750 } 751 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 752 (1 + apic_id_limit + nb_numa_nodes) * 753 sizeof(*numa_fw_cfg)); 754 755 return fw_cfg; 756 } 757 758 static long get_file_size(FILE *f) 759 { 760 long where, size; 761 762 /* XXX: on Unix systems, using fstat() probably makes more sense */ 763 764 where = ftell(f); 765 fseek(f, 0, SEEK_END); 766 size = ftell(f); 767 fseek(f, where, SEEK_SET); 768 769 return size; 770 } 771 772 static void load_linux(FWCfgState *fw_cfg, 773 const char *kernel_filename, 774 const char *initrd_filename, 775 const char *kernel_cmdline, 776 hwaddr max_ram_size) 777 { 778 uint16_t protocol; 779 int setup_size, kernel_size, initrd_size = 0, cmdline_size; 780 uint32_t initrd_max; 781 uint8_t header[8192], *setup, *kernel, *initrd_data; 782 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 783 FILE *f; 784 char *vmode; 785 786 /* Align to 16 bytes as a paranoia measure */ 787 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 788 789 /* load the kernel header */ 790 f = fopen(kernel_filename, "rb"); 791 if (!f || !(kernel_size = get_file_size(f)) || 792 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 793 MIN(ARRAY_SIZE(header), kernel_size)) { 794 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 795 kernel_filename, strerror(errno)); 796 exit(1); 797 } 798 799 /* kernel protocol version */ 800 #if 0 801 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 802 #endif 803 if (ldl_p(header+0x202) == 0x53726448) { 804 protocol = lduw_p(header+0x206); 805 } else { 806 /* This looks like a multiboot kernel. If it is, let's stop 807 treating it like a Linux kernel. */ 808 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 809 kernel_cmdline, kernel_size, header)) { 810 return; 811 } 812 protocol = 0; 813 } 814 815 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 816 /* Low kernel */ 817 real_addr = 0x90000; 818 cmdline_addr = 0x9a000 - cmdline_size; 819 prot_addr = 0x10000; 820 } else if (protocol < 0x202) { 821 /* High but ancient kernel */ 822 real_addr = 0x90000; 823 cmdline_addr = 0x9a000 - cmdline_size; 824 prot_addr = 0x100000; 825 } else { 826 /* High and recent kernel */ 827 real_addr = 0x10000; 828 cmdline_addr = 0x20000; 829 prot_addr = 0x100000; 830 } 831 832 #if 0 833 fprintf(stderr, 834 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 835 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 836 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 837 real_addr, 838 cmdline_addr, 839 prot_addr); 840 #endif 841 842 /* highest address for loading the initrd */ 843 if (protocol >= 0x203) { 844 initrd_max = ldl_p(header+0x22c); 845 } else { 846 initrd_max = 0x37ffffff; 847 } 848 849 if (initrd_max >= max_ram_size - acpi_data_size) { 850 initrd_max = max_ram_size - acpi_data_size - 1; 851 } 852 853 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 854 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 855 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 856 857 if (protocol >= 0x202) { 858 stl_p(header+0x228, cmdline_addr); 859 } else { 860 stw_p(header+0x20, 0xA33F); 861 stw_p(header+0x22, cmdline_addr-real_addr); 862 } 863 864 /* handle vga= parameter */ 865 vmode = strstr(kernel_cmdline, "vga="); 866 if (vmode) { 867 unsigned int video_mode; 868 /* skip "vga=" */ 869 vmode += 4; 870 if (!strncmp(vmode, "normal", 6)) { 871 video_mode = 0xffff; 872 } else if (!strncmp(vmode, "ext", 3)) { 873 video_mode = 0xfffe; 874 } else if (!strncmp(vmode, "ask", 3)) { 875 video_mode = 0xfffd; 876 } else { 877 video_mode = strtol(vmode, NULL, 0); 878 } 879 stw_p(header+0x1fa, video_mode); 880 } 881 882 /* loader type */ 883 /* High nybble = B reserved for QEMU; low nybble is revision number. 884 If this code is substantially changed, you may want to consider 885 incrementing the revision. */ 886 if (protocol >= 0x200) { 887 header[0x210] = 0xB0; 888 } 889 /* heap */ 890 if (protocol >= 0x201) { 891 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 892 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 893 } 894 895 /* load initrd */ 896 if (initrd_filename) { 897 if (protocol < 0x200) { 898 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 899 exit(1); 900 } 901 902 initrd_size = get_image_size(initrd_filename); 903 if (initrd_size < 0) { 904 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 905 initrd_filename, strerror(errno)); 906 exit(1); 907 } 908 909 initrd_addr = (initrd_max-initrd_size) & ~4095; 910 911 initrd_data = g_malloc(initrd_size); 912 load_image(initrd_filename, initrd_data); 913 914 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 915 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 916 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 917 918 stl_p(header+0x218, initrd_addr); 919 stl_p(header+0x21c, initrd_size); 920 } 921 922 /* load kernel and setup */ 923 setup_size = header[0x1f1]; 924 if (setup_size == 0) { 925 setup_size = 4; 926 } 927 setup_size = (setup_size+1)*512; 928 kernel_size -= setup_size; 929 930 setup = g_malloc(setup_size); 931 kernel = g_malloc(kernel_size); 932 fseek(f, 0, SEEK_SET); 933 if (fread(setup, 1, setup_size, f) != setup_size) { 934 fprintf(stderr, "fread() failed\n"); 935 exit(1); 936 } 937 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 938 fprintf(stderr, "fread() failed\n"); 939 exit(1); 940 } 941 fclose(f); 942 memcpy(setup, header, MIN(sizeof(header), setup_size)); 943 944 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 945 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 946 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 947 948 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 949 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 950 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 951 952 option_rom[nb_option_roms].name = "linuxboot.bin"; 953 option_rom[nb_option_roms].bootindex = 0; 954 nb_option_roms++; 955 } 956 957 #define NE2000_NB_MAX 6 958 959 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 960 0x280, 0x380 }; 961 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 962 963 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 964 { 965 static int nb_ne2k = 0; 966 967 if (nb_ne2k == NE2000_NB_MAX) 968 return; 969 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 970 ne2000_irq[nb_ne2k], nd); 971 nb_ne2k++; 972 } 973 974 DeviceState *cpu_get_current_apic(void) 975 { 976 if (current_cpu) { 977 X86CPU *cpu = X86_CPU(current_cpu); 978 return cpu->apic_state; 979 } else { 980 return NULL; 981 } 982 } 983 984 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 985 { 986 X86CPU *cpu = opaque; 987 988 if (level) { 989 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 990 } 991 } 992 993 static X86CPU *pc_new_cpu(const char *cpu_model, int64_t apic_id, 994 DeviceState *icc_bridge, Error **errp) 995 { 996 X86CPU *cpu = NULL; 997 Error *local_err = NULL; 998 999 if (icc_bridge == NULL) { 1000 error_setg(&local_err, "Invalid icc-bridge value"); 1001 goto out; 1002 } 1003 1004 cpu = cpu_x86_create(cpu_model, &local_err); 1005 if (local_err != NULL) { 1006 goto out; 1007 } 1008 1009 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); 1010 object_unref(OBJECT(cpu)); 1011 1012 object_property_set_int(OBJECT(cpu), apic_id, "apic-id", &local_err); 1013 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 1014 1015 out: 1016 if (local_err) { 1017 error_propagate(errp, local_err); 1018 object_unref(OBJECT(cpu)); 1019 cpu = NULL; 1020 } 1021 return cpu; 1022 } 1023 1024 static const char *current_cpu_model; 1025 1026 void pc_hot_add_cpu(const int64_t id, Error **errp) 1027 { 1028 DeviceState *icc_bridge; 1029 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1030 1031 if (id < 0) { 1032 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1033 return; 1034 } 1035 1036 if (cpu_exists(apic_id)) { 1037 error_setg(errp, "Unable to add CPU: %" PRIi64 1038 ", it already exists", id); 1039 return; 1040 } 1041 1042 if (id >= max_cpus) { 1043 error_setg(errp, "Unable to add CPU: %" PRIi64 1044 ", max allowed: %d", id, max_cpus - 1); 1045 return; 1046 } 1047 1048 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1049 error_setg(errp, "Unable to add CPU: %" PRIi64 1050 ", resulting APIC ID (%" PRIi64 ") is too large", 1051 id, apic_id); 1052 return; 1053 } 1054 1055 icc_bridge = DEVICE(object_resolve_path_type("icc-bridge", 1056 TYPE_ICC_BRIDGE, NULL)); 1057 pc_new_cpu(current_cpu_model, apic_id, icc_bridge, errp); 1058 } 1059 1060 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) 1061 { 1062 int i; 1063 X86CPU *cpu = NULL; 1064 Error *error = NULL; 1065 unsigned long apic_id_limit; 1066 1067 /* init CPUs */ 1068 if (cpu_model == NULL) { 1069 #ifdef TARGET_X86_64 1070 cpu_model = "qemu64"; 1071 #else 1072 cpu_model = "qemu32"; 1073 #endif 1074 } 1075 current_cpu_model = cpu_model; 1076 1077 apic_id_limit = pc_apic_id_limit(max_cpus); 1078 if (apic_id_limit > ACPI_CPU_HOTPLUG_ID_LIMIT) { 1079 error_report("max_cpus is too large. APIC ID of last CPU is %lu", 1080 apic_id_limit - 1); 1081 exit(1); 1082 } 1083 1084 for (i = 0; i < smp_cpus; i++) { 1085 cpu = pc_new_cpu(cpu_model, x86_cpu_apic_id_from_index(i), 1086 icc_bridge, &error); 1087 if (error) { 1088 error_report_err(error); 1089 exit(1); 1090 } 1091 } 1092 1093 /* map APIC MMIO area if CPU has APIC */ 1094 if (cpu && cpu->apic_state) { 1095 /* XXX: what if the base changes? */ 1096 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(icc_bridge), 0, 1097 APIC_DEFAULT_ADDRESS, 0x1000); 1098 } 1099 1100 /* tell smbios about cpuid version and features */ 1101 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 1102 } 1103 1104 /* pci-info ROM file. Little endian format */ 1105 typedef struct PcRomPciInfo { 1106 uint64_t w32_min; 1107 uint64_t w32_max; 1108 uint64_t w64_min; 1109 uint64_t w64_max; 1110 } PcRomPciInfo; 1111 1112 typedef struct PcGuestInfoState { 1113 PcGuestInfo info; 1114 Notifier machine_done; 1115 } PcGuestInfoState; 1116 1117 static 1118 void pc_guest_info_machine_done(Notifier *notifier, void *data) 1119 { 1120 PcGuestInfoState *guest_info_state = container_of(notifier, 1121 PcGuestInfoState, 1122 machine_done); 1123 PCIBus *bus = find_i440fx(); 1124 1125 if (bus) { 1126 int extra_hosts = 0; 1127 1128 QLIST_FOREACH(bus, &bus->child, sibling) { 1129 /* look for expander root buses */ 1130 if (pci_bus_is_root(bus)) { 1131 extra_hosts++; 1132 } 1133 } 1134 if (extra_hosts && guest_info_state->info.fw_cfg) { 1135 uint64_t *val = g_malloc(sizeof(*val)); 1136 *val = cpu_to_le64(extra_hosts); 1137 fw_cfg_add_file(guest_info_state->info.fw_cfg, 1138 "etc/extra-pci-roots", val, sizeof(*val)); 1139 } 1140 } 1141 1142 acpi_setup(&guest_info_state->info); 1143 } 1144 1145 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 1146 ram_addr_t above_4g_mem_size) 1147 { 1148 PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state); 1149 PcGuestInfo *guest_info = &guest_info_state->info; 1150 int i, j; 1151 1152 guest_info->ram_size_below_4g = below_4g_mem_size; 1153 guest_info->ram_size = below_4g_mem_size + above_4g_mem_size; 1154 guest_info->apic_id_limit = pc_apic_id_limit(max_cpus); 1155 guest_info->apic_xrupt_override = kvm_allows_irq0_override(); 1156 guest_info->numa_nodes = nb_numa_nodes; 1157 guest_info->node_mem = g_malloc0(guest_info->numa_nodes * 1158 sizeof *guest_info->node_mem); 1159 for (i = 0; i < nb_numa_nodes; i++) { 1160 guest_info->node_mem[i] = numa_info[i].node_mem; 1161 } 1162 1163 guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit * 1164 sizeof *guest_info->node_cpu); 1165 1166 for (i = 0; i < max_cpus; i++) { 1167 unsigned int apic_id = x86_cpu_apic_id_from_index(i); 1168 assert(apic_id < guest_info->apic_id_limit); 1169 for (j = 0; j < nb_numa_nodes; j++) { 1170 if (test_bit(i, numa_info[j].node_cpu)) { 1171 guest_info->node_cpu[apic_id] = j; 1172 break; 1173 } 1174 } 1175 } 1176 1177 guest_info_state->machine_done.notify = pc_guest_info_machine_done; 1178 qemu_add_machine_init_done_notifier(&guest_info_state->machine_done); 1179 return guest_info; 1180 } 1181 1182 /* setup pci memory address space mapping into system address space */ 1183 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1184 MemoryRegion *pci_address_space) 1185 { 1186 /* Set to lower priority than RAM */ 1187 memory_region_add_subregion_overlap(system_memory, 0x0, 1188 pci_address_space, -1); 1189 } 1190 1191 void pc_acpi_init(const char *default_dsdt) 1192 { 1193 char *filename; 1194 1195 if (acpi_tables != NULL) { 1196 /* manually set via -acpitable, leave it alone */ 1197 return; 1198 } 1199 1200 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, default_dsdt); 1201 if (filename == NULL) { 1202 fprintf(stderr, "WARNING: failed to find %s\n", default_dsdt); 1203 } else { 1204 QemuOpts *opts = qemu_opts_create(qemu_find_opts("acpi"), NULL, 0, 1205 &error_abort); 1206 Error *err = NULL; 1207 1208 qemu_opt_set(opts, "file", filename, &error_abort); 1209 1210 acpi_table_add_builtin(opts, &err); 1211 if (err) { 1212 error_report("WARNING: failed to load %s: %s", filename, 1213 error_get_pretty(err)); 1214 error_free(err); 1215 } 1216 g_free(filename); 1217 } 1218 } 1219 1220 FWCfgState *xen_load_linux(const char *kernel_filename, 1221 const char *kernel_cmdline, 1222 const char *initrd_filename, 1223 ram_addr_t below_4g_mem_size, 1224 PcGuestInfo *guest_info) 1225 { 1226 int i; 1227 FWCfgState *fw_cfg; 1228 1229 assert(kernel_filename != NULL); 1230 1231 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 1232 rom_set_fw(fw_cfg); 1233 1234 load_linux(fw_cfg, kernel_filename, initrd_filename, 1235 kernel_cmdline, below_4g_mem_size); 1236 for (i = 0; i < nb_option_roms; i++) { 1237 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1238 !strcmp(option_rom[i].name, "multiboot.bin")); 1239 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1240 } 1241 guest_info->fw_cfg = fw_cfg; 1242 return fw_cfg; 1243 } 1244 1245 FWCfgState *pc_memory_init(MachineState *machine, 1246 MemoryRegion *system_memory, 1247 ram_addr_t below_4g_mem_size, 1248 ram_addr_t above_4g_mem_size, 1249 MemoryRegion *rom_memory, 1250 MemoryRegion **ram_memory, 1251 PcGuestInfo *guest_info) 1252 { 1253 int linux_boot, i; 1254 MemoryRegion *ram, *option_rom_mr; 1255 MemoryRegion *ram_below_4g, *ram_above_4g; 1256 FWCfgState *fw_cfg; 1257 PCMachineState *pcms = PC_MACHINE(machine); 1258 1259 assert(machine->ram_size == below_4g_mem_size + above_4g_mem_size); 1260 1261 linux_boot = (machine->kernel_filename != NULL); 1262 1263 /* Allocate RAM. We allocate it as a single memory region and use 1264 * aliases to address portions of it, mostly for backwards compatibility 1265 * with older qemus that used qemu_ram_alloc(). 1266 */ 1267 ram = g_malloc(sizeof(*ram)); 1268 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1269 machine->ram_size); 1270 *ram_memory = ram; 1271 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1272 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1273 0, below_4g_mem_size); 1274 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1275 e820_add_entry(0, below_4g_mem_size, E820_RAM); 1276 if (above_4g_mem_size > 0) { 1277 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1278 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1279 below_4g_mem_size, above_4g_mem_size); 1280 memory_region_add_subregion(system_memory, 0x100000000ULL, 1281 ram_above_4g); 1282 e820_add_entry(0x100000000ULL, above_4g_mem_size, E820_RAM); 1283 } 1284 1285 if (!guest_info->has_reserved_memory && 1286 (machine->ram_slots || 1287 (machine->maxram_size > machine->ram_size))) { 1288 MachineClass *mc = MACHINE_GET_CLASS(machine); 1289 1290 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1291 mc->name); 1292 exit(EXIT_FAILURE); 1293 } 1294 1295 /* initialize hotplug memory address space */ 1296 if (guest_info->has_reserved_memory && 1297 (machine->ram_size < machine->maxram_size)) { 1298 ram_addr_t hotplug_mem_size = 1299 machine->maxram_size - machine->ram_size; 1300 1301 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1302 error_report("unsupported amount of memory slots: %"PRIu64, 1303 machine->ram_slots); 1304 exit(EXIT_FAILURE); 1305 } 1306 1307 if (QEMU_ALIGN_UP(machine->maxram_size, 1308 TARGET_PAGE_SIZE) != machine->maxram_size) { 1309 error_report("maximum memory size must by aligned to multiple of " 1310 "%d bytes", TARGET_PAGE_SIZE); 1311 exit(EXIT_FAILURE); 1312 } 1313 1314 pcms->hotplug_memory_base = 1315 ROUND_UP(0x100000000ULL + above_4g_mem_size, 1ULL << 30); 1316 1317 if (pcms->enforce_aligned_dimm) { 1318 /* size hotplug region assuming 1G page max alignment per slot */ 1319 hotplug_mem_size += (1ULL << 30) * machine->ram_slots; 1320 } 1321 1322 if ((pcms->hotplug_memory_base + hotplug_mem_size) < 1323 hotplug_mem_size) { 1324 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1325 machine->maxram_size); 1326 exit(EXIT_FAILURE); 1327 } 1328 1329 memory_region_init(&pcms->hotplug_memory, OBJECT(pcms), 1330 "hotplug-memory", hotplug_mem_size); 1331 memory_region_add_subregion(system_memory, pcms->hotplug_memory_base, 1332 &pcms->hotplug_memory); 1333 } 1334 1335 /* Initialize PC system firmware */ 1336 pc_system_firmware_init(rom_memory, guest_info->isapc_ram_fw); 1337 1338 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1339 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1340 &error_abort); 1341 vmstate_register_ram_global(option_rom_mr); 1342 memory_region_add_subregion_overlap(rom_memory, 1343 PC_ROM_MIN_VGA, 1344 option_rom_mr, 1345 1); 1346 1347 fw_cfg = bochs_bios_init(); 1348 rom_set_fw(fw_cfg); 1349 1350 if (guest_info->has_reserved_memory && pcms->hotplug_memory_base) { 1351 uint64_t *val = g_malloc(sizeof(*val)); 1352 *val = cpu_to_le64(ROUND_UP(pcms->hotplug_memory_base, 0x1ULL << 30)); 1353 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1354 } 1355 1356 if (linux_boot) { 1357 load_linux(fw_cfg, machine->kernel_filename, machine->initrd_filename, 1358 machine->kernel_cmdline, below_4g_mem_size); 1359 } 1360 1361 for (i = 0; i < nb_option_roms; i++) { 1362 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1363 } 1364 guest_info->fw_cfg = fw_cfg; 1365 return fw_cfg; 1366 } 1367 1368 qemu_irq *pc_allocate_cpu_irq(void) 1369 { 1370 return qemu_allocate_irqs(pic_irq_request, NULL, 1); 1371 } 1372 1373 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1374 { 1375 DeviceState *dev = NULL; 1376 1377 if (pci_bus) { 1378 PCIDevice *pcidev = pci_vga_init(pci_bus); 1379 dev = pcidev ? &pcidev->qdev : NULL; 1380 } else if (isa_bus) { 1381 ISADevice *isadev = isa_vga_init(isa_bus); 1382 dev = isadev ? DEVICE(isadev) : NULL; 1383 } 1384 return dev; 1385 } 1386 1387 static void cpu_request_exit(void *opaque, int irq, int level) 1388 { 1389 CPUState *cpu = current_cpu; 1390 1391 if (cpu && level) { 1392 cpu_exit(cpu); 1393 } 1394 } 1395 1396 static const MemoryRegionOps ioport80_io_ops = { 1397 .write = ioport80_write, 1398 .read = ioport80_read, 1399 .endianness = DEVICE_NATIVE_ENDIAN, 1400 .impl = { 1401 .min_access_size = 1, 1402 .max_access_size = 1, 1403 }, 1404 }; 1405 1406 static const MemoryRegionOps ioportF0_io_ops = { 1407 .write = ioportF0_write, 1408 .read = ioportF0_read, 1409 .endianness = DEVICE_NATIVE_ENDIAN, 1410 .impl = { 1411 .min_access_size = 1, 1412 .max_access_size = 1, 1413 }, 1414 }; 1415 1416 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1417 ISADevice **rtc_state, 1418 bool create_fdctrl, 1419 ISADevice **floppy, 1420 bool no_vmport, 1421 uint32 hpet_irqs) 1422 { 1423 int i; 1424 DriveInfo *fd[MAX_FD]; 1425 DeviceState *hpet = NULL; 1426 int pit_isa_irq = 0; 1427 qemu_irq pit_alt_irq = NULL; 1428 qemu_irq rtc_irq = NULL; 1429 qemu_irq *a20_line; 1430 ISADevice *i8042, *port92, *vmmouse, *pit = NULL; 1431 qemu_irq *cpu_exit_irq; 1432 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1433 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1434 1435 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1436 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1437 1438 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1439 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1440 1441 /* 1442 * Check if an HPET shall be created. 1443 * 1444 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1445 * when the HPET wants to take over. Thus we have to disable the latter. 1446 */ 1447 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1448 /* In order to set property, here not using sysbus_try_create_simple */ 1449 hpet = qdev_try_create(NULL, TYPE_HPET); 1450 if (hpet) { 1451 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1452 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1453 * IRQ8 and IRQ2. 1454 */ 1455 uint8_t compat = object_property_get_int(OBJECT(hpet), 1456 HPET_INTCAP, NULL); 1457 if (!compat) { 1458 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1459 } 1460 qdev_init_nofail(hpet); 1461 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1462 1463 for (i = 0; i < GSI_NUM_PINS; i++) { 1464 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1465 } 1466 pit_isa_irq = -1; 1467 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1468 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1469 } 1470 } 1471 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); 1472 1473 qemu_register_boot_set(pc_boot_set, *rtc_state); 1474 1475 if (!xen_enabled()) { 1476 if (kvm_irqchip_in_kernel()) { 1477 pit = kvm_pit_init(isa_bus, 0x40); 1478 } else { 1479 pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1480 } 1481 if (hpet) { 1482 /* connect PIT to output control line of the HPET */ 1483 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1484 } 1485 pcspk_init(isa_bus, pit); 1486 } 1487 1488 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 1489 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1490 1491 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1492 i8042 = isa_create_simple(isa_bus, "i8042"); 1493 i8042_setup_a20_line(i8042, &a20_line[0]); 1494 if (!no_vmport) { 1495 vmport_init(isa_bus); 1496 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1497 } else { 1498 vmmouse = NULL; 1499 } 1500 if (vmmouse) { 1501 DeviceState *dev = DEVICE(vmmouse); 1502 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1503 qdev_init_nofail(dev); 1504 } 1505 port92 = isa_create_simple(isa_bus, "port92"); 1506 port92_init(port92, &a20_line[1]); 1507 1508 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); 1509 DMA_init(0, cpu_exit_irq); 1510 1511 for(i = 0; i < MAX_FD; i++) { 1512 fd[i] = drive_get(IF_FLOPPY, 0, i); 1513 create_fdctrl |= !!fd[i]; 1514 } 1515 *floppy = create_fdctrl ? fdctrl_init_isa(isa_bus, fd) : NULL; 1516 } 1517 1518 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus) 1519 { 1520 int i; 1521 1522 for (i = 0; i < nb_nics; i++) { 1523 NICInfo *nd = &nd_table[i]; 1524 1525 if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) { 1526 pc_init_ne2k_isa(isa_bus, nd); 1527 } else { 1528 pci_nic_init_nofail(nd, pci_bus, "e1000", NULL); 1529 } 1530 } 1531 } 1532 1533 void pc_pci_device_init(PCIBus *pci_bus) 1534 { 1535 int max_bus; 1536 int bus; 1537 1538 max_bus = drive_get_max_bus(IF_SCSI); 1539 for (bus = 0; bus <= max_bus; bus++) { 1540 pci_create_simple(pci_bus, -1, "lsi53c895a"); 1541 } 1542 } 1543 1544 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 1545 { 1546 DeviceState *dev; 1547 SysBusDevice *d; 1548 unsigned int i; 1549 1550 if (kvm_irqchip_in_kernel()) { 1551 dev = qdev_create(NULL, "kvm-ioapic"); 1552 } else { 1553 dev = qdev_create(NULL, "ioapic"); 1554 } 1555 if (parent_name) { 1556 object_property_add_child(object_resolve_path(parent_name, NULL), 1557 "ioapic", OBJECT(dev), NULL); 1558 } 1559 qdev_init_nofail(dev); 1560 d = SYS_BUS_DEVICE(dev); 1561 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 1562 1563 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1564 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 1565 } 1566 } 1567 1568 static void pc_dimm_plug(HotplugHandler *hotplug_dev, 1569 DeviceState *dev, Error **errp) 1570 { 1571 int slot; 1572 HotplugHandlerClass *hhc; 1573 Error *local_err = NULL; 1574 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1575 MachineState *machine = MACHINE(hotplug_dev); 1576 PCDIMMDevice *dimm = PC_DIMM(dev); 1577 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1578 MemoryRegion *mr = ddc->get_memory_region(dimm); 1579 uint64_t existing_dimms_capacity = 0; 1580 uint64_t align = TARGET_PAGE_SIZE; 1581 uint64_t addr; 1582 1583 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 1584 if (local_err) { 1585 goto out; 1586 } 1587 1588 if (memory_region_get_alignment(mr) && pcms->enforce_aligned_dimm) { 1589 align = memory_region_get_alignment(mr); 1590 } 1591 1592 addr = pc_dimm_get_free_addr(pcms->hotplug_memory_base, 1593 memory_region_size(&pcms->hotplug_memory), 1594 !addr ? NULL : &addr, align, 1595 memory_region_size(mr), &local_err); 1596 if (local_err) { 1597 goto out; 1598 } 1599 1600 existing_dimms_capacity = pc_existing_dimms_capacity(&local_err); 1601 if (local_err) { 1602 goto out; 1603 } 1604 1605 if (existing_dimms_capacity + memory_region_size(mr) > 1606 machine->maxram_size - machine->ram_size) { 1607 error_setg(&local_err, "not enough space, currently 0x%" PRIx64 1608 " in use of total hot pluggable 0x" RAM_ADDR_FMT, 1609 existing_dimms_capacity, 1610 machine->maxram_size - machine->ram_size); 1611 goto out; 1612 } 1613 1614 object_property_set_int(OBJECT(dev), addr, PC_DIMM_ADDR_PROP, &local_err); 1615 if (local_err) { 1616 goto out; 1617 } 1618 trace_mhp_pc_dimm_assigned_address(addr); 1619 1620 slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP, &local_err); 1621 if (local_err) { 1622 goto out; 1623 } 1624 1625 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, 1626 machine->ram_slots, &local_err); 1627 if (local_err) { 1628 goto out; 1629 } 1630 object_property_set_int(OBJECT(dev), slot, PC_DIMM_SLOT_PROP, &local_err); 1631 if (local_err) { 1632 goto out; 1633 } 1634 trace_mhp_pc_dimm_assigned_slot(slot); 1635 1636 if (!pcms->acpi_dev) { 1637 error_setg(&local_err, 1638 "memory hotplug is not enabled: missing acpi device"); 1639 goto out; 1640 } 1641 1642 if (kvm_enabled() && !kvm_has_free_slot(machine)) { 1643 error_setg(&local_err, "hypervisor has no free memory slots left"); 1644 goto out; 1645 } 1646 1647 memory_region_add_subregion(&pcms->hotplug_memory, 1648 addr - pcms->hotplug_memory_base, mr); 1649 vmstate_register_ram(mr, dev); 1650 1651 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1652 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1653 out: 1654 error_propagate(errp, local_err); 1655 } 1656 1657 static void pc_dimm_unplug_request(HotplugHandler *hotplug_dev, 1658 DeviceState *dev, Error **errp) 1659 { 1660 HotplugHandlerClass *hhc; 1661 Error *local_err = NULL; 1662 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1663 1664 if (!pcms->acpi_dev) { 1665 error_setg(&local_err, 1666 "memory hotplug is not enabled: missing acpi device"); 1667 goto out; 1668 } 1669 1670 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1671 hhc->unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1672 1673 out: 1674 error_propagate(errp, local_err); 1675 } 1676 1677 static void pc_dimm_unplug(HotplugHandler *hotplug_dev, 1678 DeviceState *dev, Error **errp) 1679 { 1680 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1681 PCDIMMDevice *dimm = PC_DIMM(dev); 1682 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 1683 MemoryRegion *mr = ddc->get_memory_region(dimm); 1684 HotplugHandlerClass *hhc; 1685 Error *local_err = NULL; 1686 1687 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1688 hhc->unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1689 1690 if (local_err) { 1691 goto out; 1692 } 1693 1694 memory_region_del_subregion(&pcms->hotplug_memory, mr); 1695 vmstate_unregister_ram(mr, dev); 1696 1697 object_unparent(OBJECT(dev)); 1698 1699 out: 1700 error_propagate(errp, local_err); 1701 } 1702 1703 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 1704 DeviceState *dev, Error **errp) 1705 { 1706 HotplugHandlerClass *hhc; 1707 Error *local_err = NULL; 1708 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1709 1710 if (!dev->hotplugged) { 1711 goto out; 1712 } 1713 1714 if (!pcms->acpi_dev) { 1715 error_setg(&local_err, 1716 "cpu hotplug is not enabled: missing acpi device"); 1717 goto out; 1718 } 1719 1720 hhc = HOTPLUG_HANDLER_GET_CLASS(pcms->acpi_dev); 1721 hhc->plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 1722 if (local_err) { 1723 goto out; 1724 } 1725 1726 /* increment the number of CPUs */ 1727 rtc_set_memory(pcms->rtc, 0x5f, rtc_get_memory(pcms->rtc, 0x5f) + 1); 1728 out: 1729 error_propagate(errp, local_err); 1730 } 1731 1732 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1733 DeviceState *dev, Error **errp) 1734 { 1735 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1736 pc_dimm_plug(hotplug_dev, dev, errp); 1737 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1738 pc_cpu_plug(hotplug_dev, dev, errp); 1739 } 1740 } 1741 1742 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1743 DeviceState *dev, Error **errp) 1744 { 1745 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1746 pc_dimm_unplug_request(hotplug_dev, dev, errp); 1747 } else { 1748 error_setg(errp, "acpi: device unplug request for not supported device" 1749 " type: %s", object_get_typename(OBJECT(dev))); 1750 } 1751 } 1752 1753 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1754 DeviceState *dev, Error **errp) 1755 { 1756 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1757 pc_dimm_unplug(hotplug_dev, dev, errp); 1758 } else { 1759 error_setg(errp, "acpi: device unplug for not supported device" 1760 " type: %s", object_get_typename(OBJECT(dev))); 1761 } 1762 } 1763 1764 static HotplugHandler *pc_get_hotpug_handler(MachineState *machine, 1765 DeviceState *dev) 1766 { 1767 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); 1768 1769 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1770 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1771 return HOTPLUG_HANDLER(machine); 1772 } 1773 1774 return pcmc->get_hotplug_handler ? 1775 pcmc->get_hotplug_handler(machine, dev) : NULL; 1776 } 1777 1778 static void 1779 pc_machine_get_hotplug_memory_region_size(Object *obj, Visitor *v, void *opaque, 1780 const char *name, Error **errp) 1781 { 1782 PCMachineState *pcms = PC_MACHINE(obj); 1783 int64_t value = memory_region_size(&pcms->hotplug_memory); 1784 1785 visit_type_int(v, &value, name, errp); 1786 } 1787 1788 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1789 void *opaque, const char *name, 1790 Error **errp) 1791 { 1792 PCMachineState *pcms = PC_MACHINE(obj); 1793 uint64_t value = pcms->max_ram_below_4g; 1794 1795 visit_type_size(v, &value, name, errp); 1796 } 1797 1798 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1799 void *opaque, const char *name, 1800 Error **errp) 1801 { 1802 PCMachineState *pcms = PC_MACHINE(obj); 1803 Error *error = NULL; 1804 uint64_t value; 1805 1806 visit_type_size(v, &value, name, &error); 1807 if (error) { 1808 error_propagate(errp, error); 1809 return; 1810 } 1811 if (value > (1ULL << 32)) { 1812 error_set(&error, ERROR_CLASS_GENERIC_ERROR, 1813 "Machine option 'max-ram-below-4g=%"PRIu64 1814 "' expects size less than or equal to 4G", value); 1815 error_propagate(errp, error); 1816 return; 1817 } 1818 1819 if (value < (1ULL << 20)) { 1820 error_report("Warning: small max_ram_below_4g(%"PRIu64 1821 ") less than 1M. BIOS may not work..", 1822 value); 1823 } 1824 1825 pcms->max_ram_below_4g = value; 1826 } 1827 1828 static void pc_machine_get_vmport(Object *obj, Visitor *v, void *opaque, 1829 const char *name, Error **errp) 1830 { 1831 PCMachineState *pcms = PC_MACHINE(obj); 1832 OnOffAuto vmport = pcms->vmport; 1833 1834 visit_type_OnOffAuto(v, &vmport, name, errp); 1835 } 1836 1837 static void pc_machine_set_vmport(Object *obj, Visitor *v, void *opaque, 1838 const char *name, Error **errp) 1839 { 1840 PCMachineState *pcms = PC_MACHINE(obj); 1841 1842 visit_type_OnOffAuto(v, &pcms->vmport, name, errp); 1843 } 1844 1845 static bool pc_machine_get_aligned_dimm(Object *obj, Error **errp) 1846 { 1847 PCMachineState *pcms = PC_MACHINE(obj); 1848 1849 return pcms->enforce_aligned_dimm; 1850 } 1851 1852 static void pc_machine_initfn(Object *obj) 1853 { 1854 PCMachineState *pcms = PC_MACHINE(obj); 1855 1856 object_property_add(obj, PC_MACHINE_MEMHP_REGION_SIZE, "int", 1857 pc_machine_get_hotplug_memory_region_size, 1858 NULL, NULL, NULL, NULL); 1859 1860 pcms->max_ram_below_4g = 1ULL << 32; /* 4G */ 1861 object_property_add(obj, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1862 pc_machine_get_max_ram_below_4g, 1863 pc_machine_set_max_ram_below_4g, 1864 NULL, NULL, NULL); 1865 object_property_set_description(obj, PC_MACHINE_MAX_RAM_BELOW_4G, 1866 "Maximum ram below the 4G boundary (32bit boundary)", 1867 NULL); 1868 1869 pcms->vmport = ON_OFF_AUTO_AUTO; 1870 object_property_add(obj, PC_MACHINE_VMPORT, "OnOffAuto", 1871 pc_machine_get_vmport, 1872 pc_machine_set_vmport, 1873 NULL, NULL, NULL); 1874 object_property_set_description(obj, PC_MACHINE_VMPORT, 1875 "Enable vmport (pc & q35)", 1876 NULL); 1877 1878 pcms->enforce_aligned_dimm = true; 1879 object_property_add_bool(obj, PC_MACHINE_ENFORCE_ALIGNED_DIMM, 1880 pc_machine_get_aligned_dimm, 1881 NULL, NULL); 1882 } 1883 1884 static unsigned pc_cpu_index_to_socket_id(unsigned cpu_index) 1885 { 1886 unsigned pkg_id, core_id, smt_id; 1887 x86_topo_ids_from_idx(smp_cores, smp_threads, cpu_index, 1888 &pkg_id, &core_id, &smt_id); 1889 return pkg_id; 1890 } 1891 1892 static void pc_machine_class_init(ObjectClass *oc, void *data) 1893 { 1894 MachineClass *mc = MACHINE_CLASS(oc); 1895 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1896 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1897 1898 pcmc->get_hotplug_handler = mc->get_hotplug_handler; 1899 mc->get_hotplug_handler = pc_get_hotpug_handler; 1900 mc->cpu_index_to_socket_id = pc_cpu_index_to_socket_id; 1901 hc->plug = pc_machine_device_plug_cb; 1902 hc->unplug_request = pc_machine_device_unplug_request_cb; 1903 hc->unplug = pc_machine_device_unplug_cb; 1904 } 1905 1906 static const TypeInfo pc_machine_info = { 1907 .name = TYPE_PC_MACHINE, 1908 .parent = TYPE_MACHINE, 1909 .abstract = true, 1910 .instance_size = sizeof(PCMachineState), 1911 .instance_init = pc_machine_initfn, 1912 .class_size = sizeof(PCMachineClass), 1913 .class_init = pc_machine_class_init, 1914 .interfaces = (InterfaceInfo[]) { 1915 { TYPE_HOTPLUG_HANDLER }, 1916 { } 1917 }, 1918 }; 1919 1920 static void pc_machine_register_types(void) 1921 { 1922 type_register_static(&pc_machine_info); 1923 } 1924 1925 type_init(pc_machine_register_types) 1926