1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "exec/target_page.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial-isa.h" 30 #include "hw/char/parallel.h" 31 #include "hw/hyperv/hv-balloon.h" 32 #include "hw/i386/fw_cfg.h" 33 #include "hw/i386/vmport.h" 34 #include "system/cpus.h" 35 #include "hw/ide/ide-bus.h" 36 #include "hw/timer/hpet.h" 37 #include "hw/loader.h" 38 #include "hw/rtc/mc146818rtc.h" 39 #include "hw/intc/i8259.h" 40 #include "hw/timer/i8254.h" 41 #include "hw/input/i8042.h" 42 #include "hw/audio/pcspk.h" 43 #include "system/system.h" 44 #include "system/xen.h" 45 #include "system/reset.h" 46 #include "kvm/kvm_i386.h" 47 #include "kvm/tdx.h" 48 #include "hw/xen/xen.h" 49 #include "qobject/qlist.h" 50 #include "qemu/error-report.h" 51 #include "hw/acpi/cpu_hotplug.h" 52 #include "acpi-build.h" 53 #include "hw/mem/nvdimm.h" 54 #include "hw/cxl/cxl_host.h" 55 #include "hw/usb.h" 56 #include "hw/i386/intel_iommu.h" 57 #include "hw/net/ne2000-isa.h" 58 #include "hw/virtio/virtio-iommu.h" 59 #include "hw/virtio/virtio-md-pci.h" 60 #include "hw/i386/kvm/xen_overlay.h" 61 #include "hw/i386/kvm/xen_evtchn.h" 62 #include "hw/i386/kvm/xen_gnttab.h" 63 #include "hw/i386/kvm/xen_xenstore.h" 64 #include "hw/mem/memory-device.h" 65 #include "e820_memory_layout.h" 66 #include "trace.h" 67 #include "sev.h" 68 #include CONFIG_DEVICES 69 70 #ifdef CONFIG_XEN_EMU 71 #include "hw/xen/xen-legacy-backend.h" 72 #include "hw/xen/xen-bus.h" 73 #endif 74 75 /* 76 * Helper for setting model-id for CPU models that changed model-id 77 * depending on QEMU versions up to QEMU 2.4. 78 */ 79 #define PC_CPU_MODEL_IDS(v) \ 80 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 81 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 82 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 83 84 GlobalProperty pc_compat_10_0[] = {}; 85 const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); 86 87 GlobalProperty pc_compat_9_2[] = {}; 88 const size_t pc_compat_9_2_len = G_N_ELEMENTS(pc_compat_9_2); 89 90 GlobalProperty pc_compat_9_1[] = { 91 { "ICH9-LPC", "x-smi-swsmi-timer", "off" }, 92 { "ICH9-LPC", "x-smi-periodic-timer", "off" }, 93 { TYPE_INTEL_IOMMU_DEVICE, "stale-tm", "on" }, 94 { TYPE_INTEL_IOMMU_DEVICE, "aw-bits", "39" }, 95 }; 96 const size_t pc_compat_9_1_len = G_N_ELEMENTS(pc_compat_9_1); 97 98 GlobalProperty pc_compat_9_0[] = { 99 { TYPE_X86_CPU, "x-amd-topoext-features-only", "false" }, 100 { TYPE_X86_CPU, "x-l1-cache-per-thread", "false" }, 101 { TYPE_X86_CPU, "guest-phys-bits", "0" }, 102 { "sev-guest", "legacy-vm-type", "on" }, 103 { TYPE_X86_CPU, "legacy-multi-node", "on" }, 104 }; 105 const size_t pc_compat_9_0_len = G_N_ELEMENTS(pc_compat_9_0); 106 107 GlobalProperty pc_compat_8_2[] = {}; 108 const size_t pc_compat_8_2_len = G_N_ELEMENTS(pc_compat_8_2); 109 110 GlobalProperty pc_compat_8_1[] = {}; 111 const size_t pc_compat_8_1_len = G_N_ELEMENTS(pc_compat_8_1); 112 113 GlobalProperty pc_compat_8_0[] = { 114 { "virtio-mem", "unplugged-inaccessible", "auto" }, 115 }; 116 const size_t pc_compat_8_0_len = G_N_ELEMENTS(pc_compat_8_0); 117 118 GlobalProperty pc_compat_7_2[] = { 119 { "ICH9-LPC", "noreboot", "true" }, 120 }; 121 const size_t pc_compat_7_2_len = G_N_ELEMENTS(pc_compat_7_2); 122 123 GlobalProperty pc_compat_7_1[] = {}; 124 const size_t pc_compat_7_1_len = G_N_ELEMENTS(pc_compat_7_1); 125 126 GlobalProperty pc_compat_7_0[] = {}; 127 const size_t pc_compat_7_0_len = G_N_ELEMENTS(pc_compat_7_0); 128 129 GlobalProperty pc_compat_6_2[] = { 130 { "virtio-mem", "unplugged-inaccessible", "off" }, 131 }; 132 const size_t pc_compat_6_2_len = G_N_ELEMENTS(pc_compat_6_2); 133 134 GlobalProperty pc_compat_6_1[] = { 135 { TYPE_X86_CPU, "hv-version-id-build", "0x1bbc" }, 136 { TYPE_X86_CPU, "hv-version-id-major", "0x0006" }, 137 { TYPE_X86_CPU, "hv-version-id-minor", "0x0001" }, 138 { "ICH9-LPC", "x-keep-pci-slot-hpc", "false" }, 139 }; 140 const size_t pc_compat_6_1_len = G_N_ELEMENTS(pc_compat_6_1); 141 142 GlobalProperty pc_compat_6_0[] = { 143 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 144 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 145 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 146 { TYPE_X86_CPU, "x-vendor-cpuid-only", "off" }, 147 { "ICH9-LPC", ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, "off" }, 148 { "ICH9-LPC", "x-keep-pci-slot-hpc", "true" }, 149 }; 150 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 151 152 GlobalProperty pc_compat_5_2[] = { 153 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 154 }; 155 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 156 157 GlobalProperty pc_compat_5_1[] = { 158 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 159 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 160 }; 161 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 162 163 GlobalProperty pc_compat_5_0[] = { 164 }; 165 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 166 167 GlobalProperty pc_compat_4_2[] = { 168 { "mch", "smbase-smram", "off" }, 169 }; 170 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 171 172 GlobalProperty pc_compat_4_1[] = {}; 173 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 174 175 GlobalProperty pc_compat_4_0[] = {}; 176 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 177 178 GlobalProperty pc_compat_3_1[] = { 179 { "intel-iommu", "dma-drain", "off" }, 180 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 181 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 182 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 183 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 184 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 185 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 186 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 187 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 188 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 189 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 190 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 191 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 192 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 193 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 194 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 195 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 196 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 197 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 198 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 199 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 200 }; 201 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 202 203 GlobalProperty pc_compat_3_0[] = { 204 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 205 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 206 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 207 }; 208 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 209 210 GlobalProperty pc_compat_2_12[] = { 211 { TYPE_X86_CPU, "legacy-cache", "on" }, 212 { TYPE_X86_CPU, "topoext", "off" }, 213 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 214 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 215 }; 216 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 217 218 GlobalProperty pc_compat_2_11[] = { 219 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 220 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 221 }; 222 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 223 224 GlobalProperty pc_compat_2_10[] = { 225 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 226 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 227 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 228 }; 229 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 230 231 GlobalProperty pc_compat_2_9[] = { 232 { "mch", "extended-tseg-mbytes", "0" }, 233 }; 234 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 235 236 GlobalProperty pc_compat_2_8[] = { 237 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 238 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 239 { "ICH9-LPC", "x-smi-broadcast", "off" }, 240 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 241 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 242 }; 243 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 244 245 GlobalProperty pc_compat_2_7[] = { 246 { TYPE_X86_CPU, "l3-cache", "off" }, 247 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 248 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 249 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 250 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 251 { "isa-pcspk", "migrate", "off" }, 252 }; 253 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 254 255 GlobalProperty pc_compat_2_6[] = { 256 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 257 { "vmxnet3", "romfile", "" }, 258 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 259 { "apic-common", "legacy-instance-id", "on", } 260 }; 261 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 262 263 /* 264 * @PC_FW_DATA: 265 * Size of the chunk of memory at the top of RAM for the BIOS ACPI tables 266 * and other BIOS datastructures. 267 * 268 * BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K 269 * reported to be used at the moment, 32K should be enough for a while. 270 */ 271 #define PC_FW_DATA (0x20000 + 0x8000) 272 273 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 274 { 275 GSIState *s; 276 277 s = g_new0(GSIState, 1); 278 if (kvm_ioapic_in_kernel()) { 279 kvm_pc_setup_irq_routing(pci_enabled); 280 } 281 *irqs = qemu_allocate_irqs(gsi_handler, s, IOAPIC_NUM_PINS); 282 283 return s; 284 } 285 286 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 287 unsigned size) 288 { 289 } 290 291 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 292 { 293 return 0xffffffffffffffffULL; 294 } 295 296 /* MS-DOS compatibility mode FPU exception support */ 297 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 298 unsigned size) 299 { 300 if (tcg_enabled()) { 301 cpu_set_ignne(); 302 } 303 } 304 305 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 306 { 307 return 0xffffffffffffffffULL; 308 } 309 310 /* PC cmos mappings */ 311 312 #define REG_EQUIPMENT_BYTE 0x14 313 314 static void cmos_init_hd(MC146818RtcState *s, int type_ofs, int info_ofs, 315 int16_t cylinders, int8_t heads, int8_t sectors) 316 { 317 mc146818rtc_set_cmos_data(s, type_ofs, 47); 318 mc146818rtc_set_cmos_data(s, info_ofs, cylinders); 319 mc146818rtc_set_cmos_data(s, info_ofs + 1, cylinders >> 8); 320 mc146818rtc_set_cmos_data(s, info_ofs + 2, heads); 321 mc146818rtc_set_cmos_data(s, info_ofs + 3, 0xff); 322 mc146818rtc_set_cmos_data(s, info_ofs + 4, 0xff); 323 mc146818rtc_set_cmos_data(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 324 mc146818rtc_set_cmos_data(s, info_ofs + 6, cylinders); 325 mc146818rtc_set_cmos_data(s, info_ofs + 7, cylinders >> 8); 326 mc146818rtc_set_cmos_data(s, info_ofs + 8, sectors); 327 } 328 329 /* convert boot_device letter to something recognizable by the bios */ 330 static int boot_device2nibble(char boot_device) 331 { 332 switch(boot_device) { 333 case 'a': 334 case 'b': 335 return 0x01; /* floppy boot */ 336 case 'c': 337 return 0x02; /* hard drive boot */ 338 case 'd': 339 return 0x03; /* CD-ROM boot */ 340 case 'n': 341 return 0x04; /* Network boot */ 342 } 343 return 0; 344 } 345 346 static void set_boot_dev(PCMachineState *pcms, MC146818RtcState *s, 347 const char *boot_device, Error **errp) 348 { 349 #define PC_MAX_BOOT_DEVICES 3 350 int nbds, bds[3] = { 0, }; 351 int i; 352 353 nbds = strlen(boot_device); 354 if (nbds > PC_MAX_BOOT_DEVICES) { 355 error_setg(errp, "Too many boot devices for PC"); 356 return; 357 } 358 for (i = 0; i < nbds; i++) { 359 bds[i] = boot_device2nibble(boot_device[i]); 360 if (bds[i] == 0) { 361 error_setg(errp, "Invalid boot device for PC: '%c'", 362 boot_device[i]); 363 return; 364 } 365 } 366 mc146818rtc_set_cmos_data(s, 0x3d, (bds[1] << 4) | bds[0]); 367 mc146818rtc_set_cmos_data(s, 0x38, (bds[2] << 4) | !pcms->fd_bootchk); 368 } 369 370 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 371 { 372 PCMachineState *pcms = opaque; 373 X86MachineState *x86ms = X86_MACHINE(pcms); 374 375 set_boot_dev(pcms, MC146818_RTC(x86ms->rtc), boot_device, errp); 376 } 377 378 static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) 379 { 380 int val, nb; 381 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 382 FLOPPY_DRIVE_TYPE_NONE }; 383 384 #ifdef CONFIG_FDC_ISA 385 /* floppy type */ 386 if (floppy) { 387 for (int i = 0; i < 2; i++) { 388 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 389 } 390 } 391 #endif 392 393 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 394 cmos_get_fd_drive_type(fd_type[1]); 395 mc146818rtc_set_cmos_data(rtc_state, 0x10, val); 396 397 val = mc146818rtc_get_cmos_data(rtc_state, REG_EQUIPMENT_BYTE); 398 nb = 0; 399 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 400 nb++; 401 } 402 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 403 nb++; 404 } 405 switch (nb) { 406 case 0: 407 break; 408 case 1: 409 val |= 0x01; /* 1 drive, ready for boot */ 410 break; 411 case 2: 412 val |= 0x41; /* 2 drives, ready for boot */ 413 break; 414 } 415 mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); 416 } 417 418 typedef struct check_fdc_state { 419 ISADevice *floppy; 420 bool multiple; 421 } CheckFdcState; 422 423 static int check_fdc(Object *obj, void *opaque) 424 { 425 CheckFdcState *state = opaque; 426 Object *fdc; 427 uint32_t iobase; 428 Error *local_err = NULL; 429 430 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 431 if (!fdc) { 432 return 0; 433 } 434 435 iobase = object_property_get_uint(obj, "iobase", &local_err); 436 if (local_err || iobase != 0x3f0) { 437 error_free(local_err); 438 return 0; 439 } 440 441 if (state->floppy) { 442 state->multiple = true; 443 } else { 444 state->floppy = ISA_DEVICE(obj); 445 } 446 return 0; 447 } 448 449 static const char * const fdc_container_path[] = { 450 "unattached", "peripheral", "peripheral-anon" 451 }; 452 453 /* 454 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 455 * and ACPI objects. 456 */ 457 static ISADevice *pc_find_fdc0(void) 458 { 459 int i; 460 Object *container; 461 CheckFdcState state = { 0 }; 462 463 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 464 container = machine_get_container(fdc_container_path[i]); 465 object_child_foreach(container, check_fdc, &state); 466 } 467 468 if (state.multiple) { 469 warn_report("multiple floppy disk controllers with " 470 "iobase=0x3f0 have been found"); 471 error_printf("the one being picked for CMOS setup might not reflect " 472 "your intent"); 473 } 474 475 return state.floppy; 476 } 477 478 static void pc_cmos_init_late(PCMachineState *pcms) 479 { 480 X86MachineState *x86ms = X86_MACHINE(pcms); 481 MC146818RtcState *s = MC146818_RTC(x86ms->rtc); 482 int16_t cylinders; 483 int8_t heads, sectors; 484 int val; 485 int i, trans; 486 487 val = 0; 488 if (pcms->idebus[0] && 489 ide_get_geometry(pcms->idebus[0], 0, 490 &cylinders, &heads, §ors) >= 0) { 491 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 492 val |= 0xf0; 493 } 494 if (pcms->idebus[0] && 495 ide_get_geometry(pcms->idebus[0], 1, 496 &cylinders, &heads, §ors) >= 0) { 497 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 498 val |= 0x0f; 499 } 500 mc146818rtc_set_cmos_data(s, 0x12, val); 501 502 val = 0; 503 for (i = 0; i < 4; i++) { 504 /* NOTE: ide_get_geometry() returns the physical 505 geometry. It is always such that: 1 <= sects <= 63, 1 506 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 507 geometry can be different if a translation is done. */ 508 BusState *idebus = pcms->idebus[i / 2]; 509 if (idebus && 510 ide_get_geometry(idebus, i % 2, 511 &cylinders, &heads, §ors) >= 0) { 512 trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; 513 assert((trans & ~3) == 0); 514 val |= trans << (i * 2); 515 } 516 } 517 mc146818rtc_set_cmos_data(s, 0x39, val); 518 519 pc_cmos_init_floppy(s, pc_find_fdc0()); 520 521 /* various important CMOS locations needed by PC/Bochs bios */ 522 523 /* memory size */ 524 /* base memory (first MiB) */ 525 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 526 mc146818rtc_set_cmos_data(s, 0x15, val); 527 mc146818rtc_set_cmos_data(s, 0x16, val >> 8); 528 /* extended memory (next 64MiB) */ 529 if (x86ms->below_4g_mem_size > 1 * MiB) { 530 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 531 } else { 532 val = 0; 533 } 534 if (val > 65535) 535 val = 65535; 536 mc146818rtc_set_cmos_data(s, 0x17, val); 537 mc146818rtc_set_cmos_data(s, 0x18, val >> 8); 538 mc146818rtc_set_cmos_data(s, 0x30, val); 539 mc146818rtc_set_cmos_data(s, 0x31, val >> 8); 540 /* memory between 16MiB and 4GiB */ 541 if (x86ms->below_4g_mem_size > 16 * MiB) { 542 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 543 } else { 544 val = 0; 545 } 546 if (val > 65535) 547 val = 65535; 548 mc146818rtc_set_cmos_data(s, 0x34, val); 549 mc146818rtc_set_cmos_data(s, 0x35, val >> 8); 550 /* memory above 4GiB */ 551 val = x86ms->above_4g_mem_size / 65536; 552 mc146818rtc_set_cmos_data(s, 0x5b, val); 553 mc146818rtc_set_cmos_data(s, 0x5c, val >> 8); 554 mc146818rtc_set_cmos_data(s, 0x5d, val >> 16); 555 556 val = 0; 557 val |= 0x02; /* FPU is there */ 558 val |= 0x04; /* PS/2 mouse installed */ 559 mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); 560 } 561 562 static void handle_a20_line_change(void *opaque, int irq, int level) 563 { 564 X86CPU *cpu = opaque; 565 566 /* XXX: send to all CPUs ? */ 567 /* XXX: add logic to handle multiple A20 line sources */ 568 x86_cpu_set_a20(cpu, level); 569 } 570 571 #define NE2000_NB_MAX 6 572 573 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 574 0x280, 0x380 }; 575 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 576 577 static gboolean pc_init_ne2k_isa(ISABus *bus, NICInfo *nd, Error **errp) 578 { 579 static int nb_ne2k = 0; 580 581 if (nb_ne2k == NE2000_NB_MAX) { 582 error_setg(errp, 583 "maximum number of ISA NE2000 devices exceeded"); 584 return false; 585 } 586 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 587 ne2000_irq[nb_ne2k], nd); 588 nb_ne2k++; 589 return true; 590 } 591 592 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 593 { 594 X86CPU *cpu = opaque; 595 596 if (level) { 597 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 598 } 599 } 600 601 static 602 void pc_machine_done(Notifier *notifier, void *data) 603 { 604 PCMachineState *pcms = container_of(notifier, 605 PCMachineState, machine_done); 606 X86MachineState *x86ms = X86_MACHINE(pcms); 607 608 cxl_hook_up_pxb_registers(pcms->pcibus, &pcms->cxl_devices_state, 609 &error_fatal); 610 611 if (pcms->cxl_devices_state.is_enabled) { 612 cxl_fmws_link_targets(&error_fatal); 613 } 614 615 /* set the number of CPUs */ 616 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 617 618 pci_bus_add_fw_cfg_extra_pci_roots(x86ms->fw_cfg, pcms->pcibus, 619 &error_abort); 620 621 acpi_setup(); 622 if (x86ms->fw_cfg) { 623 fw_cfg_build_smbios(pcms, x86ms->fw_cfg, pcms->smbios_entry_point_type); 624 fw_cfg_add_e820(x86ms->fw_cfg); 625 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 626 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 627 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 628 } 629 630 pc_cmos_init_late(pcms); 631 } 632 633 /* setup pci memory address space mapping into system address space */ 634 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 635 MemoryRegion *pci_address_space) 636 { 637 /* Set to lower priority than RAM */ 638 memory_region_add_subregion_overlap(system_memory, 0x0, 639 pci_address_space, -1); 640 } 641 642 void xen_load_linux(PCMachineState *pcms) 643 { 644 int i; 645 FWCfgState *fw_cfg; 646 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 647 X86MachineState *x86ms = X86_MACHINE(pcms); 648 649 assert(MACHINE(pcms)->kernel_filename != NULL); 650 651 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, 652 &address_space_memory); 653 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 654 rom_set_fw(fw_cfg); 655 656 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 657 for (i = 0; i < nb_option_roms; i++) { 658 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 659 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 660 !strcmp(option_rom[i].name, "pvh.bin") || 661 !strcmp(option_rom[i].name, "multiboot.bin") || 662 !strcmp(option_rom[i].name, "multiboot_dma.bin")); 663 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 664 } 665 x86ms->fw_cfg = fw_cfg; 666 } 667 668 #define PC_ROM_MIN_VGA 0xc0000 669 #define PC_ROM_MIN_OPTION 0xc8000 670 #define PC_ROM_MAX 0xe0000 671 #define PC_ROM_ALIGN 0x800 672 #define PC_ROM_SIZE (PC_ROM_MAX - PC_ROM_MIN_VGA) 673 674 static hwaddr pc_above_4g_end(PCMachineState *pcms) 675 { 676 X86MachineState *x86ms = X86_MACHINE(pcms); 677 678 if (pcms->sgx_epc.size != 0) { 679 return sgx_epc_above_4g_end(&pcms->sgx_epc); 680 } 681 682 return x86ms->above_4g_mem_start + x86ms->above_4g_mem_size; 683 } 684 685 static void pc_get_device_memory_range(PCMachineState *pcms, 686 hwaddr *base, 687 ram_addr_t *device_mem_size) 688 { 689 MachineState *machine = MACHINE(pcms); 690 ram_addr_t size; 691 hwaddr addr; 692 693 size = machine->maxram_size - machine->ram_size; 694 addr = ROUND_UP(pc_above_4g_end(pcms), 1 * GiB); 695 696 /* size device region assuming 1G page max alignment per slot */ 697 size += (1 * GiB) * machine->ram_slots; 698 699 *base = addr; 700 *device_mem_size = size; 701 } 702 703 static uint64_t pc_get_cxl_range_start(PCMachineState *pcms) 704 { 705 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 706 MachineState *ms = MACHINE(pcms); 707 hwaddr cxl_base; 708 ram_addr_t size; 709 710 if (pcmc->has_reserved_memory && 711 (ms->ram_size < ms->maxram_size)) { 712 pc_get_device_memory_range(pcms, &cxl_base, &size); 713 cxl_base += size; 714 } else { 715 cxl_base = pc_above_4g_end(pcms); 716 } 717 718 return cxl_base; 719 } 720 721 static int cxl_get_fmw_end(Object *obj, void *opaque) 722 { 723 struct CXLFixedWindow *fw; 724 uint64_t *start = opaque; 725 726 if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { 727 return 0; 728 } 729 fw = CXL_FMW(obj); 730 731 *start += fw->size; 732 733 return 0; 734 } 735 736 static uint64_t pc_get_cxl_range_end(PCMachineState *pcms) 737 { 738 uint64_t start = pc_get_cxl_range_start(pcms) + MiB; 739 740 /* Ordering doesn't matter so no need to build a sorted list */ 741 object_child_foreach_recursive(object_get_root(), cxl_get_fmw_end, 742 &start); 743 return start; 744 } 745 746 static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_size) 747 { 748 X86CPU *cpu = X86_CPU(first_cpu); 749 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 750 MachineState *ms = MACHINE(pcms); 751 752 if (cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 753 /* 64-bit systems */ 754 return pc_pci_hole64_start() + pci_hole64_size - 1; 755 } 756 757 /* 32-bit systems */ 758 if (pcmc->broken_32bit_mem_addr_check) { 759 /* old value for compatibility reasons */ 760 return ((hwaddr)1 << cpu->phys_bits) - 1; 761 } 762 763 /* 764 * 32-bit systems don't have hole64 but they might have a region for 765 * memory devices. Even if additional hotplugged memory devices might 766 * not be usable by most guest OSes, we need to still consider them for 767 * calculating the highest possible GPA so that we can properly report 768 * if someone configures them on a CPU that cannot possibly address them. 769 */ 770 if (pcmc->has_reserved_memory && 771 (ms->ram_size < ms->maxram_size)) { 772 hwaddr devmem_start; 773 ram_addr_t devmem_size; 774 775 pc_get_device_memory_range(pcms, &devmem_start, &devmem_size); 776 devmem_start += devmem_size; 777 return devmem_start - 1; 778 } 779 780 /* configuration without any memory hotplug */ 781 return pc_above_4g_end(pcms) - 1; 782 } 783 784 /* 785 * AMD systems with an IOMMU have an additional hole close to the 786 * 1Tb, which are special GPAs that cannot be DMA mapped. Depending 787 * on kernel version, VFIO may or may not let you DMA map those ranges. 788 * Starting Linux v5.4 we validate it, and can't create guests on AMD machines 789 * with certain memory sizes. It's also wrong to use those IOVA ranges 790 * in detriment of leading to IOMMU INVALID_DEVICE_REQUEST or worse. 791 * The ranges reserved for Hyper-Transport are: 792 * 793 * FD_0000_0000h - FF_FFFF_FFFFh 794 * 795 * The ranges represent the following: 796 * 797 * Base Address Top Address Use 798 * 799 * FD_0000_0000h FD_F7FF_FFFFh Reserved interrupt address space 800 * FD_F800_0000h FD_F8FF_FFFFh Interrupt/EOI IntCtl 801 * FD_F900_0000h FD_F90F_FFFFh Legacy PIC IACK 802 * FD_F910_0000h FD_F91F_FFFFh System Management 803 * FD_F920_0000h FD_FAFF_FFFFh Reserved Page Tables 804 * FD_FB00_0000h FD_FBFF_FFFFh Address Translation 805 * FD_FC00_0000h FD_FDFF_FFFFh I/O Space 806 * FD_FE00_0000h FD_FFFF_FFFFh Configuration 807 * FE_0000_0000h FE_1FFF_FFFFh Extended Configuration/Device Messages 808 * FE_2000_0000h FF_FFFF_FFFFh Reserved 809 * 810 * See AMD IOMMU spec, section 2.1.2 "IOMMU Logical Topology", 811 * Table 3: Special Address Controls (GPA) for more information. 812 */ 813 #define AMD_HT_START 0xfd00000000UL 814 #define AMD_HT_END 0xffffffffffUL 815 #define AMD_ABOVE_1TB_START (AMD_HT_END + 1) 816 #define AMD_HT_SIZE (AMD_ABOVE_1TB_START - AMD_HT_START) 817 818 void pc_memory_init(PCMachineState *pcms, 819 MemoryRegion *system_memory, 820 MemoryRegion *rom_memory, 821 uint64_t pci_hole64_size) 822 { 823 int linux_boot, i; 824 MemoryRegion *option_rom_mr; 825 MemoryRegion *ram_below_4g, *ram_above_4g; 826 FWCfgState *fw_cfg; 827 MachineState *machine = MACHINE(pcms); 828 MachineClass *mc = MACHINE_GET_CLASS(machine); 829 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 830 X86MachineState *x86ms = X86_MACHINE(pcms); 831 hwaddr maxphysaddr, maxusedaddr; 832 hwaddr cxl_base, cxl_resv_end = 0; 833 X86CPU *cpu = X86_CPU(first_cpu); 834 835 assert(machine->ram_size == x86ms->below_4g_mem_size + 836 x86ms->above_4g_mem_size); 837 838 linux_boot = (machine->kernel_filename != NULL); 839 840 /* 841 * The HyperTransport range close to the 1T boundary is unique to AMD 842 * hosts with IOMMUs enabled. Restrict the ram-above-4g relocation 843 * to above 1T to AMD vCPUs only. @enforce_amd_1tb_hole is only false in 844 * older machine types (<= 7.0) for compatibility purposes. 845 */ 846 if (IS_AMD_CPU(&cpu->env) && pcmc->enforce_amd_1tb_hole) { 847 /* Bail out if max possible address does not cross HT range */ 848 if (pc_max_used_gpa(pcms, pci_hole64_size) >= AMD_HT_START) { 849 x86ms->above_4g_mem_start = AMD_ABOVE_1TB_START; 850 } 851 852 /* 853 * Advertise the HT region if address space covers the reserved 854 * region or if we relocate. 855 */ 856 if (cpu->phys_bits >= 40) { 857 e820_add_entry(AMD_HT_START, AMD_HT_SIZE, E820_RESERVED); 858 } 859 } 860 861 /* 862 * phys-bits is required to be appropriately configured 863 * to make sure max used GPA is reachable. 864 */ 865 maxusedaddr = pc_max_used_gpa(pcms, pci_hole64_size); 866 maxphysaddr = ((hwaddr)1 << cpu->phys_bits) - 1; 867 if (maxphysaddr < maxusedaddr) { 868 error_report("Address space limit 0x%"PRIx64" < 0x%"PRIx64 869 " phys-bits too low (%u)", 870 maxphysaddr, maxusedaddr, cpu->phys_bits); 871 exit(EXIT_FAILURE); 872 } 873 874 /* 875 * Split single memory region and use aliases to address portions of it, 876 * done for backwards compatibility with older qemus. 877 */ 878 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 879 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 880 0, x86ms->below_4g_mem_size); 881 memory_region_add_subregion(system_memory, 0, ram_below_4g); 882 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 883 if (x86ms->above_4g_mem_size > 0) { 884 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 885 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 886 machine->ram, 887 x86ms->below_4g_mem_size, 888 x86ms->above_4g_mem_size); 889 memory_region_add_subregion(system_memory, x86ms->above_4g_mem_start, 890 ram_above_4g); 891 e820_add_entry(x86ms->above_4g_mem_start, x86ms->above_4g_mem_size, 892 E820_RAM); 893 } 894 895 if (pcms->sgx_epc.size != 0) { 896 e820_add_entry(pcms->sgx_epc.base, pcms->sgx_epc.size, E820_RESERVED); 897 } 898 899 if (!pcmc->has_reserved_memory && 900 (machine->ram_slots || 901 (machine->maxram_size > machine->ram_size))) { 902 903 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 904 mc->name); 905 exit(EXIT_FAILURE); 906 } 907 908 /* initialize device memory address space */ 909 if (pcmc->has_reserved_memory && 910 (machine->ram_size < machine->maxram_size)) { 911 ram_addr_t device_mem_size; 912 hwaddr device_mem_base; 913 914 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 915 error_report("unsupported amount of memory slots: %"PRIu64, 916 machine->ram_slots); 917 exit(EXIT_FAILURE); 918 } 919 920 if (QEMU_ALIGN_UP(machine->maxram_size, 921 TARGET_PAGE_SIZE) != machine->maxram_size) { 922 error_report("maximum memory size must by aligned to multiple of " 923 "%d bytes", TARGET_PAGE_SIZE); 924 exit(EXIT_FAILURE); 925 } 926 927 pc_get_device_memory_range(pcms, &device_mem_base, &device_mem_size); 928 929 if (device_mem_base + device_mem_size < device_mem_size) { 930 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 931 machine->maxram_size); 932 exit(EXIT_FAILURE); 933 } 934 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 935 } 936 937 if (pcms->cxl_devices_state.is_enabled) { 938 MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; 939 hwaddr cxl_size = MiB; 940 941 cxl_base = pc_get_cxl_range_start(pcms); 942 memory_region_init(mr, OBJECT(machine), "cxl_host_reg", cxl_size); 943 memory_region_add_subregion(system_memory, cxl_base, mr); 944 cxl_base = ROUND_UP(cxl_base + cxl_size, 256 * MiB); 945 cxl_resv_end = cxl_fmws_set_memmap(cxl_base, maxphysaddr); 946 cxl_fmws_update_mmio(); 947 } 948 949 /* Initialize PC system firmware */ 950 pc_system_firmware_init(pcms, rom_memory); 951 952 if (!is_tdx_vm()) { 953 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 954 if (machine_require_guest_memfd(machine)) { 955 memory_region_init_ram_guest_memfd(option_rom_mr, NULL, "pc.rom", 956 PC_ROM_SIZE, &error_fatal); 957 } else { 958 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 959 &error_fatal); 960 if (pcmc->pci_enabled) { 961 memory_region_set_readonly(option_rom_mr, true); 962 } 963 } 964 memory_region_add_subregion_overlap(rom_memory, 965 PC_ROM_MIN_VGA, 966 option_rom_mr, 967 1); 968 } 969 970 fw_cfg = fw_cfg_arch_create(machine, 971 x86ms->boot_cpus, x86ms->apic_id_limit); 972 973 rom_set_fw(fw_cfg); 974 975 if (machine->device_memory) { 976 uint64_t *val = g_malloc(sizeof(*val)); 977 uint64_t res_mem_end; 978 979 if (pcms->cxl_devices_state.is_enabled) { 980 res_mem_end = cxl_resv_end; 981 } else { 982 res_mem_end = machine->device_memory->base 983 + memory_region_size(&machine->device_memory->mr); 984 } 985 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 986 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 987 } 988 989 if (linux_boot) { 990 x86_load_linux(x86ms, fw_cfg, PC_FW_DATA, pcmc->pvh_enabled); 991 } 992 993 for (i = 0; i < nb_option_roms; i++) { 994 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 995 } 996 x86ms->fw_cfg = fw_cfg; 997 998 /* Init default IOAPIC address space */ 999 x86ms->ioapic_as = &address_space_memory; 1000 1001 /* Init ACPI memory hotplug IO base address */ 1002 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 1003 } 1004 1005 /* 1006 * The 64bit pci hole starts after "above 4G RAM" and 1007 * potentially the space reserved for memory hotplug. 1008 */ 1009 uint64_t pc_pci_hole64_start(void) 1010 { 1011 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1012 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1013 MachineState *ms = MACHINE(pcms); 1014 uint64_t hole64_start = 0; 1015 ram_addr_t size = 0; 1016 1017 if (pcms->cxl_devices_state.is_enabled) { 1018 hole64_start = pc_get_cxl_range_end(pcms); 1019 } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_size)) { 1020 pc_get_device_memory_range(pcms, &hole64_start, &size); 1021 hole64_start += size; 1022 } else { 1023 hole64_start = pc_above_4g_end(pcms); 1024 } 1025 1026 return ROUND_UP(hole64_start, 1 * GiB); 1027 } 1028 1029 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1030 { 1031 DeviceState *dev = NULL; 1032 1033 if (pci_bus) { 1034 PCIDevice *pcidev = pci_vga_init(pci_bus); 1035 dev = pcidev ? &pcidev->qdev : NULL; 1036 } else if (isa_bus) { 1037 ISADevice *isadev = isa_vga_init(isa_bus); 1038 dev = isadev ? DEVICE(isadev) : NULL; 1039 } 1040 1041 return dev; 1042 } 1043 1044 static const MemoryRegionOps ioport80_io_ops = { 1045 .write = ioport80_write, 1046 .read = ioport80_read, 1047 .endianness = DEVICE_LITTLE_ENDIAN, 1048 .impl = { 1049 .min_access_size = 1, 1050 .max_access_size = 1, 1051 }, 1052 }; 1053 1054 static const MemoryRegionOps ioportF0_io_ops = { 1055 .write = ioportF0_write, 1056 .read = ioportF0_read, 1057 .endianness = DEVICE_LITTLE_ENDIAN, 1058 .impl = { 1059 .min_access_size = 1, 1060 .max_access_size = 1, 1061 }, 1062 }; 1063 1064 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, 1065 bool create_i8042, bool no_vmport, Error **errp) 1066 { 1067 int i; 1068 DriveInfo *fd[MAX_FD]; 1069 qemu_irq *a20_line; 1070 ISADevice *i8042, *port92, *vmmouse; 1071 1072 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1073 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1074 1075 for (i = 0; i < MAX_FD; i++) { 1076 fd[i] = drive_get(IF_FLOPPY, 0, i); 1077 create_fdctrl |= !!fd[i]; 1078 } 1079 if (create_fdctrl) { 1080 #ifdef CONFIG_FDC_ISA 1081 ISADevice *fdc = isa_new(TYPE_ISA_FDC); 1082 if (fdc) { 1083 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1084 isa_fdc_init_drives(fdc, fd); 1085 } 1086 #endif 1087 } 1088 1089 if (!create_i8042) { 1090 if (!no_vmport) { 1091 error_setg(errp, 1092 "vmport requires the i8042 controller to be enabled"); 1093 } 1094 return; 1095 } 1096 1097 i8042 = isa_create_simple(isa_bus, TYPE_I8042); 1098 if (!no_vmport) { 1099 isa_create_simple(isa_bus, TYPE_VMPORT); 1100 vmmouse = isa_try_new("vmmouse"); 1101 } else { 1102 vmmouse = NULL; 1103 } 1104 if (vmmouse) { 1105 object_property_set_link(OBJECT(vmmouse), TYPE_I8042, OBJECT(i8042), 1106 &error_abort); 1107 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1108 } 1109 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1110 1111 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1112 qdev_connect_gpio_out_named(DEVICE(i8042), 1113 I8042_A20_LINE, 0, a20_line[0]); 1114 qdev_connect_gpio_out_named(DEVICE(port92), 1115 PORT92_A20_LINE, 0, a20_line[1]); 1116 g_free(a20_line); 1117 } 1118 1119 void pc_basic_device_init(struct PCMachineState *pcms, 1120 ISABus *isa_bus, qemu_irq *gsi, 1121 ISADevice *rtc_state, 1122 bool create_fdctrl, 1123 uint32_t hpet_irqs) 1124 { 1125 int i; 1126 DeviceState *hpet = NULL; 1127 int pit_isa_irq = 0; 1128 qemu_irq pit_alt_irq = NULL; 1129 ISADevice *pit = NULL; 1130 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1131 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1132 X86MachineState *x86ms = X86_MACHINE(pcms); 1133 1134 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1135 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1136 1137 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1138 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1139 1140 /* 1141 * Check if an HPET shall be created. 1142 */ 1143 if (pcms->hpet_enabled) { 1144 qemu_irq rtc_irq; 1145 1146 hpet = qdev_try_new(TYPE_HPET); 1147 if (!hpet) { 1148 error_report("couldn't create HPET device"); 1149 exit(1); 1150 } 1151 /* 1152 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-*, 1153 * use IRQ16~23, IRQ8 and IRQ2. If the user has already set 1154 * the property, use whatever mask they specified. 1155 */ 1156 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1157 HPET_INTCAP, NULL); 1158 if (!compat) { 1159 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1160 } 1161 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1162 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1163 1164 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 1165 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1166 } 1167 pit_isa_irq = -1; 1168 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1169 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1170 1171 /* overwrite connection created by south bridge */ 1172 qdev_connect_gpio_out(DEVICE(rtc_state), 0, rtc_irq); 1173 } 1174 1175 object_property_add_alias(OBJECT(pcms), "rtc-time", OBJECT(rtc_state), 1176 "date"); 1177 1178 #ifdef CONFIG_XEN_EMU 1179 if (xen_mode == XEN_EMULATE) { 1180 xen_overlay_create(); 1181 xen_evtchn_create(IOAPIC_NUM_PINS, gsi); 1182 xen_gnttab_create(); 1183 xen_xenstore_create(); 1184 if (pcms->pcibus) { 1185 pci_create_simple(pcms->pcibus, -1, "xen-platform"); 1186 } 1187 xen_bus_init(); 1188 } 1189 #endif 1190 1191 qemu_register_boot_set(pc_boot_set, pcms); 1192 set_boot_dev(pcms, MC146818_RTC(rtc_state), 1193 MACHINE(pcms)->boot_config.order, &error_fatal); 1194 1195 if (!xen_enabled() && 1196 (x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) { 1197 if (kvm_pit_in_kernel()) { 1198 pit = kvm_pit_init(isa_bus, 0x40); 1199 } else { 1200 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1201 } 1202 if (hpet) { 1203 /* connect PIT to output control line of the HPET */ 1204 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1205 } 1206 object_property_set_link(OBJECT(pcms->pcspk), "pit", 1207 OBJECT(pit), &error_fatal); 1208 isa_realize_and_unref(pcms->pcspk, isa_bus, &error_fatal); 1209 } 1210 1211 if (pcms->vmport == ON_OFF_AUTO_AUTO) { 1212 pcms->vmport = (xen_enabled() || !pcms->i8042_enabled) 1213 ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON; 1214 } 1215 1216 /* Super I/O */ 1217 pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, 1218 pcms->vmport != ON_OFF_AUTO_ON, &error_fatal); 1219 1220 pcms->machine_done.notify = pc_machine_done; 1221 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1222 } 1223 1224 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1225 { 1226 MachineClass *mc = MACHINE_CLASS(pcmc); 1227 bool default_is_ne2k = g_str_equal(mc->default_nic, TYPE_ISA_NE2000); 1228 NICInfo *nd; 1229 1230 while ((nd = qemu_find_nic_info(TYPE_ISA_NE2000, default_is_ne2k, NULL))) { 1231 pc_init_ne2k_isa(isa_bus, nd, &error_fatal); 1232 } 1233 1234 /* Anything remaining should be a PCI NIC */ 1235 if (pci_bus) { 1236 pci_init_nic_devices(pci_bus, mc->default_nic); 1237 } 1238 } 1239 1240 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1241 { 1242 qemu_irq *i8259; 1243 1244 if (kvm_pic_in_kernel()) { 1245 i8259 = kvm_i8259_init(isa_bus); 1246 } else if (xen_enabled()) { 1247 i8259 = xen_interrupt_controller_init(); 1248 } else { 1249 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1250 } 1251 1252 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1253 i8259_irqs[i] = i8259[i]; 1254 } 1255 1256 g_free(i8259); 1257 } 1258 1259 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1260 Error **errp) 1261 { 1262 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1263 const MachineState *ms = MACHINE(hotplug_dev); 1264 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1265 Error *local_err = NULL; 1266 1267 /* 1268 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1269 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1270 * addition to cover this case. 1271 */ 1272 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1273 error_setg(errp, 1274 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1275 return; 1276 } 1277 1278 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1279 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1280 return; 1281 } 1282 1283 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1284 if (local_err) { 1285 error_propagate(errp, local_err); 1286 return; 1287 } 1288 1289 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp); 1290 } 1291 1292 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1293 DeviceState *dev, Error **errp) 1294 { 1295 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1296 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1297 MachineState *ms = MACHINE(hotplug_dev); 1298 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1299 1300 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1301 1302 if (is_nvdimm) { 1303 nvdimm_plug(ms->nvdimms_state); 1304 } 1305 1306 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1307 } 1308 1309 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1310 DeviceState *dev, Error **errp) 1311 { 1312 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1313 1314 /* 1315 * When "acpi=off" is used with the Q35 machine type, no ACPI is built, 1316 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1317 * addition to cover this case. 1318 */ 1319 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1320 error_setg(errp, 1321 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1322 return; 1323 } 1324 1325 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1326 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1327 return; 1328 } 1329 1330 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1331 errp); 1332 } 1333 1334 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1335 DeviceState *dev, Error **errp) 1336 { 1337 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1338 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1339 Error *local_err = NULL; 1340 1341 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1342 if (local_err) { 1343 goto out; 1344 } 1345 1346 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1347 qdev_unrealize(dev); 1348 out: 1349 error_propagate(errp, local_err); 1350 } 1351 1352 static void pc_hv_balloon_pre_plug(HotplugHandler *hotplug_dev, 1353 DeviceState *dev, Error **errp) 1354 { 1355 /* The vmbus handler has no hotplug handler; we should never end up here. */ 1356 g_assert(!dev->hotplugged); 1357 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), errp); 1358 } 1359 1360 static void pc_hv_balloon_plug(HotplugHandler *hotplug_dev, 1361 DeviceState *dev, Error **errp) 1362 { 1363 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1364 } 1365 1366 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1367 DeviceState *dev, Error **errp) 1368 { 1369 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1370 pc_memory_pre_plug(hotplug_dev, dev, errp); 1371 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1372 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1373 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1374 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1375 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1376 /* Declare the APIC range as the reserved MSI region */ 1377 char *resv_prop_str = g_strdup_printf("0xfee00000:0xfeefffff:%d", 1378 VIRTIO_IOMMU_RESV_MEM_T_MSI); 1379 QList *reserved_regions = qlist_new(); 1380 1381 qlist_append_str(reserved_regions, resv_prop_str); 1382 qdev_prop_set_array(dev, "reserved-regions", reserved_regions); 1383 1384 g_free(resv_prop_str); 1385 } 1386 1387 if (object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE) || 1388 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { 1389 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1390 1391 if (pcms->iommu) { 1392 error_setg(errp, "QEMU does not support multiple vIOMMUs " 1393 "for x86 yet."); 1394 return; 1395 } 1396 pcms->iommu = dev; 1397 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1398 pc_hv_balloon_pre_plug(hotplug_dev, dev, errp); 1399 } 1400 } 1401 1402 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1403 DeviceState *dev, Error **errp) 1404 { 1405 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1406 pc_memory_plug(hotplug_dev, dev, errp); 1407 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1408 x86_cpu_plug(hotplug_dev, dev, errp); 1409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1410 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON)) { 1412 pc_hv_balloon_plug(hotplug_dev, dev, errp); 1413 } 1414 } 1415 1416 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1417 DeviceState *dev, Error **errp) 1418 { 1419 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1420 pc_memory_unplug_request(hotplug_dev, dev, errp); 1421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1422 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1423 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1424 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), 1425 errp); 1426 } else { 1427 error_setg(errp, "acpi: device unplug request for not supported device" 1428 " type: %s", object_get_typename(OBJECT(dev))); 1429 } 1430 } 1431 1432 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1433 DeviceState *dev, Error **errp) 1434 { 1435 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1436 pc_memory_unplug(hotplug_dev, dev, errp); 1437 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1438 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1439 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) { 1440 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp); 1441 } else { 1442 error_setg(errp, "acpi: device unplug for not supported device" 1443 " type: %s", object_get_typename(OBJECT(dev))); 1444 } 1445 } 1446 1447 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1448 DeviceState *dev) 1449 { 1450 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1451 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1452 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) || 1453 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || 1454 object_dynamic_cast(OBJECT(dev), TYPE_HV_BALLOON) || 1455 object_dynamic_cast(OBJECT(dev), TYPE_X86_IOMMU_DEVICE)) { 1456 return HOTPLUG_HANDLER(machine); 1457 } 1458 1459 return NULL; 1460 } 1461 1462 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1463 void *opaque, Error **errp) 1464 { 1465 PCMachineState *pcms = PC_MACHINE(obj); 1466 OnOffAuto vmport = pcms->vmport; 1467 1468 visit_type_OnOffAuto(v, name, &vmport, errp); 1469 } 1470 1471 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1472 void *opaque, Error **errp) 1473 { 1474 PCMachineState *pcms = PC_MACHINE(obj); 1475 1476 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1477 } 1478 1479 static bool pc_machine_get_fd_bootchk(Object *obj, Error **errp) 1480 { 1481 PCMachineState *pcms = PC_MACHINE(obj); 1482 1483 return pcms->fd_bootchk; 1484 } 1485 1486 static void pc_machine_set_fd_bootchk(Object *obj, bool value, Error **errp) 1487 { 1488 PCMachineState *pcms = PC_MACHINE(obj); 1489 1490 pcms->fd_bootchk = value; 1491 } 1492 1493 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1494 { 1495 PCMachineState *pcms = PC_MACHINE(obj); 1496 1497 return pcms->smbus_enabled; 1498 } 1499 1500 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1501 { 1502 PCMachineState *pcms = PC_MACHINE(obj); 1503 1504 pcms->smbus_enabled = value; 1505 } 1506 1507 static bool pc_machine_get_sata(Object *obj, Error **errp) 1508 { 1509 PCMachineState *pcms = PC_MACHINE(obj); 1510 1511 return pcms->sata_enabled; 1512 } 1513 1514 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1515 { 1516 PCMachineState *pcms = PC_MACHINE(obj); 1517 1518 pcms->sata_enabled = value; 1519 } 1520 1521 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1522 { 1523 PCMachineState *pcms = PC_MACHINE(obj); 1524 1525 return pcms->hpet_enabled; 1526 } 1527 1528 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1529 { 1530 PCMachineState *pcms = PC_MACHINE(obj); 1531 1532 pcms->hpet_enabled = value; 1533 } 1534 1535 static bool pc_machine_get_i8042(Object *obj, Error **errp) 1536 { 1537 PCMachineState *pcms = PC_MACHINE(obj); 1538 1539 return pcms->i8042_enabled; 1540 } 1541 1542 static void pc_machine_set_i8042(Object *obj, bool value, Error **errp) 1543 { 1544 PCMachineState *pcms = PC_MACHINE(obj); 1545 1546 pcms->i8042_enabled = value; 1547 } 1548 1549 static bool pc_machine_get_default_bus_bypass_iommu(Object *obj, Error **errp) 1550 { 1551 PCMachineState *pcms = PC_MACHINE(obj); 1552 1553 return pcms->default_bus_bypass_iommu; 1554 } 1555 1556 static void pc_machine_set_default_bus_bypass_iommu(Object *obj, bool value, 1557 Error **errp) 1558 { 1559 PCMachineState *pcms = PC_MACHINE(obj); 1560 1561 pcms->default_bus_bypass_iommu = value; 1562 } 1563 1564 static void pc_machine_get_smbios_ep(Object *obj, Visitor *v, const char *name, 1565 void *opaque, Error **errp) 1566 { 1567 PCMachineState *pcms = PC_MACHINE(obj); 1568 SmbiosEntryPointType smbios_entry_point_type = pcms->smbios_entry_point_type; 1569 1570 visit_type_SmbiosEntryPointType(v, name, &smbios_entry_point_type, errp); 1571 } 1572 1573 static void pc_machine_set_smbios_ep(Object *obj, Visitor *v, const char *name, 1574 void *opaque, Error **errp) 1575 { 1576 PCMachineState *pcms = PC_MACHINE(obj); 1577 1578 visit_type_SmbiosEntryPointType(v, name, &pcms->smbios_entry_point_type, errp); 1579 } 1580 1581 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1582 const char *name, void *opaque, 1583 Error **errp) 1584 { 1585 PCMachineState *pcms = PC_MACHINE(obj); 1586 uint64_t value = pcms->max_ram_below_4g; 1587 1588 visit_type_size(v, name, &value, errp); 1589 } 1590 1591 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1592 const char *name, void *opaque, 1593 Error **errp) 1594 { 1595 PCMachineState *pcms = PC_MACHINE(obj); 1596 uint64_t value; 1597 1598 if (!visit_type_size(v, name, &value, errp)) { 1599 return; 1600 } 1601 if (value > 4 * GiB) { 1602 error_setg(errp, 1603 "Machine option 'max-ram-below-4g=%"PRIu64 1604 "' expects size less than or equal to 4G", value); 1605 return; 1606 } 1607 1608 if (value < 1 * MiB) { 1609 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1610 "BIOS may not work with less than 1MiB", value); 1611 } 1612 1613 pcms->max_ram_below_4g = value; 1614 } 1615 1616 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1617 const char *name, void *opaque, 1618 Error **errp) 1619 { 1620 PCMachineState *pcms = PC_MACHINE(obj); 1621 uint64_t value = pcms->max_fw_size; 1622 1623 visit_type_size(v, name, &value, errp); 1624 } 1625 1626 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1627 const char *name, void *opaque, 1628 Error **errp) 1629 { 1630 PCMachineState *pcms = PC_MACHINE(obj); 1631 uint64_t value; 1632 1633 if (!visit_type_size(v, name, &value, errp)) { 1634 return; 1635 } 1636 1637 /* 1638 * We don't have a theoretically justifiable exact lower bound on the base 1639 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1640 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1641 * only 18MiB-4KiB below 4GiB. For now, restrict the cumulative mapping to 1642 * 16MiB in size. 1643 */ 1644 if (value > 16 * MiB) { 1645 error_setg(errp, 1646 "User specified max allowed firmware size %" PRIu64 " is " 1647 "greater than 16MiB. If combined firmware size exceeds " 1648 "16MiB the system may not boot, or experience intermittent" 1649 "stability issues.", 1650 value); 1651 return; 1652 } 1653 1654 pcms->max_fw_size = value; 1655 } 1656 1657 1658 static void pc_machine_initfn(Object *obj) 1659 { 1660 PCMachineState *pcms = PC_MACHINE(obj); 1661 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1662 1663 #ifdef CONFIG_VMPORT 1664 pcms->vmport = ON_OFF_AUTO_AUTO; 1665 #else 1666 pcms->vmport = ON_OFF_AUTO_OFF; 1667 #endif /* CONFIG_VMPORT */ 1668 pcms->max_ram_below_4g = 0; /* use default */ 1669 pcms->smbios_entry_point_type = pcmc->default_smbios_ep_type; 1670 pcms->south_bridge = pcmc->default_south_bridge; 1671 1672 /* acpi build is enabled by default if machine supports it */ 1673 pcms->acpi_build_enabled = pcmc->has_acpi_build; 1674 pcms->smbus_enabled = true; 1675 pcms->sata_enabled = true; 1676 pcms->i8042_enabled = true; 1677 pcms->max_fw_size = 8 * MiB; 1678 #if defined(CONFIG_HPET) 1679 pcms->hpet_enabled = true; 1680 #endif 1681 pcms->fd_bootchk = true; 1682 pcms->default_bus_bypass_iommu = false; 1683 1684 pc_system_flash_create(pcms); 1685 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1686 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1687 OBJECT(pcms->pcspk), "audiodev"); 1688 if (pcmc->pci_enabled) { 1689 cxl_machine_init(obj, &pcms->cxl_devices_state); 1690 } 1691 } 1692 1693 static void pc_machine_reset(MachineState *machine, ResetType type) 1694 { 1695 CPUState *cs; 1696 X86CPU *cpu; 1697 1698 qemu_devices_reset(type); 1699 1700 /* Reset APIC after devices have been reset to cancel 1701 * any changes that qemu_devices_reset() might have done. 1702 */ 1703 CPU_FOREACH(cs) { 1704 cpu = X86_CPU(cs); 1705 1706 x86_cpu_after_reset(cpu); 1707 } 1708 } 1709 1710 static void pc_machine_wakeup(MachineState *machine) 1711 { 1712 cpu_synchronize_all_states(); 1713 pc_machine_reset(machine, RESET_TYPE_WAKEUP); 1714 cpu_synchronize_all_post_reset(); 1715 } 1716 1717 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1718 { 1719 X86IOMMUState *iommu = x86_iommu_get_default(); 1720 IntelIOMMUState *intel_iommu; 1721 1722 if (iommu && 1723 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1724 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1725 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1726 if (!intel_iommu->caching_mode) { 1727 error_setg(errp, "Device assignment is not allowed without " 1728 "enabling caching-mode=on for Intel IOMMU."); 1729 return false; 1730 } 1731 } 1732 1733 return true; 1734 } 1735 1736 static void pc_machine_class_init(ObjectClass *oc, const void *data) 1737 { 1738 MachineClass *mc = MACHINE_CLASS(oc); 1739 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc); 1740 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1741 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1742 1743 pcmc->pci_enabled = true; 1744 pcmc->has_acpi_build = true; 1745 pcmc->smbios_defaults = true; 1746 pcmc->gigabyte_align = true; 1747 pcmc->has_reserved_memory = true; 1748 pcmc->enforce_amd_1tb_hole = true; 1749 pcmc->isa_bios_alias = true; 1750 pcmc->pvh_enabled = true; 1751 pcmc->kvmclock_create_always = true; 1752 x86mc->apic_xrupt_override = true; 1753 assert(!mc->get_hotplug_handler); 1754 mc->get_hotplug_handler = pc_get_hotplug_handler; 1755 mc->hotplug_allowed = pc_hotplug_allowed; 1756 mc->auto_enable_numa_with_memhp = true; 1757 mc->auto_enable_numa_with_memdev = true; 1758 mc->has_hotpluggable_cpus = true; 1759 mc->default_boot_order = "cad"; 1760 mc->block_default_type = IF_IDE; 1761 mc->max_cpus = 255; 1762 mc->reset = pc_machine_reset; 1763 mc->wakeup = pc_machine_wakeup; 1764 hc->pre_plug = pc_machine_device_pre_plug_cb; 1765 hc->plug = pc_machine_device_plug_cb; 1766 hc->unplug_request = pc_machine_device_unplug_request_cb; 1767 hc->unplug = pc_machine_device_unplug_cb; 1768 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1769 mc->nvdimm_supported = true; 1770 mc->smp_props.dies_supported = true; 1771 mc->smp_props.modules_supported = true; 1772 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true; 1773 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true; 1774 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true; 1775 mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true; 1776 mc->default_ram_id = "pc.ram"; 1777 pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO; 1778 1779 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1780 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1781 NULL, NULL); 1782 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1783 "Maximum ram below the 4G boundary (32bit boundary)"); 1784 1785 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1786 pc_machine_get_vmport, pc_machine_set_vmport, 1787 NULL, NULL); 1788 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1789 "Enable vmport (pc & q35)"); 1790 1791 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1792 pc_machine_get_smbus, pc_machine_set_smbus); 1793 object_class_property_set_description(oc, PC_MACHINE_SMBUS, 1794 "Enable/disable system management bus"); 1795 1796 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1797 pc_machine_get_sata, pc_machine_set_sata); 1798 object_class_property_set_description(oc, PC_MACHINE_SATA, 1799 "Enable/disable Serial ATA bus"); 1800 1801 object_class_property_add_bool(oc, "hpet", 1802 pc_machine_get_hpet, pc_machine_set_hpet); 1803 object_class_property_set_description(oc, "hpet", 1804 "Enable/disable high precision event timer emulation"); 1805 1806 object_class_property_add_bool(oc, PC_MACHINE_I8042, 1807 pc_machine_get_i8042, pc_machine_set_i8042); 1808 object_class_property_set_description(oc, PC_MACHINE_I8042, 1809 "Enable/disable Intel 8042 PS/2 controller emulation"); 1810 1811 object_class_property_add_bool(oc, "default-bus-bypass-iommu", 1812 pc_machine_get_default_bus_bypass_iommu, 1813 pc_machine_set_default_bus_bypass_iommu); 1814 1815 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1816 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1817 NULL, NULL); 1818 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1819 "Maximum combined firmware size"); 1820 1821 object_class_property_add(oc, PC_MACHINE_SMBIOS_EP, "str", 1822 pc_machine_get_smbios_ep, pc_machine_set_smbios_ep, 1823 NULL, NULL); 1824 object_class_property_set_description(oc, PC_MACHINE_SMBIOS_EP, 1825 "SMBIOS Entry Point type [32, 64]"); 1826 1827 object_class_property_add_bool(oc, "fd-bootchk", 1828 pc_machine_get_fd_bootchk, 1829 pc_machine_set_fd_bootchk); 1830 } 1831 1832 static const TypeInfo pc_machine_info = { 1833 .name = TYPE_PC_MACHINE, 1834 .parent = TYPE_X86_MACHINE, 1835 .abstract = true, 1836 .instance_size = sizeof(PCMachineState), 1837 .instance_init = pc_machine_initfn, 1838 .class_size = sizeof(PCMachineClass), 1839 .class_init = pc_machine_class_init, 1840 .interfaces = (const InterfaceInfo[]) { 1841 { TYPE_HOTPLUG_HANDLER }, 1842 { } 1843 }, 1844 }; 1845 1846 static void pc_machine_register_types(void) 1847 { 1848 type_register_static(&pc_machine_info); 1849 } 1850 1851 type_init(pc_machine_register_types) 1852