1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/i386/x86.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "hw/i386/vmport.h" 35 #include "sysemu/cpus.h" 36 #include "hw/block/fdc.h" 37 #include "hw/ide.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_bus.h" 40 #include "hw/nvram/fw_cfg.h" 41 #include "hw/timer/hpet.h" 42 #include "hw/firmware/smbios.h" 43 #include "hw/loader.h" 44 #include "elf.h" 45 #include "migration/vmstate.h" 46 #include "multiboot.h" 47 #include "hw/rtc/mc146818rtc.h" 48 #include "hw/intc/i8259.h" 49 #include "hw/dma/i8257.h" 50 #include "hw/timer/i8254.h" 51 #include "hw/input/i8042.h" 52 #include "hw/irq.h" 53 #include "hw/audio/pcspk.h" 54 #include "hw/pci/msi.h" 55 #include "hw/sysbus.h" 56 #include "sysemu/sysemu.h" 57 #include "sysemu/tcg.h" 58 #include "sysemu/numa.h" 59 #include "sysemu/kvm.h" 60 #include "sysemu/xen.h" 61 #include "sysemu/reset.h" 62 #include "sysemu/runstate.h" 63 #include "kvm/kvm_i386.h" 64 #include "hw/xen/xen.h" 65 #include "hw/xen/start_info.h" 66 #include "ui/qemu-spice.h" 67 #include "exec/memory.h" 68 #include "sysemu/arch_init.h" 69 #include "qemu/bitmap.h" 70 #include "qemu/config-file.h" 71 #include "qemu/error-report.h" 72 #include "qemu/option.h" 73 #include "qemu/cutils.h" 74 #include "hw/acpi/acpi.h" 75 #include "hw/acpi/cpu_hotplug.h" 76 #include "acpi-build.h" 77 #include "hw/mem/pc-dimm.h" 78 #include "hw/mem/nvdimm.h" 79 #include "qapi/error.h" 80 #include "qapi/qapi-visit-common.h" 81 #include "qapi/visitor.h" 82 #include "hw/core/cpu.h" 83 #include "hw/usb.h" 84 #include "hw/i386/intel_iommu.h" 85 #include "hw/net/ne2000-isa.h" 86 #include "standard-headers/asm-x86/bootparam.h" 87 #include "hw/virtio/virtio-pmem-pci.h" 88 #include "hw/virtio/virtio-mem-pci.h" 89 #include "hw/mem/memory-device.h" 90 #include "sysemu/replay.h" 91 #include "qapi/qmp/qerror.h" 92 #include "e820_memory_layout.h" 93 #include "fw_cfg.h" 94 #include "trace.h" 95 #include CONFIG_DEVICES 96 97 GlobalProperty pc_compat_6_0[] = { 98 { "qemu64" "-" TYPE_X86_CPU, "family", "6" }, 99 { "qemu64" "-" TYPE_X86_CPU, "model", "6" }, 100 { "qemu64" "-" TYPE_X86_CPU, "stepping", "3" }, 101 }; 102 const size_t pc_compat_6_0_len = G_N_ELEMENTS(pc_compat_6_0); 103 104 GlobalProperty pc_compat_5_2[] = { 105 { "ICH9-LPC", "x-smi-cpu-hotunplug", "off" }, 106 }; 107 const size_t pc_compat_5_2_len = G_N_ELEMENTS(pc_compat_5_2); 108 109 GlobalProperty pc_compat_5_1[] = { 110 { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, 111 { TYPE_X86_CPU, "kvm-msi-ext-dest-id", "off" }, 112 }; 113 const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); 114 115 GlobalProperty pc_compat_5_0[] = { 116 }; 117 const size_t pc_compat_5_0_len = G_N_ELEMENTS(pc_compat_5_0); 118 119 GlobalProperty pc_compat_4_2[] = { 120 { "mch", "smbase-smram", "off" }, 121 }; 122 const size_t pc_compat_4_2_len = G_N_ELEMENTS(pc_compat_4_2); 123 124 GlobalProperty pc_compat_4_1[] = {}; 125 const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1); 126 127 GlobalProperty pc_compat_4_0[] = {}; 128 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 129 130 GlobalProperty pc_compat_3_1[] = { 131 { "intel-iommu", "dma-drain", "off" }, 132 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 133 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 134 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 135 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 136 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 137 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 138 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 139 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 140 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 141 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 142 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 143 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 144 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 145 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 146 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 147 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 148 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 149 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 150 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 151 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 152 }; 153 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 154 155 GlobalProperty pc_compat_3_0[] = { 156 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 157 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 158 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 159 }; 160 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 161 162 GlobalProperty pc_compat_2_12[] = { 163 { TYPE_X86_CPU, "legacy-cache", "on" }, 164 { TYPE_X86_CPU, "topoext", "off" }, 165 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 166 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 167 }; 168 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 169 170 GlobalProperty pc_compat_2_11[] = { 171 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 172 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 173 }; 174 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 175 176 GlobalProperty pc_compat_2_10[] = { 177 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 178 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 179 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 180 }; 181 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 182 183 GlobalProperty pc_compat_2_9[] = { 184 { "mch", "extended-tseg-mbytes", "0" }, 185 }; 186 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 187 188 GlobalProperty pc_compat_2_8[] = { 189 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 190 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 191 { "ICH9-LPC", "x-smi-broadcast", "off" }, 192 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 193 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 194 }; 195 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 196 197 GlobalProperty pc_compat_2_7[] = { 198 { TYPE_X86_CPU, "l3-cache", "off" }, 199 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 200 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 201 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 202 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 203 { "isa-pcspk", "migrate", "off" }, 204 }; 205 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 206 207 GlobalProperty pc_compat_2_6[] = { 208 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 209 { "vmxnet3", "romfile", "" }, 210 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 211 { "apic-common", "legacy-instance-id", "on", } 212 }; 213 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 214 215 GlobalProperty pc_compat_2_5[] = {}; 216 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 217 218 GlobalProperty pc_compat_2_4[] = { 219 PC_CPU_MODEL_IDS("2.4.0") 220 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 221 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 222 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 223 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 224 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 225 { TYPE_X86_CPU, "check", "off" }, 226 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 227 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 228 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 229 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 230 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 231 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 232 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 233 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 234 }; 235 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 236 237 GlobalProperty pc_compat_2_3[] = { 238 PC_CPU_MODEL_IDS("2.3.0") 239 { TYPE_X86_CPU, "arat", "off" }, 240 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 241 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 242 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 243 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 244 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 245 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 246 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 247 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 249 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 250 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 251 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 252 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 253 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 254 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 255 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 256 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 257 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 258 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 259 }; 260 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 261 262 GlobalProperty pc_compat_2_2[] = { 263 PC_CPU_MODEL_IDS("2.2.0") 264 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 269 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 270 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 271 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 272 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 273 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 274 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 275 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 276 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 277 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 278 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 279 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 280 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 281 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 282 }; 283 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 284 285 GlobalProperty pc_compat_2_1[] = { 286 PC_CPU_MODEL_IDS("2.1.0") 287 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 288 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 289 }; 290 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 291 292 GlobalProperty pc_compat_2_0[] = { 293 PC_CPU_MODEL_IDS("2.0.0") 294 { "virtio-scsi-pci", "any_layout", "off" }, 295 { "PIIX4_PM", "memory-hotplug-support", "off" }, 296 { "apic", "version", "0x11" }, 297 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 298 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 299 { "pci-serial", "prog_if", "0" }, 300 { "pci-serial-2x", "prog_if", "0" }, 301 { "pci-serial-4x", "prog_if", "0" }, 302 { "virtio-net-pci", "guest_announce", "off" }, 303 { "ICH9-LPC", "memory-hotplug-support", "off" }, 304 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 305 { "ioh3420", COMPAT_PROP_PCP, "off" }, 306 }; 307 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 308 309 GlobalProperty pc_compat_1_7[] = { 310 PC_CPU_MODEL_IDS("1.7.0") 311 { TYPE_USB_DEVICE, "msos-desc", "no" }, 312 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 313 { "hpet", HPET_INTCAP, "4" }, 314 }; 315 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 316 317 GlobalProperty pc_compat_1_6[] = { 318 PC_CPU_MODEL_IDS("1.6.0") 319 { "e1000", "mitigation", "off" }, 320 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 321 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 322 { "i440FX-pcihost", "short_root_bus", "1" }, 323 { "q35-pcihost", "short_root_bus", "1" }, 324 }; 325 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 326 327 GlobalProperty pc_compat_1_5[] = { 328 PC_CPU_MODEL_IDS("1.5.0") 329 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 330 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 331 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 332 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 333 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 334 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 335 { "virtio-net-pci", "any_layout", "off" }, 336 { TYPE_X86_CPU, "pmu", "on" }, 337 { "i440FX-pcihost", "short_root_bus", "0" }, 338 { "q35-pcihost", "short_root_bus", "0" }, 339 }; 340 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 341 342 GlobalProperty pc_compat_1_4[] = { 343 PC_CPU_MODEL_IDS("1.4.0") 344 { "scsi-hd", "discard_granularity", "0" }, 345 { "scsi-cd", "discard_granularity", "0" }, 346 { "ide-hd", "discard_granularity", "0" }, 347 { "ide-cd", "discard_granularity", "0" }, 348 { "virtio-blk-pci", "discard_granularity", "0" }, 349 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 350 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 351 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 352 { "e1000", "romfile", "pxe-e1000.rom" }, 353 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 354 { "pcnet", "romfile", "pxe-pcnet.rom" }, 355 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 356 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 357 { "486-" TYPE_X86_CPU, "model", "0" }, 358 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 359 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 360 }; 361 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 362 363 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled) 364 { 365 GSIState *s; 366 367 s = g_new0(GSIState, 1); 368 if (kvm_ioapic_in_kernel()) { 369 kvm_pc_setup_irq_routing(pci_enabled); 370 } 371 *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS); 372 373 return s; 374 } 375 376 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 377 unsigned size) 378 { 379 } 380 381 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 382 { 383 return 0xffffffffffffffffULL; 384 } 385 386 /* MSDOS compatibility mode FPU exception support */ 387 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 388 unsigned size) 389 { 390 if (tcg_enabled()) { 391 cpu_set_ignne(); 392 } 393 } 394 395 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 396 { 397 return 0xffffffffffffffffULL; 398 } 399 400 /* PC cmos mappings */ 401 402 #define REG_EQUIPMENT_BYTE 0x14 403 404 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 405 int16_t cylinders, int8_t heads, int8_t sectors) 406 { 407 rtc_set_memory(s, type_ofs, 47); 408 rtc_set_memory(s, info_ofs, cylinders); 409 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 410 rtc_set_memory(s, info_ofs + 2, heads); 411 rtc_set_memory(s, info_ofs + 3, 0xff); 412 rtc_set_memory(s, info_ofs + 4, 0xff); 413 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 414 rtc_set_memory(s, info_ofs + 6, cylinders); 415 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 416 rtc_set_memory(s, info_ofs + 8, sectors); 417 } 418 419 /* convert boot_device letter to something recognizable by the bios */ 420 static int boot_device2nibble(char boot_device) 421 { 422 switch(boot_device) { 423 case 'a': 424 case 'b': 425 return 0x01; /* floppy boot */ 426 case 'c': 427 return 0x02; /* hard drive boot */ 428 case 'd': 429 return 0x03; /* CD-ROM boot */ 430 case 'n': 431 return 0x04; /* Network boot */ 432 } 433 return 0; 434 } 435 436 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 437 { 438 #define PC_MAX_BOOT_DEVICES 3 439 int nbds, bds[3] = { 0, }; 440 int i; 441 442 nbds = strlen(boot_device); 443 if (nbds > PC_MAX_BOOT_DEVICES) { 444 error_setg(errp, "Too many boot devices for PC"); 445 return; 446 } 447 for (i = 0; i < nbds; i++) { 448 bds[i] = boot_device2nibble(boot_device[i]); 449 if (bds[i] == 0) { 450 error_setg(errp, "Invalid boot device for PC: '%c'", 451 boot_device[i]); 452 return; 453 } 454 } 455 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 456 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 457 } 458 459 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 460 { 461 set_boot_dev(opaque, boot_device, errp); 462 } 463 464 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 465 { 466 int val, nb, i; 467 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 468 FLOPPY_DRIVE_TYPE_NONE }; 469 470 /* floppy type */ 471 if (floppy) { 472 for (i = 0; i < 2; i++) { 473 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 474 } 475 } 476 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 477 cmos_get_fd_drive_type(fd_type[1]); 478 rtc_set_memory(rtc_state, 0x10, val); 479 480 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 481 nb = 0; 482 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 483 nb++; 484 } 485 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 486 nb++; 487 } 488 switch (nb) { 489 case 0: 490 break; 491 case 1: 492 val |= 0x01; /* 1 drive, ready for boot */ 493 break; 494 case 2: 495 val |= 0x41; /* 2 drives, ready for boot */ 496 break; 497 } 498 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 499 } 500 501 typedef struct pc_cmos_init_late_arg { 502 ISADevice *rtc_state; 503 BusState *idebus[2]; 504 } pc_cmos_init_late_arg; 505 506 typedef struct check_fdc_state { 507 ISADevice *floppy; 508 bool multiple; 509 } CheckFdcState; 510 511 static int check_fdc(Object *obj, void *opaque) 512 { 513 CheckFdcState *state = opaque; 514 Object *fdc; 515 uint32_t iobase; 516 Error *local_err = NULL; 517 518 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 519 if (!fdc) { 520 return 0; 521 } 522 523 iobase = object_property_get_uint(obj, "iobase", &local_err); 524 if (local_err || iobase != 0x3f0) { 525 error_free(local_err); 526 return 0; 527 } 528 529 if (state->floppy) { 530 state->multiple = true; 531 } else { 532 state->floppy = ISA_DEVICE(obj); 533 } 534 return 0; 535 } 536 537 static const char * const fdc_container_path[] = { 538 "/unattached", "/peripheral", "/peripheral-anon" 539 }; 540 541 /* 542 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 543 * and ACPI objects. 544 */ 545 ISADevice *pc_find_fdc0(void) 546 { 547 int i; 548 Object *container; 549 CheckFdcState state = { 0 }; 550 551 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 552 container = container_get(qdev_get_machine(), fdc_container_path[i]); 553 object_child_foreach(container, check_fdc, &state); 554 } 555 556 if (state.multiple) { 557 warn_report("multiple floppy disk controllers with " 558 "iobase=0x3f0 have been found"); 559 error_printf("the one being picked for CMOS setup might not reflect " 560 "your intent"); 561 } 562 563 return state.floppy; 564 } 565 566 static void pc_cmos_init_late(void *opaque) 567 { 568 pc_cmos_init_late_arg *arg = opaque; 569 ISADevice *s = arg->rtc_state; 570 int16_t cylinders; 571 int8_t heads, sectors; 572 int val; 573 int i, trans; 574 575 val = 0; 576 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 577 &cylinders, &heads, §ors) >= 0) { 578 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 579 val |= 0xf0; 580 } 581 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 582 &cylinders, &heads, §ors) >= 0) { 583 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 584 val |= 0x0f; 585 } 586 rtc_set_memory(s, 0x12, val); 587 588 val = 0; 589 for (i = 0; i < 4; i++) { 590 /* NOTE: ide_get_geometry() returns the physical 591 geometry. It is always such that: 1 <= sects <= 63, 1 592 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 593 geometry can be different if a translation is done. */ 594 if (arg->idebus[i / 2] && 595 ide_get_geometry(arg->idebus[i / 2], i % 2, 596 &cylinders, &heads, §ors) >= 0) { 597 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 598 assert((trans & ~3) == 0); 599 val |= trans << (i * 2); 600 } 601 } 602 rtc_set_memory(s, 0x39, val); 603 604 pc_cmos_init_floppy(s, pc_find_fdc0()); 605 606 qemu_unregister_reset(pc_cmos_init_late, opaque); 607 } 608 609 void pc_cmos_init(PCMachineState *pcms, 610 BusState *idebus0, BusState *idebus1, 611 ISADevice *s) 612 { 613 int val; 614 static pc_cmos_init_late_arg arg; 615 X86MachineState *x86ms = X86_MACHINE(pcms); 616 617 /* various important CMOS locations needed by PC/Bochs bios */ 618 619 /* memory size */ 620 /* base memory (first MiB) */ 621 val = MIN(x86ms->below_4g_mem_size / KiB, 640); 622 rtc_set_memory(s, 0x15, val); 623 rtc_set_memory(s, 0x16, val >> 8); 624 /* extended memory (next 64MiB) */ 625 if (x86ms->below_4g_mem_size > 1 * MiB) { 626 val = (x86ms->below_4g_mem_size - 1 * MiB) / KiB; 627 } else { 628 val = 0; 629 } 630 if (val > 65535) 631 val = 65535; 632 rtc_set_memory(s, 0x17, val); 633 rtc_set_memory(s, 0x18, val >> 8); 634 rtc_set_memory(s, 0x30, val); 635 rtc_set_memory(s, 0x31, val >> 8); 636 /* memory between 16MiB and 4GiB */ 637 if (x86ms->below_4g_mem_size > 16 * MiB) { 638 val = (x86ms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 639 } else { 640 val = 0; 641 } 642 if (val > 65535) 643 val = 65535; 644 rtc_set_memory(s, 0x34, val); 645 rtc_set_memory(s, 0x35, val >> 8); 646 /* memory above 4GiB */ 647 val = x86ms->above_4g_mem_size / 65536; 648 rtc_set_memory(s, 0x5b, val); 649 rtc_set_memory(s, 0x5c, val >> 8); 650 rtc_set_memory(s, 0x5d, val >> 16); 651 652 object_property_add_link(OBJECT(pcms), "rtc_state", 653 TYPE_ISA_DEVICE, 654 (Object **)&x86ms->rtc, 655 object_property_allow_set_link, 656 OBJ_PROP_LINK_STRONG); 657 object_property_set_link(OBJECT(pcms), "rtc_state", OBJECT(s), 658 &error_abort); 659 660 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 661 662 val = 0; 663 val |= 0x02; /* FPU is there */ 664 val |= 0x04; /* PS/2 mouse installed */ 665 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 666 667 /* hard drives and FDC */ 668 arg.rtc_state = s; 669 arg.idebus[0] = idebus0; 670 arg.idebus[1] = idebus1; 671 qemu_register_reset(pc_cmos_init_late, &arg); 672 } 673 674 static void handle_a20_line_change(void *opaque, int irq, int level) 675 { 676 X86CPU *cpu = opaque; 677 678 /* XXX: send to all CPUs ? */ 679 /* XXX: add logic to handle multiple A20 line sources */ 680 x86_cpu_set_a20(cpu, level); 681 } 682 683 #define NE2000_NB_MAX 6 684 685 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 686 0x280, 0x380 }; 687 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 688 689 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 690 { 691 static int nb_ne2k = 0; 692 693 if (nb_ne2k == NE2000_NB_MAX) 694 return; 695 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 696 ne2000_irq[nb_ne2k], nd); 697 nb_ne2k++; 698 } 699 700 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 701 { 702 X86CPU *cpu = opaque; 703 704 if (level) { 705 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 706 } 707 } 708 709 /* 710 * This function is very similar to smp_parse() 711 * in hw/core/machine.c but includes CPU die support. 712 */ 713 static void pc_smp_parse(MachineState *ms, SMPConfiguration *config, Error **errp) 714 { 715 unsigned cpus = config->has_cpus ? config->cpus : 0; 716 unsigned sockets = config->has_sockets ? config->sockets : 0; 717 unsigned dies = config->has_dies ? config->dies : 1; 718 unsigned cores = config->has_cores ? config->cores : 0; 719 unsigned threads = config->has_threads ? config->threads : 0; 720 721 /* compute missing values, prefer sockets over cores over threads */ 722 if (cpus == 0 || sockets == 0) { 723 cores = cores > 0 ? cores : 1; 724 threads = threads > 0 ? threads : 1; 725 if (cpus == 0) { 726 sockets = sockets > 0 ? sockets : 1; 727 cpus = cores * threads * dies * sockets; 728 } else { 729 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 730 sockets = ms->smp.max_cpus / (cores * threads * dies); 731 } 732 } else if (cores == 0) { 733 threads = threads > 0 ? threads : 1; 734 cores = cpus / (sockets * dies * threads); 735 cores = cores > 0 ? cores : 1; 736 } else if (threads == 0) { 737 threads = cpus / (cores * dies * sockets); 738 threads = threads > 0 ? threads : 1; 739 } else if (sockets * dies * cores * threads < cpus) { 740 error_setg(errp, "cpu topology: " 741 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) < " 742 "smp_cpus (%u)", 743 sockets, dies, cores, threads, cpus); 744 return; 745 } 746 747 ms->smp.max_cpus = config->has_maxcpus ? config->maxcpus : cpus; 748 749 if (ms->smp.max_cpus < cpus) { 750 error_setg(errp, "maxcpus must be equal to or greater than smp"); 751 return; 752 } 753 754 if (sockets * dies * cores * threads != ms->smp.max_cpus) { 755 error_setg(errp, "Invalid CPU topology deprecated: " 756 "sockets (%u) * dies (%u) * cores (%u) * threads (%u) " 757 "!= maxcpus (%u)", 758 sockets, dies, cores, threads, 759 ms->smp.max_cpus); 760 return; 761 } 762 763 ms->smp.cpus = cpus; 764 ms->smp.cores = cores; 765 ms->smp.threads = threads; 766 ms->smp.sockets = sockets; 767 ms->smp.dies = dies; 768 } 769 770 static 771 void pc_machine_done(Notifier *notifier, void *data) 772 { 773 PCMachineState *pcms = container_of(notifier, 774 PCMachineState, machine_done); 775 X86MachineState *x86ms = X86_MACHINE(pcms); 776 777 /* set the number of CPUs */ 778 x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); 779 780 fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); 781 782 acpi_setup(); 783 if (x86ms->fw_cfg) { 784 fw_cfg_build_smbios(MACHINE(pcms), x86ms->fw_cfg); 785 fw_cfg_build_feature_control(MACHINE(pcms), x86ms->fw_cfg); 786 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 787 fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 788 } 789 790 791 if (x86ms->apic_id_limit > 255 && !xen_enabled() && 792 !kvm_irqchip_in_kernel()) { 793 error_report("current -smp configuration requires kernel " 794 "irqchip support."); 795 exit(EXIT_FAILURE); 796 } 797 } 798 799 void pc_guest_info_init(PCMachineState *pcms) 800 { 801 int i; 802 MachineState *ms = MACHINE(pcms); 803 X86MachineState *x86ms = X86_MACHINE(pcms); 804 805 x86ms->apic_xrupt_override = true; 806 pcms->numa_nodes = ms->numa_state->num_nodes; 807 pcms->node_mem = g_malloc0(pcms->numa_nodes * 808 sizeof *pcms->node_mem); 809 for (i = 0; i < ms->numa_state->num_nodes; i++) { 810 pcms->node_mem[i] = ms->numa_state->nodes[i].node_mem; 811 } 812 813 pcms->machine_done.notify = pc_machine_done; 814 qemu_add_machine_init_done_notifier(&pcms->machine_done); 815 } 816 817 /* setup pci memory address space mapping into system address space */ 818 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 819 MemoryRegion *pci_address_space) 820 { 821 /* Set to lower priority than RAM */ 822 memory_region_add_subregion_overlap(system_memory, 0x0, 823 pci_address_space, -1); 824 } 825 826 void xen_load_linux(PCMachineState *pcms) 827 { 828 int i; 829 FWCfgState *fw_cfg; 830 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 831 X86MachineState *x86ms = X86_MACHINE(pcms); 832 833 assert(MACHINE(pcms)->kernel_filename != NULL); 834 835 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 836 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); 837 rom_set_fw(fw_cfg); 838 839 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 840 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 841 for (i = 0; i < nb_option_roms; i++) { 842 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 843 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 844 !strcmp(option_rom[i].name, "pvh.bin") || 845 !strcmp(option_rom[i].name, "multiboot.bin")); 846 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 847 } 848 x86ms->fw_cfg = fw_cfg; 849 } 850 851 void pc_memory_init(PCMachineState *pcms, 852 MemoryRegion *system_memory, 853 MemoryRegion *rom_memory, 854 MemoryRegion **ram_memory) 855 { 856 int linux_boot, i; 857 MemoryRegion *option_rom_mr; 858 MemoryRegion *ram_below_4g, *ram_above_4g; 859 FWCfgState *fw_cfg; 860 MachineState *machine = MACHINE(pcms); 861 MachineClass *mc = MACHINE_GET_CLASS(machine); 862 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 863 X86MachineState *x86ms = X86_MACHINE(pcms); 864 865 assert(machine->ram_size == x86ms->below_4g_mem_size + 866 x86ms->above_4g_mem_size); 867 868 linux_boot = (machine->kernel_filename != NULL); 869 870 /* 871 * Split single memory region and use aliases to address portions of it, 872 * done for backwards compatibility with older qemus. 873 */ 874 *ram_memory = machine->ram; 875 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 876 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 877 0, x86ms->below_4g_mem_size); 878 memory_region_add_subregion(system_memory, 0, ram_below_4g); 879 e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); 880 if (x86ms->above_4g_mem_size > 0) { 881 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 882 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", 883 machine->ram, 884 x86ms->below_4g_mem_size, 885 x86ms->above_4g_mem_size); 886 memory_region_add_subregion(system_memory, 0x100000000ULL, 887 ram_above_4g); 888 e820_add_entry(0x100000000ULL, x86ms->above_4g_mem_size, E820_RAM); 889 } 890 891 if (!pcmc->has_reserved_memory && 892 (machine->ram_slots || 893 (machine->maxram_size > machine->ram_size))) { 894 895 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 896 mc->name); 897 exit(EXIT_FAILURE); 898 } 899 900 /* always allocate the device memory information */ 901 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 902 903 /* initialize device memory address space */ 904 if (pcmc->has_reserved_memory && 905 (machine->ram_size < machine->maxram_size)) { 906 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 907 908 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 909 error_report("unsupported amount of memory slots: %"PRIu64, 910 machine->ram_slots); 911 exit(EXIT_FAILURE); 912 } 913 914 if (QEMU_ALIGN_UP(machine->maxram_size, 915 TARGET_PAGE_SIZE) != machine->maxram_size) { 916 error_report("maximum memory size must by aligned to multiple of " 917 "%d bytes", TARGET_PAGE_SIZE); 918 exit(EXIT_FAILURE); 919 } 920 921 machine->device_memory->base = 922 ROUND_UP(0x100000000ULL + x86ms->above_4g_mem_size, 1 * GiB); 923 924 if (pcmc->enforce_aligned_dimm) { 925 /* size device region assuming 1G page max alignment per slot */ 926 device_mem_size += (1 * GiB) * machine->ram_slots; 927 } 928 929 if ((machine->device_memory->base + device_mem_size) < 930 device_mem_size) { 931 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 932 machine->maxram_size); 933 exit(EXIT_FAILURE); 934 } 935 936 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 937 "device-memory", device_mem_size); 938 memory_region_add_subregion(system_memory, machine->device_memory->base, 939 &machine->device_memory->mr); 940 } 941 942 /* Initialize PC system firmware */ 943 pc_system_firmware_init(pcms, rom_memory); 944 945 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 946 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 947 &error_fatal); 948 if (pcmc->pci_enabled) { 949 memory_region_set_readonly(option_rom_mr, true); 950 } 951 memory_region_add_subregion_overlap(rom_memory, 952 PC_ROM_MIN_VGA, 953 option_rom_mr, 954 1); 955 956 fw_cfg = fw_cfg_arch_create(machine, 957 x86ms->boot_cpus, x86ms->apic_id_limit); 958 959 rom_set_fw(fw_cfg); 960 961 if (pcmc->has_reserved_memory && machine->device_memory->base) { 962 uint64_t *val = g_malloc(sizeof(*val)); 963 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 964 uint64_t res_mem_end = machine->device_memory->base; 965 966 if (!pcmc->broken_reserved_end) { 967 res_mem_end += memory_region_size(&machine->device_memory->mr); 968 } 969 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 970 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 971 } 972 973 if (linux_boot) { 974 x86_load_linux(x86ms, fw_cfg, pcmc->acpi_data_size, 975 pcmc->pvh_enabled, pcmc->linuxboot_dma_enabled); 976 } 977 978 for (i = 0; i < nb_option_roms; i++) { 979 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 980 } 981 x86ms->fw_cfg = fw_cfg; 982 983 /* Init default IOAPIC address space */ 984 x86ms->ioapic_as = &address_space_memory; 985 986 /* Init ACPI memory hotplug IO base address */ 987 pcms->memhp_io_base = ACPI_MEMORY_HOTPLUG_BASE; 988 } 989 990 /* 991 * The 64bit pci hole starts after "above 4G RAM" and 992 * potentially the space reserved for memory hotplug. 993 */ 994 uint64_t pc_pci_hole64_start(void) 995 { 996 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 997 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 998 MachineState *ms = MACHINE(pcms); 999 X86MachineState *x86ms = X86_MACHINE(pcms); 1000 uint64_t hole64_start = 0; 1001 1002 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1003 hole64_start = ms->device_memory->base; 1004 if (!pcmc->broken_reserved_end) { 1005 hole64_start += memory_region_size(&ms->device_memory->mr); 1006 } 1007 } else { 1008 hole64_start = 0x100000000ULL + x86ms->above_4g_mem_size; 1009 } 1010 1011 return ROUND_UP(hole64_start, 1 * GiB); 1012 } 1013 1014 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1015 { 1016 DeviceState *dev = NULL; 1017 1018 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1019 if (pci_bus) { 1020 PCIDevice *pcidev = pci_vga_init(pci_bus); 1021 dev = pcidev ? &pcidev->qdev : NULL; 1022 } else if (isa_bus) { 1023 ISADevice *isadev = isa_vga_init(isa_bus); 1024 dev = isadev ? DEVICE(isadev) : NULL; 1025 } 1026 rom_reset_order_override(); 1027 return dev; 1028 } 1029 1030 static const MemoryRegionOps ioport80_io_ops = { 1031 .write = ioport80_write, 1032 .read = ioport80_read, 1033 .endianness = DEVICE_NATIVE_ENDIAN, 1034 .impl = { 1035 .min_access_size = 1, 1036 .max_access_size = 1, 1037 }, 1038 }; 1039 1040 static const MemoryRegionOps ioportF0_io_ops = { 1041 .write = ioportF0_write, 1042 .read = ioportF0_read, 1043 .endianness = DEVICE_NATIVE_ENDIAN, 1044 .impl = { 1045 .min_access_size = 1, 1046 .max_access_size = 1, 1047 }, 1048 }; 1049 1050 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1051 { 1052 int i; 1053 DriveInfo *fd[MAX_FD]; 1054 qemu_irq *a20_line; 1055 ISADevice *fdc, *i8042, *port92, *vmmouse; 1056 1057 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1058 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1059 1060 for (i = 0; i < MAX_FD; i++) { 1061 fd[i] = drive_get(IF_FLOPPY, 0, i); 1062 create_fdctrl |= !!fd[i]; 1063 } 1064 if (create_fdctrl) { 1065 fdc = isa_new(TYPE_ISA_FDC); 1066 if (fdc) { 1067 isa_realize_and_unref(fdc, isa_bus, &error_fatal); 1068 isa_fdc_init_drives(fdc, fd); 1069 } 1070 } 1071 1072 i8042 = isa_create_simple(isa_bus, "i8042"); 1073 if (!no_vmport) { 1074 isa_create_simple(isa_bus, TYPE_VMPORT); 1075 vmmouse = isa_try_new("vmmouse"); 1076 } else { 1077 vmmouse = NULL; 1078 } 1079 if (vmmouse) { 1080 object_property_set_link(OBJECT(vmmouse), "i8042", OBJECT(i8042), 1081 &error_abort); 1082 isa_realize_and_unref(vmmouse, isa_bus, &error_fatal); 1083 } 1084 port92 = isa_create_simple(isa_bus, TYPE_PORT92); 1085 1086 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1087 i8042_setup_a20_line(i8042, a20_line[0]); 1088 qdev_connect_gpio_out_named(DEVICE(port92), 1089 PORT92_A20_LINE, 0, a20_line[1]); 1090 g_free(a20_line); 1091 } 1092 1093 void pc_basic_device_init(struct PCMachineState *pcms, 1094 ISABus *isa_bus, qemu_irq *gsi, 1095 ISADevice **rtc_state, 1096 bool create_fdctrl, 1097 uint32_t hpet_irqs) 1098 { 1099 int i; 1100 DeviceState *hpet = NULL; 1101 int pit_isa_irq = 0; 1102 qemu_irq pit_alt_irq = NULL; 1103 qemu_irq rtc_irq = NULL; 1104 ISADevice *pit = NULL; 1105 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1106 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1107 1108 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1109 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1110 1111 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1112 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1113 1114 /* 1115 * Check if an HPET shall be created. 1116 * 1117 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1118 * when the HPET wants to take over. Thus we have to disable the latter. 1119 */ 1120 if (pcms->hpet_enabled && (!kvm_irqchip_in_kernel() || 1121 kvm_has_pit_state2())) { 1122 hpet = qdev_try_new(TYPE_HPET); 1123 if (!hpet) { 1124 error_report("couldn't create HPET device"); 1125 exit(1); 1126 } 1127 /* 1128 * For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 and 1129 * earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, IRQ8 and 1130 * IRQ2. 1131 */ 1132 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1133 HPET_INTCAP, NULL); 1134 if (!compat) { 1135 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1136 } 1137 sysbus_realize_and_unref(SYS_BUS_DEVICE(hpet), &error_fatal); 1138 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 1139 1140 for (i = 0; i < GSI_NUM_PINS; i++) { 1141 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 1142 } 1143 pit_isa_irq = -1; 1144 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 1145 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 1146 } 1147 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 1148 1149 qemu_register_boot_set(pc_boot_set, *rtc_state); 1150 1151 if (!xen_enabled() && pcms->pit_enabled) { 1152 if (kvm_pit_in_kernel()) { 1153 pit = kvm_pit_init(isa_bus, 0x40); 1154 } else { 1155 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 1156 } 1157 if (hpet) { 1158 /* connect PIT to output control line of the HPET */ 1159 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 1160 } 1161 pcspk_init(pcms->pcspk, isa_bus, pit); 1162 } 1163 1164 i8257_dma_init(isa_bus, 0); 1165 1166 /* Super I/O */ 1167 pc_superio_init(isa_bus, create_fdctrl, pcms->vmport != ON_OFF_AUTO_ON); 1168 } 1169 1170 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 1171 { 1172 int i; 1173 1174 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 1175 for (i = 0; i < nb_nics; i++) { 1176 NICInfo *nd = &nd_table[i]; 1177 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 1178 1179 if (g_str_equal(model, "ne2k_isa")) { 1180 pc_init_ne2k_isa(isa_bus, nd); 1181 } else { 1182 pci_nic_init_nofail(nd, pci_bus, model, NULL); 1183 } 1184 } 1185 rom_reset_order_override(); 1186 } 1187 1188 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs) 1189 { 1190 qemu_irq *i8259; 1191 1192 if (kvm_pic_in_kernel()) { 1193 i8259 = kvm_i8259_init(isa_bus); 1194 } else if (xen_enabled()) { 1195 i8259 = xen_interrupt_controller_init(); 1196 } else { 1197 i8259 = i8259_init(isa_bus, x86_allocate_cpu_irq()); 1198 } 1199 1200 for (size_t i = 0; i < ISA_NUM_IRQS; i++) { 1201 i8259_irqs[i] = i8259[i]; 1202 } 1203 1204 g_free(i8259); 1205 } 1206 1207 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1208 Error **errp) 1209 { 1210 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1211 const X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1212 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1213 const MachineState *ms = MACHINE(hotplug_dev); 1214 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1215 const uint64_t legacy_align = TARGET_PAGE_SIZE; 1216 Error *local_err = NULL; 1217 1218 /* 1219 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1220 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1221 * addition to cover this case. 1222 */ 1223 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1224 error_setg(errp, 1225 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1226 return; 1227 } 1228 1229 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 1230 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 1231 return; 1232 } 1233 1234 hotplug_handler_pre_plug(x86ms->acpi_dev, dev, &local_err); 1235 if (local_err) { 1236 error_propagate(errp, local_err); 1237 return; 1238 } 1239 1240 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 1241 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 1242 } 1243 1244 static void pc_memory_plug(HotplugHandler *hotplug_dev, 1245 DeviceState *dev, Error **errp) 1246 { 1247 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1248 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1249 MachineState *ms = MACHINE(hotplug_dev); 1250 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1251 1252 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms)); 1253 1254 if (is_nvdimm) { 1255 nvdimm_plug(ms->nvdimms_state); 1256 } 1257 1258 hotplug_handler_plug(x86ms->acpi_dev, dev, &error_abort); 1259 } 1260 1261 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 1262 DeviceState *dev, Error **errp) 1263 { 1264 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1265 1266 /* 1267 * When -no-acpi is used with Q35 machine type, no ACPI is built, 1268 * but pcms->acpi_dev is still created. Check !acpi_enabled in 1269 * addition to cover this case. 1270 */ 1271 if (!x86ms->acpi_dev || !x86_machine_is_acpi_enabled(x86ms)) { 1272 error_setg(errp, 1273 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 1274 return; 1275 } 1276 1277 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 1278 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 1279 return; 1280 } 1281 1282 hotplug_handler_unplug_request(x86ms->acpi_dev, dev, 1283 errp); 1284 } 1285 1286 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 1287 DeviceState *dev, Error **errp) 1288 { 1289 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 1290 X86MachineState *x86ms = X86_MACHINE(hotplug_dev); 1291 Error *local_err = NULL; 1292 1293 hotplug_handler_unplug(x86ms->acpi_dev, dev, &local_err); 1294 if (local_err) { 1295 goto out; 1296 } 1297 1298 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 1299 qdev_unrealize(dev); 1300 out: 1301 error_propagate(errp, local_err); 1302 } 1303 1304 static void pc_virtio_md_pci_pre_plug(HotplugHandler *hotplug_dev, 1305 DeviceState *dev, Error **errp) 1306 { 1307 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1308 Error *local_err = NULL; 1309 1310 if (!hotplug_dev2 && dev->hotplugged) { 1311 /* 1312 * Without a bus hotplug handler, we cannot control the plug/unplug 1313 * order. We should never reach this point when hotplugging on x86, 1314 * however, better add a safety net. 1315 */ 1316 error_setg(errp, "hotplug of virtio based memory devices not supported" 1317 " on this bus."); 1318 return; 1319 } 1320 /* 1321 * First, see if we can plug this memory device at all. If that 1322 * succeeds, branch of to the actual hotplug handler. 1323 */ 1324 memory_device_pre_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev), NULL, 1325 &local_err); 1326 if (!local_err && hotplug_dev2) { 1327 hotplug_handler_pre_plug(hotplug_dev2, dev, &local_err); 1328 } 1329 error_propagate(errp, local_err); 1330 } 1331 1332 static void pc_virtio_md_pci_plug(HotplugHandler *hotplug_dev, 1333 DeviceState *dev, Error **errp) 1334 { 1335 HotplugHandler *hotplug_dev2 = qdev_get_bus_hotplug_handler(dev); 1336 Error *local_err = NULL; 1337 1338 /* 1339 * Plug the memory device first and then branch off to the actual 1340 * hotplug handler. If that one fails, we can easily undo the memory 1341 * device bits. 1342 */ 1343 memory_device_plug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1344 if (hotplug_dev2) { 1345 hotplug_handler_plug(hotplug_dev2, dev, &local_err); 1346 if (local_err) { 1347 memory_device_unplug(MEMORY_DEVICE(dev), MACHINE(hotplug_dev)); 1348 } 1349 } 1350 error_propagate(errp, local_err); 1351 } 1352 1353 static void pc_virtio_md_pci_unplug_request(HotplugHandler *hotplug_dev, 1354 DeviceState *dev, Error **errp) 1355 { 1356 /* We don't support hot unplug of virtio based memory devices */ 1357 error_setg(errp, "virtio based memory devices cannot be unplugged."); 1358 } 1359 1360 static void pc_virtio_md_pci_unplug(HotplugHandler *hotplug_dev, 1361 DeviceState *dev, Error **errp) 1362 { 1363 /* We don't support hot unplug of virtio based memory devices */ 1364 } 1365 1366 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 1367 DeviceState *dev, Error **errp) 1368 { 1369 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1370 pc_memory_pre_plug(hotplug_dev, dev, errp); 1371 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1372 x86_cpu_pre_plug(hotplug_dev, dev, errp); 1373 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1374 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1375 pc_virtio_md_pci_pre_plug(hotplug_dev, dev, errp); 1376 } 1377 } 1378 1379 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1380 DeviceState *dev, Error **errp) 1381 { 1382 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1383 pc_memory_plug(hotplug_dev, dev, errp); 1384 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1385 x86_cpu_plug(hotplug_dev, dev, errp); 1386 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1387 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1388 pc_virtio_md_pci_plug(hotplug_dev, dev, errp); 1389 } 1390 } 1391 1392 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 1393 DeviceState *dev, Error **errp) 1394 { 1395 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1396 pc_memory_unplug_request(hotplug_dev, dev, errp); 1397 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1398 x86_cpu_unplug_request_cb(hotplug_dev, dev, errp); 1399 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1400 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1401 pc_virtio_md_pci_unplug_request(hotplug_dev, dev, errp); 1402 } else { 1403 error_setg(errp, "acpi: device unplug request for not supported device" 1404 " type: %s", object_get_typename(OBJECT(dev))); 1405 } 1406 } 1407 1408 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 1409 DeviceState *dev, Error **errp) 1410 { 1411 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 1412 pc_memory_unplug(hotplug_dev, dev, errp); 1413 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 1414 x86_cpu_unplug_cb(hotplug_dev, dev, errp); 1415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1416 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1417 pc_virtio_md_pci_unplug(hotplug_dev, dev, errp); 1418 } else { 1419 error_setg(errp, "acpi: device unplug for not supported device" 1420 " type: %s", object_get_typename(OBJECT(dev))); 1421 } 1422 } 1423 1424 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 1425 DeviceState *dev) 1426 { 1427 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 1428 object_dynamic_cast(OBJECT(dev), TYPE_CPU) || 1429 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_PMEM_PCI) || 1430 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MEM_PCI)) { 1431 return HOTPLUG_HANDLER(machine); 1432 } 1433 1434 return NULL; 1435 } 1436 1437 static void 1438 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 1439 const char *name, void *opaque, 1440 Error **errp) 1441 { 1442 MachineState *ms = MACHINE(obj); 1443 int64_t value = 0; 1444 1445 if (ms->device_memory) { 1446 value = memory_region_size(&ms->device_memory->mr); 1447 } 1448 1449 visit_type_int(v, name, &value, errp); 1450 } 1451 1452 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 1453 void *opaque, Error **errp) 1454 { 1455 PCMachineState *pcms = PC_MACHINE(obj); 1456 OnOffAuto vmport = pcms->vmport; 1457 1458 visit_type_OnOffAuto(v, name, &vmport, errp); 1459 } 1460 1461 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 1462 void *opaque, Error **errp) 1463 { 1464 PCMachineState *pcms = PC_MACHINE(obj); 1465 1466 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 1467 } 1468 1469 static bool pc_machine_get_smbus(Object *obj, Error **errp) 1470 { 1471 PCMachineState *pcms = PC_MACHINE(obj); 1472 1473 return pcms->smbus_enabled; 1474 } 1475 1476 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 1477 { 1478 PCMachineState *pcms = PC_MACHINE(obj); 1479 1480 pcms->smbus_enabled = value; 1481 } 1482 1483 static bool pc_machine_get_sata(Object *obj, Error **errp) 1484 { 1485 PCMachineState *pcms = PC_MACHINE(obj); 1486 1487 return pcms->sata_enabled; 1488 } 1489 1490 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 1491 { 1492 PCMachineState *pcms = PC_MACHINE(obj); 1493 1494 pcms->sata_enabled = value; 1495 } 1496 1497 static bool pc_machine_get_pit(Object *obj, Error **errp) 1498 { 1499 PCMachineState *pcms = PC_MACHINE(obj); 1500 1501 return pcms->pit_enabled; 1502 } 1503 1504 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 1505 { 1506 PCMachineState *pcms = PC_MACHINE(obj); 1507 1508 pcms->pit_enabled = value; 1509 } 1510 1511 static bool pc_machine_get_hpet(Object *obj, Error **errp) 1512 { 1513 PCMachineState *pcms = PC_MACHINE(obj); 1514 1515 return pcms->hpet_enabled; 1516 } 1517 1518 static void pc_machine_set_hpet(Object *obj, bool value, Error **errp) 1519 { 1520 PCMachineState *pcms = PC_MACHINE(obj); 1521 1522 pcms->hpet_enabled = value; 1523 } 1524 1525 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 1526 const char *name, void *opaque, 1527 Error **errp) 1528 { 1529 PCMachineState *pcms = PC_MACHINE(obj); 1530 uint64_t value = pcms->max_ram_below_4g; 1531 1532 visit_type_size(v, name, &value, errp); 1533 } 1534 1535 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 1536 const char *name, void *opaque, 1537 Error **errp) 1538 { 1539 PCMachineState *pcms = PC_MACHINE(obj); 1540 uint64_t value; 1541 1542 if (!visit_type_size(v, name, &value, errp)) { 1543 return; 1544 } 1545 if (value > 4 * GiB) { 1546 error_setg(errp, 1547 "Machine option 'max-ram-below-4g=%"PRIu64 1548 "' expects size less than or equal to 4G", value); 1549 return; 1550 } 1551 1552 if (value < 1 * MiB) { 1553 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 1554 "BIOS may not work with less than 1MiB", value); 1555 } 1556 1557 pcms->max_ram_below_4g = value; 1558 } 1559 1560 static void pc_machine_get_max_fw_size(Object *obj, Visitor *v, 1561 const char *name, void *opaque, 1562 Error **errp) 1563 { 1564 PCMachineState *pcms = PC_MACHINE(obj); 1565 uint64_t value = pcms->max_fw_size; 1566 1567 visit_type_size(v, name, &value, errp); 1568 } 1569 1570 static void pc_machine_set_max_fw_size(Object *obj, Visitor *v, 1571 const char *name, void *opaque, 1572 Error **errp) 1573 { 1574 PCMachineState *pcms = PC_MACHINE(obj); 1575 Error *error = NULL; 1576 uint64_t value; 1577 1578 visit_type_size(v, name, &value, &error); 1579 if (error) { 1580 error_propagate(errp, error); 1581 return; 1582 } 1583 1584 /* 1585 * We don't have a theoretically justifiable exact lower bound on the base 1586 * address of any flash mapping. In practice, the IO-APIC MMIO range is 1587 * [0xFEE00000..0xFEE01000] -- see IO_APIC_DEFAULT_ADDRESS --, leaving free 1588 * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in 1589 * size. 1590 */ 1591 if (value > 16 * MiB) { 1592 error_setg(errp, 1593 "User specified max allowed firmware size %" PRIu64 " is " 1594 "greater than 16MiB. If combined firwmare size exceeds " 1595 "16MiB the system may not boot, or experience intermittent" 1596 "stability issues.", 1597 value); 1598 return; 1599 } 1600 1601 pcms->max_fw_size = value; 1602 } 1603 1604 1605 static void pc_machine_initfn(Object *obj) 1606 { 1607 PCMachineState *pcms = PC_MACHINE(obj); 1608 1609 #ifdef CONFIG_VMPORT 1610 pcms->vmport = ON_OFF_AUTO_AUTO; 1611 #else 1612 pcms->vmport = ON_OFF_AUTO_OFF; 1613 #endif /* CONFIG_VMPORT */ 1614 pcms->max_ram_below_4g = 0; /* use default */ 1615 /* acpi build is enabled by default if machine supports it */ 1616 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 1617 pcms->smbus_enabled = true; 1618 pcms->sata_enabled = true; 1619 pcms->pit_enabled = true; 1620 pcms->max_fw_size = 8 * MiB; 1621 #ifdef CONFIG_HPET 1622 pcms->hpet_enabled = true; 1623 #endif 1624 1625 pc_system_flash_create(pcms); 1626 pcms->pcspk = isa_new(TYPE_PC_SPEAKER); 1627 object_property_add_alias(OBJECT(pcms), "pcspk-audiodev", 1628 OBJECT(pcms->pcspk), "audiodev"); 1629 } 1630 1631 static void pc_machine_reset(MachineState *machine) 1632 { 1633 CPUState *cs; 1634 X86CPU *cpu; 1635 1636 qemu_devices_reset(); 1637 1638 /* Reset APIC after devices have been reset to cancel 1639 * any changes that qemu_devices_reset() might have done. 1640 */ 1641 CPU_FOREACH(cs) { 1642 cpu = X86_CPU(cs); 1643 1644 if (cpu->apic_state) { 1645 device_legacy_reset(cpu->apic_state); 1646 } 1647 } 1648 } 1649 1650 static void pc_machine_wakeup(MachineState *machine) 1651 { 1652 cpu_synchronize_all_states(); 1653 pc_machine_reset(machine); 1654 cpu_synchronize_all_post_reset(); 1655 } 1656 1657 static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) 1658 { 1659 X86IOMMUState *iommu = x86_iommu_get_default(); 1660 IntelIOMMUState *intel_iommu; 1661 1662 if (iommu && 1663 object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && 1664 object_dynamic_cast((Object *)dev, "vfio-pci")) { 1665 intel_iommu = INTEL_IOMMU_DEVICE(iommu); 1666 if (!intel_iommu->caching_mode) { 1667 error_setg(errp, "Device assignment is not allowed without " 1668 "enabling caching-mode=on for Intel IOMMU."); 1669 return false; 1670 } 1671 } 1672 1673 return true; 1674 } 1675 1676 static void pc_machine_class_init(ObjectClass *oc, void *data) 1677 { 1678 MachineClass *mc = MACHINE_CLASS(oc); 1679 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 1680 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1681 1682 pcmc->pci_enabled = true; 1683 pcmc->has_acpi_build = true; 1684 pcmc->rsdp_in_ram = true; 1685 pcmc->smbios_defaults = true; 1686 pcmc->smbios_uuid_encoded = true; 1687 pcmc->gigabyte_align = true; 1688 pcmc->has_reserved_memory = true; 1689 pcmc->kvmclock_enabled = true; 1690 pcmc->enforce_aligned_dimm = true; 1691 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 1692 * to be used at the moment, 32K should be enough for a while. */ 1693 pcmc->acpi_data_size = 0x20000 + 0x8000; 1694 pcmc->linuxboot_dma_enabled = true; 1695 pcmc->pvh_enabled = true; 1696 pcmc->kvmclock_create_always = true; 1697 assert(!mc->get_hotplug_handler); 1698 mc->get_hotplug_handler = pc_get_hotplug_handler; 1699 mc->hotplug_allowed = pc_hotplug_allowed; 1700 mc->cpu_index_to_instance_props = x86_cpu_index_to_props; 1701 mc->get_default_cpu_node_id = x86_get_default_cpu_node_id; 1702 mc->possible_cpu_arch_ids = x86_possible_cpu_arch_ids; 1703 mc->auto_enable_numa_with_memhp = true; 1704 mc->auto_enable_numa_with_memdev = true; 1705 mc->has_hotpluggable_cpus = true; 1706 mc->default_boot_order = "cad"; 1707 mc->smp_parse = pc_smp_parse; 1708 mc->block_default_type = IF_IDE; 1709 mc->max_cpus = 255; 1710 mc->reset = pc_machine_reset; 1711 mc->wakeup = pc_machine_wakeup; 1712 hc->pre_plug = pc_machine_device_pre_plug_cb; 1713 hc->plug = pc_machine_device_plug_cb; 1714 hc->unplug_request = pc_machine_device_unplug_request_cb; 1715 hc->unplug = pc_machine_device_unplug_cb; 1716 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 1717 mc->nvdimm_supported = true; 1718 mc->default_ram_id = "pc.ram"; 1719 1720 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 1721 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 1722 NULL, NULL); 1723 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 1724 "Maximum ram below the 4G boundary (32bit boundary)"); 1725 1726 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 1727 pc_machine_get_device_memory_region_size, NULL, 1728 NULL, NULL); 1729 1730 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 1731 pc_machine_get_vmport, pc_machine_set_vmport, 1732 NULL, NULL); 1733 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 1734 "Enable vmport (pc & q35)"); 1735 1736 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 1737 pc_machine_get_smbus, pc_machine_set_smbus); 1738 1739 object_class_property_add_bool(oc, PC_MACHINE_SATA, 1740 pc_machine_get_sata, pc_machine_set_sata); 1741 1742 object_class_property_add_bool(oc, PC_MACHINE_PIT, 1743 pc_machine_get_pit, pc_machine_set_pit); 1744 1745 object_class_property_add_bool(oc, "hpet", 1746 pc_machine_get_hpet, pc_machine_set_hpet); 1747 1748 object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", 1749 pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, 1750 NULL, NULL); 1751 object_class_property_set_description(oc, PC_MACHINE_MAX_FW_SIZE, 1752 "Maximum combined firmware size"); 1753 } 1754 1755 static const TypeInfo pc_machine_info = { 1756 .name = TYPE_PC_MACHINE, 1757 .parent = TYPE_X86_MACHINE, 1758 .abstract = true, 1759 .instance_size = sizeof(PCMachineState), 1760 .instance_init = pc_machine_initfn, 1761 .class_size = sizeof(PCMachineClass), 1762 .class_init = pc_machine_class_init, 1763 .interfaces = (InterfaceInfo[]) { 1764 { TYPE_HOTPLUG_HANDLER }, 1765 { } 1766 }, 1767 }; 1768 1769 static void pc_machine_register_types(void) 1770 { 1771 type_register_static(&pc_machine_info); 1772 } 1773 1774 type_init(pc_machine_register_types) 1775