1 /* 2 * QEMU PC System Emulator 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "hw/char/serial.h" 30 #include "hw/char/parallel.h" 31 #include "hw/i386/apic.h" 32 #include "hw/i386/topology.h" 33 #include "hw/i386/fw_cfg.h" 34 #include "sysemu/cpus.h" 35 #include "hw/block/fdc.h" 36 #include "hw/ide.h" 37 #include "hw/pci/pci.h" 38 #include "hw/pci/pci_bus.h" 39 #include "hw/nvram/fw_cfg.h" 40 #include "hw/timer/hpet.h" 41 #include "hw/firmware/smbios.h" 42 #include "hw/loader.h" 43 #include "elf.h" 44 #include "multiboot.h" 45 #include "hw/timer/mc146818rtc.h" 46 #include "hw/dma/i8257.h" 47 #include "hw/timer/i8254.h" 48 #include "hw/input/i8042.h" 49 #include "hw/audio/pcspk.h" 50 #include "hw/pci/msi.h" 51 #include "hw/sysbus.h" 52 #include "sysemu/sysemu.h" 53 #include "sysemu/tcg.h" 54 #include "sysemu/numa.h" 55 #include "sysemu/kvm.h" 56 #include "sysemu/qtest.h" 57 #include "kvm_i386.h" 58 #include "hw/xen/xen.h" 59 #include "hw/xen/start_info.h" 60 #include "ui/qemu-spice.h" 61 #include "exec/memory.h" 62 #include "exec/address-spaces.h" 63 #include "sysemu/arch_init.h" 64 #include "qemu/bitmap.h" 65 #include "qemu/config-file.h" 66 #include "qemu/error-report.h" 67 #include "qemu/option.h" 68 #include "hw/acpi/acpi.h" 69 #include "hw/acpi/cpu_hotplug.h" 70 #include "hw/boards.h" 71 #include "acpi-build.h" 72 #include "hw/mem/pc-dimm.h" 73 #include "qapi/error.h" 74 #include "qapi/qapi-visit-common.h" 75 #include "qapi/visitor.h" 76 #include "qom/cpu.h" 77 #include "hw/nmi.h" 78 #include "hw/usb.h" 79 #include "hw/i386/intel_iommu.h" 80 #include "hw/net/ne2000-isa.h" 81 #include "standard-headers/asm-x86/bootparam.h" 82 83 /* debug PC/ISA interrupts */ 84 //#define DEBUG_IRQ 85 86 #ifdef DEBUG_IRQ 87 #define DPRINTF(fmt, ...) \ 88 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 89 #else 90 #define DPRINTF(fmt, ...) 91 #endif 92 93 #define E820_NR_ENTRIES 16 94 95 struct e820_entry { 96 uint64_t address; 97 uint64_t length; 98 uint32_t type; 99 } QEMU_PACKED __attribute((__aligned__(4))); 100 101 struct e820_table { 102 uint32_t count; 103 struct e820_entry entry[E820_NR_ENTRIES]; 104 } QEMU_PACKED __attribute((__aligned__(4))); 105 106 static struct e820_table e820_reserve; 107 static struct e820_entry *e820_table; 108 static unsigned e820_entries; 109 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; 110 111 /* Physical Address of PVH entry point read from kernel ELF NOTE */ 112 static size_t pvh_start_addr; 113 114 GlobalProperty pc_compat_4_0_1[] = {}; 115 const size_t pc_compat_4_0_1_len = G_N_ELEMENTS(pc_compat_4_0_1); 116 117 GlobalProperty pc_compat_4_0[] = {}; 118 const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0); 119 120 GlobalProperty pc_compat_3_1[] = { 121 { "intel-iommu", "dma-drain", "off" }, 122 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" }, 123 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" }, 124 { "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" }, 125 { "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" }, 126 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" }, 127 { "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" }, 128 { "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" }, 129 { "EPYC" "-" TYPE_X86_CPU, "npt", "off" }, 130 { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" }, 131 { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" }, 132 { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" }, 133 { "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 134 { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 135 { "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 136 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" }, 137 { "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 138 { "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" }, 139 { "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" }, 140 { "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" }, 141 { TYPE_X86_CPU, "x-intel-pt-auto-level", "off" }, 142 }; 143 const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1); 144 145 GlobalProperty pc_compat_3_0[] = { 146 { TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" }, 147 { "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" }, 148 { "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" }, 149 }; 150 const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0); 151 152 GlobalProperty pc_compat_2_12[] = { 153 { TYPE_X86_CPU, "legacy-cache", "on" }, 154 { TYPE_X86_CPU, "topoext", "off" }, 155 { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 156 { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" }, 157 }; 158 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12); 159 160 GlobalProperty pc_compat_2_11[] = { 161 { TYPE_X86_CPU, "x-migrate-smi-count", "off" }, 162 { "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" }, 163 }; 164 const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11); 165 166 GlobalProperty pc_compat_2_10[] = { 167 { TYPE_X86_CPU, "x-hv-max-vps", "0x40" }, 168 { "i440FX-pcihost", "x-pci-hole64-fix", "off" }, 169 { "q35-pcihost", "x-pci-hole64-fix", "off" }, 170 }; 171 const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10); 172 173 GlobalProperty pc_compat_2_9[] = { 174 { "mch", "extended-tseg-mbytes", "0" }, 175 }; 176 const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9); 177 178 GlobalProperty pc_compat_2_8[] = { 179 { TYPE_X86_CPU, "tcg-cpuid", "off" }, 180 { "kvmclock", "x-mach-use-reliable-get-clock", "off" }, 181 { "ICH9-LPC", "x-smi-broadcast", "off" }, 182 { TYPE_X86_CPU, "vmware-cpuid-freq", "off" }, 183 { "Haswell-" TYPE_X86_CPU, "stepping", "1" }, 184 }; 185 const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8); 186 187 GlobalProperty pc_compat_2_7[] = { 188 { TYPE_X86_CPU, "l3-cache", "off" }, 189 { TYPE_X86_CPU, "full-cpuid-auto-level", "off" }, 190 { "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" }, 191 { "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" }, 192 { "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" }, 193 { "isa-pcspk", "migrate", "off" }, 194 }; 195 const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7); 196 197 GlobalProperty pc_compat_2_6[] = { 198 { TYPE_X86_CPU, "cpuid-0xb", "off" }, 199 { "vmxnet3", "romfile", "" }, 200 { TYPE_X86_CPU, "fill-mtrr-mask", "off" }, 201 { "apic-common", "legacy-instance-id", "on", } 202 }; 203 const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6); 204 205 GlobalProperty pc_compat_2_5[] = {}; 206 const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5); 207 208 GlobalProperty pc_compat_2_4[] = { 209 PC_CPU_MODEL_IDS("2.4.0") 210 { "Haswell-" TYPE_X86_CPU, "abm", "off" }, 211 { "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 212 { "Broadwell-" TYPE_X86_CPU, "abm", "off" }, 213 { "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" }, 214 { "host" "-" TYPE_X86_CPU, "host-cache-info", "on" }, 215 { TYPE_X86_CPU, "check", "off" }, 216 { "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" }, 217 { "qemu64" "-" TYPE_X86_CPU, "abm", "on" }, 218 { "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" }, 219 { "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" }, 220 { "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" }, 221 { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" }, 222 { "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" }, 223 { "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", } 224 }; 225 const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4); 226 227 GlobalProperty pc_compat_2_3[] = { 228 PC_CPU_MODEL_IDS("2.3.0") 229 { TYPE_X86_CPU, "arat", "off" }, 230 { "qemu64" "-" TYPE_X86_CPU, "min-level", "4" }, 231 { "kvm64" "-" TYPE_X86_CPU, "min-level", "5" }, 232 { "pentium3" "-" TYPE_X86_CPU, "min-level", "2" }, 233 { "n270" "-" TYPE_X86_CPU, "min-level", "5" }, 234 { "Conroe" "-" TYPE_X86_CPU, "min-level", "4" }, 235 { "Penryn" "-" TYPE_X86_CPU, "min-level", "4" }, 236 { "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" }, 237 { "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 238 { "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 239 { "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 240 { "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 241 { "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 242 { "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 243 { "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 244 { "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 245 { "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 246 { "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 247 { "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" }, 248 { TYPE_X86_CPU, "kvm-no-smi-migration", "on" }, 249 }; 250 const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3); 251 252 GlobalProperty pc_compat_2_2[] = { 253 PC_CPU_MODEL_IDS("2.2.0") 254 { "kvm64" "-" TYPE_X86_CPU, "vme", "off" }, 255 { "kvm32" "-" TYPE_X86_CPU, "vme", "off" }, 256 { "Conroe" "-" TYPE_X86_CPU, "vme", "off" }, 257 { "Penryn" "-" TYPE_X86_CPU, "vme", "off" }, 258 { "Nehalem" "-" TYPE_X86_CPU, "vme", "off" }, 259 { "Westmere" "-" TYPE_X86_CPU, "vme", "off" }, 260 { "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" }, 261 { "Haswell" "-" TYPE_X86_CPU, "vme", "off" }, 262 { "Broadwell" "-" TYPE_X86_CPU, "vme", "off" }, 263 { "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" }, 264 { "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" }, 265 { "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" }, 266 { "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" }, 267 { "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" }, 268 { "Haswell" "-" TYPE_X86_CPU, "f16c", "off" }, 269 { "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" }, 270 { "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" }, 271 { "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" }, 272 }; 273 const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2); 274 275 GlobalProperty pc_compat_2_1[] = { 276 PC_CPU_MODEL_IDS("2.1.0") 277 { "coreduo" "-" TYPE_X86_CPU, "vmx", "on" }, 278 { "core2duo" "-" TYPE_X86_CPU, "vmx", "on" }, 279 }; 280 const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1); 281 282 GlobalProperty pc_compat_2_0[] = { 283 PC_CPU_MODEL_IDS("2.0.0") 284 { "virtio-scsi-pci", "any_layout", "off" }, 285 { "PIIX4_PM", "memory-hotplug-support", "off" }, 286 { "apic", "version", "0x11" }, 287 { "nec-usb-xhci", "superspeed-ports-first", "off" }, 288 { "nec-usb-xhci", "force-pcie-endcap", "on" }, 289 { "pci-serial", "prog_if", "0" }, 290 { "pci-serial-2x", "prog_if", "0" }, 291 { "pci-serial-4x", "prog_if", "0" }, 292 { "virtio-net-pci", "guest_announce", "off" }, 293 { "ICH9-LPC", "memory-hotplug-support", "off" }, 294 { "xio3130-downstream", COMPAT_PROP_PCP, "off" }, 295 { "ioh3420", COMPAT_PROP_PCP, "off" }, 296 }; 297 const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0); 298 299 GlobalProperty pc_compat_1_7[] = { 300 PC_CPU_MODEL_IDS("1.7.0") 301 { TYPE_USB_DEVICE, "msos-desc", "no" }, 302 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" }, 303 { "hpet", HPET_INTCAP, "4" }, 304 }; 305 const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7); 306 307 GlobalProperty pc_compat_1_6[] = { 308 PC_CPU_MODEL_IDS("1.6.0") 309 { "e1000", "mitigation", "off" }, 310 { "qemu64-" TYPE_X86_CPU, "model", "2" }, 311 { "qemu32-" TYPE_X86_CPU, "model", "3" }, 312 { "i440FX-pcihost", "short_root_bus", "1" }, 313 { "q35-pcihost", "short_root_bus", "1" }, 314 }; 315 const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6); 316 317 GlobalProperty pc_compat_1_5[] = { 318 PC_CPU_MODEL_IDS("1.5.0") 319 { "Conroe-" TYPE_X86_CPU, "model", "2" }, 320 { "Conroe-" TYPE_X86_CPU, "min-level", "2" }, 321 { "Penryn-" TYPE_X86_CPU, "model", "2" }, 322 { "Penryn-" TYPE_X86_CPU, "min-level", "2" }, 323 { "Nehalem-" TYPE_X86_CPU, "model", "2" }, 324 { "Nehalem-" TYPE_X86_CPU, "min-level", "2" }, 325 { "virtio-net-pci", "any_layout", "off" }, 326 { TYPE_X86_CPU, "pmu", "on" }, 327 { "i440FX-pcihost", "short_root_bus", "0" }, 328 { "q35-pcihost", "short_root_bus", "0" }, 329 }; 330 const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5); 331 332 GlobalProperty pc_compat_1_4[] = { 333 PC_CPU_MODEL_IDS("1.4.0") 334 { "scsi-hd", "discard_granularity", "0" }, 335 { "scsi-cd", "discard_granularity", "0" }, 336 { "scsi-disk", "discard_granularity", "0" }, 337 { "ide-hd", "discard_granularity", "0" }, 338 { "ide-cd", "discard_granularity", "0" }, 339 { "ide-drive", "discard_granularity", "0" }, 340 { "virtio-blk-pci", "discard_granularity", "0" }, 341 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */ 342 { "virtio-serial-pci", "vectors", "0xFFFFFFFF" }, 343 { "virtio-net-pci", "ctrl_guest_offloads", "off" }, 344 { "e1000", "romfile", "pxe-e1000.rom" }, 345 { "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" }, 346 { "pcnet", "romfile", "pxe-pcnet.rom" }, 347 { "rtl8139", "romfile", "pxe-rtl8139.rom" }, 348 { "virtio-net-pci", "romfile", "pxe-virtio.rom" }, 349 { "486-" TYPE_X86_CPU, "model", "0" }, 350 { "n270" "-" TYPE_X86_CPU, "movbe", "off" }, 351 { "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" }, 352 }; 353 const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4); 354 355 void gsi_handler(void *opaque, int n, int level) 356 { 357 GSIState *s = opaque; 358 359 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n); 360 if (n < ISA_NUM_IRQS) { 361 qemu_set_irq(s->i8259_irq[n], level); 362 } 363 qemu_set_irq(s->ioapic_irq[n], level); 364 } 365 366 static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, 367 unsigned size) 368 { 369 } 370 371 static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size) 372 { 373 return 0xffffffffffffffffULL; 374 } 375 376 /* MSDOS compatibility mode FPU exception support */ 377 static qemu_irq ferr_irq; 378 379 void pc_register_ferr_irq(qemu_irq irq) 380 { 381 ferr_irq = irq; 382 } 383 384 /* XXX: add IGNNE support */ 385 void cpu_set_ferr(CPUX86State *s) 386 { 387 qemu_irq_raise(ferr_irq); 388 } 389 390 static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, 391 unsigned size) 392 { 393 qemu_irq_lower(ferr_irq); 394 } 395 396 static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size) 397 { 398 return 0xffffffffffffffffULL; 399 } 400 401 /* TSC handling */ 402 uint64_t cpu_get_tsc(CPUX86State *env) 403 { 404 return cpu_get_ticks(); 405 } 406 407 /* IRQ handling */ 408 int cpu_get_pic_interrupt(CPUX86State *env) 409 { 410 X86CPU *cpu = env_archcpu(env); 411 int intno; 412 413 if (!kvm_irqchip_in_kernel()) { 414 intno = apic_get_interrupt(cpu->apic_state); 415 if (intno >= 0) { 416 return intno; 417 } 418 /* read the irq from the PIC */ 419 if (!apic_accept_pic_intr(cpu->apic_state)) { 420 return -1; 421 } 422 } 423 424 intno = pic_read_irq(isa_pic); 425 return intno; 426 } 427 428 static void pic_irq_request(void *opaque, int irq, int level) 429 { 430 CPUState *cs = first_cpu; 431 X86CPU *cpu = X86_CPU(cs); 432 433 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); 434 if (cpu->apic_state && !kvm_irqchip_in_kernel()) { 435 CPU_FOREACH(cs) { 436 cpu = X86_CPU(cs); 437 if (apic_accept_pic_intr(cpu->apic_state)) { 438 apic_deliver_pic_intr(cpu->apic_state, level); 439 } 440 } 441 } else { 442 if (level) { 443 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 444 } else { 445 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 446 } 447 } 448 } 449 450 /* PC cmos mappings */ 451 452 #define REG_EQUIPMENT_BYTE 0x14 453 454 int cmos_get_fd_drive_type(FloppyDriveType fd0) 455 { 456 int val; 457 458 switch (fd0) { 459 case FLOPPY_DRIVE_TYPE_144: 460 /* 1.44 Mb 3"5 drive */ 461 val = 4; 462 break; 463 case FLOPPY_DRIVE_TYPE_288: 464 /* 2.88 Mb 3"5 drive */ 465 val = 5; 466 break; 467 case FLOPPY_DRIVE_TYPE_120: 468 /* 1.2 Mb 5"5 drive */ 469 val = 2; 470 break; 471 case FLOPPY_DRIVE_TYPE_NONE: 472 default: 473 val = 0; 474 break; 475 } 476 return val; 477 } 478 479 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs, 480 int16_t cylinders, int8_t heads, int8_t sectors) 481 { 482 rtc_set_memory(s, type_ofs, 47); 483 rtc_set_memory(s, info_ofs, cylinders); 484 rtc_set_memory(s, info_ofs + 1, cylinders >> 8); 485 rtc_set_memory(s, info_ofs + 2, heads); 486 rtc_set_memory(s, info_ofs + 3, 0xff); 487 rtc_set_memory(s, info_ofs + 4, 0xff); 488 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); 489 rtc_set_memory(s, info_ofs + 6, cylinders); 490 rtc_set_memory(s, info_ofs + 7, cylinders >> 8); 491 rtc_set_memory(s, info_ofs + 8, sectors); 492 } 493 494 /* convert boot_device letter to something recognizable by the bios */ 495 static int boot_device2nibble(char boot_device) 496 { 497 switch(boot_device) { 498 case 'a': 499 case 'b': 500 return 0x01; /* floppy boot */ 501 case 'c': 502 return 0x02; /* hard drive boot */ 503 case 'd': 504 return 0x03; /* CD-ROM boot */ 505 case 'n': 506 return 0x04; /* Network boot */ 507 } 508 return 0; 509 } 510 511 static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp) 512 { 513 #define PC_MAX_BOOT_DEVICES 3 514 int nbds, bds[3] = { 0, }; 515 int i; 516 517 nbds = strlen(boot_device); 518 if (nbds > PC_MAX_BOOT_DEVICES) { 519 error_setg(errp, "Too many boot devices for PC"); 520 return; 521 } 522 for (i = 0; i < nbds; i++) { 523 bds[i] = boot_device2nibble(boot_device[i]); 524 if (bds[i] == 0) { 525 error_setg(errp, "Invalid boot device for PC: '%c'", 526 boot_device[i]); 527 return; 528 } 529 } 530 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); 531 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); 532 } 533 534 static void pc_boot_set(void *opaque, const char *boot_device, Error **errp) 535 { 536 set_boot_dev(opaque, boot_device, errp); 537 } 538 539 static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy) 540 { 541 int val, nb, i; 542 FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE, 543 FLOPPY_DRIVE_TYPE_NONE }; 544 545 /* floppy type */ 546 if (floppy) { 547 for (i = 0; i < 2; i++) { 548 fd_type[i] = isa_fdc_get_drive_type(floppy, i); 549 } 550 } 551 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) | 552 cmos_get_fd_drive_type(fd_type[1]); 553 rtc_set_memory(rtc_state, 0x10, val); 554 555 val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE); 556 nb = 0; 557 if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) { 558 nb++; 559 } 560 if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) { 561 nb++; 562 } 563 switch (nb) { 564 case 0: 565 break; 566 case 1: 567 val |= 0x01; /* 1 drive, ready for boot */ 568 break; 569 case 2: 570 val |= 0x41; /* 2 drives, ready for boot */ 571 break; 572 } 573 rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val); 574 } 575 576 typedef struct pc_cmos_init_late_arg { 577 ISADevice *rtc_state; 578 BusState *idebus[2]; 579 } pc_cmos_init_late_arg; 580 581 typedef struct check_fdc_state { 582 ISADevice *floppy; 583 bool multiple; 584 } CheckFdcState; 585 586 static int check_fdc(Object *obj, void *opaque) 587 { 588 CheckFdcState *state = opaque; 589 Object *fdc; 590 uint32_t iobase; 591 Error *local_err = NULL; 592 593 fdc = object_dynamic_cast(obj, TYPE_ISA_FDC); 594 if (!fdc) { 595 return 0; 596 } 597 598 iobase = object_property_get_uint(obj, "iobase", &local_err); 599 if (local_err || iobase != 0x3f0) { 600 error_free(local_err); 601 return 0; 602 } 603 604 if (state->floppy) { 605 state->multiple = true; 606 } else { 607 state->floppy = ISA_DEVICE(obj); 608 } 609 return 0; 610 } 611 612 static const char * const fdc_container_path[] = { 613 "/unattached", "/peripheral", "/peripheral-anon" 614 }; 615 616 /* 617 * Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers 618 * and ACPI objects. 619 */ 620 ISADevice *pc_find_fdc0(void) 621 { 622 int i; 623 Object *container; 624 CheckFdcState state = { 0 }; 625 626 for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) { 627 container = container_get(qdev_get_machine(), fdc_container_path[i]); 628 object_child_foreach(container, check_fdc, &state); 629 } 630 631 if (state.multiple) { 632 warn_report("multiple floppy disk controllers with " 633 "iobase=0x3f0 have been found"); 634 error_printf("the one being picked for CMOS setup might not reflect " 635 "your intent"); 636 } 637 638 return state.floppy; 639 } 640 641 static void pc_cmos_init_late(void *opaque) 642 { 643 pc_cmos_init_late_arg *arg = opaque; 644 ISADevice *s = arg->rtc_state; 645 int16_t cylinders; 646 int8_t heads, sectors; 647 int val; 648 int i, trans; 649 650 val = 0; 651 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, 652 &cylinders, &heads, §ors) >= 0) { 653 cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); 654 val |= 0xf0; 655 } 656 if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, 657 &cylinders, &heads, §ors) >= 0) { 658 cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); 659 val |= 0x0f; 660 } 661 rtc_set_memory(s, 0x12, val); 662 663 val = 0; 664 for (i = 0; i < 4; i++) { 665 /* NOTE: ide_get_geometry() returns the physical 666 geometry. It is always such that: 1 <= sects <= 63, 1 667 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS 668 geometry can be different if a translation is done. */ 669 if (arg->idebus[i / 2] && 670 ide_get_geometry(arg->idebus[i / 2], i % 2, 671 &cylinders, &heads, §ors) >= 0) { 672 trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; 673 assert((trans & ~3) == 0); 674 val |= trans << (i * 2); 675 } 676 } 677 rtc_set_memory(s, 0x39, val); 678 679 pc_cmos_init_floppy(s, pc_find_fdc0()); 680 681 qemu_unregister_reset(pc_cmos_init_late, opaque); 682 } 683 684 void pc_cmos_init(PCMachineState *pcms, 685 BusState *idebus0, BusState *idebus1, 686 ISADevice *s) 687 { 688 int val; 689 static pc_cmos_init_late_arg arg; 690 691 /* various important CMOS locations needed by PC/Bochs bios */ 692 693 /* memory size */ 694 /* base memory (first MiB) */ 695 val = MIN(pcms->below_4g_mem_size / KiB, 640); 696 rtc_set_memory(s, 0x15, val); 697 rtc_set_memory(s, 0x16, val >> 8); 698 /* extended memory (next 64MiB) */ 699 if (pcms->below_4g_mem_size > 1 * MiB) { 700 val = (pcms->below_4g_mem_size - 1 * MiB) / KiB; 701 } else { 702 val = 0; 703 } 704 if (val > 65535) 705 val = 65535; 706 rtc_set_memory(s, 0x17, val); 707 rtc_set_memory(s, 0x18, val >> 8); 708 rtc_set_memory(s, 0x30, val); 709 rtc_set_memory(s, 0x31, val >> 8); 710 /* memory between 16MiB and 4GiB */ 711 if (pcms->below_4g_mem_size > 16 * MiB) { 712 val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB); 713 } else { 714 val = 0; 715 } 716 if (val > 65535) 717 val = 65535; 718 rtc_set_memory(s, 0x34, val); 719 rtc_set_memory(s, 0x35, val >> 8); 720 /* memory above 4GiB */ 721 val = pcms->above_4g_mem_size / 65536; 722 rtc_set_memory(s, 0x5b, val); 723 rtc_set_memory(s, 0x5c, val >> 8); 724 rtc_set_memory(s, 0x5d, val >> 16); 725 726 object_property_add_link(OBJECT(pcms), "rtc_state", 727 TYPE_ISA_DEVICE, 728 (Object **)&pcms->rtc, 729 object_property_allow_set_link, 730 OBJ_PROP_LINK_STRONG, &error_abort); 731 object_property_set_link(OBJECT(pcms), OBJECT(s), 732 "rtc_state", &error_abort); 733 734 set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal); 735 736 val = 0; 737 val |= 0x02; /* FPU is there */ 738 val |= 0x04; /* PS/2 mouse installed */ 739 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); 740 741 /* hard drives and FDC */ 742 arg.rtc_state = s; 743 arg.idebus[0] = idebus0; 744 arg.idebus[1] = idebus1; 745 qemu_register_reset(pc_cmos_init_late, &arg); 746 } 747 748 #define TYPE_PORT92 "port92" 749 #define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92) 750 751 /* port 92 stuff: could be split off */ 752 typedef struct Port92State { 753 ISADevice parent_obj; 754 755 MemoryRegion io; 756 uint8_t outport; 757 qemu_irq a20_out; 758 } Port92State; 759 760 static void port92_write(void *opaque, hwaddr addr, uint64_t val, 761 unsigned size) 762 { 763 Port92State *s = opaque; 764 int oldval = s->outport; 765 766 DPRINTF("port92: write 0x%02" PRIx64 "\n", val); 767 s->outport = val; 768 qemu_set_irq(s->a20_out, (val >> 1) & 1); 769 if ((val & 1) && !(oldval & 1)) { 770 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 771 } 772 } 773 774 static uint64_t port92_read(void *opaque, hwaddr addr, 775 unsigned size) 776 { 777 Port92State *s = opaque; 778 uint32_t ret; 779 780 ret = s->outport; 781 DPRINTF("port92: read 0x%02x\n", ret); 782 return ret; 783 } 784 785 static void port92_init(ISADevice *dev, qemu_irq a20_out) 786 { 787 qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out); 788 } 789 790 static const VMStateDescription vmstate_port92_isa = { 791 .name = "port92", 792 .version_id = 1, 793 .minimum_version_id = 1, 794 .fields = (VMStateField[]) { 795 VMSTATE_UINT8(outport, Port92State), 796 VMSTATE_END_OF_LIST() 797 } 798 }; 799 800 static void port92_reset(DeviceState *d) 801 { 802 Port92State *s = PORT92(d); 803 804 s->outport &= ~1; 805 } 806 807 static const MemoryRegionOps port92_ops = { 808 .read = port92_read, 809 .write = port92_write, 810 .impl = { 811 .min_access_size = 1, 812 .max_access_size = 1, 813 }, 814 .endianness = DEVICE_LITTLE_ENDIAN, 815 }; 816 817 static void port92_initfn(Object *obj) 818 { 819 Port92State *s = PORT92(obj); 820 821 memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1); 822 823 s->outport = 0; 824 825 qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1); 826 } 827 828 static void port92_realizefn(DeviceState *dev, Error **errp) 829 { 830 ISADevice *isadev = ISA_DEVICE(dev); 831 Port92State *s = PORT92(dev); 832 833 isa_register_ioport(isadev, &s->io, 0x92); 834 } 835 836 static void port92_class_initfn(ObjectClass *klass, void *data) 837 { 838 DeviceClass *dc = DEVICE_CLASS(klass); 839 840 dc->realize = port92_realizefn; 841 dc->reset = port92_reset; 842 dc->vmsd = &vmstate_port92_isa; 843 /* 844 * Reason: unlike ordinary ISA devices, this one needs additional 845 * wiring: its A20 output line needs to be wired up by 846 * port92_init(). 847 */ 848 dc->user_creatable = false; 849 } 850 851 static const TypeInfo port92_info = { 852 .name = TYPE_PORT92, 853 .parent = TYPE_ISA_DEVICE, 854 .instance_size = sizeof(Port92State), 855 .instance_init = port92_initfn, 856 .class_init = port92_class_initfn, 857 }; 858 859 static void port92_register_types(void) 860 { 861 type_register_static(&port92_info); 862 } 863 864 type_init(port92_register_types) 865 866 static void handle_a20_line_change(void *opaque, int irq, int level) 867 { 868 X86CPU *cpu = opaque; 869 870 /* XXX: send to all CPUs ? */ 871 /* XXX: add logic to handle multiple A20 line sources */ 872 x86_cpu_set_a20(cpu, level); 873 } 874 875 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) 876 { 877 int index = le32_to_cpu(e820_reserve.count); 878 struct e820_entry *entry; 879 880 if (type != E820_RAM) { 881 /* old FW_CFG_E820_TABLE entry -- reservations only */ 882 if (index >= E820_NR_ENTRIES) { 883 return -EBUSY; 884 } 885 entry = &e820_reserve.entry[index++]; 886 887 entry->address = cpu_to_le64(address); 888 entry->length = cpu_to_le64(length); 889 entry->type = cpu_to_le32(type); 890 891 e820_reserve.count = cpu_to_le32(index); 892 } 893 894 /* new "etc/e820" file -- include ram too */ 895 e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); 896 e820_table[e820_entries].address = cpu_to_le64(address); 897 e820_table[e820_entries].length = cpu_to_le64(length); 898 e820_table[e820_entries].type = cpu_to_le32(type); 899 e820_entries++; 900 901 return e820_entries; 902 } 903 904 int e820_get_num_entries(void) 905 { 906 return e820_entries; 907 } 908 909 bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) 910 { 911 if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { 912 *address = le64_to_cpu(e820_table[idx].address); 913 *length = le64_to_cpu(e820_table[idx].length); 914 return true; 915 } 916 return false; 917 } 918 919 /* Enables contiguous-apic-ID mode, for compatibility */ 920 static bool compat_apic_id_mode; 921 922 void enable_compat_apic_id_mode(void) 923 { 924 compat_apic_id_mode = true; 925 } 926 927 /* Calculates initial APIC ID for a specific CPU index 928 * 929 * Currently we need to be able to calculate the APIC ID from the CPU index 930 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have 931 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of 932 * all CPUs up to max_cpus. 933 */ 934 static uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) 935 { 936 uint32_t correct_id; 937 static bool warned; 938 939 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); 940 if (compat_apic_id_mode) { 941 if (cpu_index != correct_id && !warned && !qtest_enabled()) { 942 error_report("APIC IDs set in compatibility mode, " 943 "CPU topology won't match the configuration"); 944 warned = true; 945 } 946 return cpu_index; 947 } else { 948 return correct_id; 949 } 950 } 951 952 static void pc_build_smbios(PCMachineState *pcms) 953 { 954 uint8_t *smbios_tables, *smbios_anchor; 955 size_t smbios_tables_len, smbios_anchor_len; 956 struct smbios_phys_mem_area *mem_array; 957 unsigned i, array_count; 958 MachineState *ms = MACHINE(pcms); 959 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 960 961 /* tell smbios about cpuid version and features */ 962 smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); 963 964 smbios_tables = smbios_get_table_legacy(&smbios_tables_len); 965 if (smbios_tables) { 966 fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, 967 smbios_tables, smbios_tables_len); 968 } 969 970 /* build the array of physical mem area from e820 table */ 971 mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); 972 for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { 973 uint64_t addr, len; 974 975 if (e820_get_entry(i, E820_RAM, &addr, &len)) { 976 mem_array[array_count].address = addr; 977 mem_array[array_count].length = len; 978 array_count++; 979 } 980 } 981 smbios_get_tables(mem_array, array_count, 982 &smbios_tables, &smbios_tables_len, 983 &smbios_anchor, &smbios_anchor_len); 984 g_free(mem_array); 985 986 if (smbios_anchor) { 987 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", 988 smbios_tables, smbios_tables_len); 989 fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", 990 smbios_anchor, smbios_anchor_len); 991 } 992 } 993 994 static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) 995 { 996 FWCfgState *fw_cfg; 997 uint64_t *numa_fw_cfg; 998 int i; 999 const CPUArchIdList *cpus; 1000 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1001 1002 fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); 1003 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1004 1005 /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: 1006 * 1007 * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for 1008 * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, 1009 * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface 1010 * for CPU hotplug also uses APIC ID and not "CPU index". 1011 * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", 1012 * but the "limit to the APIC ID values SeaBIOS may see". 1013 * 1014 * So for compatibility reasons with old BIOSes we are stuck with 1015 * "etc/max-cpus" actually being apic_id_limit 1016 */ 1017 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); 1018 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 1019 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, 1020 acpi_tables, acpi_tables_len); 1021 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); 1022 1023 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, 1024 &e820_reserve, sizeof(e820_reserve)); 1025 fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, 1026 sizeof(struct e820_entry) * e820_entries); 1027 1028 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); 1029 /* allocate memory for the NUMA channel: one (64bit) word for the number 1030 * of nodes, one word for each VCPU->node and one word for each node to 1031 * hold the amount of memory. 1032 */ 1033 numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); 1034 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); 1035 cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); 1036 for (i = 0; i < cpus->len; i++) { 1037 unsigned int apic_id = cpus->cpus[i].arch_id; 1038 assert(apic_id < pcms->apic_id_limit); 1039 numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); 1040 } 1041 for (i = 0; i < nb_numa_nodes; i++) { 1042 numa_fw_cfg[pcms->apic_id_limit + 1 + i] = 1043 cpu_to_le64(numa_info[i].node_mem); 1044 } 1045 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, 1046 (1 + pcms->apic_id_limit + nb_numa_nodes) * 1047 sizeof(*numa_fw_cfg)); 1048 1049 return fw_cfg; 1050 } 1051 1052 static long get_file_size(FILE *f) 1053 { 1054 long where, size; 1055 1056 /* XXX: on Unix systems, using fstat() probably makes more sense */ 1057 1058 where = ftell(f); 1059 fseek(f, 0, SEEK_END); 1060 size = ftell(f); 1061 fseek(f, where, SEEK_SET); 1062 1063 return size; 1064 } 1065 1066 struct setup_data { 1067 uint64_t next; 1068 uint32_t type; 1069 uint32_t len; 1070 uint8_t data[0]; 1071 } __attribute__((packed)); 1072 1073 1074 /* 1075 * The entry point into the kernel for PVH boot is different from 1076 * the native entry point. The PVH entry is defined by the x86/HVM 1077 * direct boot ABI and is available in an ELFNOTE in the kernel binary. 1078 * 1079 * This function is passed to load_elf() when it is called from 1080 * load_elfboot() which then additionally checks for an ELF Note of 1081 * type XEN_ELFNOTE_PHYS32_ENTRY and passes it to this function to 1082 * parse the PVH entry address from the ELF Note. 1083 * 1084 * Due to trickery in elf_opts.h, load_elf() is actually available as 1085 * load_elf32() or load_elf64() and this routine needs to be able 1086 * to deal with being called as 32 or 64 bit. 1087 * 1088 * The address of the PVH entry point is saved to the 'pvh_start_addr' 1089 * global variable. (although the entry point is 32-bit, the kernel 1090 * binary can be either 32-bit or 64-bit). 1091 */ 1092 static uint64_t read_pvh_start_addr(void *arg1, void *arg2, bool is64) 1093 { 1094 size_t *elf_note_data_addr; 1095 1096 /* Check if ELF Note header passed in is valid */ 1097 if (arg1 == NULL) { 1098 return 0; 1099 } 1100 1101 if (is64) { 1102 struct elf64_note *nhdr64 = (struct elf64_note *)arg1; 1103 uint64_t nhdr_size64 = sizeof(struct elf64_note); 1104 uint64_t phdr_align = *(uint64_t *)arg2; 1105 uint64_t nhdr_namesz = nhdr64->n_namesz; 1106 1107 elf_note_data_addr = 1108 ((void *)nhdr64) + nhdr_size64 + 1109 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1110 } else { 1111 struct elf32_note *nhdr32 = (struct elf32_note *)arg1; 1112 uint32_t nhdr_size32 = sizeof(struct elf32_note); 1113 uint32_t phdr_align = *(uint32_t *)arg2; 1114 uint32_t nhdr_namesz = nhdr32->n_namesz; 1115 1116 elf_note_data_addr = 1117 ((void *)nhdr32) + nhdr_size32 + 1118 QEMU_ALIGN_UP(nhdr_namesz, phdr_align); 1119 } 1120 1121 pvh_start_addr = *elf_note_data_addr; 1122 1123 return pvh_start_addr; 1124 } 1125 1126 static bool load_elfboot(const char *kernel_filename, 1127 int kernel_file_size, 1128 uint8_t *header, 1129 size_t pvh_xen_start_addr, 1130 FWCfgState *fw_cfg) 1131 { 1132 uint32_t flags = 0; 1133 uint32_t mh_load_addr = 0; 1134 uint32_t elf_kernel_size = 0; 1135 uint64_t elf_entry; 1136 uint64_t elf_low, elf_high; 1137 int kernel_size; 1138 1139 if (ldl_p(header) != 0x464c457f) { 1140 return false; /* no elfboot */ 1141 } 1142 1143 bool elf_is64 = header[EI_CLASS] == ELFCLASS64; 1144 flags = elf_is64 ? 1145 ((Elf64_Ehdr *)header)->e_flags : ((Elf32_Ehdr *)header)->e_flags; 1146 1147 if (flags & 0x00010004) { /* LOAD_ELF_HEADER_HAS_ADDR */ 1148 error_report("elfboot unsupported flags = %x", flags); 1149 exit(1); 1150 } 1151 1152 uint64_t elf_note_type = XEN_ELFNOTE_PHYS32_ENTRY; 1153 kernel_size = load_elf(kernel_filename, read_pvh_start_addr, 1154 NULL, &elf_note_type, &elf_entry, 1155 &elf_low, &elf_high, 0, I386_ELF_MACHINE, 1156 0, 0); 1157 1158 if (kernel_size < 0) { 1159 error_report("Error while loading elf kernel"); 1160 exit(1); 1161 } 1162 mh_load_addr = elf_low; 1163 elf_kernel_size = elf_high - elf_low; 1164 1165 if (pvh_start_addr == 0) { 1166 error_report("Error loading uncompressed kernel without PVH ELF Note"); 1167 exit(1); 1168 } 1169 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ENTRY, pvh_start_addr); 1170 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_load_addr); 1171 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, elf_kernel_size); 1172 1173 return true; 1174 } 1175 1176 static void load_linux(PCMachineState *pcms, 1177 FWCfgState *fw_cfg) 1178 { 1179 uint16_t protocol; 1180 int setup_size, kernel_size, cmdline_size; 1181 int dtb_size, setup_data_offset; 1182 uint32_t initrd_max; 1183 uint8_t header[8192], *setup, *kernel; 1184 hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0; 1185 FILE *f; 1186 char *vmode; 1187 MachineState *machine = MACHINE(pcms); 1188 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1189 struct setup_data *setup_data; 1190 const char *kernel_filename = machine->kernel_filename; 1191 const char *initrd_filename = machine->initrd_filename; 1192 const char *dtb_filename = machine->dtb; 1193 const char *kernel_cmdline = machine->kernel_cmdline; 1194 1195 /* Align to 16 bytes as a paranoia measure */ 1196 cmdline_size = (strlen(kernel_cmdline)+16) & ~15; 1197 1198 /* load the kernel header */ 1199 f = fopen(kernel_filename, "rb"); 1200 if (!f || !(kernel_size = get_file_size(f)) || 1201 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) != 1202 MIN(ARRAY_SIZE(header), kernel_size)) { 1203 fprintf(stderr, "qemu: could not load kernel '%s': %s\n", 1204 kernel_filename, strerror(errno)); 1205 exit(1); 1206 } 1207 1208 /* kernel protocol version */ 1209 #if 0 1210 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202)); 1211 #endif 1212 if (ldl_p(header+0x202) == 0x53726448) { 1213 protocol = lduw_p(header+0x206); 1214 } else { 1215 /* 1216 * This could be a multiboot kernel. If it is, let's stop treating it 1217 * like a Linux kernel. 1218 * Note: some multiboot images could be in the ELF format (the same of 1219 * PVH), so we try multiboot first since we check the multiboot magic 1220 * header before to load it. 1221 */ 1222 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename, 1223 kernel_cmdline, kernel_size, header)) { 1224 return; 1225 } 1226 /* 1227 * Check if the file is an uncompressed kernel file (ELF) and load it, 1228 * saving the PVH entry point used by the x86/HVM direct boot ABI. 1229 * If load_elfboot() is successful, populate the fw_cfg info. 1230 */ 1231 if (pcmc->pvh_enabled && 1232 load_elfboot(kernel_filename, kernel_size, 1233 header, pvh_start_addr, fw_cfg)) { 1234 fclose(f); 1235 1236 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1237 strlen(kernel_cmdline) + 1); 1238 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1239 1240 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, sizeof(header)); 1241 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, 1242 header, sizeof(header)); 1243 1244 /* load initrd */ 1245 if (initrd_filename) { 1246 gsize initrd_size; 1247 gchar *initrd_data; 1248 GError *gerr = NULL; 1249 1250 if (!g_file_get_contents(initrd_filename, &initrd_data, 1251 &initrd_size, &gerr)) { 1252 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1253 initrd_filename, gerr->message); 1254 exit(1); 1255 } 1256 1257 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1258 if (initrd_size >= initrd_max) { 1259 fprintf(stderr, "qemu: initrd is too large, cannot support." 1260 "(max: %"PRIu32", need %"PRId64")\n", 1261 initrd_max, (uint64_t)initrd_size); 1262 exit(1); 1263 } 1264 1265 initrd_addr = (initrd_max - initrd_size) & ~4095; 1266 1267 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1268 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1269 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, 1270 initrd_size); 1271 } 1272 1273 option_rom[nb_option_roms].bootindex = 0; 1274 option_rom[nb_option_roms].name = "pvh.bin"; 1275 nb_option_roms++; 1276 1277 return; 1278 } 1279 protocol = 0; 1280 } 1281 1282 if (protocol < 0x200 || !(header[0x211] & 0x01)) { 1283 /* Low kernel */ 1284 real_addr = 0x90000; 1285 cmdline_addr = 0x9a000 - cmdline_size; 1286 prot_addr = 0x10000; 1287 } else if (protocol < 0x202) { 1288 /* High but ancient kernel */ 1289 real_addr = 0x90000; 1290 cmdline_addr = 0x9a000 - cmdline_size; 1291 prot_addr = 0x100000; 1292 } else { 1293 /* High and recent kernel */ 1294 real_addr = 0x10000; 1295 cmdline_addr = 0x20000; 1296 prot_addr = 0x100000; 1297 } 1298 1299 #if 0 1300 fprintf(stderr, 1301 "qemu: real_addr = 0x" TARGET_FMT_plx "\n" 1302 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n" 1303 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n", 1304 real_addr, 1305 cmdline_addr, 1306 prot_addr); 1307 #endif 1308 1309 /* highest address for loading the initrd */ 1310 if (protocol >= 0x20c && 1311 lduw_p(header+0x236) & XLF_CAN_BE_LOADED_ABOVE_4G) { 1312 /* 1313 * Linux has supported initrd up to 4 GB for a very long time (2007, 1314 * long before XLF_CAN_BE_LOADED_ABOVE_4G which was added in 2013), 1315 * though it only sets initrd_max to 2 GB to "work around bootloader 1316 * bugs". Luckily, QEMU firmware(which does something like bootloader) 1317 * has supported this. 1318 * 1319 * It's believed that if XLF_CAN_BE_LOADED_ABOVE_4G is set, initrd can 1320 * be loaded into any address. 1321 * 1322 * In addition, initrd_max is uint32_t simply because QEMU doesn't 1323 * support the 64-bit boot protocol (specifically the ext_ramdisk_image 1324 * field). 1325 * 1326 * Therefore here just limit initrd_max to UINT32_MAX simply as well. 1327 */ 1328 initrd_max = UINT32_MAX; 1329 } else if (protocol >= 0x203) { 1330 initrd_max = ldl_p(header+0x22c); 1331 } else { 1332 initrd_max = 0x37ffffff; 1333 } 1334 1335 if (initrd_max >= pcms->below_4g_mem_size - pcmc->acpi_data_size) { 1336 initrd_max = pcms->below_4g_mem_size - pcmc->acpi_data_size - 1; 1337 } 1338 1339 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); 1340 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1); 1341 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); 1342 1343 if (protocol >= 0x202) { 1344 stl_p(header+0x228, cmdline_addr); 1345 } else { 1346 stw_p(header+0x20, 0xA33F); 1347 stw_p(header+0x22, cmdline_addr-real_addr); 1348 } 1349 1350 /* handle vga= parameter */ 1351 vmode = strstr(kernel_cmdline, "vga="); 1352 if (vmode) { 1353 unsigned int video_mode; 1354 /* skip "vga=" */ 1355 vmode += 4; 1356 if (!strncmp(vmode, "normal", 6)) { 1357 video_mode = 0xffff; 1358 } else if (!strncmp(vmode, "ext", 3)) { 1359 video_mode = 0xfffe; 1360 } else if (!strncmp(vmode, "ask", 3)) { 1361 video_mode = 0xfffd; 1362 } else { 1363 video_mode = strtol(vmode, NULL, 0); 1364 } 1365 stw_p(header+0x1fa, video_mode); 1366 } 1367 1368 /* loader type */ 1369 /* High nybble = B reserved for QEMU; low nybble is revision number. 1370 If this code is substantially changed, you may want to consider 1371 incrementing the revision. */ 1372 if (protocol >= 0x200) { 1373 header[0x210] = 0xB0; 1374 } 1375 /* heap */ 1376 if (protocol >= 0x201) { 1377 header[0x211] |= 0x80; /* CAN_USE_HEAP */ 1378 stw_p(header+0x224, cmdline_addr-real_addr-0x200); 1379 } 1380 1381 /* load initrd */ 1382 if (initrd_filename) { 1383 gsize initrd_size; 1384 gchar *initrd_data; 1385 GError *gerr = NULL; 1386 1387 if (protocol < 0x200) { 1388 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n"); 1389 exit(1); 1390 } 1391 1392 if (!g_file_get_contents(initrd_filename, &initrd_data, 1393 &initrd_size, &gerr)) { 1394 fprintf(stderr, "qemu: error reading initrd %s: %s\n", 1395 initrd_filename, gerr->message); 1396 exit(1); 1397 } 1398 if (initrd_size >= initrd_max) { 1399 fprintf(stderr, "qemu: initrd is too large, cannot support." 1400 "(max: %"PRIu32", need %"PRId64")\n", 1401 initrd_max, (uint64_t)initrd_size); 1402 exit(1); 1403 } 1404 1405 initrd_addr = (initrd_max-initrd_size) & ~4095; 1406 1407 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 1408 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1409 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); 1410 1411 stl_p(header+0x218, initrd_addr); 1412 stl_p(header+0x21c, initrd_size); 1413 } 1414 1415 /* load kernel and setup */ 1416 setup_size = header[0x1f1]; 1417 if (setup_size == 0) { 1418 setup_size = 4; 1419 } 1420 setup_size = (setup_size+1)*512; 1421 if (setup_size > kernel_size) { 1422 fprintf(stderr, "qemu: invalid kernel header\n"); 1423 exit(1); 1424 } 1425 kernel_size -= setup_size; 1426 1427 setup = g_malloc(setup_size); 1428 kernel = g_malloc(kernel_size); 1429 fseek(f, 0, SEEK_SET); 1430 if (fread(setup, 1, setup_size, f) != setup_size) { 1431 fprintf(stderr, "fread() failed\n"); 1432 exit(1); 1433 } 1434 if (fread(kernel, 1, kernel_size, f) != kernel_size) { 1435 fprintf(stderr, "fread() failed\n"); 1436 exit(1); 1437 } 1438 fclose(f); 1439 1440 /* append dtb to kernel */ 1441 if (dtb_filename) { 1442 if (protocol < 0x209) { 1443 fprintf(stderr, "qemu: Linux kernel too old to load a dtb\n"); 1444 exit(1); 1445 } 1446 1447 dtb_size = get_image_size(dtb_filename); 1448 if (dtb_size <= 0) { 1449 fprintf(stderr, "qemu: error reading dtb %s: %s\n", 1450 dtb_filename, strerror(errno)); 1451 exit(1); 1452 } 1453 1454 setup_data_offset = QEMU_ALIGN_UP(kernel_size, 16); 1455 kernel_size = setup_data_offset + sizeof(struct setup_data) + dtb_size; 1456 kernel = g_realloc(kernel, kernel_size); 1457 1458 stq_p(header+0x250, prot_addr + setup_data_offset); 1459 1460 setup_data = (struct setup_data *)(kernel + setup_data_offset); 1461 setup_data->next = 0; 1462 setup_data->type = cpu_to_le32(SETUP_DTB); 1463 setup_data->len = cpu_to_le32(dtb_size); 1464 1465 load_image_size(dtb_filename, setup_data->data, dtb_size); 1466 } 1467 1468 memcpy(setup, header, MIN(sizeof(header), setup_size)); 1469 1470 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); 1471 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1472 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); 1473 1474 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); 1475 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); 1476 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); 1477 1478 option_rom[nb_option_roms].bootindex = 0; 1479 option_rom[nb_option_roms].name = "linuxboot.bin"; 1480 if (pcmc->linuxboot_dma_enabled && fw_cfg_dma_enabled(fw_cfg)) { 1481 option_rom[nb_option_roms].name = "linuxboot_dma.bin"; 1482 } 1483 nb_option_roms++; 1484 } 1485 1486 #define NE2000_NB_MAX 6 1487 1488 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 1489 0x280, 0x380 }; 1490 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 1491 1492 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) 1493 { 1494 static int nb_ne2k = 0; 1495 1496 if (nb_ne2k == NE2000_NB_MAX) 1497 return; 1498 isa_ne2000_init(bus, ne2000_io[nb_ne2k], 1499 ne2000_irq[nb_ne2k], nd); 1500 nb_ne2k++; 1501 } 1502 1503 DeviceState *cpu_get_current_apic(void) 1504 { 1505 if (current_cpu) { 1506 X86CPU *cpu = X86_CPU(current_cpu); 1507 return cpu->apic_state; 1508 } else { 1509 return NULL; 1510 } 1511 } 1512 1513 void pc_acpi_smi_interrupt(void *opaque, int irq, int level) 1514 { 1515 X86CPU *cpu = opaque; 1516 1517 if (level) { 1518 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); 1519 } 1520 } 1521 1522 static void pc_new_cpu(const char *typename, int64_t apic_id, Error **errp) 1523 { 1524 Object *cpu = NULL; 1525 Error *local_err = NULL; 1526 1527 cpu = object_new(typename); 1528 1529 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); 1530 object_property_set_bool(cpu, true, "realized", &local_err); 1531 1532 object_unref(cpu); 1533 error_propagate(errp, local_err); 1534 } 1535 1536 void pc_hot_add_cpu(const int64_t id, Error **errp) 1537 { 1538 MachineState *ms = MACHINE(qdev_get_machine()); 1539 int64_t apic_id = x86_cpu_apic_id_from_index(id); 1540 Error *local_err = NULL; 1541 1542 if (id < 0) { 1543 error_setg(errp, "Invalid CPU id: %" PRIi64, id); 1544 return; 1545 } 1546 1547 if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { 1548 error_setg(errp, "Unable to add CPU: %" PRIi64 1549 ", resulting APIC ID (%" PRIi64 ") is too large", 1550 id, apic_id); 1551 return; 1552 } 1553 1554 pc_new_cpu(ms->cpu_type, apic_id, &local_err); 1555 if (local_err) { 1556 error_propagate(errp, local_err); 1557 return; 1558 } 1559 } 1560 1561 void pc_cpus_init(PCMachineState *pcms) 1562 { 1563 int i; 1564 const CPUArchIdList *possible_cpus; 1565 MachineState *ms = MACHINE(pcms); 1566 MachineClass *mc = MACHINE_GET_CLASS(pcms); 1567 1568 /* Calculates the limit to CPU APIC ID values 1569 * 1570 * Limit for the APIC ID value, so that all 1571 * CPU APIC IDs are < pcms->apic_id_limit. 1572 * 1573 * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). 1574 */ 1575 pcms->apic_id_limit = x86_cpu_apic_id_from_index(max_cpus - 1) + 1; 1576 possible_cpus = mc->possible_cpu_arch_ids(ms); 1577 for (i = 0; i < smp_cpus; i++) { 1578 pc_new_cpu(possible_cpus->cpus[i].type, possible_cpus->cpus[i].arch_id, 1579 &error_fatal); 1580 } 1581 } 1582 1583 static void pc_build_feature_control_file(PCMachineState *pcms) 1584 { 1585 MachineState *ms = MACHINE(pcms); 1586 X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); 1587 CPUX86State *env = &cpu->env; 1588 uint32_t unused, ecx, edx; 1589 uint64_t feature_control_bits = 0; 1590 uint64_t *val; 1591 1592 cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); 1593 if (ecx & CPUID_EXT_VMX) { 1594 feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; 1595 } 1596 1597 if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == 1598 (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && 1599 (env->mcg_cap & MCG_LMCE_P)) { 1600 feature_control_bits |= FEATURE_CONTROL_LMCE; 1601 } 1602 1603 if (!feature_control_bits) { 1604 return; 1605 } 1606 1607 val = g_malloc(sizeof(*val)); 1608 *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); 1609 fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); 1610 } 1611 1612 static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) 1613 { 1614 if (cpus_count > 0xff) { 1615 /* If the number of CPUs can't be represented in 8 bits, the 1616 * BIOS must use "FW_CFG_NB_CPUS". Set RTC field to 0 just 1617 * to make old BIOSes fail more predictably. 1618 */ 1619 rtc_set_memory(rtc, 0x5f, 0); 1620 } else { 1621 rtc_set_memory(rtc, 0x5f, cpus_count - 1); 1622 } 1623 } 1624 1625 static 1626 void pc_machine_done(Notifier *notifier, void *data) 1627 { 1628 PCMachineState *pcms = container_of(notifier, 1629 PCMachineState, machine_done); 1630 PCIBus *bus = pcms->bus; 1631 1632 /* set the number of CPUs */ 1633 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 1634 1635 if (bus) { 1636 int extra_hosts = 0; 1637 1638 QLIST_FOREACH(bus, &bus->child, sibling) { 1639 /* look for expander root buses */ 1640 if (pci_bus_is_root(bus)) { 1641 extra_hosts++; 1642 } 1643 } 1644 if (extra_hosts && pcms->fw_cfg) { 1645 uint64_t *val = g_malloc(sizeof(*val)); 1646 *val = cpu_to_le64(extra_hosts); 1647 fw_cfg_add_file(pcms->fw_cfg, 1648 "etc/extra-pci-roots", val, sizeof(*val)); 1649 } 1650 } 1651 1652 acpi_setup(); 1653 if (pcms->fw_cfg) { 1654 pc_build_smbios(pcms); 1655 pc_build_feature_control_file(pcms); 1656 /* update FW_CFG_NB_CPUS to account for -device added CPUs */ 1657 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1658 } 1659 1660 if (pcms->apic_id_limit > 255 && !xen_enabled()) { 1661 IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); 1662 1663 if (!iommu || !x86_iommu_ir_supported(X86_IOMMU_DEVICE(iommu)) || 1664 iommu->intr_eim != ON_OFF_AUTO_ON) { 1665 error_report("current -smp configuration requires " 1666 "Extended Interrupt Mode enabled. " 1667 "You can add an IOMMU using: " 1668 "-device intel-iommu,intremap=on,eim=on"); 1669 exit(EXIT_FAILURE); 1670 } 1671 } 1672 } 1673 1674 void pc_guest_info_init(PCMachineState *pcms) 1675 { 1676 int i; 1677 1678 pcms->apic_xrupt_override = kvm_allows_irq0_override(); 1679 pcms->numa_nodes = nb_numa_nodes; 1680 pcms->node_mem = g_malloc0(pcms->numa_nodes * 1681 sizeof *pcms->node_mem); 1682 for (i = 0; i < nb_numa_nodes; i++) { 1683 pcms->node_mem[i] = numa_info[i].node_mem; 1684 } 1685 1686 pcms->machine_done.notify = pc_machine_done; 1687 qemu_add_machine_init_done_notifier(&pcms->machine_done); 1688 } 1689 1690 /* setup pci memory address space mapping into system address space */ 1691 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 1692 MemoryRegion *pci_address_space) 1693 { 1694 /* Set to lower priority than RAM */ 1695 memory_region_add_subregion_overlap(system_memory, 0x0, 1696 pci_address_space, -1); 1697 } 1698 1699 void xen_load_linux(PCMachineState *pcms) 1700 { 1701 int i; 1702 FWCfgState *fw_cfg; 1703 1704 assert(MACHINE(pcms)->kernel_filename != NULL); 1705 1706 fw_cfg = fw_cfg_init_io(FW_CFG_IO_BASE); 1707 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 1708 rom_set_fw(fw_cfg); 1709 1710 load_linux(pcms, fw_cfg); 1711 for (i = 0; i < nb_option_roms; i++) { 1712 assert(!strcmp(option_rom[i].name, "linuxboot.bin") || 1713 !strcmp(option_rom[i].name, "linuxboot_dma.bin") || 1714 !strcmp(option_rom[i].name, "pvh.bin") || 1715 !strcmp(option_rom[i].name, "multiboot.bin")); 1716 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1717 } 1718 pcms->fw_cfg = fw_cfg; 1719 } 1720 1721 void pc_memory_init(PCMachineState *pcms, 1722 MemoryRegion *system_memory, 1723 MemoryRegion *rom_memory, 1724 MemoryRegion **ram_memory) 1725 { 1726 int linux_boot, i; 1727 MemoryRegion *ram, *option_rom_mr; 1728 MemoryRegion *ram_below_4g, *ram_above_4g; 1729 FWCfgState *fw_cfg; 1730 MachineState *machine = MACHINE(pcms); 1731 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1732 1733 assert(machine->ram_size == pcms->below_4g_mem_size + 1734 pcms->above_4g_mem_size); 1735 1736 linux_boot = (machine->kernel_filename != NULL); 1737 1738 /* Allocate RAM. We allocate it as a single memory region and use 1739 * aliases to address portions of it, mostly for backwards compatibility 1740 * with older qemus that used qemu_ram_alloc(). 1741 */ 1742 ram = g_malloc(sizeof(*ram)); 1743 memory_region_allocate_system_memory(ram, NULL, "pc.ram", 1744 machine->ram_size); 1745 *ram_memory = ram; 1746 ram_below_4g = g_malloc(sizeof(*ram_below_4g)); 1747 memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, 1748 0, pcms->below_4g_mem_size); 1749 memory_region_add_subregion(system_memory, 0, ram_below_4g); 1750 e820_add_entry(0, pcms->below_4g_mem_size, E820_RAM); 1751 if (pcms->above_4g_mem_size > 0) { 1752 ram_above_4g = g_malloc(sizeof(*ram_above_4g)); 1753 memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, 1754 pcms->below_4g_mem_size, 1755 pcms->above_4g_mem_size); 1756 memory_region_add_subregion(system_memory, 0x100000000ULL, 1757 ram_above_4g); 1758 e820_add_entry(0x100000000ULL, pcms->above_4g_mem_size, E820_RAM); 1759 } 1760 1761 if (!pcmc->has_reserved_memory && 1762 (machine->ram_slots || 1763 (machine->maxram_size > machine->ram_size))) { 1764 MachineClass *mc = MACHINE_GET_CLASS(machine); 1765 1766 error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", 1767 mc->name); 1768 exit(EXIT_FAILURE); 1769 } 1770 1771 /* always allocate the device memory information */ 1772 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 1773 1774 /* initialize device memory address space */ 1775 if (pcmc->has_reserved_memory && 1776 (machine->ram_size < machine->maxram_size)) { 1777 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1778 1779 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1780 error_report("unsupported amount of memory slots: %"PRIu64, 1781 machine->ram_slots); 1782 exit(EXIT_FAILURE); 1783 } 1784 1785 if (QEMU_ALIGN_UP(machine->maxram_size, 1786 TARGET_PAGE_SIZE) != machine->maxram_size) { 1787 error_report("maximum memory size must by aligned to multiple of " 1788 "%d bytes", TARGET_PAGE_SIZE); 1789 exit(EXIT_FAILURE); 1790 } 1791 1792 machine->device_memory->base = 1793 ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1 * GiB); 1794 1795 if (pcmc->enforce_aligned_dimm) { 1796 /* size device region assuming 1G page max alignment per slot */ 1797 device_mem_size += (1 * GiB) * machine->ram_slots; 1798 } 1799 1800 if ((machine->device_memory->base + device_mem_size) < 1801 device_mem_size) { 1802 error_report("unsupported amount of maximum memory: " RAM_ADDR_FMT, 1803 machine->maxram_size); 1804 exit(EXIT_FAILURE); 1805 } 1806 1807 memory_region_init(&machine->device_memory->mr, OBJECT(pcms), 1808 "device-memory", device_mem_size); 1809 memory_region_add_subregion(system_memory, machine->device_memory->base, 1810 &machine->device_memory->mr); 1811 } 1812 1813 /* Initialize PC system firmware */ 1814 pc_system_firmware_init(pcms, rom_memory); 1815 1816 option_rom_mr = g_malloc(sizeof(*option_rom_mr)); 1817 memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, 1818 &error_fatal); 1819 if (pcmc->pci_enabled) { 1820 memory_region_set_readonly(option_rom_mr, true); 1821 } 1822 memory_region_add_subregion_overlap(rom_memory, 1823 PC_ROM_MIN_VGA, 1824 option_rom_mr, 1825 1); 1826 1827 fw_cfg = bochs_bios_init(&address_space_memory, pcms); 1828 1829 rom_set_fw(fw_cfg); 1830 1831 if (pcmc->has_reserved_memory && machine->device_memory->base) { 1832 uint64_t *val = g_malloc(sizeof(*val)); 1833 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1834 uint64_t res_mem_end = machine->device_memory->base; 1835 1836 if (!pcmc->broken_reserved_end) { 1837 res_mem_end += memory_region_size(&machine->device_memory->mr); 1838 } 1839 *val = cpu_to_le64(ROUND_UP(res_mem_end, 1 * GiB)); 1840 fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val)); 1841 } 1842 1843 if (linux_boot) { 1844 load_linux(pcms, fw_cfg); 1845 } 1846 1847 for (i = 0; i < nb_option_roms; i++) { 1848 rom_add_option(option_rom[i].name, option_rom[i].bootindex); 1849 } 1850 pcms->fw_cfg = fw_cfg; 1851 1852 /* Init default IOAPIC address space */ 1853 pcms->ioapic_as = &address_space_memory; 1854 } 1855 1856 /* 1857 * The 64bit pci hole starts after "above 4G RAM" and 1858 * potentially the space reserved for memory hotplug. 1859 */ 1860 uint64_t pc_pci_hole64_start(void) 1861 { 1862 PCMachineState *pcms = PC_MACHINE(qdev_get_machine()); 1863 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 1864 MachineState *ms = MACHINE(pcms); 1865 uint64_t hole64_start = 0; 1866 1867 if (pcmc->has_reserved_memory && ms->device_memory->base) { 1868 hole64_start = ms->device_memory->base; 1869 if (!pcmc->broken_reserved_end) { 1870 hole64_start += memory_region_size(&ms->device_memory->mr); 1871 } 1872 } else { 1873 hole64_start = 0x100000000ULL + pcms->above_4g_mem_size; 1874 } 1875 1876 return ROUND_UP(hole64_start, 1 * GiB); 1877 } 1878 1879 qemu_irq pc_allocate_cpu_irq(void) 1880 { 1881 return qemu_allocate_irq(pic_irq_request, NULL, 0); 1882 } 1883 1884 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) 1885 { 1886 DeviceState *dev = NULL; 1887 1888 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_VGA); 1889 if (pci_bus) { 1890 PCIDevice *pcidev = pci_vga_init(pci_bus); 1891 dev = pcidev ? &pcidev->qdev : NULL; 1892 } else if (isa_bus) { 1893 ISADevice *isadev = isa_vga_init(isa_bus); 1894 dev = isadev ? DEVICE(isadev) : NULL; 1895 } 1896 rom_reset_order_override(); 1897 return dev; 1898 } 1899 1900 static const MemoryRegionOps ioport80_io_ops = { 1901 .write = ioport80_write, 1902 .read = ioport80_read, 1903 .endianness = DEVICE_NATIVE_ENDIAN, 1904 .impl = { 1905 .min_access_size = 1, 1906 .max_access_size = 1, 1907 }, 1908 }; 1909 1910 static const MemoryRegionOps ioportF0_io_ops = { 1911 .write = ioportF0_write, 1912 .read = ioportF0_read, 1913 .endianness = DEVICE_NATIVE_ENDIAN, 1914 .impl = { 1915 .min_access_size = 1, 1916 .max_access_size = 1, 1917 }, 1918 }; 1919 1920 static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) 1921 { 1922 int i; 1923 DriveInfo *fd[MAX_FD]; 1924 qemu_irq *a20_line; 1925 ISADevice *i8042, *port92, *vmmouse; 1926 1927 serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1928 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 1929 1930 for (i = 0; i < MAX_FD; i++) { 1931 fd[i] = drive_get(IF_FLOPPY, 0, i); 1932 create_fdctrl |= !!fd[i]; 1933 } 1934 if (create_fdctrl) { 1935 fdctrl_init_isa(isa_bus, fd); 1936 } 1937 1938 i8042 = isa_create_simple(isa_bus, "i8042"); 1939 if (!no_vmport) { 1940 vmport_init(isa_bus); 1941 vmmouse = isa_try_create(isa_bus, "vmmouse"); 1942 } else { 1943 vmmouse = NULL; 1944 } 1945 if (vmmouse) { 1946 DeviceState *dev = DEVICE(vmmouse); 1947 qdev_prop_set_ptr(dev, "ps2_mouse", i8042); 1948 qdev_init_nofail(dev); 1949 } 1950 port92 = isa_create_simple(isa_bus, "port92"); 1951 1952 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2); 1953 i8042_setup_a20_line(i8042, a20_line[0]); 1954 port92_init(port92, a20_line[1]); 1955 g_free(a20_line); 1956 } 1957 1958 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 1959 ISADevice **rtc_state, 1960 bool create_fdctrl, 1961 bool no_vmport, 1962 bool has_pit, 1963 uint32_t hpet_irqs) 1964 { 1965 int i; 1966 DeviceState *hpet = NULL; 1967 int pit_isa_irq = 0; 1968 qemu_irq pit_alt_irq = NULL; 1969 qemu_irq rtc_irq = NULL; 1970 ISADevice *pit = NULL; 1971 MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); 1972 MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); 1973 1974 memory_region_init_io(ioport80_io, NULL, &ioport80_io_ops, NULL, "ioport80", 1); 1975 memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); 1976 1977 memory_region_init_io(ioportF0_io, NULL, &ioportF0_io_ops, NULL, "ioportF0", 1); 1978 memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); 1979 1980 /* 1981 * Check if an HPET shall be created. 1982 * 1983 * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT 1984 * when the HPET wants to take over. Thus we have to disable the latter. 1985 */ 1986 if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) { 1987 /* In order to set property, here not using sysbus_try_create_simple */ 1988 hpet = qdev_try_create(NULL, TYPE_HPET); 1989 if (hpet) { 1990 /* For pc-piix-*, hpet's intcap is always IRQ2. For pc-q35-1.7 1991 * and earlier, use IRQ2 for compat. Otherwise, use IRQ16~23, 1992 * IRQ8 and IRQ2. 1993 */ 1994 uint8_t compat = object_property_get_uint(OBJECT(hpet), 1995 HPET_INTCAP, NULL); 1996 if (!compat) { 1997 qdev_prop_set_uint32(hpet, HPET_INTCAP, hpet_irqs); 1998 } 1999 qdev_init_nofail(hpet); 2000 sysbus_mmio_map(SYS_BUS_DEVICE(hpet), 0, HPET_BASE); 2001 2002 for (i = 0; i < GSI_NUM_PINS; i++) { 2003 sysbus_connect_irq(SYS_BUS_DEVICE(hpet), i, gsi[i]); 2004 } 2005 pit_isa_irq = -1; 2006 pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); 2007 rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); 2008 } 2009 } 2010 *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq); 2011 2012 qemu_register_boot_set(pc_boot_set, *rtc_state); 2013 2014 if (!xen_enabled() && has_pit) { 2015 if (kvm_pit_in_kernel()) { 2016 pit = kvm_pit_init(isa_bus, 0x40); 2017 } else { 2018 pit = i8254_pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); 2019 } 2020 if (hpet) { 2021 /* connect PIT to output control line of the HPET */ 2022 qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(DEVICE(pit), 0)); 2023 } 2024 pcspk_init(isa_bus, pit); 2025 } 2026 2027 i8257_dma_init(isa_bus, 0); 2028 2029 /* Super I/O */ 2030 pc_superio_init(isa_bus, create_fdctrl, no_vmport); 2031 } 2032 2033 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) 2034 { 2035 int i; 2036 2037 rom_set_order_override(FW_CFG_ORDER_OVERRIDE_NIC); 2038 for (i = 0; i < nb_nics; i++) { 2039 NICInfo *nd = &nd_table[i]; 2040 const char *model = nd->model ? nd->model : pcmc->default_nic_model; 2041 2042 if (g_str_equal(model, "ne2k_isa")) { 2043 pc_init_ne2k_isa(isa_bus, nd); 2044 } else { 2045 pci_nic_init_nofail(nd, pci_bus, model, NULL); 2046 } 2047 } 2048 rom_reset_order_override(); 2049 } 2050 2051 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) 2052 { 2053 DeviceState *dev; 2054 SysBusDevice *d; 2055 unsigned int i; 2056 2057 if (kvm_ioapic_in_kernel()) { 2058 dev = qdev_create(NULL, TYPE_KVM_IOAPIC); 2059 } else { 2060 dev = qdev_create(NULL, TYPE_IOAPIC); 2061 } 2062 if (parent_name) { 2063 object_property_add_child(object_resolve_path(parent_name, NULL), 2064 "ioapic", OBJECT(dev), NULL); 2065 } 2066 qdev_init_nofail(dev); 2067 d = SYS_BUS_DEVICE(dev); 2068 sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS); 2069 2070 for (i = 0; i < IOAPIC_NUM_PINS; i++) { 2071 gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i); 2072 } 2073 } 2074 2075 static void pc_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2076 Error **errp) 2077 { 2078 const PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2079 const PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); 2080 const MachineState *ms = MACHINE(hotplug_dev); 2081 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2082 const uint64_t legacy_align = TARGET_PAGE_SIZE; 2083 Error *local_err = NULL; 2084 2085 /* 2086 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2087 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2088 * addition to cover this case. 2089 */ 2090 if (!pcms->acpi_dev || !acpi_enabled) { 2091 error_setg(errp, 2092 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2093 return; 2094 } 2095 2096 if (is_nvdimm && !ms->nvdimms_state->is_enabled) { 2097 error_setg(errp, "nvdimm is not enabled: missing 'nvdimm' in '-M'"); 2098 return; 2099 } 2100 2101 hotplug_handler_pre_plug(pcms->acpi_dev, dev, &local_err); 2102 if (local_err) { 2103 error_propagate(errp, local_err); 2104 return; 2105 } 2106 2107 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), 2108 pcmc->enforce_aligned_dimm ? NULL : &legacy_align, errp); 2109 } 2110 2111 static void pc_memory_plug(HotplugHandler *hotplug_dev, 2112 DeviceState *dev, Error **errp) 2113 { 2114 Error *local_err = NULL; 2115 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2116 MachineState *ms = MACHINE(hotplug_dev); 2117 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 2118 2119 pc_dimm_plug(PC_DIMM(dev), MACHINE(pcms), &local_err); 2120 if (local_err) { 2121 goto out; 2122 } 2123 2124 if (is_nvdimm) { 2125 nvdimm_plug(ms->nvdimms_state); 2126 } 2127 2128 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &error_abort); 2129 out: 2130 error_propagate(errp, local_err); 2131 } 2132 2133 static void pc_memory_unplug_request(HotplugHandler *hotplug_dev, 2134 DeviceState *dev, Error **errp) 2135 { 2136 Error *local_err = NULL; 2137 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2138 2139 /* 2140 * When -no-acpi is used with Q35 machine type, no ACPI is built, 2141 * but pcms->acpi_dev is still created. Check !acpi_enabled in 2142 * addition to cover this case. 2143 */ 2144 if (!pcms->acpi_dev || !acpi_enabled) { 2145 error_setg(&local_err, 2146 "memory hotplug is not enabled: missing acpi device or acpi disabled"); 2147 goto out; 2148 } 2149 2150 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 2151 error_setg(&local_err, 2152 "nvdimm device hot unplug is not supported yet."); 2153 goto out; 2154 } 2155 2156 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2157 &local_err); 2158 out: 2159 error_propagate(errp, local_err); 2160 } 2161 2162 static void pc_memory_unplug(HotplugHandler *hotplug_dev, 2163 DeviceState *dev, Error **errp) 2164 { 2165 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2166 Error *local_err = NULL; 2167 2168 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2169 if (local_err) { 2170 goto out; 2171 } 2172 2173 pc_dimm_unplug(PC_DIMM(dev), MACHINE(pcms)); 2174 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2175 out: 2176 error_propagate(errp, local_err); 2177 } 2178 2179 static int pc_apic_cmp(const void *a, const void *b) 2180 { 2181 CPUArchId *apic_a = (CPUArchId *)a; 2182 CPUArchId *apic_b = (CPUArchId *)b; 2183 2184 return apic_a->arch_id - apic_b->arch_id; 2185 } 2186 2187 /* returns pointer to CPUArchId descriptor that matches CPU's apic_id 2188 * in ms->possible_cpus->cpus, if ms->possible_cpus->cpus has no 2189 * entry corresponding to CPU's apic_id returns NULL. 2190 */ 2191 static CPUArchId *pc_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2192 { 2193 CPUArchId apic_id, *found_cpu; 2194 2195 apic_id.arch_id = id; 2196 found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, 2197 ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), 2198 pc_apic_cmp); 2199 if (found_cpu && idx) { 2200 *idx = found_cpu - ms->possible_cpus->cpus; 2201 } 2202 return found_cpu; 2203 } 2204 2205 static void pc_cpu_plug(HotplugHandler *hotplug_dev, 2206 DeviceState *dev, Error **errp) 2207 { 2208 CPUArchId *found_cpu; 2209 Error *local_err = NULL; 2210 X86CPU *cpu = X86_CPU(dev); 2211 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2212 2213 if (pcms->acpi_dev) { 2214 hotplug_handler_plug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2215 if (local_err) { 2216 goto out; 2217 } 2218 } 2219 2220 /* increment the number of CPUs */ 2221 pcms->boot_cpus++; 2222 if (pcms->rtc) { 2223 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2224 } 2225 if (pcms->fw_cfg) { 2226 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2227 } 2228 2229 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2230 found_cpu->cpu = OBJECT(dev); 2231 out: 2232 error_propagate(errp, local_err); 2233 } 2234 static void pc_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 2235 DeviceState *dev, Error **errp) 2236 { 2237 int idx = -1; 2238 Error *local_err = NULL; 2239 X86CPU *cpu = X86_CPU(dev); 2240 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2241 2242 if (!pcms->acpi_dev) { 2243 error_setg(&local_err, "CPU hot unplug not supported without ACPI"); 2244 goto out; 2245 } 2246 2247 pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2248 assert(idx != -1); 2249 if (idx == 0) { 2250 error_setg(&local_err, "Boot CPU is unpluggable"); 2251 goto out; 2252 } 2253 2254 hotplug_handler_unplug_request(HOTPLUG_HANDLER(pcms->acpi_dev), dev, 2255 &local_err); 2256 if (local_err) { 2257 goto out; 2258 } 2259 2260 out: 2261 error_propagate(errp, local_err); 2262 2263 } 2264 2265 static void pc_cpu_unplug_cb(HotplugHandler *hotplug_dev, 2266 DeviceState *dev, Error **errp) 2267 { 2268 CPUArchId *found_cpu; 2269 Error *local_err = NULL; 2270 X86CPU *cpu = X86_CPU(dev); 2271 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2272 2273 hotplug_handler_unplug(HOTPLUG_HANDLER(pcms->acpi_dev), dev, &local_err); 2274 if (local_err) { 2275 goto out; 2276 } 2277 2278 found_cpu = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, NULL); 2279 found_cpu->cpu = NULL; 2280 object_property_set_bool(OBJECT(dev), false, "realized", NULL); 2281 2282 /* decrement the number of CPUs */ 2283 pcms->boot_cpus--; 2284 /* Update the number of CPUs in CMOS */ 2285 rtc_set_cpus_count(pcms->rtc, pcms->boot_cpus); 2286 fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); 2287 out: 2288 error_propagate(errp, local_err); 2289 } 2290 2291 static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev, 2292 DeviceState *dev, Error **errp) 2293 { 2294 int idx; 2295 CPUState *cs; 2296 CPUArchId *cpu_slot; 2297 X86CPUTopoInfo topo; 2298 X86CPU *cpu = X86_CPU(dev); 2299 MachineState *ms = MACHINE(hotplug_dev); 2300 PCMachineState *pcms = PC_MACHINE(hotplug_dev); 2301 2302 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { 2303 error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", 2304 ms->cpu_type); 2305 return; 2306 } 2307 2308 /* if APIC ID is not set, set it based on socket/core/thread properties */ 2309 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 2310 int max_socket = (max_cpus - 1) / smp_threads / smp_cores; 2311 2312 if (cpu->socket_id < 0) { 2313 error_setg(errp, "CPU socket-id is not set"); 2314 return; 2315 } else if (cpu->socket_id > max_socket) { 2316 error_setg(errp, "Invalid CPU socket-id: %u must be in range 0:%u", 2317 cpu->socket_id, max_socket); 2318 return; 2319 } 2320 if (cpu->core_id < 0) { 2321 error_setg(errp, "CPU core-id is not set"); 2322 return; 2323 } else if (cpu->core_id > (smp_cores - 1)) { 2324 error_setg(errp, "Invalid CPU core-id: %u must be in range 0:%u", 2325 cpu->core_id, smp_cores - 1); 2326 return; 2327 } 2328 if (cpu->thread_id < 0) { 2329 error_setg(errp, "CPU thread-id is not set"); 2330 return; 2331 } else if (cpu->thread_id > (smp_threads - 1)) { 2332 error_setg(errp, "Invalid CPU thread-id: %u must be in range 0:%u", 2333 cpu->thread_id, smp_threads - 1); 2334 return; 2335 } 2336 2337 topo.pkg_id = cpu->socket_id; 2338 topo.core_id = cpu->core_id; 2339 topo.smt_id = cpu->thread_id; 2340 cpu->apic_id = apicid_from_topo_ids(smp_cores, smp_threads, &topo); 2341 } 2342 2343 cpu_slot = pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); 2344 if (!cpu_slot) { 2345 MachineState *ms = MACHINE(pcms); 2346 2347 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2348 error_setg(errp, "Invalid CPU [socket: %u, core: %u, thread: %u] with" 2349 " APIC ID %" PRIu32 ", valid index range 0:%d", 2350 topo.pkg_id, topo.core_id, topo.smt_id, cpu->apic_id, 2351 ms->possible_cpus->len - 1); 2352 return; 2353 } 2354 2355 if (cpu_slot->cpu) { 2356 error_setg(errp, "CPU[%d] with APIC ID %" PRIu32 " exists", 2357 idx, cpu->apic_id); 2358 return; 2359 } 2360 2361 /* if 'address' properties socket-id/core-id/thread-id are not set, set them 2362 * so that machine_query_hotpluggable_cpus would show correct values 2363 */ 2364 /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizefn() 2365 * once -smp refactoring is complete and there will be CPU private 2366 * CPUState::nr_cores and CPUState::nr_threads fields instead of globals */ 2367 x86_topo_ids_from_apicid(cpu->apic_id, smp_cores, smp_threads, &topo); 2368 if (cpu->socket_id != -1 && cpu->socket_id != topo.pkg_id) { 2369 error_setg(errp, "property socket-id: %u doesn't match set apic-id:" 2370 " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pkg_id); 2371 return; 2372 } 2373 cpu->socket_id = topo.pkg_id; 2374 2375 if (cpu->core_id != -1 && cpu->core_id != topo.core_id) { 2376 error_setg(errp, "property core-id: %u doesn't match set apic-id:" 2377 " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_id); 2378 return; 2379 } 2380 cpu->core_id = topo.core_id; 2381 2382 if (cpu->thread_id != -1 && cpu->thread_id != topo.smt_id) { 2383 error_setg(errp, "property thread-id: %u doesn't match set apic-id:" 2384 " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.smt_id); 2385 return; 2386 } 2387 cpu->thread_id = topo.smt_id; 2388 2389 if (cpu->hyperv_vpindex && !kvm_hv_vpindex_settable()) { 2390 error_setg(errp, "kernel doesn't allow setting HyperV VP_INDEX"); 2391 return; 2392 } 2393 2394 cs = CPU(cpu); 2395 cs->cpu_index = idx; 2396 2397 numa_cpu_pre_plug(cpu_slot, dev, errp); 2398 } 2399 2400 static void pc_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, 2401 DeviceState *dev, Error **errp) 2402 { 2403 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2404 pc_memory_pre_plug(hotplug_dev, dev, errp); 2405 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2406 pc_cpu_pre_plug(hotplug_dev, dev, errp); 2407 } 2408 } 2409 2410 static void pc_machine_device_plug_cb(HotplugHandler *hotplug_dev, 2411 DeviceState *dev, Error **errp) 2412 { 2413 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2414 pc_memory_plug(hotplug_dev, dev, errp); 2415 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2416 pc_cpu_plug(hotplug_dev, dev, errp); 2417 } 2418 } 2419 2420 static void pc_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, 2421 DeviceState *dev, Error **errp) 2422 { 2423 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2424 pc_memory_unplug_request(hotplug_dev, dev, errp); 2425 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2426 pc_cpu_unplug_request_cb(hotplug_dev, dev, errp); 2427 } else { 2428 error_setg(errp, "acpi: device unplug request for not supported device" 2429 " type: %s", object_get_typename(OBJECT(dev))); 2430 } 2431 } 2432 2433 static void pc_machine_device_unplug_cb(HotplugHandler *hotplug_dev, 2434 DeviceState *dev, Error **errp) 2435 { 2436 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2437 pc_memory_unplug(hotplug_dev, dev, errp); 2438 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2439 pc_cpu_unplug_cb(hotplug_dev, dev, errp); 2440 } else { 2441 error_setg(errp, "acpi: device unplug for not supported device" 2442 " type: %s", object_get_typename(OBJECT(dev))); 2443 } 2444 } 2445 2446 static HotplugHandler *pc_get_hotplug_handler(MachineState *machine, 2447 DeviceState *dev) 2448 { 2449 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2450 object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { 2451 return HOTPLUG_HANDLER(machine); 2452 } 2453 2454 return NULL; 2455 } 2456 2457 static void 2458 pc_machine_get_device_memory_region_size(Object *obj, Visitor *v, 2459 const char *name, void *opaque, 2460 Error **errp) 2461 { 2462 MachineState *ms = MACHINE(obj); 2463 int64_t value = memory_region_size(&ms->device_memory->mr); 2464 2465 visit_type_int(v, name, &value, errp); 2466 } 2467 2468 static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, 2469 const char *name, void *opaque, 2470 Error **errp) 2471 { 2472 PCMachineState *pcms = PC_MACHINE(obj); 2473 uint64_t value = pcms->max_ram_below_4g; 2474 2475 visit_type_size(v, name, &value, errp); 2476 } 2477 2478 static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v, 2479 const char *name, void *opaque, 2480 Error **errp) 2481 { 2482 PCMachineState *pcms = PC_MACHINE(obj); 2483 Error *error = NULL; 2484 uint64_t value; 2485 2486 visit_type_size(v, name, &value, &error); 2487 if (error) { 2488 error_propagate(errp, error); 2489 return; 2490 } 2491 if (value > 4 * GiB) { 2492 error_setg(&error, 2493 "Machine option 'max-ram-below-4g=%"PRIu64 2494 "' expects size less than or equal to 4G", value); 2495 error_propagate(errp, error); 2496 return; 2497 } 2498 2499 if (value < 1 * MiB) { 2500 warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary," 2501 "BIOS may not work with less than 1MiB", value); 2502 } 2503 2504 pcms->max_ram_below_4g = value; 2505 } 2506 2507 static void pc_machine_get_vmport(Object *obj, Visitor *v, const char *name, 2508 void *opaque, Error **errp) 2509 { 2510 PCMachineState *pcms = PC_MACHINE(obj); 2511 OnOffAuto vmport = pcms->vmport; 2512 2513 visit_type_OnOffAuto(v, name, &vmport, errp); 2514 } 2515 2516 static void pc_machine_set_vmport(Object *obj, Visitor *v, const char *name, 2517 void *opaque, Error **errp) 2518 { 2519 PCMachineState *pcms = PC_MACHINE(obj); 2520 2521 visit_type_OnOffAuto(v, name, &pcms->vmport, errp); 2522 } 2523 2524 bool pc_machine_is_smm_enabled(PCMachineState *pcms) 2525 { 2526 bool smm_available = false; 2527 2528 if (pcms->smm == ON_OFF_AUTO_OFF) { 2529 return false; 2530 } 2531 2532 if (tcg_enabled() || qtest_enabled()) { 2533 smm_available = true; 2534 } else if (kvm_enabled()) { 2535 smm_available = kvm_has_smm(); 2536 } 2537 2538 if (smm_available) { 2539 return true; 2540 } 2541 2542 if (pcms->smm == ON_OFF_AUTO_ON) { 2543 error_report("System Management Mode not supported by this hypervisor."); 2544 exit(1); 2545 } 2546 return false; 2547 } 2548 2549 static void pc_machine_get_smm(Object *obj, Visitor *v, const char *name, 2550 void *opaque, Error **errp) 2551 { 2552 PCMachineState *pcms = PC_MACHINE(obj); 2553 OnOffAuto smm = pcms->smm; 2554 2555 visit_type_OnOffAuto(v, name, &smm, errp); 2556 } 2557 2558 static void pc_machine_set_smm(Object *obj, Visitor *v, const char *name, 2559 void *opaque, Error **errp) 2560 { 2561 PCMachineState *pcms = PC_MACHINE(obj); 2562 2563 visit_type_OnOffAuto(v, name, &pcms->smm, errp); 2564 } 2565 2566 static bool pc_machine_get_smbus(Object *obj, Error **errp) 2567 { 2568 PCMachineState *pcms = PC_MACHINE(obj); 2569 2570 return pcms->smbus_enabled; 2571 } 2572 2573 static void pc_machine_set_smbus(Object *obj, bool value, Error **errp) 2574 { 2575 PCMachineState *pcms = PC_MACHINE(obj); 2576 2577 pcms->smbus_enabled = value; 2578 } 2579 2580 static bool pc_machine_get_sata(Object *obj, Error **errp) 2581 { 2582 PCMachineState *pcms = PC_MACHINE(obj); 2583 2584 return pcms->sata_enabled; 2585 } 2586 2587 static void pc_machine_set_sata(Object *obj, bool value, Error **errp) 2588 { 2589 PCMachineState *pcms = PC_MACHINE(obj); 2590 2591 pcms->sata_enabled = value; 2592 } 2593 2594 static bool pc_machine_get_pit(Object *obj, Error **errp) 2595 { 2596 PCMachineState *pcms = PC_MACHINE(obj); 2597 2598 return pcms->pit_enabled; 2599 } 2600 2601 static void pc_machine_set_pit(Object *obj, bool value, Error **errp) 2602 { 2603 PCMachineState *pcms = PC_MACHINE(obj); 2604 2605 pcms->pit_enabled = value; 2606 } 2607 2608 static void pc_machine_initfn(Object *obj) 2609 { 2610 PCMachineState *pcms = PC_MACHINE(obj); 2611 2612 pcms->max_ram_below_4g = 0; /* use default */ 2613 pcms->smm = ON_OFF_AUTO_AUTO; 2614 pcms->vmport = ON_OFF_AUTO_AUTO; 2615 /* acpi build is enabled by default if machine supports it */ 2616 pcms->acpi_build_enabled = PC_MACHINE_GET_CLASS(pcms)->has_acpi_build; 2617 pcms->smbus_enabled = true; 2618 pcms->sata_enabled = true; 2619 pcms->pit_enabled = true; 2620 2621 pc_system_flash_create(pcms); 2622 } 2623 2624 static void pc_machine_reset(void) 2625 { 2626 CPUState *cs; 2627 X86CPU *cpu; 2628 2629 qemu_devices_reset(); 2630 2631 /* Reset APIC after devices have been reset to cancel 2632 * any changes that qemu_devices_reset() might have done. 2633 */ 2634 CPU_FOREACH(cs) { 2635 cpu = X86_CPU(cs); 2636 2637 if (cpu->apic_state) { 2638 device_reset(cpu->apic_state); 2639 } 2640 } 2641 } 2642 2643 static CpuInstanceProperties 2644 pc_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 2645 { 2646 MachineClass *mc = MACHINE_GET_CLASS(ms); 2647 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 2648 2649 assert(cpu_index < possible_cpus->len); 2650 return possible_cpus->cpus[cpu_index].props; 2651 } 2652 2653 static int64_t pc_get_default_cpu_node_id(const MachineState *ms, int idx) 2654 { 2655 X86CPUTopoInfo topo; 2656 2657 assert(idx < ms->possible_cpus->len); 2658 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, 2659 smp_cores, smp_threads, &topo); 2660 return topo.pkg_id % nb_numa_nodes; 2661 } 2662 2663 static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms) 2664 { 2665 int i; 2666 2667 if (ms->possible_cpus) { 2668 /* 2669 * make sure that max_cpus hasn't changed since the first use, i.e. 2670 * -smp hasn't been parsed after it 2671 */ 2672 assert(ms->possible_cpus->len == max_cpus); 2673 return ms->possible_cpus; 2674 } 2675 2676 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 2677 sizeof(CPUArchId) * max_cpus); 2678 ms->possible_cpus->len = max_cpus; 2679 for (i = 0; i < ms->possible_cpus->len; i++) { 2680 X86CPUTopoInfo topo; 2681 2682 ms->possible_cpus->cpus[i].type = ms->cpu_type; 2683 ms->possible_cpus->cpus[i].vcpus_count = 1; 2684 ms->possible_cpus->cpus[i].arch_id = x86_cpu_apic_id_from_index(i); 2685 x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, 2686 smp_cores, smp_threads, &topo); 2687 ms->possible_cpus->cpus[i].props.has_socket_id = true; 2688 ms->possible_cpus->cpus[i].props.socket_id = topo.pkg_id; 2689 ms->possible_cpus->cpus[i].props.has_core_id = true; 2690 ms->possible_cpus->cpus[i].props.core_id = topo.core_id; 2691 ms->possible_cpus->cpus[i].props.has_thread_id = true; 2692 ms->possible_cpus->cpus[i].props.thread_id = topo.smt_id; 2693 } 2694 return ms->possible_cpus; 2695 } 2696 2697 static void x86_nmi(NMIState *n, int cpu_index, Error **errp) 2698 { 2699 /* cpu index isn't used */ 2700 CPUState *cs; 2701 2702 CPU_FOREACH(cs) { 2703 X86CPU *cpu = X86_CPU(cs); 2704 2705 if (!cpu->apic_state) { 2706 cpu_interrupt(cs, CPU_INTERRUPT_NMI); 2707 } else { 2708 apic_deliver_nmi(cpu->apic_state); 2709 } 2710 } 2711 } 2712 2713 static void pc_machine_class_init(ObjectClass *oc, void *data) 2714 { 2715 MachineClass *mc = MACHINE_CLASS(oc); 2716 PCMachineClass *pcmc = PC_MACHINE_CLASS(oc); 2717 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2718 NMIClass *nc = NMI_CLASS(oc); 2719 2720 pcmc->pci_enabled = true; 2721 pcmc->has_acpi_build = true; 2722 pcmc->rsdp_in_ram = true; 2723 pcmc->smbios_defaults = true; 2724 pcmc->smbios_uuid_encoded = true; 2725 pcmc->gigabyte_align = true; 2726 pcmc->has_reserved_memory = true; 2727 pcmc->kvmclock_enabled = true; 2728 pcmc->enforce_aligned_dimm = true; 2729 /* BIOS ACPI tables: 128K. Other BIOS datastructures: less than 4K reported 2730 * to be used at the moment, 32K should be enough for a while. */ 2731 pcmc->acpi_data_size = 0x20000 + 0x8000; 2732 pcmc->save_tsc_khz = true; 2733 pcmc->linuxboot_dma_enabled = true; 2734 pcmc->pvh_enabled = true; 2735 assert(!mc->get_hotplug_handler); 2736 mc->get_hotplug_handler = pc_get_hotplug_handler; 2737 mc->cpu_index_to_instance_props = pc_cpu_index_to_props; 2738 mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; 2739 mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; 2740 mc->auto_enable_numa_with_memhp = true; 2741 mc->has_hotpluggable_cpus = true; 2742 mc->default_boot_order = "cad"; 2743 mc->hot_add_cpu = pc_hot_add_cpu; 2744 mc->block_default_type = IF_IDE; 2745 mc->max_cpus = 255; 2746 mc->reset = pc_machine_reset; 2747 hc->pre_plug = pc_machine_device_pre_plug_cb; 2748 hc->plug = pc_machine_device_plug_cb; 2749 hc->unplug_request = pc_machine_device_unplug_request_cb; 2750 hc->unplug = pc_machine_device_unplug_cb; 2751 nc->nmi_monitor_handler = x86_nmi; 2752 mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; 2753 mc->nvdimm_supported = true; 2754 2755 object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", 2756 pc_machine_get_device_memory_region_size, NULL, 2757 NULL, NULL, &error_abort); 2758 2759 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", 2760 pc_machine_get_max_ram_below_4g, pc_machine_set_max_ram_below_4g, 2761 NULL, NULL, &error_abort); 2762 2763 object_class_property_set_description(oc, PC_MACHINE_MAX_RAM_BELOW_4G, 2764 "Maximum ram below the 4G boundary (32bit boundary)", &error_abort); 2765 2766 object_class_property_add(oc, PC_MACHINE_SMM, "OnOffAuto", 2767 pc_machine_get_smm, pc_machine_set_smm, 2768 NULL, NULL, &error_abort); 2769 object_class_property_set_description(oc, PC_MACHINE_SMM, 2770 "Enable SMM (pc & q35)", &error_abort); 2771 2772 object_class_property_add(oc, PC_MACHINE_VMPORT, "OnOffAuto", 2773 pc_machine_get_vmport, pc_machine_set_vmport, 2774 NULL, NULL, &error_abort); 2775 object_class_property_set_description(oc, PC_MACHINE_VMPORT, 2776 "Enable vmport (pc & q35)", &error_abort); 2777 2778 object_class_property_add_bool(oc, PC_MACHINE_SMBUS, 2779 pc_machine_get_smbus, pc_machine_set_smbus, &error_abort); 2780 2781 object_class_property_add_bool(oc, PC_MACHINE_SATA, 2782 pc_machine_get_sata, pc_machine_set_sata, &error_abort); 2783 2784 object_class_property_add_bool(oc, PC_MACHINE_PIT, 2785 pc_machine_get_pit, pc_machine_set_pit, &error_abort); 2786 } 2787 2788 static const TypeInfo pc_machine_info = { 2789 .name = TYPE_PC_MACHINE, 2790 .parent = TYPE_MACHINE, 2791 .abstract = true, 2792 .instance_size = sizeof(PCMachineState), 2793 .instance_init = pc_machine_initfn, 2794 .class_size = sizeof(PCMachineClass), 2795 .class_init = pc_machine_class_init, 2796 .interfaces = (InterfaceInfo[]) { 2797 { TYPE_HOTPLUG_HANDLER }, 2798 { TYPE_NMI }, 2799 { } 2800 }, 2801 }; 2802 2803 static void pc_machine_register_types(void) 2804 { 2805 type_register_static(&pc_machine_info); 2806 } 2807 2808 type_init(pc_machine_register_types) 2809